CXA1992AR

RF Signal Processing Servo Amplifier

Description
The CXA1992AR is a bipolar IC developed for CD 52 pin LQFP (Plastic)
player RF signal processing and servo control.

Features
• Automatic focus bias adjustment circuit
• Automatic tracking balance and gain adjustment
circuits
• RF level control circuit
• Interruption countermeasure circuit
Absolute Maximum Ratings (Ta = 25°C)
• Sled overrun prevention circuit
• Supply voltage VCC 12 V
• Anti-shock circuit
• Operating temperature Topr –20 to +75 °C
• Defect detection and prevention circuits
• Storage temperature Tstg –65 to +150 °C
• RF 1-V amplifier, RF amplifier
• Allowable power dissipation
• APC circuit
PD 600 mW
• Focus and tracking error amplifier
• Focus, tracking and sled servo control circuits
Recommended Operating Conditions
• Focus OK circuit
Operating supply voltage VCC – VEE 3.0 to 5.5 V
• Mirror detection circuit
• Single power supply and dual power supplies

Applications
CD players

Structure
Bipolar silicon monolithic IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

–1–
E96X16-PS
 CXA1992AR

Block Diagram

RF_M

RF_O
RFTC

RF_I

FOK
CC1
PD2

CC2
PD1

CP
PD

CB
LD
39 38 37 36 35 34 33 32 31 30 29 28 27
VEE

RF SUMMING AMP
PD2 IV PD1 IV
AMP AMP

FE_BIAS 40 26 SENS2
VCC
APC

IIL
VEE
F 41 ↓ 25 SENS1
LASER POWER CONTROL
VCC TTL
F IV AMP

VCC
VCC FE AMP
E 42 24 C. OUT

E IV AMP VEE

DFCT
IFB2

IFB5
IFB3
IFB1

IFB4

EI 43
IFB6

23 XRST
BAL2
BAL1

BAL4
BAL3

VEE
LEVEL S
VEE
TGFL

VEE
VEE 44 VEE FO. BIAS 22 DATA
TOG4
TOG3
TOG2
TOG1

WINDOW COMP. MIRR

VCC IIL
↓
TTL
TRK. GAIN TTL ↓
TEO 45 21 XLT
WINDOW COMP. FOK IIL

E-F BALANCE

DFCT1
WINDOW COMP.
LDON

MIRR
LPFI 46 20 CLK
TGFL
LPCL

CC1
LPC

FOH
FOL
TGH
TEI 47 TGL IIL DATA REGISTER 19 LOCK
BALH INPUT SHIFT REGISTER
ADDRESS DECODER
BALL SENS SELECTOR
ATSC OUTPUT DECODER
TZC
ATSC 48 FZC VCC 18 VCC
ATSC
WINDOW
COMP.
DFCTO IFB1-6 FS1-4 TG1-2 TM1-7 PS1-4
TZC COMP. BAL1-4
TZC 49 TOG1-4 ISET 17 ISET

DFCT
TM1

TRACKING VCC VCC

TDFCT 50 PHASE COMPENSATION 16 SL_O
TG1 TM4 TM6
VCC

VC 51 15 SL_M
VCC
TM7
VCC
VEE FS1
FOCUS
PHASE COMPENSATION
TM3 TM5
FZC 52 14 SL_P
VEE VEE TM2
FS2
DFCT Charge
FZC COMP. up FSET

TG2
FS4

VEE
1 2 3 4 5 6 7 8 9 10 11 12 13
FGD

SRCH
FEO

TA_M
FLB

TGU

TA_O
FEI

FE_O

TG2
FDFCT

FE_M

FSET

–2–
 CXA1992AR

Pin Description
Pin
Symbol I/O Equivalent circuit Description
No.

10µ
25p
Focus error amplifier output.
147
1 FEO O 1
Connected internally to the window
174k comparator input for bias
10µ adjustment.
300µ

2 FEI I 147 Focus error input.

2
100k

147
3 3µ Capacitor connection pin for defect
3 FDFCT I
time constant.

68k Ground this pin through a capacitor

4 FGD I 147 for cutting the focus servo high-
4 frequency gain.
130k
4µ

40k 330k
5 External time constant setting pin
5 FLB I for boosting the focus servo low-
470k
frequency.

6 FE_O O Focus drive output.

6
13 TA_O O 13 Tracking drive output.
16

250µ
16 SL_O O Sled drive output.

90k
147
7 FE_M I 7 Focus amplifier inverted input.
50k
2µ

–3–
 CXA1992AR

Pin
Symbol I/O Equivalent circuit Description
No.

147
External time constant setting pin for
8 SRCH I 8 20k
generating focus search waveform.
50k 11µ

110k
147 20k
External time constant setting pin
9 TGU I 9 for switching tracking high-
frequency gain.
82k

External time constant setting pin for

10 TG2 I 10 switching tracking high-frequency
470k
gain.

147k Peak frequency setting pin for focus

11 FSET I 11 and tracking phase compensation
amplifier.
15k 15k

100k
147
12 TA_M I 12 Tracking amplifier inverted input.

11µ

147
14 SL_P I 14 Sled amplifier non-inverted input.

2µ

147
15 SL_M I 15 Sled amplifier inverted input.

22µ

–4–
 CXA1992AR

Pin
Symbol I/O Equivalent circuit Description
No.

Connect an external capacitance to

147 set the current which determines
17 ISET I
17 the Focus search, Track jump, and
Sled kick heights.
50µ

18 VCC I 18 VCC Positive power supply.

The sled overrun prevention circuit

19 LOCK I operates when this pin is Low.
20µ
(no pull-up resistance)
19 147 1k Serial data transfer clock input from
20 CLK I 20
CPU. (no pull-up resistance)
22

Serial data input from CPU.

22 DATA I
(no pull-up resistance)

Latch input from CPU.

21 XLT I 20µ (no pull-up resistance)
147 2k
21
23
5p Reset input; resets at Low.
23 XRST I
(no pull-up resistance)

24 C. OUT O Track number count signal output.

20k
24 Outputs FZC, DFCT1, TZC, BALH,
147
25 SENS1 O 25 TGH, FOH, ATSC, and others
26
according to the command from CPU.

100k
Outputs DFCT2, MIRR, BALL, TGL,
26 SENS2 O FOL, and others according to the
command from the CPU.

20k
147
27 FOK O 27 40k Focus OK comparator output.

100k

–5–
 CXA1992AR

Pin
Symbol I/O Equivalent circuit Description
No.

Input for the defect bottom hold

28 CC2 I
147 output with capacitance coupled.
147 29
30

Defect bottom hold output.

29 CC1 O Connected internally to the
interruption comparator input.

147
28
120k
11k 43k Connection pin for defect bottom
30 CB I hold capacitor.

31 Connection pin for MIRR hold

100k
capacitor.
31 CP I 1.5k
MIRR comparator non-inverted
input.

Input for the RF summing amplifier

32 RF_I I
output with capacitance coupled.

147 RF sunning amplifier output. Eye-

33 RF_O O 32
pattern check point.

147
33 147
34
RF summing amplifier inverted
10k 10k input.
34 RF_M I The RF amplifier gain is determined
by the resistance connected
between this pin and RFO pin.

147 50µ
External time constant setting pin
35 RFTC I 35
during RF level control.
50µ

10µ

–6–
 CXA1992AR

Pin
Symbol I/O Equivalent circuit Description
No.

10k
1k
36 LD O 36 APC amplifier output.

20µ
8µ

147 55k
37 PD I 37 APC amplifier input.
10k

10k 8k

2k

38 RF I-V amplifier inverted input.

PD1 I 147
39 38 Connect these pins to the photo
PD2 I
39 diode A + C and B + D pins.
100µ 11.6k

4k

Bias adjustment of focus error

147 amplifier.
40 FE_BIAS I 40
Leave this pin open for automatic
6µ
adjustment.

12p

260k
F I-V and E I-V amplifier inverted
41 F I 147 input.
42 E I 41 Connect these pins to photo diodes
42 F and E.
500
10µ

–7–
 CXA1992AR

Pin
Symbol I/O Equivalent circuit Description
No.

6.8k 110k 56k 27k 13k

I-V amplifier E gain adjustment.

147 260k
43 EI — 43 (When not using automatic balance
75k adjustment)

44 VEE — 44 VEE Negative power supply.

147
7.5k 16k 7.5k 3.3k 1.5k
45 Tracking error amplifier output.
45 TEO O 150k
10k E-F signal is output.
150k

147 Comparator input for balance

46 LPFI I 46 adjustment.
(Input from TEO through LPF)
7µ

47 TEI I Tracking error input.

147 100k
47

147
50 3µ Capacitor connection pin for defect
50 TDFCT I
time constant.

–8–
 CXA1992AR

Pin
Symbol I/O Equivalent circuit Description
No.

1k 100k

147
Window comparator input for ATSC
48 ATSC I 48
detection.
100k 1k

10µ 10µ

10µ

147 Tracking zero-cross comparator

49 TZC I 49
input.
75k

50 120
51 VC O 51 (VCC + VEE)/2 direct voltage output.
120

VC

10µ
51k
147
52 FZC I 52 Focus zero-cross comparator input.
75k 9k

–9–
 CXA1992AR

Electrical Characteristics (VCC = 1.5V, VEE = 1.5V, Topr = 25°C)

SW conditions Input Measure- Measurement

TEST Item SD Min. Typ. Max. Unit
(ON switches) pin ment pin conditions
Current
T1 51 RST 18 18 18.4 24.4 34.2 mA
consumption 1

Current
T2 51 RST 44 44 –34.2 –24.4 –18.4 mA
consumption 2

Center amplifier
T3 51, 51D RST — 51 –100 0 100 mV
output offset

T4 Offset RST 33 –50 0 50 mV

RF amplifier

38
T5 Voltage gain 33S, 38, 39 RST 33 1kHz I/O ratio 25.1 28.1 31.1 dB
39

Max. output
T6 33D, 38 RST 38 33 V2 = 0.2VDC 1.2 1.3 — V
amplitude - High

Max. output
T7 33D, 39 RST 39 33 V2 = 0.2VDC — –0.6 –0.3 V
amplitude - Low
38
T8 Offset 1D 39F 1 1FB6: ON –120 0 120 mV
39

Voltage gain 1
T9 1S, 38 39F 38 1 1kHz I/O ratio 27 30 33 dB
(PHD1)

Voltage gain 2
T10 1S, 39 39F 39 1 1kHz I/O ratio 27 30 33 dB
(PHD2)

Voltage gain
T11 1S 39F –3 0 3 dB
difference

Max. output
T12 1D, 39 39F 39 1 V2 = 100mVDC 1 1.3 — V
voltage – High

Max. output
T13 1D, 38 39F 38 1 V2 = 100mVDC — –1.3 –1 V
voltage – Low
FE amplifier

IFB1, 2, 3, 4, 5, 6:
T14 BIAS0 1D 3BF 1 560 801 1042 mV
OFF

IFB1: ON, BIAS0:

T15 BIAS1 1D 3BE 1 –31.3 –25 –18.8 mV
reference

IFB2: ON, BIAS0: reference

T16 BIAS2 1D 3BD 1 5 6 7 dB
Output gain difference with T15

IFB3: ON, BIAS0: reference

T17 BIAS3 1D 3BB 1 5 6 7 dB
Output gain difference with V17

IFB4: ON, BIAS0: reference

T18 BIAS4 1D 3B7 1 5 6 7 dB
Output gain difference with V18

IFB5: ON, BIAS0: reference

T19 BIAS5 1D 3AF 1 5 6 7 dB
Output gain difference with V19

IFB6: ON, BIAS0: reference

T20 BIAS6 1D 39F 1 5 6 7 dB
Output gain difference with V20

– 10 –
 CXA1992AR

SW conditions Input Measure- Measurement

TEST Item SD Min. Typ. Max. Unit
(ON switches) pin ment pin conditions
IFB6: ON
FOH threshold 1D, 25D, 40 39F 40 1 5 20 35 mV
FE amplifier

Pin 1 voltage when SENS1

T21
(Pin 25) goes from High to Low

IFB6: ON
T22 FOL threshold 1D, 26D, 40 39F 40 1 Pin 1 voltage when SENS2 –35 –20 –5 mV
(Pin 26) goes from High to Low

34F 41 TOG: OFF,

T23 Offset 45D 45 –25 0 25 mV
308 42 BAL1, 2, 3: ON
36F V1 = 2 kHz, I/O ratio
T24 GAIN UP (F) 41, 45S 41 45 8.6 11.6 14.6 dB
308 TOG: OFF, BAL1, 2, 3: ON
36F V1 = 2 kHz, I/O ratio
T25 GAIN UP (E) 42, 45S 42 45 8.6 11.6 14.6 dB
308 TOG: OFF, BAL1, 2, 3: ON
Voltage gain V1 = 2kHz, TOG: OFF
T26 41, 45S 34F 41 45 2.5 5.5 8.5 dB
F0 I/O ratio
Voltage gain 34E V1 = 2kHz, TOG1: ON
T27 41, 45S 41 45 –2.6 –2.1 –1.6 dB
F1 30F Reference to F0
Voltage gain V1 = 2kHz, TOG2: ON
T28 41, 45S 34D 41 45 –4.4 –3.9 –3.4 dB
F2 Reference to F0
Voltage gain V1 = 2kHz, TOG3: ON
T29 41, 45S 34B 41 45 –7.7 –7.2 –6.7 dB
F3 Reference to F0
TE amplifier

Voltage gain V1 = 2kHz, TOG4: ON

T30 41, 45S 347 41 45 –12.2 –11.7 –11.2 dB
F4 Reference to F0
Voltage gain 34F V1 = 2kHz, BAL: OFF
T31 42, 45S 30F 42 45 –0.33 2.67 5.67 dB
E0 00 I/O ratio
Voltage gain V1 = 2kHz, BAL1: ON
T32 42, 45S 30E 42 45 0.17 0.47 0.77 dB
E1 Reference to E0
Voltage gain V1 = 2kHz, BAL2: ON
T33 42, 45S 30D 42 45 0.6 0.9 1.2 dB
E2 Reference to E0
Voltage gain V1 = 2kHz, BAL3: ON
T34 42, 45S 30B 42 45 1.46 1.76 2.06 dB
E3 Reference to E0
Voltage gain V1 = 2kHz, BAL4: ON
T35 42, 45S 307 42 45 3.03 3.33 3.63 dB
E4 Reference to E0
Max. output 34F V1 = 1VDC, TOG: OFF,
T36 41, 45D 41 45 0.5 0.7 — V
voltage – High 308 BAL1, 2, 3: ON
Max. output 34F V1 = 1VDC, TOG: OFF,
T37 42, 45D 42 45 — –0.8 –0.5 V
voltage – Low 308 BAL1, 2, 3: ON
Output voltage
T38 36D, 37 3C4 37 36 I37 = 364µA –900 –694 –500 mV
1

Output voltage
T39 36D, 37 3C4 37 36 I37 = 439µA –900 –538 –100 mV
2

Output voltage
APC

T40 36D, 37 3C4 37 36 I37 = 515µA –100 367 800 mV

3

Output voltage
T41 36, 36D 3C4 37 36 0.8mA sink –200 130 500 mV
4

I37 = 515µA,
T42 LD OFF 36, 36D, 37 3C0 37 36 1.1 1.3 — V
LD: OFF
– 11 –
 CXA1992AR

SW conditions Input Measure- Measurement

TEST Item SD Min. Typ. Max. Unit
(ON switches) pin ment pin conditions

37 I37 = 273µA
T43 50% limit 32, 36D, 37 3C7 36 300 1020 1510 mV
32 Output difference with LPC ON/OFF
RF level controll

37 I37 = 394µA
T44 17% limit 32, 36D, 37 3C5 36 230 610 1050 mV
32 Output difference with LPC ON/OFF

36D, 37, 38, 37 I37 = 742µA

T45 –50% limit 3C7 38 36 –1510 –970 –300 mV
39 39
Output difference with LPC ON/OFF

36D, 37, 38, 37 I37 = 621µA

T46 –17% limit 3C5 38 36 –900 –580 –80 mV
39 39
Output difference with LPC ON/OFF

Direct voltage
T47 2, 6D 08 2 6 17.8 20.8 23.8 dB
gain

T48 FCS total gain — — — T9 + T47 49 51 53 dB

Feed through 00 Output gain difference between

T49 2, 6S 2 6 — — –30 dB
1 08 SD = 00 and SD = 08.

Pin 52 voltage when SENS1

Focus servo

T50 FZC threshold 26D, 52 00 52 52 181 221 261 mV

(Pin 25) goes from Low to High

Max. output V1 = 200mVDC

T51 2, 6D, 6S 08 2 6 1 1.3 — V
voltage – High

Max. output V1 = –200mVDC

T52 2, 6D, 6S 08 2 6 — –1.3 –1 V
voltage – Low

Search
T53 6D 02 — 6 –640 –500 –360 mV
voltage (–)

Search
T54 6D 03 — 6 360 500 640 mV
voltage (+)

Direct voltage
T55 13D, 47 25 47 13 12.2 14.6 17.6 dB
gain

T56 TRK total gain — — — T26 + T55 18.1 20.1 22.1 dB

Feed through 20 Output gain difference between

T57 13S, 47 47 13 — — –39 dB
1 25 SD = 20 and SD = 25.

Max. output 20
T58 13D, 47 47 13 V1 = –0.5VDC 1 1.3 — V
voltage – High 25
Tracking servo

Max. output 20
T59 13D, 47 47 13 V1 = 0.5VDC — –1.3 –1 V
voltage – Low 25

Jump output
T60 13D 2C 13 –640 –500 –360 mV
voltage (–)

Jump output
T61 13D 28 13 360 500 640 mV
voltage (+)

ATSC Input voltage when TG2

T62 10, 10D, 48 10 48 48 –25 –15 –7 mV
threshold (–) (Pin 10) goes from Vcc/2 to Vcc

ATSC Input voltage when TG2 (Pin 10)

T63 10, 10D, 48 10 48 48 7 15 25 mV
threshold (+) goes from Vcc/2 to Vcc

25D, 49, Pin 49 voltage when

T64 TZC threshold 20 49 49 –20 0 20 mV
49B SENS1 (Pin 25) is 0V

– 12 –
 CXA1992AR

SW conditions Input Measure- Measurement

TEST Item SD Min. Typ. Max. Unit
(ON switches) pin ment pin conditions
BAL COMP 25D, 46, Pin 46 voltage when SENS1
T65 300 46 46 5 20 35 mV
threshold – High 46B (Pin 25) goes from High to Low
Tracking servo

BAL COMP 26D, 46, Pin 46 voltage when SENS2

T66 300 46 46 –35 –20 –5 mV
threshold – Low 46B (Pin 26) goes from High to Low

GAIN COMP 25D, 41, 308 Pin 45 voltage when SENS1

T67 41 45 350 400 450 mV
threshold – High 45D 34F (Pin 25) goes from High to Low

GAIN COMP 26D, 41, 308 Pin 45 voltage when SENS2

T68 41 45 260 300 340 mV
threshold – Low 45D 34F (Pin 26) goes from Low to High

FOK Pin 32 voltage when

FOK

T69 27D, 32 — 32 32 –400 –367 –330 mV

threshold Pin 27 is 0V

14, 14B, 15, V1 = 100Hz, I/O ratio

T70 Voltage gain 25 14 16 50 — — dB
16S

14, 14B, 20 Output gain difference between

T71 Feed through 14 16 — — –34 dB
16S 25 SD = 20 and SD = 25.

Max. output 14, 14B,

Sled servo

T72 25 14 16 V1 = 400mVDC 1 1.3 — V

voltage – High 16D

Max. output 14, 14B,

T73 25 14 16 V1 = 400mVDC — –1.3 –1 V
voltage – Low 16D

T74 Kick voltage 1 16D 20 — 16 REV × 1 –750 –600 –450 mV

T75 Kick voltage 2 16D 20 — 16 FWD × 1 450 600 750 mV

Max. operating Measures at SENS2

T76 26S, 32 20 32 26 30 — — kHz
frequency 1 pin.
MIRROR

Min. input Measures at SENS2

T77 26S, 32 20 32 26 — — 0.3 Vp-p
operating voltage 1 pin.

Max. input Measures at SENS2

T78 26S, 32 20 32 26 1.8 — — Vp-p
operating voltage 1 pin.

Min. operating 38 Measures at SENS1

T79 25S, 38, 39 10 25 — — 1 kHz
frequency 1 39 pin.

Max. operating 38 Measures at SENS1

T80 25S, 38, 39 10 25 2.5 — — kHz
DEFECT

frequency 1 39 pin.

Min. input 38 Measures at SENS1

T81 25S, 38, 39 10 25 — — 0.5 Vp-p
operating voltage 1 39 pin.

Max. input 38 Measures at SENS1

T82 25S, 38, 39 10 25 1.8 — — Vp-p
operating voltage 1 39 pin.

– 13 –
 Electrical Characteristics Measurement Circuit STORAGE2 GND

GND DC OUTPUT
VCC

GND R18 R21

I37 I36 10k 100 GND
0mA 0mA R31 R35
R24 100k 10k GND GND
VEE 10k
V2 R12 R14 S33D S33S
R9 R11 330 10k R15 S28
10k 10k 1M
C6 C7 C9 R54
C5 3300p 1000p 3300p
AC S27S 100
S39 S38 S37 0.1µ STORAGE1
S32
S36 S36D S27D
R17
DC 22k
R48
10k GND
39 38 37 36 35 34 33 32 31 30 29 28 27
R53
100

LD

PD
CP
CB
I40 S26S GND

PD1

PD2
CC2

CC1
FOK

RF_I

RF_O

RFTC
RF_M
0mA S26D R47
S40 R40 10k
40 FE_BIAS SENS2 26 R52
10k S25S 100
R6
S25D R46
390k S41 R39 10k R51
41 F SENS1 25
10k S24S 100
R5
390k S24D R45
S42 R38 10k
42 E C. OUT 24
10k
R4
13k S43
43 EI XRST 23 XRST

C2 33µ
44 VEE DATA 22 DATA
A44 S45
R2
100 S45S
45 TEO XLT 21 XLT
S45D
R1 S46
10k S46B 46 LPFI CLK 20 CLK

– 14 –
A46 S47
47 TEI LOCK 19 D_GND
S19
C10 33µ
S48
48 ATSC VCC 18
R43 120k
S17 A18
S49 R50
S49B 49 TZC ISET 17 10k
R37 S16D
A49 A50 120k S16S R49
S50 100
C1 50 TDFCT SL_O 16
R42
1000P R36 R41 13k R44
I51 S51 60k 10k 5.1k
R3 0mA S51I 51 VC SL_M 15
10k C11 47µ
S51D S16 S15
S52
52 FZC SL_P 14
S14
S14B

FE_O
TA_O

FLB
TA_M

FGD
FSET

FDFCT
TG2

FEI
TGU

FEO
SRCH

FE_M
A14
1 2 3 4 5 6 7 8 9 10 11 12 13

C8
S1S R28 0.01µ
S2 S3 S7 510k S12
S5 R20 S9
S4 C4 100k
V1 S1D
1000P S10
R13
C3 R23 S10D R27 R30 R33
47k
AC 1000P 200k 10k 100k 200k

R8 R16 S6S S13S R34

DC 10k 13k S8D 13k
A3 S6D S13D

R7 R10 R19 R22 R25 R26 R29 R32

10k 100 100 10k 10k 10k 10k 100
GND
CXA1992AR
 CXA1992AR

Application Circuit 1 (±2.5V power supply)

Vcc
Vcc
1µ
1k 3.3µ 22 100µ

A
LD 10µH
PD
C VEE VEE
VEE 100 MICRO

1µ
B 500 COMPUTER

1M
22k 0.01µ 0.033µ

0.033µ
DSP

0.01µ
D

39 38 37 36 35 34 33 32 31 30 29 28 27

RF_M

RF_O

CP
PD

CC1

FOK
PD1

LD
PD2

RFTC

RF_I

CC2
CB
40 26
FE_BIAS SENS2
F
41 F SENS1 25
E
42 E C. OUT 24

43 EI XRST 23

VEE 44 VEE DATA 22

45 TEO XLT 21
100k 150k
46 LPFI CLK 20
0.01µ 0.01µ
47 TEI LOCK 19
0.047µ 47k
48 ATSC Vcc 18 Vcc
330k 470p 60k
49 TZC ISET 17 VEE

0.022µ 50 TDFCT SL_O 16 DRIVER

100k
0.1µ
51 VC SL_M 15
0.015µ 8.2k
FDFCT

FZC
SRCH

TA_M
TA_O
FE_O

FE_M

FSET
52 SL_P 14
FGD

TGU
FEO

TG2
FLB
FEI

3.3µ

0.022µ 1 2 3 4 5 6 7 8 9 10 11 12 13
680k 22µ 15k

82k
0.1µ
10k 4.7µ 100k
10k 0.1µ 100k 0.033µ
2200p 0.1µ 510k 0.015µ
DRIVER Vcc DRIVER

Application Circuit 2 (Single +5V power supply)

Vcc
Vcc
1µ
1k 3.3µ 22 100µ

A
LD 10µH
PD
C
100 MICRO
1µ

B 500 COMPUTER
1M

22k 0.01µ 0.033µ

0.033µ

DSP
0.01µ

39 38 37 36 35 34 33 32 31 30 29 28 27
RF_M

RF_O

CP
PD

CC1

FOK
PD1

LD
PD2

RFTC

RF_I

CC2
CB

40 26
FE_BIAS SENS2
F
41 F SENS1 25
E
42 E C. OUT 24

43 EI XRST 23

44 VEE DATA 22

45 TEO XLT 21
100k 150k
46 LPFI CLK 20
0.01µ 0.01µ
47 TEI LOCK 19
0.047µ 47k
48 ATSC Vcc 18 Vcc
330k 470p 60k
49 TZC ISET 17
0.022µ 0.1µ
50 TDFCT SL_O 16 DRIVER
100k

10µ
VCC 0.015µ
51 VC SL_M 15
8.2k
FDFCT

FZC
SRCH

TA_M
TA_O
FE_O

FE_M

10µ
FSET

52 SL_P 14
FGD

TGU
FEO

TG2
FLB
FEI

3.3µ

0.022µ 1 2 3 4 5 6 7 8 9 10 11 12 13
680k 22µ 15k
82k
2200p

10k 4.7µ 100k

10k 0.1µ 0.1µ 0.1µ 100k 0.033µ
510k 0.015µ
DRIVER Vcc DRIVER

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 15 –
 CXA1992AR

Description of Functions

RF Amplifier
The photo diode currents input to the input pins (PD1 and PD2) are each I-V converted through a 58kΩ
equivalent resistor by the PD I-V amplifiers. These signals are added by the RF summing amplifier, and the
photo diode (A + B + C + D) current-voltage converted voltage is output to the RFO pin. An eye-pattern check
can be performed at this pin.

1k
3.3µ 22k

RF_M RF_O
A 34 33
58k

PD1
C 10k
38 VA
iPD1→

B PD1 IV AMP
VC RF SUMMING AMP
58k
VC
PD2
D 10k
39 VB
iPD2→

PD2 IV AMP
VC

The low frequency component of the RFO output voltage is VRFO = 2.2 × (VA + VB) = 127.6kΩ × (iPD1 + iPD2).

– 16 –
 CXA1992AR

Focus Error Amplifier

R3 R7
58k 174k
R5
32k
PD2 39 VB
FEO
B+D 1
PD2 IV AMP
FE AMP R10
VC R2 10k
58k
FEI
R4 2

VA 32k
PD1 38 R9 C1
10k 2200p
A+C
PD1 IV AMP
R6 GND GND
VC 174k
VCC R1 FE_M
4k 7

R8 R11
×1 ×2 ×4 ×8 ×16 ×32 100k 100k
FOCUS
PHASE FE_O
EF_BIAS 40 6 DRIVER
VC COMPENSATION
IFB5
IFB3

IFB6
IFB2

IFB4
IFB1

VIN > VH L
VIN < VH H
25mV/STEP VC
VH
RESET : IFB1 to IFB6 ON FOH
25 SENS1
VEE
20mV SENS
VIN SELECTOR
VC
FOL
26 SENS2
VL
VIN > VL H
VIN < VL L
–20mV

VC

The focus error amplifier calculates the difference between output VA and VB of the RF I-V amplifier, and
output current-voltage converted voltage of the photo diode (A + C – B – D).

The FEO output voltage:

174kΩ
VFEO = (VA – VB)
32kΩ
174kΩ
= {(–58kΩ × iPD1) – (–58kΩ × iPD2)}
32kΩ

= 315.4kΩ (iPD2 – iPD1)

The focus error amplifier has a built-in bias adjustment circuit to enable software-based automatic adjustment.
The focus bias adjustment is performed by turning the focus bias adjustment switches (IFB1 to IFB6) ON and
OFF.
The 6-bit focus bias adjustment switches are controlled with commands.
IFB1 to IFB6 are all ON after a reset.
The voltage is varied by approximately 25mV per step.

– 17 –
 CXA1992AR

• Focus error amplifier offset adjustment (when adjusting the IC offset)

The offset adjustment is performed by comparing the FEO when the focus servo is OFF with the reference
level.
The FEO and reference level are compared by the window comparator, and the comparison results are output
from SENS1 and SENS2. (ADDRESS D11001110D6)
Adjust the offset so that SENS1 and SENS2 are both High.
Set the reference level to the center ±20mV.

25mV < 40mV < 50mV

Reference level width

Variable voltage per step Variable voltage per 2 steps

• Focus bias fine adjustment

Fine adjustment is performed by turning the focus bias adjustment switches (IFB1 to IFB6) ON and OFF while
monitoring a DSP jitter meter with the microcomputer.
The 6-bit focus bias adjustment switches are controlled with commands.

• When performing conventional focus bias adjustment

Fix the focus bias adjustment switches to the desired settings. (for example, IFB6 ON)
In this condition, adjust the focus bias by turning a volume connected to FE_BIAS (Pin 40).

[Example circuit]

VCC

Volume 47k 40 FE_BIAS

3.9k

VEE

– 18 –
 CXA1992AR

Tracking Error Amplifier

R23 R24
100k 150k

C3 C4
0.01µ 0.01µ

TEO GND GND LPFI

45 46
VIN > VH L
R2 R5 VIN < VH H
260k 13k TE AMP VH
BALH
R16
NORMAL 96k
C2 R3 SENS1
R14 20mV 25
12p 26k
13k TGFL VC
R9 VIN
VC 17k BALL
F 41
VF R8 GAIN UP R18
– VL
17k GAIN UP 7.5k VIN > VL H
+ –20mV VIN < VL L SENS
VC
R4 R13 R22
VC VIN > VH L SELECTOR
F I-V AMP R1 1.5k
R17

3.3k
R21
7.5k
10k

R20
VIN < VH H
R19

13k TGFL
16k

260k 6.8k VH
V NORMAL TGH
400mV
R12
TOG4
TOG3
TOG2
TOG1

C1 96k
E 42
12p
VC SENS2 CPU
VC VIN 26
VE TGL
VC
VC VL
300mV VIN > VL H
BAL1 110k
R10

R15
R11
BAL2 56k
75k

BAL4 13k
BAL3 27k
R7
R6

E I-V AMP RE VIN < VL L

XRST
VC 23
DATA
COMAND
COMAND 22
CONTROL
CONTROL XLT
VC 21
CLK
20

43
EI

The difference between E I-V amplifier output VE and F I-V amplifier output VF is taken and output from TEO.

The tracking error amplifier has built-in balance and gain adjustment circuits to enable software-based
automatic adjustment.
The balance adjustment is performed by varying the combined resistance value of the T-configured feedback
resistance at the E I-V amplifier.

E I-V AMP feedback resistance = R1 + R4 + R1 × R4

RE

F I-V AMP feedback resistance = R2 + R5 + R2 × R5 = 403kΩ

R3

Vary the combined resistance value of the E I-V amplifier's feedback resistance by using the balance
adjustment switches (BAL1 to BAL4).
The gain adjustment is performed by resistance dividing the TE AMP output by the gain adjustment switches
(TOG1 to TOG4).
The balance and gain adjustment switches are controlled with commands.
Set the cut-off frequency of the external LPF between 10Hz to 100Hz.

– 19 –
 CXA1992AR

• Balance adjustment
The balance adjustment is performed by passing the tracking error signal (TEO signal) through the external
LPF, extracting the offset DC, and comparing it to the reference level.
However, the TEO signal frequency distribution ranges form DC to 2kHz. Merely sending the signal through
the LPF leaves lower frequency components, and the complete offset DC can not be extracted.
To extract it, monitor the TEO signal frequency at all times, and perform adjustment only when a frequency
that can lower a sufficient gain appears on the LPF.
Use the C.OUT output to check this frequency.
The offset DC and reference level are compared by the window comparator.
The comparison signal is output from the SENS1 and SENS2 pins. (ADDRESS D11001100D6)
Adjust the balance so that the SENS1 and SENS2 pins are both High.
VIN < VL < VH VL < VIN < VH VL < VH < VIN
SENS1 pin
H H L
BALH
SENS2 pin
L H H
BALL
VH: High level threshold value
VIN: Window comparator input signal
VL: Low level threshold value

• Gain adjustment
Gain adjustment is performed by passing the TEO signal through the HPF and comparing the AC component
to the reference level.
The AC component is generated by taking the difference between TE and the offset DC input to Pin 46.
The AC component and reference level are compared by the window comparator.
The comparison signal is output from the SENS1 and SENS2 pins. (ADDRESS D11001101D6)
The comparison signal is as follows.

(1) (2) (3)

VH

VL

VIN

SENS1 pin H H
TGH

SENS2 pin
TGL L

The gain should be adjusted so that the SENS1 and SENS2 pins are as shown in status (2).

When the TEO signal level is low and TGH (SENS1 pin) does not go Low, the gain should be raised with the
TGFL command for adjustment. If the adjustment does not bring the result of Low, check the pulse duty of TGL
(SENS2 pin).

– 20 –
 CXA1992AR

APC & Laser Power Control

VCC

R1 C2
22 100µ

LD
36
R6
1k VCC

LDON
L1
10µH 130mV R10
R8 56k
PD 10k
37

C1 R3
1µ 100
R2 R5
500 R12
55k 56k
R4 R11
LD PD
10k 10k VREF
VEE
GND
VEE VEE VL
LPC ON/OFF
R14
12.5k 50%/17%
RF_I 1.1Vpp
32

C3
0.01µ R7 670mV
1.47V 39.5k
33
RF_O
R9 VC
RF 23.5k

VC

35
RFTC

R13
1M C4
1µ
VEE VEE

• APC
When the laser diode is driven by a constant current, the optical power output has extremely large negative
temperature characteristics.
The APC circuit is used to maintain the optical power output at a constant level.
The laser diode current is controlled according to the monitor photo diode output.

• Laser power control

The RF level is stabilized by attaching an offset to the APC VL and controlling the laser power in sync with the
RF level fluctuations.
The RF_O and RF_I levels are compared and the larger of the two is smoothed by the RFTC's external CR.
This signal is then compared with the reference level.
The laser power is controlled by attaching an offset to VL according to the results of comparison with the
reference level.
Set the reference level to 670mV. (center voltage reference)
LPC ON/OFF and LD ON/OFF control is performed with commands.
The laser power control limit can also be switched between ±50% and ±17% with commands.
LPC LPCL VL variable range
OFF — Approximately 1.27V
ON ±50% Approximately 1.27V ± 625mV
ON ±17% Approximately 1.27V ± 208mV
– 21 –
 CXA1992AR

Center Voltage Generation Circuit

(The figure below shows a single voltage application; Connect to GND for dual power supplies.)
Maximum current is approximately ±3mA. Output impedance is approximately 50Ω.

VCC VCC

30k
VC

50 VC
51

30k

VEE GND

Connected internally to the VEE pin.

– 22 –
 CXA1992AR

Focus Servo

9k
0.022µ FZC
52 51k
FZC
FEO
SENS
1 25 SENS1
FE SELECTOR
10k
75k
2
10k FEI
2200p 100k DFCT FS4 68k
FE_O FOCUS COIL
FS3 Focus 100k
3 phase 6
FDFCT Compensation
0.1µ

FGD
4 50k FE_M 100k
7
680k
40k 11µ 22µ
0.1µ
ISET 60k
17
50k FS1
FS2 Charge
FLB FSET up
SRCH
5 11 8

0.015µ
0.1µ 510k 4.7µ

The above figure shows a block diagram of the focus servo.

Ordinarily the FE signal is input to the focus phase compensation circuit through a 68kΩ resistance; however,
when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the internal
100kΩ resistance and the capacitance connected to Pin 3. When this DFCT prevention circuit is not used,
leave Pin 3 open. The defect switch operation can be enabled and disabled with command.

The capacitor connected between Pin 5 and GND is a time constant to boost the low frequency in the normal
playback state.
The peak frequency of the focus phase compensation is approximately 1.2kHz when a resistance of 510kΩ is
connected to Pin 11.
The focus search height is approximately ±1.1Vp-p when using the constants indicated in the above figure.
This height is inversely proportional to the resistance connected between Pin 17 and VEE. However, changing
this resistance also changes the height of the track jump and sled kick as well.
The FZC comparator inverted input is set to 15% of Vcc and VC (Pin 51); (Vcc – VC) × 15%.
∗ 510kΩ resistance is recommended for Pin 11.

– 23 –
 CXA1992AR

Tracking and Sled Servo

TE TGH
+ GAIN 26 SENS2
SENS
45 WINDOW TGL
TEO SELECTOR
– COMPARATOR 25 SENS1

BUFFER AMP BALH

100k 150k BALANCE
46 WINDOW 47k
LPFI COMPARATOR BALL
0.01µ

0.01µ

SLED ON/OFF 19 LOCK

CONTROL

SLED MOTOR
SL_O
16 M
TEI DFCT

0.015µ
47 TM1 TG1

120k
680k

100k SL_M
680k 15
TDFCT 100k 66p TM6 22µA
50 8.2k
0.1µ

TM5 TM2 SL_P

22µA 14
0.047µ 47k 1k
ATSC
3.3µ
48
470p

ATSC
330k

1k

82k 22µ
100k TM4 11µA
0.022µ TZC TA_M 100k 15k
49 12
TM3
TZC 11µA
20k 10k 90k TRACKING
TGU Tracking Phase COIL
9 TA_O
0.033µ Compensation 13
TG2 TG2
10 TM7
470k
FSET
11

510k

0.015µ

The above figure shows a block diagram of the tracking and sled servo.
The capacitor connected between Pins 9 and 10 is a time constant to cut the high-frequency gain when TG2 is
OFF. The peak frequency of the tracking phase compensation is approximately 1.2kHz when a 510kΩ
resistance is connected to Pin 11. In the CXA1992AR, TG1 and TG2 are inter-linked switches.
To jump tracks in FWD and REV directions, turn TM3 or TM4 ON. During this time, the peak voltage applied to
the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin 12. To be
more specific,
Track jump peak voltage = TM3 (or TM4) current × feedback resistance value
The FWD and REV sled kick is performed by turning TM5 or TM6 ON. During this time, the peak voltage
applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 15;
Sled kick peak voltage = TM5 (or TM6) current × feedback resistance
The values of the current for each switch are determined by the resistance connected between Pin 17 and VEE.
When this resistance is 60kΩ :
TM3 (or TM4) = ±11µA, and TM5 (or TM6) = ±22µA.
As is the case with the FE signal, the TE signal is switched to pass through a low-pass filter formed by the
internal resistance (100kΩ) and the capacitance connected to Pin 50.

– 24 –
 CXA1992AR

The ISET pin is used to connect external resistance. This external resistance sets the current which
determines the focus search, track jump, and sled kick heights.

• Focus search current

VBG 1
I1 = ×
R 2
I1 I2 (VBG: approximately 1.27V)
I2 = 2I1
FS1

• Track jump current (TM3 and TM4 current)

VBG 1
I= ×
R 2

• Sled kick current (TM5 and TM6 current, when D1 = D0 = 0 during 1X$ commands)

VBG
I=
R

Use external resistance of between 30kΩ to 240kΩ.

Using external resistance outside this range may cause oscillation.

– 25 –
 CXA1992AR

Focus OK Circuit

RF VCC

RF_O 20k
33 54k
C5 ×1
0.01µ 27 FOK
32 VG
RF_I

15k 92k

0.63V

FOCUS OK AMP FOCUS OK

COMPARATOR

The focus OK circuit creates the timing window okaying the focus servo from the focus search state.
The HPF output is obtained at Pin 32 from Pin 33 (RF signal), and the LPF output (opposite phase) of the
focus OK amplifier output is also obtained.
The focus OK output is inverted when VRFI – VRFO ≈ –0.37V.
Note that, C5 determines the time constant of the HPF for the mirror circuit and the LPF of the focus OK
amplifier. Ordinarily, with a C5 equal to 0.01µF selected, the fc is equal to 1kHz, and block error rate
degradation brought about by RF envelope defects caused by scratched discs can be prevented.

Defect Circuit
After the RFI signal is reverted, two time constants, long and short, are held at bottom. The short time constant
bottom hold responds to 0.1ms or greater disc mirror defects, and the long time constant bottom hold holds the
pre-defect mirror level. By differentiating and level-shifting these constants with capacitor coupling and
comparing both signals, the mirror defect detection signal is generated.
0.033µ
CC1 CC2
29 28

FLIP DFCT2
FLOP
26 SENS2
a
RF_O 33 b c
×2 e SENS
SELECTOR 25 SENS1
DEFECT AMP d DFCT1
DEFECT SW

DEFECT BOTTOM DEFECT COMPARATOR

30 HOLD
CB
0.01µ

a RFO

b DEFECT
AMP

BOTTOM
c HOLD (1) d BOTTOM
solid line HOLD (2)
CC1 dotted line
CC2
H
e DFCT1
L

– 26 –
 CXA1992AR

Mirror Circuit
The mirror circuit performs peak and bottom hold after the RFI signal has been amplified.
The peak and bottom holds are both held through the use of a time constant. For the peak hold, a time
constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the rotation cycle envelope
fluctuation.

RF_O
33 RF MIRROR HOLD AMP
0.033µ
31
H CP
32 PEAK &
× 1.4 BOTTOM ×1
RF_I
G HOLD I J
K
MIRROR AMP MIRR
SENS
SELECTOR 26 SENS2

MIRROR
COMPARATOR

RF_O

0V

G
(RF_I) 0V

H
(PEAK HOLD) 0V

I
(BOTTOM HOLD) 0V

J
K
(MIRROR HOLD)

H
MIRR
L

The DC playback envelope signal J is obtained by amplifying the difference between the peak and bottom hold
signals H and I. Signal J has a large time constant of 2/3 its peak value, and the mirror output is obtained by
comparing it to the peak hold signal K. Accordingly, when on the disc track, the mirror output is Low; when
between tracks (mirrored portion), it is High; and when a defect is detected, it is High. The mirror hold time
constant must be sufficiently large compared with the traverse signal.
In the CXA1992AR, this mirror output is used only during braking operations, and no external output pin is
attached. Accordingly, when connecting DSP with MIRR input pin, input the C.OUT output to the MIRR input of
the DSP.

– 27 –
 CXA1992AR

SENS Selector

FZC HIGH-Z

DFCT1 DFCT2

TZC MIRR

BALH BALL
25 SENS1 26 SENS2
TGH TGL

FOH FOL

ATSC

What is output to the SENS1 and SENS2 pins varies according to the address input to the DATA pin.

DATA (Pin 22) 8-bit transfer

ADDRESS DATA SENS1 SENS2
D7 D6 D5 D4 D3 D2 D1 D0
H
0 0 0 0 X X X X FZC
(HIGH-Z)
0 0 0 1 X X X X DFCT1 DFCT2
0 0 1 0 X X X X TZC MIRR
0 1 0 0 X X X X H H
1 1 1 1 X X X X (HIGH-Z) (HIGH-Z)

DATA (Pin 22) 12-bit transfer

ADDRESS DATA SENS1 SENS2
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 1 0 0 X X X X X X BALH BALL
0 0 1 1 0 1 X X X X X X TGH TGL
0 0 1 1 1 0 X X X X X X FOH FOL
H
0 0 1 1 1 1 X X X X X X ATSC
(HIGH-Z)

Notes)
• 12-bit transfer should be performed during $3XX commands. When 8 bits are transferred, SENS1 and
SENS2 are switched according to the D3 and D2 data.
• SENS1 and SENS2 are switched without latching.

– 28 –
 CXA1992AR

Commands
The input data to operate this IC is configured as 8-bit/12-bit data; however, below, this input data is
represented by 2-digit hexadecimal numerals in the form $XX, where X is a hexadecimal numeral between 0
and F/$XXX for 12-bit.
Commands for the CXA1992AR can be broadly divided into four groups ranging in value from $0X, $1X, $2X,
$3XX.

1. $0X (FZC at SENS1 pin (Pin 25), H (Hi-Z) at SENS2 pin (Pin 26))

These commands are related to focus servo control.

The bit configuration is as shown below.

D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 FS4 — FS2 FS1

Four focus related switches exist: FS1, FS2, FS4 and DFCT.

$00 When FS1 = 0, Pin 8 is charged to (22µA – 11µA) × 50kΩ = 0.55V.

If, in addition, FS2 = 0, this voltage is no longer transferred, and the output at Pin 6 becomes 0V.
$02 From the state described above, the only FS2 becomes 1. When this occurs, a negative signal is output
to Pin 6. This voltage level is obtained by equation 1 below.

resistance between Pins 6 and 7

(22µA – 11µA) × 50kΩ × .... Equation 1
50kΩ

The SRCH DOWN speed can be increased by the charge up circuit.

$03 From the state described above, FS1 becomes 1, and a current source of +22µA is split off.
Then, a CR charge/discharge circuit is formed, and the voltage at Pin 8 decreases with the time as
shown in Fig. 1 below.

0V

Fig. 1. Voltage at Pin 8 when FS1 goes from 0 → 1

This time constant is obtained with the 50kΩ resistance and an external capacitor.

By alternating the commands between $02 and $03, the focus search voltage can be constructed. (Fig. 2)

0V

$ 00 02 03 02 03 02 00

Fig. 2. Constructing the search voltage by alternating between $02 and $03. (Voltage at Pin 6)

– 29 –
 CXA1992AR

1-1. FS4
This switch is provided between the focus error input and the focus phase compensation, and is in charge of
turning the focus servo ON and OFF.

$00 → $08
Focus off Focus on

1-2. Procedure of focus activation

For description, suppose that the polarity is as described below.
a) The lens is searching the disc from far to near;
b) The output voltage (Pin 6) is changing from negative to positive; and
c) The focus S-curve is varying as shown below.

Fig. 3. S-curve

The focus servo is activated at the operating point indicated by A in Fig. 3. Ordinarily, focus searching and the
turning the focus servo switch ON are performed during the focus S-curve transits the point A indicated in Fig.
3. To prevent misoperation, this signal is ANDed with the focus OK signal.
In this IC, FZC (Focus Zero Cross) signal is output from the SENS1 pin (Pin 25) as the point A transit signal.
In addition, focus OK is output as a signal indicating that the signal is in focus (can be in focus in this case).
Following the line of the above description, focusing can be well obtained by observing the following timing
chart.
(20ms) (200ms)
$02
($00) $03 $08

Drive voltage

∗ The broken lines in the figure

Focus error indicate the voltage assuming
the signal is not in focus.

SENS1
(FZC)

The instant when the signal is brought into focus.

Focus OK

Fig. 4. Focus ON timing chart

– 30 –
 CXA1992AR

Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be
minimized. To do this, the software sequence shown in B is better than the sequence shown in A.

FZC ↓ ? Transfer $08

NO
YES

F. OK ? F. OK ?
NO NO
YES YES

Transfer $08 FZC ↓ ?

NO
YES

Latch Latch

(A) (B)

Fig. 5. Poor and good software command sequences

2. $1X (DFCT1 at SENS1 pin (Pin 25), DFCT2 at SENS2 pin (Pin 26))

These commands deal with switching TG1/TG2, brake circuit ON/OFF,

and the sled kick output.
Sled kick height

Relative
The bit configuration is as follows:

value
D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 (PS1) (PS0)
0 0 ±1
0 0 0 1 TG1, TG2 Break Sled kick 0 1 ±2
circuit height 1 0 ±3
ON/OFF ON/OFF 1 1 ±4

TG1, TG2, TM7

The purpose of TG1 and TG2 is to switch the tracking servo gain Up/Normal. TG1 and TG2 are interlinked
switches. The brake circuit (TM7) is to prevent the frequently occurred phenomena where the merely 10-track
jump has been performed actually though a 100-track jump was intended to be done due to the extremely
degraded actuator settling caused by the servo motor exceeding the linear range after a 100 or 10-track jump.
For the prevention method, when the actuator travels radially; that is, when it traverses from the inner track to
the outer track of the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between
the RF envelope and the tracking error is 180° out-of-phase to cut the unneeded portion of the tracking error
and apply braking.

– 31 –
 CXA1992AR

[∗A] [∗B] D2
Envelope Waveform (MIRR)
[∗G]
RF_I 32
Detection Shaping [∗C] TM7
D Q Low: open
[∗D] [∗E]
BRK
[∗F] High: make
CK
[∗H]
TZC 49 Waveform Edge Detection
Shaping (Latch)

CXA1992

Fig. 6. TM7 movement during braking operation

From inner to outer track From outer to inner track

[∗A]

[∗B]

[∗C] ("MIRR")

[∗D]
("TZC")
[∗E]

[∗F]

[∗G]

Braking is applied
[∗H] 0V from here.

Fig. 7. Internal waveform

3. $2X (TZC at SENS1 pin (Pin 25), MIRR at SENS2 pin (Pin 26))

These commands deal with turning the tracking servo and sled servo ON/OFF, and creating the jump pulse
and fast forward pulse during access operations.

D7 D6 D5 D4 D3 D2 D1 D0

0 0 1 0 Tracking Sled
control control
00 off 00 off
01 Servo ON 01 Servo ON
10 F-JUMP 10 F-FAST FORWARD
11 R-JUMP 11 R-FAST FORWARD
↓ ↓
TM1, TM3, TM4, TM2, TM5, TM6

– 32 –
 CXA1992AR

4. $3XX

These commands mainly control the balance and gain control circuit switches used during automatic tracking
adjustment and the bias circuit switch used during automatic focus bias adjustment.
In the initial resetting state, BAL1 to BAL4 switches and TOG1 to TOG4 switches are ON. Also, the IFB1 to 6
switches are ON.

• Balance adjustment
The balance adjustment switches BAL1 to BAL4 can be controlled by setting D6 = 0 and D7 = 0. The switches
are set using D0 to D3.
At this time, SENS1 outputs BALH and SENS2 outputs BALL.
Data is set by specifying switch conditions D0 to D3 and sending a latch pulse with D6 = 0 and D7 = 0.
Sending a latch pulse with D6, D7 ≈ 0 does not change the balance switch settings.

START

C.OUT
is the frequency high
BAL1 to BAL4 enough ?
Switch Control NO
YES

SENS1/2
Balance OK ?

Adjustment Completed

Balance adjustment

• Gain adjustment
The gain adjustment switches TOG1 to TOG4 can be controlled by setting D6 = 1 and D7 = 0. These switches
are set using D0 to D3.
At this time, SENS1 outputs TGH and SENS2 outputs TGL.
In a fashion similar to the method used with the balance adjustment, set the data by specifying switch
conditions D0 to D3 and sending a latch pulse with D6 = 1 and D7 = 0.

START

TOG1 to TOG4
Switch control
SENS1/2
GAIN OK ?
NO
YES

Adjustment Completed

Gain adjustment

– 33 –
 CXA1992AR

• Focus bias adjustment

The focus bias adjustment switches IFB1 to 6 can be controlled by setting D6 = 0 and D7 = 1. The switches
are set using D0 to D5.
At this time, SENS1 outputs FOH and SENS2 outputs FOL.
Data is set by specifying switch conditions D0 to D5 and sending a latch pulse with D6 = 0 and D7 = 1.

START

IFB1 to 6
Switch Control

SENS1/2
BIAS OK ?
NO
YES

Adjustment Completed

Focus bias adjustment method

• TGFL
The tracking gain can be switched by setting D5 with D6 = 1 and D7 = 0.
The tracking gain is GAIN UP with D5 = 1 and NORMAL GAIN with D5 = 0.
The TEO signal level can be made higher by approximately 6dB for GAIN UP.
When the TEO signal level is low and TGH (SENS1 pin) does not go Low during tracking adjustment, the
gain should be raised with the TGFL command for adjustment.

• LPC
The laser power control circuit can be turned ON and OFF by setting D0 with D6 = 1 and D7 = 1.
The circuit is ON with D0 = 1 and OFF with D0 = 0.

• LPCL
The laser power control limit can be switched between ±17% and ±50% by setting D1 with D6 = 1 and D7 = 1.
The control limit is ±17% with D1 = 0 and ±50% with D1 = 1.

• LDON
The laser diode can be turned ON and OFF by setting D2 with D6 = 1 and D7 = 1.
The laser diode is ON with D2 = 1 and OFF with D2 = 0.

– 34 –
 CXA1992AR

• ATSC
The anti-shock function can be controlled by setting D3 with D6 = 1 and D7 = 1.
This function is disabled with D3 = 1 and enabled with D3 = 0.
At this time, SENS1 outputs ATSC.
Even if ATSC is disabled, ATSC is output to SENS1.
When an anti-shock signal is generated during the enable status, TG1 and TG2 switch to GAIN UP mode.
(In the Block Diagram, TG1 is set to the side and TG2 is OFF. Even if TG1 and TG2 are NORMAL mode,
they switch to GAIN UP mode in conjunction with ATSC.)
When the anti-shock function is not used, Pin 48 (ATSC) should be connected to VC.

• RDFCT2
DFCT2 can be reset by setting D4 with D6 = 1 and D7 = 1.
DFCT2 is reset with D4 = 1.
After a reset, High is held when DFCT1 rises.
During $1X commands, DFCT2 is output from SENS2.
DFCT2 operates even if DFCT is disabled.
Whether or not DFCT rises at the proper timing for the microcomputer can also be confirmed.

• INT
The interruption (scratched disc) countermeasure circuit can be set to operating status by setting D5 with D6
= 1 and D7 = 1.
This circuit is enabled when D5 = 1 and disabled when D5 = 0.
Even if DFCT1 does not rise, this circuit is effective for scratched discs which cause MIRR to rise.
When MIRR rises, the DFCT switch is routed through the low-pass filter.
The interruption countermeasure circuit is forcibly turned OFF regardless of the command when the tracking
gain is increased. (including when the gain is increased by ATSC or LOCK)
Even if DFCT is disabled, the interruption countermeasure circuit operates when INT is enabled.

Parallel direct interface

• LOCK (Sled overrun prevention circuit)
This circuit operates when LOCK is low.
When LOCK is low, the sled is OFF, and TG1 and TG2 are UP (TRACKING GAIN UP).

LOCK

SLED TM2 SW: side

SLED ON
TM2 SW: side
SLED OFF

TRACKING GAIN UP
TG1 SW: side
TG2 OFF
NORMAL
TG1 SW: side
TG2 ON

When LOCK is not used, Pin 19 (LOCK) should be pulled up to VCC with the resistor of approximately 47kΩ.

– 35 –
 CXA1992AR

CPU Serial Interface Timing Chart

DATA D0 D1 D2 D3 D4 D5 D6 D7 D0
tWCK tWCK tSU th

CLK
1/fck tCD

tD
XLT
tWL

(VCC = 3.0V)
Item Symbol Min. Typ. Max. Unit
Clock frequency fck 1 MHz
Clock pulse width fwck 500 ns
Setup time tsu 500 ns
Hold time th 500 ns
Delay time tD 500 ns
Latch pulse width tWL 1000 ns
Data transfer interval tCD 1000 ns
Low level input voltage VIL 0.0 (VCC – VEE) × 0.1 V
High level input voltage VIH (VCC – VEE) × 0.9 VCC V

– 36 –
 System Control

DATA (Pin 22) 8-bit transfer

Item ADDRESS DATA SENS1 SENS2
D7 D6 D5 D4 D3 D2 D1 D0
FS4 FS2 FS2
FOCUS Focus SRCH ON SRCH UP H
0 0 0 0 — FZC
CONTROL 1 = ON 1 = ON 1 = UP (HIGH-Z)
0 = OFF 0 = OFF 0 = DOWN
TG1, TG2 BRAKE SLED SLED
TRACKING KICK + 2 KICK + 1
0 0 0 1 DFCT1 DFCT2
CONTROL 1 = GAIN UP 1 = ENABLE
0 = NORMAL 0 = DISABLE
TRACKING
0 0 1 0 TRACKING MODE ∗1 SLED MODE ∗2 TZC MIRR
SLED MODE

– 37 –
∗1 TRACKING MODE ∗2 SLED MODE

D3 D2 D1 D0
OFF 0 0 OFF 0 0
ON 0 1 ON 0 1
FWD JUMP 1 0 FWD MOVE 1 0
REV JUMP 1 1 REV MOVE 1 1
CXA1992AR
 DATA (Pin 22) 12-bit transfer
Item ADDRESS DATA SENS1 SENS2
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DFCT BAL4 BAL3 BAL2 BAL1
E-F
0 0 1 1 0 0 — BALH BALL
BALANCE 1 = DISABLE 1 = OFF 1 = OFF 1 = OFF 1 = OFF
0 = ENABLE 0 = ON 0 = ON 0 = ON 0 = ON
TGFL TOG4 TOG3 TOG2 TOG1
TRACKING
0 0 1 1 0 1 — TGH TGL
GAIN 1 = GAIN UP 1 = OFF 1 = OFF 1 = OFF 1 = OFF
0 = NORMAL 0 = ON 0 = ON 0 = ON 0 = ON
IFB6 IFB5 IFB4 IFB3 IFB2 IFB1
FOCUS
0 0 1 1 1 0 FOH FOL
BIAS 1 = OFF 1 = OFF 1 = OFF 1 = OFF 1 = OFF 1 = OFF
0 = ON 0 = ON 0 = ON 0 = ON 0 = ON 0 = ON
INT RDFCT2 ATSC LDON LPCL LPC
H
Others 0 0 1 1 1 1 ATSC
1 = ENABLE 1 = RESET 1 = DISABLE 1 = ON 1 = ±50% 1 = ON (HIGH-Z)

– 38 –
0 = DISABLE 0 = NORMAL 0 = ENABLE 0 = OFF 0 = ±17% 0 = OFF

Notes)
• When ATSC is enabled, even if TG1 and TG2 are NORMAL mode, TG1 and TG2 switch to GAIN UP mode in conjunction with ATSC and LOCK.
• INT is forcibly disabled regardless of the command when the tracking gain is increased. (including when the gain is increased by ATSC or LOCK)
When reset
• SENS1 = FZC
• SENS2 = High (Hi-Z)
• RDFCT2 = 1 (Reset)
• IFB1 to IFB6 = 0 (switch ON)
• TOG1 to TOG4 = 0 (switch ON)
• BAL1 to BAL4 = 1 (switch ON)
• Other data is "0".
CXA1992AR
 CXA1992AR

Serial Data Truth Table

Serial Data HEX Functions

FOCUS CONTROL FS4 FS2 FS1
0000 0000 $00 0 0 0 Notes) • FS1
0000 0001 $01 0 0 1 1: OFF
0000 0010 $02 0 1 0 0: ON
0000 0011 $03 0 1 1
0000 0100 $04 0 0 0
0000 0101 $05 0 0 1 • FS2
0000 0110 $06 0 1 0 1: ON
0000 0111 $07 0 1 1 0: OFF
0000 1000 $08 1 0 0
0000 1001 $09 1 0 1
0000 1010 $0A 1 1 0 • FS4
0000 1011 $0B 1 1 1 In the Block Diagram:
0000 1100 $0C 1 0 0 1:SW side
0000 1101 $0D 1 0 1
0000 1110 $0E 1 1 0 0:SW side
0000 1111 $0F 1 1 1
BRAK SLD KICK
TG1 Fig. 6 KICK KICK
TRACKING CONTROL
TG2 D2 +2 +1
0001 0000 $10 0 0 0 0 Notes) • TG1
0001 0001 $11 0 0 0 1 In the Block Diagram:
0001 0010 $12 0 0 1 0 1:SW side
0001 0011 $13 0 0 1 1 0:SW side
0001 0100 $14 0 1 0 0
0001 0101 $15 0 1 0 1
0001 0110 $16 0 1 1 0 • TG2
0001 0111 $17 0 1 1 1 1: OFF
0001 1000 $18 1 0 0 0 0: ON
0001 1001 $19 1 0 0 1
0001 1010 $1A 1 0 1 0
0001 1011 $1B 1 0 1 1 • BRAKE
0001 1100 $1C 1 1 0 0 When D2 in Fig. 6 is:
0001 1101 $1D 1 1 0 1 1: 1
0001 1110 $1E 1 1 1 0
0001 1111 $1F 1 1 1 1 0: 0

• Sled kick height

D1 D0 Relative value
0 0 ±1
0 1 ±2
1 0 ±3
1 1 ±4

– 39 –
 CXA1992AR

Serial Data HEX Function

TRACKING/SLED MODE TM6 TM5 TM4 TM3 TM2 TM1
0010 0000 $20 0 0 0 0 0 0 Notes) • TM1/TM2
0010 0001 $21 0 0 0 0 1 0 In the Block Diagram:
0010 0010 $22 0 1 0 0 0 0 1:SW side
0010 0011 $23 1 0 0 0 0 0
0010 0100 $24 0 0 0 0 0 1 0:SW side
0010 0101 $25 0 0 0 0 1 1
0010 0110 $26 0 1 0 0 0 1 • TM3/TM4/TM5/TM6
0010 0111 $27 1 0 0 0 0 1 1: ON
0010 1000 $28 0 0 0 1 0 0
0010 1001 $29 0 0 0 1 1 0 0: OFF
0010 1010 $2A 0 1 0 1 0 0
0010 1011 $2B 1 0 0 1 0 0
0010 1100 $2C 0 0 1 0 0 0
0010 1101 $2D 0 0 1 0 1 0
0010 1110 $2E 0 1 1 0 0 0
0010 1111 $2F 1 0 1 0 0 0

– 40 –
 CXA1992AR

Serial Data HEX BAL SW TOG SW IFB SW RDF

TGFL INT ATSC LDON LPCL LPC DFCT
$3XX 4 3 2 1 4 3 2 1 6 5 4 3 2 1 CT2

0011 0000 0000 $300 1 1 1 1 ———— — —————— — — — — — — E

0011 0000 0001 $301 1 1 1 0 ———— — —————— — — — — — — E
0011 0000 0010 $302 1 1 0 1 ———— — —————— — — — — — — E
0011 0000 0011 $303 1 1 0 0 ———— — —————— — — — — — — E
0011 0000 0100 $304 1 0 1 1 ———— — —————— — — — — — — E
0011 0000 0101 $305 1 0 1 0 ———— — —————— — — — — — — E
0011 0000 0110 $306 1 0 0 1 ———— — —————— — — — — — — E
0011 0000 0111 $307 1 0 0 0 ———— — —————— — — — — — — E
0011 0000 1000 $308 0 1 1 1 ———— — —————— — — — — — — E
0011 0000 1001 $309 0 1 1 0 ———— — —————— — — — — — — E
0011 0000 1010 $30A 0 1 0 1 ———— — —————— — — — — — — E
0011 0000 1011 $30B 0 1 0 0 ———— — —————— — — — — — — E
0011 0000 1100 $30C 0 0 1 1 ———— — —————— — — — — — — E
0011 0000 1101 $30D 0 0 1 0 ———— — —————— — — — — — — E
0011 0000 1110 $30E 0 0 0 1 ———— — —————— — — — — — — E
0011 0000 1111 $30F 0 0 0 0 ———— — —————— — — — — — — E
0011 0001 0000 $310 1 1 1 1 ———— — —————— — — — — — — E
0011 0001 0001 $311 1 1 1 0 ———— — —————— — — — — — — E
0011 0001 0010 $312 1 1 0 1 ———— — —————— — — — — — — E
0011 0001 0011 $313 1 1 0 0 ———— — —————— — — — — — — E
0011 0001 0100 $314 1 0 1 1 ———— — —————— — — — — — — E
0011 0001 0101 $315 1 0 1 0 ———— — —————— — — — — — — E
0011 0001 0110 $316 1 0 0 1 ———— — —————— — — — — — — E
0011 0001 0111 $317 1 0 0 0 ———— — —————— — — — — — — E
0011 0001 1000 $318 0 1 1 1 ———— — —————— — — — — — — E
0011 0001 1001 $319 0 1 1 0 ———— — —————— — — — — — — E
0011 0001 1010 $31A 0 1 0 1 ———— — —————— — — — — — — E
0011 0001 1011 $31B 0 1 0 0 ———— — —————— — — — — — — E
0011 0001 1100 $31C 0 0 1 1 ———— — —————— — — — — — — E
0011 0001 1101 $31D 0 0 1 0 ———— — —————— — — — — — — E
0011 0001 1110 $31E 0 0 0 1 ———— — —————— — — — — — — E
0011 0001 1111 $31F 0 0 0 0 ———— — —————— — — — — — — E
0011 0010 0000 $320 1 1 1 1 ———— — —————— — — — — — — D
0011 0010 0001 $321 1 1 1 0 ———— — —————— — — — — — — D
0011 0010 0010 $322 1 1 0 1 ———— — —————— — — — — — — D
0011 0010 0011 $323 1 1 0 0 ———— — —————— — — — — — — D
0011 0010 0100 $324 1 0 1 1 ———— — —————— — — — — — — D
0011 0010 0101 $325 1 0 1 0 ———— — —————— — — — — — — D
0011 0010 0110 $326 1 0 0 1 ———— — —————— — — — — — — D
0011 0010 0111 $327 1 0 0 0 ———— — —————— — — — — — — D
0011 0010 1000 $328 0 1 1 1 ———— — —————— — — — — — — D
0011 0010 1001 $329 0 1 1 0 ———— — —————— — — — — — — D
0011 0010 1010 $32A 0 1 0 1 ———— — —————— — — — — — — D
0011 0010 1011 $32B 0 1 0 0 ———— — —————— — — — — — — D
0011 0010 1100 $32C 0 0 1 1 ———— — —————— — — — — — — D
0011 0010 1101 $32D 0 0 1 0 ———— — —————— — — — — — — D
0011 0010 1110 $32E 0 0 0 1 ———— — —————— — — — — — — D
0011 0010 1111 $32F 0 0 0 0 ———— — —————— — — — — — — D

– 41 –
 CXA1992AR

Serial Data HEX BAL SW TOG SW IFB SW RDF

TGFL INT ATSC LDON LPCL LPC DFCT
$3XX 4 3 2 1 4 3 2 1 6 5 4 3 2 1 CT2

0011 0011 0000 $330 1 1 1 1 ———— — —————— — — — — — — D

0011 0011 0001 $331 1 1 1 0 ———— — —————— — — — — — — D
0011 0011 0010 $332 1 1 0 1 ———— — —————— — — — — — — D
0011 0011 0011 $333 1 1 0 0 ———— — —————— — — — — — — D
0011 0011 0100 $334 1 0 1 1 ———— — —————— — — — — — — D
0011 0011 0101 $335 1 0 1 0 ———— — —————— — — — — — — D
0011 0011 0110 $336 1 0 0 1 ———— — —————— — — — — — — D
0011 0011 0111 $337 1 0 0 0 ———— — —————— — — — — — — D
0011 0011 1000 $338 0 1 1 1 ———— — —————— — — — — — — D
0011 0011 1001 $339 0 1 1 0 ———— — —————— — — — — — — D
0011 0011 1010 $33A 0 1 0 1 ———— — —————— — — — — — — D
0011 0011 1011 $33B 0 1 0 0 ———— — —————— — — — — — — D
0011 0011 1100 $33C 0 0 1 1 ———— — —————— — — — — — — D
0011 0011 1101 $33D 0 0 1 0 ———— — —————— — — — — — — D
0011 0011 1110 $33E 0 0 0 1 ———— — —————— — — — — — — D
0011 0011 1111 $33F 0 0 0 0 ———— — —————— — — — — — — D
0011 0100 0000 $340 ———— 1 1 1 1 0 —————— — — — — — — —
0011 0100 0001 $341 ———— 1 1 1 0 0 —————— — — — — — — —
0011 0100 0010 $342 ———— 1 1 0 1 0 —————— — — — — — — —
0011 0100 0011 $343 ———— 1 1 0 0 0 —————— — — — — — — —
0011 0100 0100 $344 ———— 1 0 1 1 0 —————— — — — — — — —
0011 0100 0101 $345 ———— 1 0 1 0 0 —————— — — — — — — —
0011 0100 0110 $346 ———— 1 0 0 1 0 —————— — — — — — — —
0011 0100 0111 $347 ———— 1 0 0 0 0 —————— — — — — — — —
0011 0100 1000 $348 ———— 0 1 1 1 0 —————— — — — — — — —
0011 0100 1001 $349 ———— 0 1 1 0 0 —————— — — — — — — —
0011 0100 1010 $34A ———— 0 1 0 1 0 —————— — — — — — — —
0011 0100 1011 $34B ———— 0 1 0 0 0 —————— — — — — — — —
0011 0100 1100 $34C ———— 0 0 1 1 0 —————— — — — — — — —
0011 0100 1101 $34D ———— 0 0 1 0 0 —————— — — — — — — —
0011 0100 1110 $34E ———— 0 0 0 1 0 —————— — — — — — — —
0011 0100 1111 $34F ———— 0 0 0 0 0 —————— — — — — — — —
0011 0101 0000 $350 ———— 1 1 1 1 0 —————— — — — — — — —
0011 0101 0001 $351 ———— 1 1 1 0 0 —————— — — — — — — —
0011 0101 0010 $352 ———— 1 1 0 1 0 —————— — — — — — — —
0011 0101 0011 $353 ———— 1 1 0 0 0 —————— — — — — — — —
0011 0101 0100 $354 ———— 1 0 1 1 0 —————— — — — — — — —
0011 0101 0101 $355 ———— 1 0 1 0 0 —————— — — — — — — —
0011 0101 0110 $356 ———— 1 0 0 1 0 —————— — — — — — — —
0011 0101 0111 $357 ———— 1 0 0 0 0 —————— — — — — — — —
0011 0101 1000 $358 ———— 0 1 1 1 0 —————— — — — — — — —
0011 0101 1001 $359 ———— 0 1 1 0 0 —————— — — — — — — —
0011 0101 1010 $35A ———— 0 1 0 1 0 —————— — — — — — — —
0011 0101 1011 $35B ———— 0 1 0 0 0 —————— — — — — — — —
0011 0101 1100 $35C ———— 0 0 1 1 0 —————— — — — — — — —
0011 0101 1101 $35D ———— 0 0 1 0 0 —————— — — — — — — —
0011 0101 1110 $35E ———— 0 0 0 1 0 —————— — — — — — — —
0011 0101 1111 $35F ———— 0 0 0 0 0 —————— — — — — — — —

– 42 –
 CXA1992AR

Serial Data HEX BAL SW TOG SW IFB SW RDF

TGFL INT ATSC LDON LPCL LPC DFCT
$3XX 4 3 2 1 4 3 2 1 6 5 4 3 2 1 CT2

0011 0110 0000 $360 ———— 1 1 1 1 1 —————— — — — — — — —

0011 0110 0001 $361 ———— 1 1 1 0 1 —————— — — — — — — —
0011 0110 0010 $362 ———— 1 1 0 1 1 —————— — — — — — — —
0011 0110 0011 $363 ———— 1 1 0 0 1 —————— — — — — — — —
0011 0110 0100 $364 ———— 1 0 1 1 1 —————— — — — — — — —
0011 0110 0101 $365 ———— 1 0 1 0 1 —————— — — — — — — —
0011 0110 0110 $366 ———— 1 0 0 1 1 —————— — — — — — — —
0011 0110 0111 $367 ———— 1 0 0 0 1 —————— — — — — — — —
0011 0110 1000 $368 ———— 0 1 1 1 1 —————— — — — — — — —
0011 0110 1001 $369 ———— 0 1 1 0 1 —————— — — — — — — —
0011 0110 1010 $36A ———— 0 1 0 1 1 —————— — — — — — — —
0011 0110 1011 $36B ———— 0 1 0 0 1 —————— — — — — — — —
0011 0110 1100 $36C ———— 0 0 1 1 1 —————— — — — — — — —
0011 0110 1101 $36D ———— 0 0 1 0 1 —————— — — — — — — —
0011 0110 1110 $36E ———— 0 0 0 1 1 —————— — — — — — — —
0011 0110 1111 $36F ———— 0 0 0 0 1 —————— — — — — — — —
0011 0111 0000 $370 ———— 1 1 1 1 1 —————— — — — — — — —
0011 0111 0001 $371 ———— 1 1 1 0 1 —————— — — — — — — —
0011 0111 0010 $372 ———— 1 1 0 1 1 —————— — — — — — — —
0011 0111 0011 $373 ———— 1 1 0 0 1 —————— — — — — — — —
0011 0111 0100 $374 ———— 1 0 1 1 1 —————— — — — — — — —
0011 0111 0101 $375 ———— 1 0 1 0 1 —————— — — — — — — —
0011 0111 0110 $376 ———— 1 0 0 1 1 —————— — — — — — — —
0011 0111 0111 $377 ———— 1 0 0 0 1 —————— — — — — — — —
0011 0111 1000 $378 ———— 0 1 1 1 1 —————— — — — — — — —
0011 0111 1001 $379 ———— 0 1 1 0 1 —————— — — — — — — —
0011 0111 1010 $37A ———— 0 1 0 1 1 —————— — — — — — — —
0011 0111 1011 $37B ———— 0 1 0 0 1 —————— — — — — — — —
0011 0111 1100 $37C ———— 0 0 1 1 1 —————— — — — — — — —
0011 0111 1101 $37D ———— 0 0 1 0 1 —————— — — — — — — —
0011 0111 1110 $37E ———— 0 0 0 1 1 —————— — — — — — — —
0011 0111 1111 $37F ———— 0 0 0 0 1 —————— — — — — — — —
0011 1000 0000 $380 — — — —— — — — — 1 1 1 1 1 1 — — — — — — —
0011 1000 0001 $381 — — — —— — — — — 1 1 1 1 1 0 — — — — — — —
0011 1000 0010 $382 — — — —— — — — — 1 1 1 1 0 1 — — — — — — —
0011 1000 0011 $383 — — — —— — — — — 1 1 1 1 0 0 — — — — — — —
0011 1000 0100 $384 — — — —— — — — — 1 1 1 0 1 1 — — — — — — —
0011 1000 0101 $385 — — — —— — — — — 1 1 1 0 1 0 — — — — — — —
0011 1000 0110 $386 — — — —— — — — — 1 1 1 0 0 1 — — — — — — —
0011 1000 0111 $387 — — — —— — — — — 1 1 1 0 0 0 — — — — — — —
0011 1000 1000 $388 — — — —— — — — — 1 1 0 1 1 1 — — — — — — —
0011 1000 1001 $389 — — — —— — — — — 1 1 0 1 1 0 — — — — — — —
0011 1000 1010 $38A — — — —— — — — — 1 1 0 1 0 1 — — — — — — —
0011 1000 1011 $38B — — — —— — — — — 1 1 0 1 0 0 — — — — — — —
0011 1000 1100 $38C — — — —— — — — — 1 1 0 0 1 1 — — — — — — —
0011 1000 1101 $38D — — — —— — — — — 1 1 0 0 1 0 — — — — — — —
0011 1000 1110 $38E — — — —— — — — — 1 1 0 0 0 1 — — — — — — —
0011 1000 1111 $38F — — — —— — — — — 1 1 0 0 0 0 — — — — — — —

– 43 –
 CXA1992AR

Serial Data HEX BAL SW TOG SW IFB SW RDF

TGFL INT ATSC LDON LPCL LPC DFCT
$3XX 4 3 2 1 4 3 2 1 6 5 4 3 2 1 CT2

0011 1001 0000 $390 — — — —— — — — — 1 0 1 1 1 1 — — — — — — —

0011 1001 0001 $391 — — — —— — — — — 1 0 1 1 1 0 — — — — — — —
0011 1001 0010 $392 — — — —— — — — — 1 0 1 1 0 1 — — — — — — —
0011 1001 0011 $393 — — — —— — — — — 1 0 1 1 0 0 — — — — — — —
0011 1001 0100 $394 — — — —— — — — — 1 0 1 0 1 1 — — — — — — —
0011 1001 0101 $395 — — — —— — — — — 1 0 1 0 1 0 — — — — — — —
0011 1001 0110 $396 — — — —— — — — — 1 0 1 0 0 1 — — — — — — —
0011 1001 0111 $397 — — — —— — — — — 1 0 1 0 0 0 — — — — — — —
0011 1001 1000 $398 — — — —— — — — — 1 0 0 1 1 1 — — — — — — —
0011 1001 1001 $399 — — — —— — — — — 1 0 0 1 1 0 — — — — — — —
0011 1001 1010 $39A — — — —— — — — — 1 0 0 1 0 1 — — — — — — —
0011 1001 1011 $39B — — — —— — — — — 1 0 0 1 0 0 — — — — — — —
0011 1001 1100 $39C — — — —— — — — — 1 0 0 0 1 1 — — — — — — —
0011 1001 1101 $39D — — — —— — — — — 1 0 0 0 1 0 — — — — — — —
0011 1001 1110 $39E — — — —— — — — — 1 0 0 0 0 1 — — — — — — —
0011 1001 1111 $39F — — — —— — — — — 1 0 0 0 0 0 — — — — — — —
0011 1010 0000 $3A0 — — — —— — — — — 0 1 1 1 1 1 — — — — — — —
0011 1010 0001 $3A1 — — — —— — — — — 0 1 1 1 1 0 — — — — — — —
0011 1010 0010 $3A2 — — — —— — — — — 0 1 1 1 0 1 — — — — — — —
0011 1010 0011 $3A3 — — — —— — — — — 0 1 1 1 0 0 — — — — — — —
0011 1010 0100 $3A4 — — — —— — — — — 0 1 1 0 1 1 — — — — — — —
0011 1010 0101 $3A5 — — — —— — — — — 0 1 1 0 1 0 — — — — — — —
0011 1010 0110 $3A6 — — — —— — — — — 0 1 1 0 0 1 — — — — — — —
0011 1010 0111 $3A7 — — — —— — — — — 0 1 1 0 0 0 — — — — — — —
0011 1010 1000 $3A8 — — — —— — — — — 0 1 0 1 1 1 — — — — — — —
0011 1010 1001 $3A9 — — — —— — — — — 0 1 0 1 1 0 — — — — — — —
0011 1010 1010 $3AA — — — —— — — — — 0 1 0 1 0 1 — — — — — — —
0011 1010 1011 $3AB — — — —— — — — — 0 1 0 1 0 0 — — — — — — —
0011 1010 1100 $3AC — — — —— — — — — 0 1 0 0 1 1 — — — — — — —
0011 1010 1101 $3AD — — — —— — — — — 0 1 0 0 1 0 — — — — — — —
0011 1010 1110 $3AE — — — —— — — — — 0 1 0 0 0 1 — — — — — — —
0011 1010 1111 $3AF — — — —— — — — — 0 1 0 0 0 0 — — — — — — —
0011 1011 0000 $3B0 — — — —— — — — — 0 0 1 1 1 1 — — — — — — —
0011 1011 0001 $3B1 — — — —— — — — — 0 0 1 1 1 0 — — — — — — —
0011 1011 0010 $3B2 — — — —— — — — — 0 0 1 1 0 1 — — — — — — —
0011 1011 0011 $3B3 — — — —— — — — — 0 0 1 1 0 0 — — — — — — —
0011 1011 0100 $3B4 — — — —— — — — — 0 0 1 0 1 1 — — — — — — —
0011 1011 0101 $3B5 — — — —— — — — — 0 0 1 0 1 0 — — — — — — —
0011 1011 0110 $3B6 — — — —— — — — — 0 0 1 0 0 1 — — — — — — —
0011 1011 0111 $3B7 — — — —— — — — — 0 0 1 0 0 0 — — — — — — —
0011 1011 1000 $3B8 — — — —— — — — — 0 0 0 1 1 1 — — — — — — —
0011 1011 1001 $3B9 — — — —— — — — — 0 0 0 1 1 0 — — — — — — —
0011 1011 1010 $3BA — — — —— — — — — 0 0 0 1 0 1 — — — — — — —
0011 1011 1011 $3BB — — — —— — — — — 0 0 0 1 0 0 — — — — — — —
0011 1011 1100 $3BC — — — —— — — — — 0 0 0 0 1 1 — — — — — — —
0011 1011 1101 $3BD — — — —— — — — — 0 0 0 0 1 0 — — — — — — —
0011 1011 1110 $3BE — — — —— — — — — 0 0 0 0 0 1 — — — — — — —
0011 1011 1111 $3BF — — — —— — — — — 0 0 0 0 0 0 — — — — — — —

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 CXA1992AR

Serial Data HEX BAL SW TOG SW IFB SW RDF

TGFL INT ATSC LDON LPCL LPC DFCT
$3XX 4 3 2 1 4 3 2 1 6 5 4 3 2 1 CT2

0011 1100 0000 $3C0 — — — —— — — — — —————— 0 0 E 0 0 0 —

0011 1100 0001 $3C1 — — — —— — — — — —————— 0 0 E 0 0 1 —
0011 1100 0010 $3C2 — — — —— — — — — —————— 0 0 E 0 1 0 —
0011 1100 0011 $3C3 — — — —— — — — — —————— 0 0 E 0 1 1 —
0011 1100 0100 $3C4 — — — —— — — — — —————— 0 0 E 1 0 0 —
0011 1100 0101 $3C5 — — — —— — — — — —————— 0 0 E 1 0 1 —
0011 1100 0110 $3C6 — — — —— — — — — —————— 0 0 E 1 1 0 —
0011 1100 0111 $3C7 — — — —— — — — — —————— 0 0 E 1 1 1 —
0011 1100 1000 $3C8 — — — —— — — — — —————— 0 0 D 0 0 0 —
0011 1100 1001 $3C9 — — — —— — — — — —————— 0 0 D 0 0 1 —
0011 1100 1010 $3CA — — — —— — — — — —————— 0 0 D 0 1 0 —
0011 1100 1011 $3CB — — — —— — — — — —————— 0 0 D 0 1 1 —
0011 1100 1100 $3CC — — — —— — — — — —————— 0 0 D 1 0 0 —
0011 1100 1101 $3CD — — — —— — — — — —————— 0 0 D 1 0 1 —
0011 1100 1110 $3CE — — — —— — — — — —————— 0 0 D 1 1 0 —
0011 1100 1111 $3CF — — — —— — — — — —————— 0 0 D 1 1 1 —
0011 1101 0000 $3D0 — — — —— — — — — —————— 0 1 E 0 0 0 —
0011 1101 0001 $3D1 — — — —— — — — — —————— 0 1 E 0 0 1 —
0011 1101 0010 $3D2 — — — —— — — — — —————— 0 1 E 0 1 0 —
0011 1101 0011 $3D3 — — — —— — — — — —————— 0 1 E 0 1 1 —
0011 1101 0100 $3D4 — — — —— — — — — —————— 0 1 E 1 0 0 —
0011 1101 0101 $3D5 — — — —— — — — — —————— 0 1 E 1 0 1 —
0011 1101 0110 $3D6 — — — —— — — — — —————— 0 1 E 1 1 0 —
0011 1101 0111 $3D7 — — — —— — — — — —————— 0 1 E 1 1 1 —
0011 1101 1000 $3D8 — — — —— — — — — —————— 0 1 D 0 0 0 —
0011 1101 1001 $3D9 — — — —— — — — — —————— 0 1 D 0 0 1 —
0011 1101 1010 $3DA — — — —— — — — — —————— 0 1 D 0 1 0 —
0011 1101 1011 $3DB — — — —— — — — — —————— 0 1 D 0 1 1 —
0011 1101 1100 $3DC — — — —— — — — — —————— 0 1 D 1 0 0 —
0011 1101 1101 $3DD — — — —— — — — — —————— 0 1 D 1 0 1 —
0011 1101 1110 $3DE — — — —— — — — — —————— 0 1 D 1 1 0 —
0011 1101 1111 $3DF — — — —— — — — — —————— 0 1 D 1 1 1 —
0011 1110 0000 $3E0 — — — —— — — — — —————— 1 0 E 0 0 0 —
0011 1110 0001 $3E1 — — — —— — — — — —————— 1 0 E 0 0 1 —
0011 1110 0010 $3E2 — — — —— — — — — —————— 1 0 E 0 1 0 —
0011 1110 0011 $3E3 — — — —— — — — — —————— 1 0 E 0 1 1 —
0011 1110 0100 $3E4 — — — —— — — — — —————— 1 0 E 1 0 0 —
0011 1110 0101 $3E5 — — — —— — — — — —————— 1 0 E 1 0 1 —
0011 1110 0110 $3E6 — — — —— — — — — —————— 1 0 E 1 1 0 —
0011 1110 0111 $3E7 — — — —— — — — — —————— 1 0 E 1 1 1 —
0011 1110 1000 $3E8 — — — —— — — — — —————— 1 0 D 0 0 0 —
0011 1110 1001 $3E9 — — — —— — — — — —————— 1 0 D 0 0 1 —
0011 1110 1010 $3EA — — — —— — — — — —————— 1 0 D 0 1 0 —
0011 1110 1011 $3EB — — — —— — — — — —————— 1 0 D 0 1 1 —
0011 1110 1100 $3EC — — — —— — — — — —————— 1 0 D 1 0 0 —
0011 1110 1101 $3ED — — — —— — — — — —————— 1 0 D 1 0 1 —
0011 1110 1110 $3EE — — — —— — — — — —————— 1 0 D 1 1 0 —
0011 1110 1111 $3EF — — — —— — — — — —————— 1 0 D 1 1 1 —

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 CXA1992AR

Serial Data HEX BAL SW TOG SW IFB SW RDF

TGFL INT ATSC LDON LPCL LPC DFCT
$3XX 4 3 2 1 4 3 2 1 6 5 4 3 2 1 CT2

0011 1111 0000 $3F0 — — — —— — — — — —————— 1 1 E 0 0 0 —

0011 1111 0001 $3F1 — — — —— — — — — —————— 1 1 E 0 0 1 —
0011 1111 0010 $3F2 — — — —— — — — — —————— 1 1 E 0 1 0 —
0011 1111 0011 $3F3 — — — —— — — — — —————— 1 1 E 0 1 1 —
0011 1111 0100 $3F4 — — — —— — — — — —————— 1 1 E 1 0 0 —
0011 1111 0101 $3F5 — — — —— — — — — —————— 1 1 E 1 0 1 —
0011 1111 0110 $3F6 — — — —— — — — — —————— 1 1 E 1 1 0 —
0011 1111 0111 $3F7 — — — —— — — — — —————— 1 1 E 1 1 1 —
0011 1111 1000 $3F8 — — — —— — — — — —————— 1 1 D 0 0 0 —
0011 1111 1001 $3F9 — — — —— — — — — —————— 1 1 D 0 0 1 —
0011 1111 1010 $3FA — — — —— — — — — —————— 1 1 D 0 1 0 —
0011 1111 1011 $3FB — — — —— — — — — —————— 1 1 D 0 1 1 —
0011 1111 1100 $3FC — — — —— — — — — —————— 1 1 D 1 0 0 —
0011 1111 1101 $3FD — — — —— — — — — —————— 1 1 D 1 0 1 —
0011 1111 1110 $3FE — — — —— — — — — —————— 1 1 D 1 1 0 —
0011 1111 1111 $3FF — — — —— — — — — —————— 1 1 D 1 1 1 —

Notes) • 0 means OFF and 1 means ON for TOG SW and BAL SW. These are not equal to the setting values
of each bit for serial data.
• "—" in the Truth Table indicates that the status does not change.
• TGFL
In the Block Diagram:
1:SW side
0:SW side
• ATSC E: enable/D: disable
• DFCT E: enable/D: disable

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 CXA1992AR

Initial State (resetting state)

ADDRESS DATA
Item HEX
D7 D6 D5 D4 D3 D2 D1 D0
FOCUS CONTROL 0 0 0 0 0 0 0 0 $00
TRACKING CONTROL 0 0 0 1 0 0 0 0 $10
TRACKING SLED MODE 0 0 1 0 0 0 0 0 $20

ADDRESS DATA
Item HEX
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
E-F BALANCE 0 0 1 1 0 0 0 0 0 0 0 0 $300
TRACKING GAIN 0 0 1 1 0 1 0 0 0 0 0 0 $340
FOCUS BIAS 0 0 1 1 1 0 0 0 0 0 0 0 $380
Others 0 0 1 1 1 1 0 1 0 0 0 0 $3D0

The above data means the following operation modes.

FOCUS CONTROL : FOCUS OFF, FOCUS SEARCH OFF, FOCUS SEACH DOWN
TRACKING CONTROL : TG1-TG2 NORMAL, BRAKE DISABLE, SLED KICK relative height value ±1
TRACKING SLED MODE : TRACKING OFF, SLED OFF
E-F BALANCE : BAL1 to BAL4 = 0 (switch ON). DFCT ENABLE
TRACKING GAIN : TOG1 to TOG4 = 0 (switch ON), TGFL NORMAL
FOCUS BIAS : IFB1 to IFB6 = 0 (switch ON)
Others : INT DISABLE, DFCT2 RESET, ATSC ENABLE, LDON OFF, LPCL ±17%, LPC OFF

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 CXA1992AR

Notes on Operation

1. Focus OK circuit
1) Refer to the "Description of Operation" for the time constant setting of the focus OK amplifier LPF and the
mirror amplifier HPF.
2) The equivalent circuit for the output pin (FOK) is shown in the diagram below.

VCC

20k
FOK
27
40k
The FOK and comparator output are as follows: RL

Output voltage High : VFOKH ≈ near Vcc 100k

Output voltage Low : VFOKL ≈ Vsat (NPN) + VEE VCC

VEE VEE

2. Sled amplifier
The sled amplifier may oscillate when used by the buffer amplifier. Use with a gain of approximately 20dB.

3. Focus/Tracking internal phase compensation and reference design material

Item SD Measurement pin Conditions Typ. Unit

1.2kHz gain 08 CFLB = 0.1µF 21.5 dB
FCS

6
1.2kHz phase 08 CFGD = 0.1µF 63 deg
1.2kHz gain 25 13 dB
1.2kHz phase 25 –125 deg
TRK

13 CTGU = 0.1µF
2.7kHz gain 25 → 13 26.5 dB
2.7kHz phase 25 → 13 –130 deg

4. Laser Poser Control

The RF level is stabilized by attaching an offset to the APC VL and controlling the laser power in sync with the
RF level fluctuations.
The laser life is shortened by increasing the laser power when the less light is reflected from the disc.
It is recommended that the typical laser power value is set lower to maintain the laser life.
Take care of the laser maximum ratings when using the laser power control circuit.

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 CXA1992AR

Package Outline Unit: mm

52PIN LQFP(PLASTIC)
+ 0.1
12.0 ± 0.2 1.5 0
∗ 10.0 ± 0.1
0.1

39 27

40 26
B

52 14

1 13
0.65
+ 0.08
0.32 – 0.07
0.13 M

0.25
0.6 ± 0.15

0.145 – 0.025
0.1 ± 0.1

+ 0.04
+ 0.08
(11.0)

0.32 – 0.07

(0.125)
(0.3)
(0.5)

0° to 10°

DETAIL A DETAIL B

NOTE: “∗” Dimensions do not include mold protrusion.

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE LQFP-52P-L01 LEAD TREATMENT PALLADIUM PLATING

EIAJ CODE LQFP052-P-1010 LEAD MATERIAL COPPER ALLOY

JEDEC CODE PACKAGE MASS 0.3g

– 49 –
This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.