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1 Multiplekser 2 ke 1 dataflow
//Design
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux_2to1 is
port(
A,B : in STD_LOGIC;
S: in STD_LOGIC;
Z: out STD_LOGIC
);
end mux_2to1;
//Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY testbench_mux IS
END testbench_mux;
COMPONENT mux_2to1
PORT(
A : IN std_logic;
B : IN std_logic;
S : IN std_logic;
Z : OUT std_logic
);
END COMPONENT;
signal A : std_logic;
signal B : std_logic;
signal S : std_logic;
signal Z : std_logic;
BEGIN
uut: mux_2to1 PORT MAP (
A => A,
B => B,
S => S,
Z => Z
);
stim_proc: process
begin
A <='1';
B <='0';
S <='1';
wait;
end process;
END;
//Simulasi
entity mux_2to1_2bit is
port(
//Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY testbench_mux1 IS
END testbench_mux1;
COMPONENT mux_2to1_2bit
PORT(
A : IN std_logic_vector(1 downto 0);
B : IN std_logic_vector(1 downto 0);
S : IN std_logic_vector(1 downto 0);
Z : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
BEGIN
uut: mux_2to1_2bit PORT MAP (
A => A,
B => B,
S => S,
Z => Z
);
stim_proc: process
begin
A <="11";
B <="01";
S <="00";
wait;
end process;
END;
//Simulasi
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity not_gate is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC
);
end not_gate;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or_gate is
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end or_gate;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2to1_2bit is
Port ( i0,i1,i2,i3,s : in STD_LOGIC;
m1,m2 : out STD_LOGIC);
end mux2to1_2bit;
component or_gate
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
component not_gate
Port ( a : in STD_LOGIC;
b : out STD_LOGIC
);
end component;
signal out_and1, out_and2, out_and3, out_and4, not_out1, not_out2 : STD_LOGIC;
begin
and_one : and_gate port map(
a => i0,
b => s,
c => out_and1);
not_one : not_gate port map(
a => s,
b => not_out1
);
and_two : and_gate port map(
a => i1,
b => not_out1,
c => out_and2);
and_three : and_gate port map(
a => i2,
b => s,
c => out_and3);
not_two : not_gate port map(
a => s,
b => not_out2
);
and_four : and_gate port map(
a => i3,
b => not_out2,
c => out_and4);
or_opt1 : or_gate port map(
a => out_and1,
b => out_and2,
c => m1);
or_opt2 : or_gate port map(
a => out_and3,
b => out_and4,
c => m2);
end mux2to1_2bit_arch;
//Testbench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity testbench_mux is
-- Port ( );
end testbench_mux;
begin
uut: mux2to1_2bit PORT MAP (
i0 => x_int(0),
i1 => y_int(0),
i2 => x_int(1),
i3 => y_int(1),
s => s_int,
m1 => m_int(0),
m2 => m_int(1)
);
process
begin
wait for 100 ns; x_int <= "01";s_int <= '0';
wait for 100 ns; y_int <= "01";
wait for 100 ns; x_int <= "11"; y_int <= "00";
wait for 100 ns; x_int <= "10"; y_int <= "11";
wait for 100 ns; x_int <= "01";s_int <= '1';
wait for 100 ns; x_int <= "01";
wait for 100 ns; x_int <= "01";
wait for 100 ns; x_int <= "01"; y_int <= "00";
wait for 100 ns; x_int <= "01"; y_int <= "11";
wait for 100 ns;
end process;
end structural;
//Simulasi
entity mux_2to1 is
port(
A,B : in STD_LOGIC;
S: in STD_LOGIC;
Z: out STD_LOGIC
);
end mux_2to1;
end process;
end behavior;
//Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY testbench_mux IS
END testbench_mux;
COMPONENT mux_2to1
PORT(
A : IN std_logic;
B : IN std_logic;
S : IN std_logic;
Z : OUT std_logic
);
END COMPONENT;
signal A : std_logic;
signal B : std_logic;
signal S : std_logic;
signal Z : std_logic;
BEGIN
uut: mux_2to1 PORT MAP (
A => A,
B => B,
S => S,
Z => Z
);
stim_proc: process
begin
A <= '1';
B <= '0';
S <= '0';
wait for 100 ns;
S <= '1';
wait for 100 ns;
wait;
end process;
END;
//Simulasi
2.5 Multiplekser 2 ke 1 2bit behavior
//Design
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux_2to1_2bitwide is
port(
end process;
end behavior;
//Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY testbench_mux IS
END testbench_mux;
COMPONENT mux_2to1_2bitwide
PORT(
A : IN std_logic_vector(1 downto 0);
B : IN std_logic_vector(1 downto 0);
S : IN std_logic;
Z : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
BEGIN
uut: mux_2to1_2bitwide PORT MAP (
A => A,
B => B,
S => S,
Z => Z
);
stim_proc: process
begin
A <= "10";
B <= "11";
S <= '0';
wait for 100 ns;
S <= '1';
wait for 100 ns;
wait;
end process;
END;
//Simulasi