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approach was to source world’s largest and world’s fastest Analog devices compete with the TS201SABP TigerSHARC
processing componentry and utilise this in such a way that capable of achieving 4800 MMACS. The TS210S performs
modular expansion is possible. a maximum of eight 16-bit MAC operations per 600 MHz
clock cycle. Both were the fastest devices in their class at the
time of analysis.
2.1. Raw data bandwidth
The figures mentioned are for 16-bit calculations only:
they are not necessarily representative of the full picture. For
By contrast, bounds could be placed on sample rate and es-
example, the C64 device mentioned also achieves up to 5760
timated conversion precision, and this allowed a measure
8-bit MMACS. Both devices have various signal-processing
of maximum data throughput in such a system. In fact, a
related accelerators built in. However the MMAC and other
60 MHz sample rate was adopted with 12/14-bit conversion
figures are peak values: whether these are achievable depends
precision limited by available devices. This meant a peak
very much on software structure, other concurrent opera-
bidirectional data throughput of 10.8 Gbps for 12-channel
tions, and the requirements for external memory. Neverthe-
I/Q after a decimation-by-two.
less, the figures do indicate a generous upper bound on the
It was firstly evident that a single digital signal proces-
fastest processing capability advertised by the two leading
sor (DSP) would not be capable of meaningfully process-
DSP manufacturers.
ing such data flow, and was secondly evident that physical
It is evident that both device are capable of a peak pro-
means of transporting such amounts of data are problem-
cessing speed of the approximately required 3 billion calcula-
atic. It therefore becomes necessary to subdivide the problem
tions per second but do not “sufficiently exceed this.” A more
into smaller blocks. 4-channel blocks were found suitable
detailed analysis reveals problems of memory bandwidth and
since the peak data throughput would then be 3.36 Gbps,
input-output bus bandwidths that would effectively prevent
which is conveyable between modules using paralleled low-
the devices from handling the large data throughput required
voltage differential signalling (LVDS) connections. A single
without careful design of supporting hardware. Such sup-
field-programmable gate array (FPGA) was capable of han-
porting hardware would probably be best achieved using a
dling the peak data throughput within each 4-channel block,
reprogrammable device such as an FPGA.
performing a decimation, and supporting data communica-
Focussing on FPGA devices revealed the potential for
tions at 3.36 Gbps using built-in LVDS drivers. Given bidi-
performing all calculations in FPGA. A brief survey of con-
rectional data communications, a 12-channel system was
temporary FPGA devices reinforces this conclusion.
achieved with oversampled raw data interchange between
The biggest and fastest FPGA devices currently include
several FPGAs given the caveat that each data path conveyed
the StratixII EP2S180 FPGA from Altera with 179 400 logic
no more than 4-channels worth of 30 MHz I/Q data.
elements (LEs) and 96 DSP blocks each capable of 4 MACs
This led to the modular and expandable architectural for- at up to 420 MHz when paired to support 18-bit opera-
mat shown in Figure 1 for a 4-channel variant, and shown in tion.
full in Figure 2 with specification shown in Table 1. This sys- In this device, use of the DSP blocks alone delivers up
tem is capable of processing, down to baseband outputs, the to 161 280 MMACS even when none of the built-in logic el-
data generated by 12 receive channels, and simultaneously ement resources are reserved for processing. If a proportion
generating 12 transmit channels from baseband input. These of the 179 400 logic elements (LEs, each containing a look-up
data chains included MIMO and space-time block-coding al- table and flip-flop) is also used to implement parallel MAC
gorithms. functions, 962 multipliers can be created (given in Altera’s
data sheets as “soft MACs”). Assuming that these operate at
2.2. Signal processing a slower frequency of 180 MHz (which is the practical up-
per limit observed by the authors for implementation of dis-
At the time of system design, a very rough estimate of com- tributed filters using soft MACs), another 173 160 MMACS
plexity was given for a 2-channel Alamouti [1] implementa- are available for use. It is of course unrealistic to assume that
tion of 3 billion multiply-accumulate calculations per second the entire FPGA can be utilised as dedicated MACs, but al-
[2]. Given that a 12-channel system was being constructed lowing 25% unusable capacity for these would mean that
from three 4-channel modules, and that Alamouti is gener- over 290 000 MMACS are available in total.
ally considered to be relatively simple, computational capa- The largest Xilinx FPGA, the Virtex-4 series XC4VSX55,
bilities of each STAR module were required to significantly has 55 295 logic cells, 512 embedded “XtremeDSP” slices
exceed this if such modules were expected to be able to per- each capable of a single 18 × 18 multiply, and operates at
form meaningful processing. up to 500 MHz (256 000 MMACS). Scaling for density on
Dedicated DSP processors have traditionally been used the same Altera quoted soft-MAC construction density, up to
for wireless baseband processing. A survey of available de- 296 multipliers could be created from the logic cells. If oper-
vices as per [2], updated here, reveals clock rates of up to ated at 180 MHz, this provides another 53 280 MMACS. With
1 GHz. Leading edge DSPs contain multiple independent a 25% assumed overhead, a total of over 290 000 MMACS are
multiply-accumulate (MAC) cores, with Texas Instruments available in this device.
TMS320C6416T series device being capable of up to 8000 Since an FPGA was required for interfacing, and pro-
16-bit MMACS(million multiply accumulates per second). vided a theoretical processing capability far in excess of a
J. Dowle et al. 3
RF RF RF RF RF RF RF RF
IF IF IF IF IF IF IF IF
RF TX RF TX RF RX RF RX
RF & IF
LO’s
3
way
RxFLT 1
RxFLT 2
TxFLT 1
TxFLT 2
3
TX & RX way
RF/IF LO’s 3
way DAC 1 DAC 2 DAC 3 DAC 4 ADC 1 ADC 2 ADC 3 ADC 4 Gen 10 bit Gen 8 bit
14 bit 14 bit 14 bit 14 bit 12 bit 12 bit 12 bit 12 bit ADC ×8 DAC ×8
3
way Mix Sig unit
PLL 60 MHz
RX CLK
SYN CTL RX CTL
TX CTL
REF 10 MHz TRX CTL
REF SEL
REF (10 MHz)
10 MHz FPGA
OCXO LVDS
Serial LVDS
second ary
Serial LVDS
to next
primary
4 CH
Flash group
JTAG 1
32 bit 16 bit
REF & LO unit
JTAG 3
LVDS Arm
to next processor DSP
4 CH JTAG 2
group
RAM Flash Flash
RS 232
50
60 & 10 MHz
CLK’s
Backplane
Expansion port +8.5 V +15 V +28 V +4 V
Figure 1: STAR platform in an early 4-channel configuration, showing some of the details of the system architecture.
DSP, the STAR platform was designed such that the major- 2.3. System architecture
ity of baseband processing would be performed by FPGA,
with additional FPGA devices provided for front-end sample A dual conversion approach was chosen for the RF sections
handling. For experimental and comparative purposes, pro- of the system and the overall system architecture constructed,
vision was made for the current fastest DSP processor to be as shown in Figures 1 and 2. It can be seen that there are
also present on each of the baseband processing boards, al- three processing slices each capable of four bidirectional RF
though on later board revisions this was removed as unnec- channels and a large degree of baseband signal processing.
essary and replaced with two further FPGAs. There are thus An oven-controlled crystal oscillator (OCXO) with bet-
three per PCB, a total of nine FPGAs per 12-channel plat- ter than 0.2 PPM (parts per million) drift accuracy pro-
form. vides a stable reference frequency, and a flexible software
4 EURASIP Journal on Applied Signal Processing
TRXSW TRXSW TRXSW TRXSW TRXSW TRXSW TRXSW TRXSW TRXSW TRXSW TRXSW TRXSW
unit 1 unit 2 unit 3 unit 4 unit 5 unit 6 unit 7 unit 8 unit 9 unit 10 unit 11 unit 12
TRX CTL 1 TRX CTL 2 TRX CTL 3 TRX CTL 4 TRX CTL 5 TRX CTL 6 TRX CTL 7 TRX CTL 8 TRX CTL 9 TRX CTL 10 TRX CTL 11 TRX CTL 12
TRX control’s TRX control’s 2 TRX control’s 3
RF TX RF RX RF TX RF RX RF TX RF RX RF TX RF RX RF TX RF RX RF TX RF RX RF TX RF RX RF TX RF RX RF TX RF RX RF TX RF RX RF TX RF RX RF TX RF RX
unit 1 unit 1 unit 2 unit 2 unit 3 unit 3 unit 4 unit 4 unit 5 unit 5 unit 6 unit 6 unit 7 unit 7 unit 8 unit 8 unit 9 unit 9 unit 10 unit 10 unit 11 unit 11 unit 12 unit 12
TX & RX LO’s
RxFLT 1
TxFLT 1
RxFLT 1
RxFLT 1
TxFLT 1
TxFLT 1
PLL 12
TX RF LO way
TX RX TX RX TX RX TX RX Gen 8 bit Gen 8 bit TX RX TX RX TX RX TX RX Gen 8 bit Gen 8 bit TX RX TX RX TX RX TX RX Gen 8 bit Gen 8 bit
D/A A/D D/A A/D D/A A/D D/A A/D quad D/A quad A/D D/A A/D D/A A/D D/A A/D D/A A/D quad D/A quad A/D D/A A/D D/A A/D D/A A/D D/A A/D quad D/A quad A/D
PLL 12 1 1 2 2 3 3 4 4 1 1 2 2 3 3 4 4 1 1 2 2 3 3 4 4
Serial LVDS 2
Serial LVDS 2
REF 10 MHz
Serial LVDS 2
O 32 32
Serial LVDS 1
Serial LVDS 1
Serial LVDS 1
PLL ption 12
al
RX IF LO way JTAG 1
JTAG 1
JTAG 1
REF BUF Arm Arm Arm
DSP processor DSP processor DSP processor
JTAG 2
JTAG 2
JTAG 2
JTAG 3
JTAG 3
JTAG 3
10 MHz
OCXO Digital unit 1 Digital unit 2 Digital unit 3
REF & LO unit
PRE–REG SWREG +8 V 5 RF
+12.5 V
+8.5 V
TBD Amp
SWREG +3 V 6
+3.6 V
TBD Amp
50
programmable synthesizer generates all derivative clocks and The embedded Linux system, connected by ethernet to a
frequencies from this. company internet or intranet, allows storage and transmis-
Custom switched mode power regulators followed by sion of very large volumes of data (over 10 Gb have been
low-noise low-drop-out linear voltage regulators provide transferred during various tests), albeit not at speeds that
power supplies with very low-noise component to each would always be suitable for real-time data transfer.
subsystem within the STAR platform. The embedded Linux control processor has been dedi-
cated to low-speed control and monitoring applications, and
2.4. System control integrated with a highly novel web-based management in-
terface [4] for ease of control, setup, and analysis of system
Whilst there is a strong MMACS argument for the use of operation.
FPGA in baseband signal processing, it is still recognised that
control software is easier and quicker to develop using high- 3. ALGORITHMIC DEVELOPMENT
level language and scripting tools [3]. For this reason, the
platform incorporates a small ARM processor running Linux The STAR platform has hosted implementation of a num-
[4]. ber of MIMO and space-time algorithms comprising several
J. Dowle et al. 5
Design
3.1. Simulation refinement reports
H.txt
3.2. Example development process The experience of the team developing the STAR platform
has been that a multidisciplinary multi-talented team is
Figure 3 outlines an example of an algorithmic module de- required for system implementation. Successful results are
velopment process for channel estimation on FPGA starting unlikely where development is split along the lines of (i) the-
from a fixed-point Octave simulation. Test vector files are ory, (ii) simulation, (iii) VHDL coding, (iv) hardware. The
generated, using Monte-Carlo style simulation inputs, that development process is highly coupled, much more than for
are time aligned to describe inputs and outputs of the mod- a traditional specification-bound DSP development.
ule. These files contain a sequence of fixed-point numbers It is more desirable to split a multidisciplinary team along
with the bit precision required for each input and output. the boundaries of module requirements such as (i) digi-
These are used to derive various testbeds. tal front-end, (ii) channel estimator, (iii) equaliser. . . and
In the example shown, VHDL modules are authored and so forth, where each module team has the responsibility to
simulated functionally in ModelSim before being moved to move that module from a set of equations, through simu-
Quartus II for full timing simulation and logic synthesis. lations that are incrementally increasing in reality, through
In each case, the VHDL design is intended to be bit-exact VHDL simulations to final code.
with the Octave source. Since the actual implementation can Given a floating point overall system simulation, fixed-
involve unusual number-theoretic transformations or novel point modules can be substituted into this when available,
numerical tricks, it is common that bit-exactness will be bro- and interfacing requirements checked and fixed. The final re-
ken during the process, in which case the implementation sult will be two-fold: a working VHDL implementation and a
technique is folded back into the Octave source code and the bit-exact system simulation. The simulation is invaluable in
simulation testbed is repeated to again ensure continued bit- tracking down implementation problems and will aid with
exactness. It is therefore important to acknowledge that the diagnosing issues identified in field testing.
6 EURASIP Journal on Applied Signal Processing
The STAR platform was used in such a way to develop a symbol block and during both bursts, and in practice, this
three separate systems designed to explore interesting spaces is generally achievable by judicious choice of symbol block
within the multidimensional multiantenna, MIMO, and length.
block coding algorithm continuum. These three systems are Similarly, the received signal for the second burst, when
now introduced before particular implementation issues are time-reversed and complex conjugated by the receiver, is
identified in Section 4 and results and analysis from these are
presented in Section 5. r3 (t) = r2∗ (N − t) = −g0∗ d2 (t) − g1∗ d2 (t + 1) − g2∗ d2 (t + 2)
− g3∗ d2 (t + 3) + p0∗ d1 (t) + p1∗ d1 (t + 1) + p2∗ d1 (t + 2)
3.4. Time-reversal space-time block coding
+ p3∗ d1 (t + 3) + n∗2 (N − t) for t = 0, . . . , N.
Recently, an Alamouti [1] inspired, but computationally sim- (4)
pler, time-domain block processing scheme [8–10] was de-
veloped. Named time-reversal (TR) space-time block coding With some simplification, it is then possible to form a matrix
(STBC), this lends itself to decoupled and parallel equalisa- using the q notation of [8] as
tion schemes and is particularly suitable for FPGA-based im-
plementation [11]. In particular, the receive decoding pro-
r1 (t) g q−1 p q−1 d1 (t) n (t)
cess is simplified through the ordering and coding of trans- = + 1 . (5)
mit sequences. r3 (t) pH (q) −g H (q) d2 (t) n3 (t)
As part of the STAR implementation work, the equations
were first reordered into simplified time-domain formula- This can then be solved in one of several ways and linear
tions [6] and then investigated in the presence of channel combining in this case is used to extract a single stream of
error effects and timing synchronization errors [11]. decoded data from the equations.
In principal, TR-STBC is a 2 × 1 system where formatting The architecture of the receiver is shown in Figure 4,
and processed repetition of transmitted data ensure dual di- where all operations apart from the Viterbi equaliser and
versity across two timeslots, but obviously provide no capac- ARM control processor were performed in FPGA. The finite
ity gain. Data transmission format is shown in Table 2, where state machine (FSM) controller was replaceable in the STAR
S1 and S2 are transmit data blocks each comprising multiple platform by a custom flexible embedded processor for ease
data words as shown for the case of S1 : of programmability [3]. Although there is a single receive
antenna, there are two streams of data to be decoded post
S1 = d1 (0), d1 (1), . . . , d1 (N) . (1) matched filtering, and the second of these is denoted by the
grey blocks in the figure. The debug buffer shown could ac-
In blocks S1 and S2 , the individual data symbols themselves cept data from, or inject given data into, any major position
are time reversed and each is complex conjugated denoted in the data flow path. This was an invaluable means of apply-
for simplicity by D as is ing test-vector stimulus (as in Figure 3) to the implemented
system in order to perform real-time black-box testing of in-
S1 = d1∗ (N), d1∗ (N − 1), . . . , dl∗ (0) dividual implemented modules in situ.
(2)
= D1 (0), D1 (1), . . . , D1 (N) .
3.5. Adaptive multivariate (AMV) DFE-MIMO
If the channel impulse response from Antenna 1 to the re-
ceive antenna is g0 , g1 , g2 , and g3 assuming a 4-tap channel There are many MIMO schemes ranging from the sim-
response, and the channel impulse response from Antenna 2 plest linear equaliser through to complicated maximum-
to the receive antenna is p0 , p1 , p2 , and p3 , then the received likelihood (ML) solutions which require exponentially in-
signal for the first data burst can be expressed as creasing amounts of computational resources when scaled.
Despite the dramatic continuous improvements in compu-
r1 (t) = g0 d1 (t) + g1 d1 (t − 1) + g2 d1 (t − 2) + g3 d1 (t − 3) tational technology, suboptimal but realizable MIMO so-
+ p0 d2 (t) + p1 d2 (t − 1) + p2 d2 (t − 2) + p3 d2 (t − 3) lutions are more likely to be implementable with current
+ n1 (t) for t = 0, . . . , N, technology. BLAST [12] is one such family of algorithms
(3) without the computational load of a full ML solution, but
aimed at better performance than linear equalisation. Sim-
where n1 (t) is assumed to be white noise with zero mean. We ilarly, the decision feedback equalizer (DFE) was chosen as
have made the assumption that the channel is stationary over a candidate for investigation on the STAR platform in the
J. Dowle et al. 7
FPGA
Channel Channel 1
Multi–rate signal processing block estimator
RF interface Channel 2
Demod Pluse Decimate
and ADCs filter
Forward 1 Viterbi
Matched equalizer
Forward 2 on
Synchronizer × filter
T.I. DSP
RAM
Data 1
Linear
Controller combiner Data 2
Control
Status Arm CPU
Debug
buffer Ethernet
hope that it could provide a good reduced complexity equal- To calculate the tap weights adaptively, we take (7) and
isation solution—less then a full maximum-likelihood se- write in the form of a normal equation
quence estimator (MLSE), but with similar performance lev- ⎡ ⎤
els. It also provides a continuous path for improvement y1 (t)
⎢ ⎥
through delayed decision-feedback sequence estimation [13] ⎢ ⎥
⎢ ··· ⎥
to full MLSE.
⎢ ⎥
fb ⎢ ym (t) ⎥
| w1, j , . . . , wn, j ⎢ ⎥
ff ff fb
Multivariate DFE is based upon the standard single- z j (t) = w1, j , . . . , wm, j ⎢ ⎥
⎢ x
1 (t) ⎥
thread DFE as presented in most undergraduate textbooks. ⎢ ⎥ (8)
⎢ ··· ⎥
For a given sample instance t, a soft decision input z(t) is a ⎣ ⎦
scalar quantity represented by −
xn (t)
ff fb
y(t)
= wj | wj − .
z(t) = w f f y(t) − w f b x
(t), (6) x
(t)
ff fb
For calculating filter weights, [w j | w j ] must be found
where w f f and w f b are row vectors representing complex FIR such that the decision error be minimized:
filter tap weights, and y(t) and x
(t) represent the state of the
ff fb ff fb y
shift registers shown in Figure 5 at time t. There are multi- wj | wj = argmin wj | wj − − xj , (9)
x
y + z 3.6. OFDM-MIMO
wf f +
− Orthogonal frequency division multiplexing (OFDM) is a
wfb
multi-carrier-based digital modulation technique, in which
a number of orthogonal waves are multiplexed in one sym-
bol waveform, aiming to mitigate ISI in a frequency selec-
Figure 5: SISO DFE block diagram showing feed forward and feed- tive fading channel. It is advantageous both in terms of ab-
back filters. solute data rate and in terms of spectral efficiency (bps/Hz).
OFDM-MIMO is a particularly attractive combination since
it combines the advantages of both OFDM and MIMO tech-
modulation format of π/4 DQPSK for its immunity to fre- nology. MIMO is inherently capable of providing high spec-
quency drift. tral efficiency limited theoretically only by the minimum of
In addition to the DFE processing, the receiver FPGA the number of transmit or receive antennae, while OFDM
comprised modules for IF to baseband demodulation, root provides high spectral efficiencies and effective ISI mitiga-
raised cosine matched filtering, and synchronization. The tion. The OFDM implementation transforms a frequency
DFE filter weights were calculated for every packet based on selective fading channel response into single tap flat fading
training. A separate module performed weight updates and channels in the frequency domain.
allowed effective algorithmic experimentation. For these reasons, OFDM-MIMO was chosen for imple-
A 1 MHz pulse shaping root raised cosine filter with mentation on the STAR platform, with similar rationale to
100% roll-off receive filter and 60 MHz baseband sampling published implementations by other authors [16, 17]. Dis-
rate was used with a 120 MHz processing clock [15]. crete matrix multi-tone modelling was chosen to reduce the
For efficiency, the sum of the multiple FIR filters was im- complexity in a frequency selective fading system implemen-
plemented with a single high-speed multiply and accumu- tation, and this holds good for both flat and frequency selec-
late circuit by concatenating all inputs and tap weights in the tive fading channels. In our model, K data symbols are trans-
right order without resetting the accumulator in between. In mitted from each antenna per block, and a cyclic prefix added
other words, the sum of the FIR filters can be implemented to the beginning of the data sequence such that the last (L − 1)
as one larger FIR filter: symbols are transmitted before the full block of K symbols.
4 This is true of sequences from each of MT transmit antennae.
wi yi = WY There are MR receive antennae with a multi-path length L.
i=1 (11) The architecture is shown in Figures 8 and 9 for transmit and
T
for W = w1 , w2 , . . . , w4 , Y = y1 , y2 , . . . , y4 . receive processing elements, with the algorithm that was im-
plemented also described in [18]. Timing-critical elements
Figure 7 shows a single DFE decision device building block. were implemented in VHDL but offline channel estimation,
Four instances of this block were used to construct a 4 × 4 fine timing synchronization, and frequency correction and
DFE receiver [15]. The feedback filters could similarly be detection were implemented in Matlab. This demonstrated
merged into a single block multiply and accumulate opera- the underlying principles of implementation, but provided
tion. However, one of the benefits of DFE is that the feed- a very rapid path to evaluation of OFDM-MIMO under
back filter only operates from a finite set of constellation real channel conditions but without lengthy development re-
points and thus eliminates the need of a multiplier in some quirements. Other authors [16, 17] have implemented sim-
instances. In the STAR implementation, a better resource ilar systems, demonstrating that the FFT, IFFT, and back-
utilisation was thus to keep the feedback filters separate. Us- end processing could easily be performed in FPGA if re-
ing built-in FPGA memory, it is very convenient to construct quired.
block RAM to store filter weights as well as the shift regis- Let the MR × MT impulse response matrix describing the
ter states. The filters shown in Figure 7 are built from RAM channels be G[l] for the lth tap for l = 0, 1, . . . , L − 1. The
blocks to correspond directly to [y T | −
xT ]. i, jth element of G[l] are represented by gi, j (l) denoting the
With filter weights stored in RAM, the adaptive algorithm channel impulse response from jth transmit antenna to the
simply updates those weights through a single write inter- ith receive antenna for the lth tap. s j [k] is the signal prior to
face, while the DFE uses the read interface provided that the IFFT: K symbols to be transmitted on antenna j at time (or
DFE modules do not need to access the memory location that tone) k for k = 0, 1, . . . , K − 1.
the adaptive algorithm module is currently writing—which Similarly, y j [k] is a block of symbols received after the
is a timing issue. In the case of the LMS algorithm, weight FFT on antenna i for time (or tone) k for k = 0, 1, . . . ,
updates are independent for every tap and can be written as K − 1.
The sequence of symbols to be transmitted over each an-
W (new) = W (old) + μ data error, (12)
tenna is first inverse Fourier transformed (IFFT) and a cyclic
and each filter coefficient is updated by adding a scaled ver- prefix (CP) of length (L − 1) is added before the K symbols.
sion of the variable that the coefficient is multiplying for that Thus K +L − 1 symbols are transmitted from each antenna. At
instant in time. This allows the adaptive algorithm to inte- the receiver, the CP is stripped off and then an FFT is taken
grate very closely with the filters, although RLS was found to of the remaining K symbols from each antenna. The signal at
be less optimal in this respect [15]. the ith antenna (after FFT) for the kth time (or tone) is given
J. Dowle et al. 9
LMS LMS
controller
+ −
+
.
. +
.
MV–DFE
Figure 6: Architectural structure of the AMV-DFE-MIMO receiver showing the data path from transmitters through the MIMO DFE
structure and adaptive algorithm. This is entirely implemented in FPGA.
Training en
Filter weights
LMS Training seq.
RAM
RAM
Data in1
+
Data in2 +
+ −
Data in3
Data in4 +
fb out
+ 8 PSK quantizer
−
Filter weights
LMS
RAM
fb in1
+
π/4 DQPSK Decision out
fb in2 decision device
fb in3
by If we now define
MT −1
L
yi [k] = ωi, j [k]s j [k] + ni [k] for i = 1, 2, 3, . . . , MR , H[k] = G[l]e− j(2πld/K) (15)
j =1 l=0
(13)
as the MIMO channel impulse response matrix for the kth
where ni [k] designates additive noise and ωi, j [k] is the FFT tone computed from the FFT of the time domain channel
of the channel impulse response: impulse response matrix for the L taps, so
−1
L
− j(2πld/K) H[k]i, j = ωi, j [k] . (16)
ωi, j [k] = gi, j [l]e for k = 0, 1, 2, . . . , (K − 1).
l=0 So H[k] is an MR × MT matrix, y[k] and n[k] are MR element
(14) vectors, and s[k] is an MT element vector. The MIMO model
10 EURASIP Journal on Applied Signal Processing
I1
LP
BPF DAC RFMOD
LP
Q1
sin (WIFt + π/4)
Figure 8: OFDM-MIMO transmit structure showing those elements that had been implemented in FPGA (shaded) and those offline in
Matlab (unshaded), but with only a single RF chain reproduced for clarity. For some tests, the Matlab/FPGA interface was actually moved
up to the BPF rather than at the CP insertion block for convenience. S/P and P/S are serial-to-parallel and parallel-to-serial converters,
respectively.
I1
S/P CP FFT P/S
Channel estimation
Q1
I2 Synchronization MIMO
frequency offset S/P CP FFT P/S decoder
Q2
using
I3 estimation and
S/P CP FFT P/S MMSE Data out
Q3 correction
or ML
I4
Q4 S/P CP FFT P/S
Figure 9: OFDM-MIMO receive structure showing those elements that had been implemented in FPGA (shaded) and those offline in Matlab
(unshaded), but with only a single RF chain reproduced for clarity. For some tests, the Matlab/FPGA interface was moved to the decimator
rather than the CP block for convenience. S/P and P/S are serial-to-parallel and parallel-to-serial converters, respectively.
equation now becomes allow repeatable tests to be performed with static data when
necessary and allow as well a range of different data packets
to be tested as required.
y[k] = H[k]s[k] + n[k] for k = 0, 1, 2, . . . , (K − 1). (17)
In terms of packet data structure, since receive data is
four times oversampled, there are 640 synchronization chips
In summary, the MIMO-OFDM method configures the fre- and 2560 training chips (multiplexed between antennas as
quency selective channel of bandwidth B into K orthogonal shown in Figure 10 and including CP), followed by 10 data
flat fading channels, each of B/K bandwidth. words comprising 3200 OFDM chips (again including CP).
In the FPGA implementation, an over-air frame struc- It was found that the ring time of the combined analogue
ture as shown in Figure 10 was formatted, controlled, and RF filters extended 96 chips beyond the total 6400 structured
synchronized in the FPGA, with ten consecutive data words chips in a packet, and thus a guard time was inserted between
transferred in each packet. For experimental purposes, ran- packets to accommodate this.
dom or Matlab-generated data was uploaded to FPGA and Time synchronization was performed by correlation be-
used in transmission continuously until such time as the tween synchronization words—gross synchronization was
data was adjusted. This obviously differs from the implemen- implemented in FPGA, whilst fine oversampled alignment
tation required in a production implementation, but does performed in Matlab using standard techniques.
J. Dowle et al. 11
Figure 10: OFDM-MIMO on-air packet structure, including synchronization, training, and data words, formatted, and controlled in FPGA,
for 4 × 4 experimental test setup. There were a total of 10 data words transmitted per antenna per packet.
The frequency offset, foff , at a function of the sampling chosen methods covered a wide span of possibilities. This was
instant, for Tc training duration (Nc symbols) at fs sampling a deliberate approach to build expertise in the design team,
frequency, was estimated by determining the phase angle of and test as wide a variety of algorithm types and modulation
the timing detection metric: formats as possible. Note also that although 12-channel
sounding tests have been performed to prove platform in-
tegrity, at the time of writing, a full 12-channel MIMO im-
θ τsync fs λ τsync plementation has not been completed using the platform.
foff τsync = = , (18)
2πTc 2πNc
5. ANALYSIS OF STAR DEVELOPMENTS
where θ(τ) is the phase angle of the sum of the correlations
of training symbols (which can be calculated unambiguously The STAR platform development began with a very brief
within a range equal to half the subcarrier spacing). initial exploratory phase followed closely by simultaneous
Experience revealed that whilst the system was highly tol- platform development and academic search and evaluation
erant to timing synchronization errors, frequency offset es- to determine suitable algorithmic approaches. The hard-
timation was the single most critical factor in the OFDM- ware platform comprises enclosure, power supplies, high-
MIMO performance. Bearing in mind that this was a QPSK precision clocks synthesizer, RF, mixed-signal, and digital
system, it is expected to be significantly more critical when components on 23 printed circuit boards (PCBs). The total
utilising higher density constellations. development time for the first working non-MIMO system,
Back-end Matlab processing allowed a comparison of ML a multichannel channel sounder, was 10 months.
and MMSE decoding. Although currently uncorroborated,
preliminary indications show that ML, whilst normally pro-
5.1. Development phases
viding higher performance than MMSE, tends to perform
worse when frequency offset estimation errors occur. It is also The first algorithm implementation was TR-STBC, and
evident that, at high receive power levels, MMSE and ML es- utilised most of the 12 engineers for approximately 4 months,
timates tended to converge. although evaluation and testing continued with fewer engi-
neers for longer. At the close of the TR-STBC subproject de-
4. IMPLEMENTATION ISSUES ASSOCIATED velopment, a decision was made to continue on with AMV-
WITH THE ALGORITHMS DFE-MIMO and OFDM-MIMO developments in parallel
since sufficient STAR platforms existed.
Each of the three implemented systems followed the imple- The same 12-member engineering team cooperated on
mentation methodology of Section 3.2 and resulted in work- both implementations. The OFDM-MIMO system FPGA
ing systems that allowed the investigation of algorithm op- component was limited to pulse shaping of stored trans-
eration under various real operating scenarios. The test plat- mit data, receiver front-end, decimation, simple filtering,
forms were mobile, and antenna construction modular such and data capture subsystems. Actual OFDM decoding was
that various geometries could be explored. Table 3 compares performed offline using Matlab. This system was thus suf-
the implementations, and although far from an exhaustive ficient to explore the implementation of the high-band-
list of possible MIMO and space-time algorithm options, the width OFDM-MIMO front end and the effects of different
12 EURASIP Journal on Applied Signal Processing
channels, antennae, and gains, but was not encumbered by Research on these effects is ongoing, but with relevance to
channel estimation, FFT design, and data reconstruction is- compensation algorithms more so than to a discussion of im-
sues. However these final three issues have been demon- plementation platform. Antennae were in a proprietary steer-
strated as FPGA implementations by other authors, most no- able multielement patch arrangement to be published sepa-
tably Wouters et al. [17] in the 2 × 2 PICARD demonstrator, rately.
and discussed by Kaiser et al. in [16], as well as in the DFE-
MIMO and TR-STBC systems here (excluding the FFTs).
6. CONCLUSION
Approximately 3 months were required to deliver the fi-
nal two working MIMO systems, with only two engineers al- Firstly, the use of programmable FPGA logic for performing
located to constructing the OFDM-MIMO implementation. MIMO and space-time baseband signal processing has been
Again indoor and outdoor evaluative testing programmes demonstrated. The claim is that this required less effort, and
followed the developments using a reduced team. resulted in a more stable system than a similar DSP-based
implementation, and that certainly follow-on developments
5.2. Development team would undoubtedly benefit in this way.
Secondly, that the enormous processing capability of a
The full engineering team comprised 3 recent graduates, 4 platform like STAR is sufficient to implement several vari-
engineers with 1 to 3 years experience, 3 senior engineers, eties of space-time algorithm, that these can be developed
one principal engineer, and a project manager. One of the se- rapidly and accurately using only FPGAs for baseband signal
nior engineers was devoted to Matlab simulations and none processing. Details of three example implementations have
of the team had experience of FPGAs or VHDL, although been presented, with performance data published elsewhere.
several had experience porting algorithms to DSP. Each implementation was the first-known implementation
The timescales indicate that, although the initial invest- of the relevant technique, either in real time, or using an
ment in equipment and the learning-curve for FPGA devel- FPGA-based system.
opment were large, given such a newly experienced team, the
time required to utilise the hardware in different ways to ex- ACKNOWLEDGMENTS
plore three diverse ST/MIMO algorithms was not excessive.
This work was partially funded by the NZ Foundation for Re-
5.3. Experimental conditions search, Science, and Technology. Thanks are due to Andrew
Jones for his RF and platform design and the diagrams of
Channels test environments for all implementations in- Figures 1 and 2. Finally, the efforts of the entire Tait Electron-
cluded interior office space, university campus, parkland, ics Ltd. Group Research STAR team are gratefully acknowl-
urban street-scape, and building-to-building link. Distances edged.
ranged from approximately 3 m to 500 m with the majority
of indoor tests confined to below 40 m [2]. Channel rank
problems were endemic, with the DFE-MIMO system [15] REFERENCES
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[8] E. Lindskog and A. Paulraj, “A transmit diversity scheme tronics Ltd., Christchurch as a Design En-
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IEEE International Conference on Communications (ICC ’00), processing using field programmable gate
vol. 1, pp. 307–311, New Orleans, La, USA, June 2000. arrays (FPGA), multiple-input multiple-
output (MIMO) communications systems, and electronic hard-
[9] P. Stoica and E. Lindskog, “Space-time block coding for chan-
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degree from the University of Canterbury,
November 2001.
Christchurch, New Zealand, in 2000, work-
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of IEEE International Conference on Acoustics, Speech, and Sig- sign Engineer, working on space-time and
nal Processing (ICASSP ’02), vol. 3, pp. 2405–2408, Orlando, MIMO algorithms for digital wireless com-
Fla, USA, May 2002. munications. In 2005, he began working to-
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Australia, December 2003. Honour Society.
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Multiuser detection and interference rejection,” Ph.D. disser- derabad, India, from 1979 to 1996, and in
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from 1996 to 1998. He served as an As-
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sistant Professor in the Department of Aerospace Engineering in
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the Indian Institute of Science, Bangalore, India, from 1998 to
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1999, where he taught a part of the course in navigation, guid-
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burg, Va, USA, June 2004.
Tait Electronics Ltd, Christchurch, as a Senior Design Engineer.
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European Signal Processing Conference (EUSIPCO ’04), Vienna, thogonal frequency division multiplexing (OFDM), multiple-input
Austria, September 2004. multiple-output (MIMO) communication systems, and power am-
[17] M. Wouters, P. Van Wesemael, R. Vandebriel, A. Dewilde, and plifier linearization. He holds patents in the areas of adaptive time
M. Libois, “Real time prototyping of broadband wireless LAN division duplexing, network timing protocol, and digital commu-
systems,” in Proceedings of IEEE 15th International Workshop nication system.
14 EURASIP Journal on Applied Signal Processing
Preliminaryȱcallȱforȱpapers OrganizingȱCommittee
HonoraryȱChair
The 2011 European Signal Processing Conference (EUSIPCOȬ2011) is the MiguelȱA.ȱLagunasȱ(CTTC)
nineteenth in a series of conferences promoted by the European Association for GeneralȱChair
Signal Processing (EURASIP, www.eurasip.org). This year edition will take place AnaȱI.ȱPérezȬNeiraȱ(UPC)
in Barcelona, capital city of Catalonia (Spain), and will be jointly organized by the GeneralȱViceȬChair
Centre Tecnològic de Telecomunicacions de Catalunya (CTTC) and the CarlesȱAntónȬHaroȱ(CTTC)
Universitat Politècnica de Catalunya (UPC). TechnicalȱProgramȱChair
XavierȱMestreȱ(CTTC)
EUSIPCOȬ2011 will focus on key aspects of signal processing theory and
TechnicalȱProgramȱCo
Technical Program CoȬChairs
Chairs
applications
li ti as listed
li t d below.
b l A
Acceptance
t off submissions
b i i will
ill be
b based
b d on quality,
lit JavierȱHernandoȱ(UPC)
relevance and originality. Accepted papers will be published in the EUSIPCO MontserratȱPardàsȱ(UPC)
proceedings and presented during the conference. Paper submissions, proposals PlenaryȱTalks
for tutorials and proposals for special sessions are invited in, but not limited to, FerranȱMarquésȱ(UPC)
the following areas of interest. YoninaȱEldarȱ(Technion)
SpecialȱSessions
IgnacioȱSantamaríaȱ(Unversidadȱ
Areas of Interest deȱCantabria)
MatsȱBengtssonȱ(KTH)
• Audio and electroȬacoustics.
• Design, implementation, and applications of signal processing systems. Finances
MontserratȱNájarȱ(UPC)
Montserrat Nájar (UPC)
• Multimedia
l d signall processing andd coding.
d
Tutorials
• Image and multidimensional signal processing. DanielȱP.ȱPalomarȱ
• Signal detection and estimation. (HongȱKongȱUST)
• Sensor array and multiȬchannel signal processing. BeatriceȱPesquetȬPopescuȱ(ENST)
• Sensor fusion in networked systems. Publicityȱ
• Signal processing for communications. StephanȱPfletschingerȱ(CTTC)
MònicaȱNavarroȱ(CTTC)
• Medical imaging and image analysis.
Publications
• NonȬstationary, nonȬlinear and nonȬGaussian signal processing. AntonioȱPascualȱ(UPC)
CarlesȱFernándezȱ(CTTC)
Submissions IIndustrialȱLiaisonȱ&ȱExhibits
d i l Li i & E hibi
AngelikiȱAlexiouȱȱ
Procedures to submit a paper and proposals for special sessions and tutorials will (UniversityȱofȱPiraeus)
be detailed at www.eusipco2011.org. Submitted papers must be cameraȬready, no AlbertȱSitjàȱ(CTTC)
more than 5 pages long, and conforming to the standard specified on the InternationalȱLiaison
EUSIPCO 2011 web site. First authors who are registered students can participate JuȱLiuȱ(ShandongȱUniversityȬChina)
in the best student paper competition. JinhongȱYuanȱ(UNSWȬAustralia)
TamasȱSziranyiȱ(SZTAKIȱȬHungary)
RichȱSternȱ(CMUȬUSA)
ImportantȱDeadlines: RicardoȱL.ȱdeȱQueirozȱȱ(UNBȬBrazil)
P
Proposalsȱforȱspecialȱsessionsȱ
l f i l i 15 D 2010
15ȱDecȱ2010
Proposalsȱforȱtutorials 18ȱFeb 2011
Electronicȱsubmissionȱofȱfullȱpapers 21ȱFeb 2011
Notificationȱofȱacceptance 23ȱMay 2011
SubmissionȱofȱcameraȬreadyȱpapers 6ȱJun 2011
Webpage:ȱwww.eusipco2011.org