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Description

The RiLa opamp is an experimental amplifier that is made of 10 N-Channel Metal Oxide
Semiconductor Field Effect Transistors and 5 PNP and 3 NPN Bipolar Junction Transistors.

PART NAME SIZE

RiLa 70mm x 100mm x 35mm

Pin Name I/O Description

V+ I Positive Supply Voltage

V- I Negative Supply Voltage

Vin- I Inverting Signal Input

Vin+ I Non-Inverting Signal Input

GND N/A Ground

Output O Amplified Signal Output

PIN TOP VIEW


Absolute Maximum Ratings

PARAMETER MAX UNIT

Supply voltage ±9 V

Power dissipation 1.72 W

Input voltage ±6 V

Electrical characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

offset voltage Vs=​±9V 400 mV

Input voltage -6 6 V

Open loop gain Vs=​±9V 0,177 V/mV

Output swing Vs=​±9V, RL=10kΩ -7 7.9 V

Common-mode Vcm=100mV, 48 dB
rejection ratio

Slew rate unity gain 3.306 V/μs

Supply current Vs=​±9V 31.9 mA


Experimental bode phase diagram
Detailed Description

This opamp have three main stages, a differential pair with active load, a common
source gain stage and a Class AB output stage. First and second stage have wilson
current mirror. The differential pair consists of two 2n7000 transistors M1 and M2. It
was seek to ensure a single ended gain of 30dB fixing a polarization current of 10mA
by the means of calculation of a reference resistance R1. This polarization current is
generated by the wilson current mirror formed by M4 and M3.
Av = gmM 2 (roM 2 //roQ2 ) (1)
The equation (1) comes from taking the half differential equivalent circuit, assuming
symmetry.
By replacing on equation (1) the known parameters.
VA VA
Id
Av = V GS −V tM 2
( IdM 2 // IdQ2 )
M2
5×10−3
31, 6 = ( 5,79 // 100 )
V GS −1,498 5×10−3 5×10−3
M2

⇒ V gsM 2 = 1, 68V
Having in mind that the Gate is ground connected,
V GS M 2 = V GM 2 − V S M 2 =− V S M 2 =− 1, 68V
The source voltage of M2 is equal to M3‘s drain voltage,
V S M 2 = V DM 3 =− 1, 68V
To obtain the gate voltage of M3, first drain voltage of M4 is obtained using
2Id = β M 4 (V GS M 4 − V tM 4 )2 (1 + λM 4 V DS M 4 ) (2)
27,5×10−3
βM 3 = (1)2 (1+0,049×1,6)
= 0, 025

from (2)
2Id = β M 4 (V GM 4 − V S M 4 − V tM 4 )2 (1 + λM 4 (V DM 4 − V S M 4 )) (3)
VG = VD =VX
M4 M4

⇒ V X =− 6.91v = V sM 3
To obtain V G :
M3

2Id = β M 3 (V G −VS − V tM 3 )2 (1 + λM 3 (V D − V S ))
M3 M3 M3 M3

VG =− 4.9v
M3
V DD −V G 9−(−4.9)
RREF = M3
= = 1400Ω
2Id 10×10−3

With the common source stage was looked towards adding a 20dB gain to the
already obtained gain at the output of the differential pair. This stage also have a
wilson current mirror. A capacitor was used as signal ground, to eradicate the effect
of the current source resistance on the gain. The drain resistance R4 of this stage
was calculated to satisfy the desired gain.
To calculate the drain resistance to obtain the desired gain it was used the gain
equation Av = g m(roM 6 //Rd)

VA
M6
Av roM 6 Av
⇒ Rd = gm roM 6 −Av
= Id
VA
√2β M 6 Id M6
Id −Av

The result is R4 shown in the schematic.


Between differential pair and common source stages another stage was added to
obtain a negative voltage in the source of M6. With this a better output swing voltage
was obtained.
Finally the output stage was made to provide the amplifier with a low output
resistance so that it can deliver the output signal to the load without loss of gain.
Before the class AB output stage, a voltage follower was implemented to lower the
DC level of the signal.
The offset resistance R10 was varied until obtain a good value of offset.

To improve the margin phase and make the system stable miller compensation was
used. 1nF capacitor was added to common source stage (C4).

To measure slew rate the RiLa opamp was configured as buffer and a square wave was the
entrance. In vs out is shown below
The CMRR was calculated by applying a common mode voltage over the inverting
and non-inverting inputs. subsequently, the output was measured.

According to the obtained data, the following equation is applied:

where A is the Open Loop Gain.

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