ICGST- AIML journal, ISSN: 1687-4846, Volume 9, Issue 2, December 2009

Simulation Based ATPG for Crosstalk Delay Faults in VLSI Circuits using
Genetic Algorithm
S.Jayanthy1, M.C.Bhuvaneswari 2
1
Asst.Professor, Department of ECE., Sri Ramakrishna Engineering College, Coimbatore, India
2
Asst.Professor, EEE Department, P.S.G. College Of Technology, Coimbatore, India
sjayanthyabi@yahoo.co.in

Abstract validated chip to malfunction and lead to performance

As design trends move toward nanometer technology,
new Automatic Test Pattern Generation (ATPG)
problems are emerging. During design validation, the
effect of crosstalk on reliability and performance cannot
be ignored. So new ATPG Techniques has to be
developed for testing crosstalk faults which affect the
timing behaviour of circuits. In this paper, we present a
Genetic Algorithm (GA) based test generation for
crosstalk induced delay faults in VLSI circuits. The GA
produces reduced test set which contains as few as
possible test vector pairs, which detect as many as
possible crosstalk delay faults. It uses a crosstalk delay
fault simulator which computes the fitness of each test
sequence. Tests are generated for ISCAS’85 and scan
version of ISCAS’89 benchmark circuits. Experimental
results demonstrate that GA gives higher fault coverage
and compact test vectors for most of the benchmark
circuits.
Keywords: Crosstalk delay faults, Genetic algorithm,
ATPG, Fault simulator.
1. Introduction
As a consequence of technological advances which have
resulted in an increase of VLSI chip density, increased
number of interconnect layers and in an improvement of
timing performances, the test for static stuck-at faults
only has turned out to be insufficient, and it is now also
required to deal with physical defects which affect the
timing behavior of a given circuit. Various noise sources
such as crosstalk and power supply noise has a
significant impact on the timing performance of deep
submicron design (DSM) designs. The increasing number
of transistors in the chip leads to more devices switching
simultaneously resulting in power supply noise which
reduces device voltage levels and increases signal delay.
Interconnection lines which were assumed to be
electrically isolated can now interfere with each other
leading to functional problems. One such interaction
caused by parasitic coupling between wires is known as
crosstalk. These noise effects can cause completely
degradation of deep submicron design.
There are two main types of cross talk effects: cross talk
induced pulses and cross talk induced delay. The type of
cross talk effect dealt in this paper is cross talk induced
delay. Cross talk delay is induced when two lines, an
aggressor line (A-line) and victim line (V-line) have
simultaneous or near simultaneous transitions, which
may cause undesirable effects including glitches, increase
or decrease in the signal delay [1]. If both the lines transit
in the same direction, the effective delay is reduced
leading to crosstalk speedup. If aggressor and victim
transit in the opposite direction then there will be an
increase in delay leading to crosstalk slowdown.
The designer has two options to eliminate errors caused
by crosstalk either by resizing drivers, rerouting signals,
shielding interconnect lines and other such redesign
techniques or to develop techniques to generate tests for
crosstalk.
The latter option is often taken by designers as redesign
may be very expensive. Moreover test generation for
crosstalk also enables more aggressive design and
enables more comprehensive post-manufacturing testing.
In this paper, we present a GA based test generation
algorithm for crosstalk delay faults. The GA generates
candidate test vectors and the crosstalk delay fault
simulator computes the fitness of candidate test vectors.
The remainder of the paper is organized as follows.
Section 2 discusses prior work. Section 3 describes the
algorithm for finding a reducing list of target faults,
Section 4 gives a brief description of crosstalk delay fault
simulator, Section 5 describes the features of GA, Section
6 describes test generation in GA framework and Section
7 presents the experimental results for ISCAS’85 and
scan version of ISCAS’ 89 benchmark circuits. The paper
is concluded in Section 8.
2. Prior Work
Rubio, Itazaki, Xu and Kinoshita[2] proposes a
methodology which is based on a search for a two
vectors input pattern that forces a determinate value to
the affected nodes and provokes a transition of the
affecting lines allowing the propagation of the possible

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 ICGST- AIML journal, ISSN: 1687-4846, Volume 9, Issue 2, December 2009
noise effect to the primary output nodes. The relationship
of transition propagation in logic circuits has been used
to generate the test patterns. Their paper deals with
crosstalk pulses.
Chen, Gupta and Breuer [3, 4, 5] have given a mixed
signal test generator XGEN, for crosstalk induced delay
faults. They proposed a mixed signal test generation
process where characteristics of crosstalk induced noise
are accurately modeled. By using Laplace
transformations they have obtained an expression for
crosstalk in the s-domain, which they have transformed
back to the time domain. These expressions are used to
quantify the dependence of the pulse attributes on the
lumped circuit parameters and the rise time of the input
transition. Static timing analysis provides timing
windows at gate inputs and outputs. The target timing
window is the intersection of the aggressor and victim
timing window. For a specific target coupling fault a pair
of vectors create a crosstalk effect at the target and either
a logic error or delay at the primary output. Their ATPG
algorithm uses 11 valued algebra, analog delays and
modified Path oriented decision making algorithm
(PODEM) for back trace procedure. Their algorithm is
not complete because of restricted propagation conditions
of fault effects, and a constrained logic value system is
used.
Krstic, Liou, Jiang and Cheng [6] developed a
constrained path delay model as a combination of a
critical path and a set of crosstalk noise sources
interacting with the path. It uses a conventional path
delay ATPG process without justification to sensitize the
fault. Then a genetic algorithm is used to deal with
timing information and justification of effecting
transitions to primary inputs.
In [7] Xiaoliang Bai, Sujit Dey and Angela Krstic have
proposed a solution for multiple aggressor crosstalk
problems. In their work, an implication graph is
constructed that consists of logic variables and structural
information to check for logic conflicts. A modified
version of PODEM algorithm is used to search for test
vectors.
Aniket and Arunachalam [8] proposed an algorithm for
testing crosstalk induced delay faults. Their algorithm
generates a list of critical paths by static timing analysis
of the circuits. A robust testability criterion is applied to
check for sensibility of the paths. For a sensitable path
the associated aggressors –victim pairs are activated in a
manner that will maximize the aggressor influence on the
path to induce maximum crosstalk slowdown along a
path.
H. Li and X. Li [9] proposed a test generator which uses
a single precise crosstalk delay fault model. A sub path is
sensitized to generate necessary transitions coupled to a
path. A path delay fault ATPG is modified for targeting
crosstalk constrained path delay faults. In order to reduce
the numbers of target faults constraints are added on the
sub path and states are pre specified during test
generation for the critical path.
Palit, Duganapalli, Anheier [10] have developed a test
generator for crosstalk faults using modified PODEM
algorithm. In order to test crosstalk faults suitable
transitions are applied at primary inputs individually to
induce specific signal transitions at aggressor and victim
12
lines and to propagate the effect at victim to at least one
primary output. Then combining them will give the
transition test vector for crosstalk fault.
Chun, T. Kim, Y. Kim, M.H.Yang and S.Yang [11] have
proposed an ATPG which finds test patterns for crosstalk
delay faults using don’t care values in delay test patterns
generated by a conventional path delay fault ATPG. The
don’t care values are used to apply some extra constraint
transitions which makes crosstalk-induced noise
maximal.
Ganeshpure, Kundu [12] have given an ATPG that
combines 0-1 Integer Linear Program with traditional
stuck-at fault ATPG. The maximal aggressor activation is
formulated as a linear programming problem while the
fault effect propagation is treated as an ATPG problem
and the gate delays are subsumed by a circuit
transformation.
It can be seen that most of these test generation
algorithms involves backtracking through components
which is time consuming.
In a simulation based approach processing occurs in the
forward direction only and no backtracking is required.
Chary and Bushnell [13] have developed a simulation
based crosstalk delay fault test generation for coupling
faults. They used a crosstalk candidate reduction
algorithm which produces a compact set of target faults
by removing those faults that can never be excited or
detected .A multiple delay sequential fault simulator is
used to generate path-delay fault tests. An analog macro
model is used to precompute the delay appearing on a
interconnect due to the coupling fault. They have
assumed only one aggressor and one victim for each
coupling fault. Moreover their input test patterns were
random vectors.
Saluja and Phadoongsidhi [14] have proposed a fault
simulator for crosstalk delay faults caused by coupling
between multiple aggressor and single victim signal
lines. They have used a binary logic digital simulator to
generate crosstalk delay tests. But their input test vectors
were test vectors for stuck-at faults.
The simulation based techniques proposed have a
disadvantage that good heuristics are required to generate
test vectors and test sets were larger.
Our work uses GA to produce short, high quality test
vectors and reduce simulation time.
3. Static timing analysis
The number of crosstalk faults between all possible
combinations of A-lines and V-lines are very large and
impractical to detect for large complex circuits. Some of
the faults cannot be tested or need not be tested in a
circuit. Hence reduced set of crosstalk delay faults are
derived by static timing analysis of the circuit. The
number of critical paths and the lines that lie on the
critical path are calculated using the topological and
timing information. Then the lists of target faults are
obtained which are smaller than the set of all possible
combinations of faults.
The algorithm for calculating the reduced target fault list
[15].
1. The latest transition time and the earliest transition
time for each line are calculated.
 ICGST- AIML journal, ISSN: 1687-4846, Volume 9, Issue 2, December 2009
2. From the maximum value of the latest transition time
the longest path (critical path) is found. The lines in the
longest path are found. These form the set of victim lines.
3. The timing window of the selected victim line is
compared with aggressor line and if the windows overlap
than that selected V- and A- line pair is added to the
target fault list.
The input fault list to the simulator is the reduced set of
target faults.
4. Crosstalk delay fault simulator
Given a test vector sequence as inputs, the objective of
the fault simulator is to determine which of these faults
are detected. Faults Detected are those that cause a logic
error that is, a glitch at the POs. The delay effect at the
primary output is also noted.
The basic simulator is time wheel based event driven
simulator [16].It uses three valued logic.The fault
simulator is capable of detecting n-aggressor/single
victim faults.
Fault simulation based ATPG Algorithm.
1. Simulate the good circuit for random vectors.
2. Read the fault from the fault list.
3. Simulate the good and bad circuits for the fault for
each vector.
4. The victim and aggressors should have opposite
transition. Then fault is activated.
5. Inject the fault by delaying the victim alone by a time
step equal to one unit delay. Other events are scheduled
as usual as for a good circuit. Continue simulation until
the end of timeframe.
6. Compare the values at all POs and sequential inputs
with the good circuit.
7. If the good and bad circuits differ, then fault is
detected and the victim and activated aggressors pairs
are removed from the fault list.
8. Repeat from step2 for all the faults in the fault list.
9. Read the next vector and repeat steps 2 to 8.
A H
P
M
B L
N Mutation operator
C J
I Q
F
K Replacement strategy
G
O
Figure 1. Example circuit
In Figure1, it was found from the static timing analysis
that the example circuit consist of six longest paths
namely:[C,I,L,P],[F,I,L,P], [C,I,L,Q],[C,I,O,Q],[F,I,L,Q]
and [F,I,O,Q]. The victim set is [C, F, I, L, O, P, Q].The
total number of target crosstalk faults for the circuit is 42.
Two patterns (00001, 01000) are applied at the primary
inputs of the logic circuit. The set of aggressors /victim
taken for consideration are [H, I, O, P, Q/L]. Aggressors
O, P are activated. Hence the victim L is given a one unit
delay in the logic cone. A glitch is observed on Q and
delay effect is observed on P. The activated aggressors
13
are removed from the fault list. The other aggressors are
considered for the next test pattern. The other faults are
read from the fault list and fault simulation is done. The
whole process is repeated for all the test vectors in the
test set.
5. Overview of Genetic Algorithms
In the area of VLSI test, GA has been successfully used
in stuck-at fault test and gate delay fault test. The
simplicity, robustness, efficiency and effectiveness of
GA make them a promising tool for complex
applications. GA maintains a population pool of
candidate solutions called strings or chromosomes. Each
string is associated with a fitness value determined by a
user defined fitness function.
Figure 2 shows the flowchart of GA. GA starts with an
initial population typically generated randomly and the
evolutionary process of reproduction, crossover and
mutation are used to generate an entirely new population
from the existing population. The new population and the
existing population compete for membership in the
generation’s membership pool. Selection of the
chromosomes for new population is governed by the
replacement strategy. The old population is discarded.
The sequence of selection, crossover mutation completes
one-generation cycle. GA progresses through generations
until the goal is reached such as fixed number of
generations. [17]- [21].
.
Start
Generate initial population
Reproduction operator
Cross-over operator
Criteria
met
Yes
No
End
Figure 2. Flow chart of genetic algorithm
6. GA based test generation algorithm.
The goal of crosstalk delay fault test generation is
generating a reduced test set, which contains as few as
 ICGST- AIML journal, ISSN: 1687-4846, Volume 9, Issue 2, December 2009

possible test vectors as possible. This is essentially a Phase II

process exploring the space of test vector pair. So GA
can be utilized to optimize the process of exploring.
Every test vector/sequence can be treated as an individual
or string. Thus we can view the number of test
vector/sequence pairs as a population. To assess every
test vector/sequence pair in a population in any
generation of evolution, the crosstalk delay fault
simulator is suitable.
The pseudo code for GA based ATPG algorithm
presented in this paper is shown in Figure 3.The ATPG
algorithm performs in two phases. In the first phase the
initial population of test vectors and sequences are
generated by pseudo random process. In the second phase
the GA phase, the test vectors are evolved based on
fitness function. The fitness function used is:
Fitness = NFi
Where NFi is the number of faults detected.
{ used is one point crossover. A crossover probability of 1
FL= {reduced set of crosstalk delay faults}
initial pop=phase I (FL);
if (FL =NULL)
break;
phase II (initial pop, FL);
} for (l=0;l<no_gen;l++)
Figure3. Pseudo code of overall GA based ATPG algorithm
Phase1
In this phase the initial sequences composed of M vectors
are generated based on pseudo random process. The
generated sequences are fault simulated for the faults in
the fault list. If the sequence detects fault that fault is
removed from the fault list and the corresponding
sequence is added into the solution set. If no faults are
detected by the sequence, then the last sequence
generated in the corresponding cycle is added to the set.
This process is repeated for max_iter. The pseudo code
of phase I is shown in Figure 4.
The initial population of GA is composed of the
sequences generated in phase I. To generate a new
population from the existing one, two individuals
(parents) are selected and crossed to create two entirely
individuals (child) and each child is mutated with some
small mutation probability. The selection operator is rank
based selection. In rank based selection, the solutions are
sorted according to their fitness from the worst (rank1) to
the best (rankN).Each member in the sorted list is
assigned a fitness equal to the rank of the solution in the
list. Thereafter the proportionate selection operator is
applied with the ranked fitness value and better solutions
are chosen. The two parents are crossed to create two
entirely new individuals (i.e.) child and each child is
mutated with some small mutation probability. The two
new individuals are than placed in the new population
and the process continues until the generation is entirely
filled. The previous population is discarded. Crossover
and mutation probability of 0.01 is used in all circuits.
The no_gen is assumed to be 8, to reduce the execution
time. During test generation pop_size of 16 is used. The
pseudo code for phase II is shown in Figure 5
Function Phase II
{
Initial pop from phase1;
{for (k=0; k<popsize;k++)
{select two individuals from
population;
apply crossover with probability 1;
apply mutation with probability 0.01;}
compute fitness of the individuals;
for (each sequence)
if (sequence detects the faults in the fault list
{ add sequence to the solution set;
drop the faults detected by the
sequence;
}
}
}

Function Phase I Figure 5 Pseudo code of phase II of GA based ATPG algorithm

initial pop (FL)
For (i=0; i<max_iter, i++) 7. Experimental results
{ The crosstalk delay fault simulator and genetic algorithm
initial pop=phase I(FL); based test generator is implemented in 3700 lines of C
randomly generate sequences of length L; language under the LINUX environment on an IBM
for (each sequence) compatible PC. The random and GA based ATPG is
{if sequence detects faults in the fault list applied to ISCAS’85 combinational circuits and several
{ scan version of ISCAS’89 sequential circuits. Table 1
add sequence to the test set; gives the characteristics of ISCAS’85 combinational
drop the faults detected by that sequence; circuits and the scan version of ISCAS’89 sequential
} circuits. After the circuit name, the number of primary
} inputs (PIs), number of primary outputs (POs), number of
return (initial population); gates, number of paths and the number of critical paths
} are given. The entire circuit paths are analyzed using the
tree data structure. The total number of paths in the
Figure 4 Pseudo code of phase I of GA based ATPG algorithm
circuit is calculated using depth first search algorithm
which employs recursive search procedure. Critical paths
are paths whose delay is longer than a given percentage
of the longest propagation delay in the circuit. The

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 ICGST- AIML journal, ISSN: 1687-4846, Volume 9, Issue 2, December 2009

selection is done using static timing analysis and given Table 1: The ISCAS’85 AND ISCAS’89 Circuit
gate delay. The gate delay for static timing analysis is characteristics
assumed to be one time unit. No. of No. of No. of
No. of No. of
Table2 and Table 3 shows the coupling fault coverage Circuit
PIs POs Gates
total critical
obtained for a few benchmark circuits. Fault effect at PO paths paths
gives the number of faults for which delay effect due to c17 5 2 6 11 6
the coupling fault was noticed at the primary output. c432 36 7 160 83926 2199
Faults detected are those that cause a logic error at the c499 41 32 202 9440 14
primary output. As it not practical to test all faults for
c880 60 26 383 8642 92
large circuits reduced set of target faults are calculated by
selecting victims which lie in the critical path and for s27 7 4 10 28 6
each fault the aggressor-victim timing window should s208 19 10 96 145 2
overlap. The input fault list for each circuit consists of s208.1 18 9 104 142 1
every combination of single aggressor/single victim
s298 17 20 119 231 1
pairs. Gates are assumed to have a unit delay and the
crosstalk delay value to be injected is also assumed to be s344 24 26 160 355 1
one time unit. s349 24 26 161 365 1
The bold number in Table2 and Table 3 represents the s386 13 13 159 207 10
maximum number of faults detected for each circuit for
s420.1 34 17 218 474 1
GA compared to random vectors. In Table2 for the
combinational circuit’s c449 and c880 95% of the s510 25 13 211 369 1
coupling faults produced a delay at the primary output. s526 24 27 193 410 1
For 13 of the 15 scan version of the sequential circuits s820 23 24 289 492 11
98%of the coupling faults produced a delay effect at the
s1196 32 32 529 3097 9
primary output. The sequential circuit s1196, s1238 and
combinational circuit c432 with critical paths of 9, 30 s1238 32 32 508 3558 30
and 2199 respectively had produced a delay effect for s1488 14 25 653 962 1
only 86%, 78.2%and 84.8% of the coupling faults s1494 14 25 647 976 1
respectively. This may be due to the fact that the basis for
finding the critical paths and target fault reduction is
static timing analysis which does not consider the false
Table2: Fault Effect at Primary Output
paths.
No. of Fault effect at PO CPU
No. of Time
Circuit target Rando
victims GA (secs)
In Table3 the number faults detected using GA based faults m
ATPG were much greater than random vectors for 17 of c17 7 42 42 42 0.20
the 19 benchmark circuits tested. The numbers of faults c432 103 9327 6629 7918 125.35
detected were about 70% for the combinational circuit’s c449 207 21879 17937 20806 22.7
c432 and c449. For c880 fault coverage of 48%was
reported. The numbers of faults detected were 24% to c880 70 9279 5722 8922 24.68
66% for 10 of scan version of the sequential benchmark s27 10 74 70 72 0.03
circuits. However for some specific scan version of s208 18 743 559 726 1.00
sequential circuit with coupling faults from 4000 to
s208.1 12 558 371 512 1.26
10000 the GA based test generator reported lesser fault
coverage’s of 12% to 18%. The low fault coverage is not s298 10 537 532 533 2.31
unusual because due to conflicting Boolean conditions s344 21 1190 1185 1189 7.53
there are many coupling faults that are impossible to s349 21 1197 1192 1196 7.56
sensitize or to propagate to the primary output. Moreover
s386 49 4195 4152 4189 2.45
the unit delay injected might be insufficient to cause a
logic error at the primary output. For most of the s420.1 14 1276 927 1257 4.05
benchmark circuits compact test vectors were obtained. s510 13 1098 1091 1098 4.76
The CPU execution time shown in Table2 and Table3 is s526 10 891 729 886 4.21
the execution time for GA based test generation. It was
s820 43 7738 7362 7728 11.61
slightly higher for larger circuits. The graph shown in
Figure 6 gives the comparison chart showing the s1196 55 10630 5791 9150 20.03
efficiency of genetic algorithm over random vectors for s1238 45 5822 2764 4556 20.36
different benchmark circuits with respect to the number s1488 18 4305 4302 4304 29.76
of target faults detected.
S1494 18 4283 4280 4282 45.03

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 ICGST- AIML journal, ISSN: 1687-4846, Volume 9, Issue 2, December 2009

Table3: Faults Detected. version of the sequential circuits produced delay effect
No. of CPU for 72% to 99% of the coupling faults. For coupling
Faults detected
Circuit target Time faults that produce a logic error at the primary output the
faults Random GA (secs) method achieved 48% to 72% fault coverage on four
c17 42 19 26 0.20 combinational circuits and 12% to 66% fault coverage on
c432 9327 5548 6540 245.12 15 scan version of sequential circuits. Genetic algorithms
are particularly suitable to parallel implementations, so
c449 21879 6622 15709 593.23
better CPU execution time can be expected by a parallel
c880 9279 180 4414 637.9 GA based test generator.
s27 74 5 28 0.43
s208 743 230 233 6.61 9. References
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Figure 6 Comparison chart
8. Conclusion
The increased design density in deep submicron designs
leads to more significant interference between the signals
because of capacitive coupling or crosstalk which can
produce Boolean errors and delay faults. To guarantee
design performance, ATPG techniques must consider
how crosstalk affects propagation delays.
In this paper crosstalk delay fault simulator in a GA
framework is developed. Redundant crosstalk faults
which never affect the performance of the circuit are
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presented for coupling faults which produces a delay
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[21] S.Jayanthy, M.C.Bhuvaneswari, T.Kavitha
“Simulation Based ATPG For Path Delay Faults
In Digital Circuits Using Genetic Algorithm”,
Proceedings of the National Conference on
Adaptive Sensors & Intelligent Systems
NCASIS’08, pp80-84, November 2008.
17
S.Jayanthy received her B.E
Electronics and Communication
Engineering from Government College
of Technology, Coimbatore and ME
(Applied Electronics) from P.S.G
College of Technology, Coimbatore in
the year 1990 and 2001 respectively.
She is presently working as Assistant
Professor in the department of Electronics and
Communication Engineering at Sri Ramakrishna
Engineering College, Coimbatore. She is currently
pursuing her Ph.D from Anna University, Chennai. and is
a research scholar at P.S.G College of Technology,
Coimbatore. Her areas of interests are VLSI Design and
Testing, Microprocessors, Microcontrollers and Genetic
algorithms.
Dr. M.C.Bhuvaneswari is a faculty in
the department of Electrical and
Electronics Engineering, P.S.G
College of Technology, Coimbatore.
She has completed her B.E in
Electronics and Communication
Engineering in 1986, from
Government College of Technology,
Coimbatore. She has obtained her Doctoral degree in the
area of VLSI Design and Testing, from P.S.G College of
Technology, affiliated to Bharathiar University in 2002.
She has published 32 research papers in National &
International Journals / Conferences. Her areas of interest
are VLSI Design and Testing, Computer Architecture,
Genetic Algorithms and Fuzzy Logic.