Ee 241

EE241
EE241 - Spring 2001

Advanced Digital Integrated Circuits
Tu-Th 12:30 – 2:00pm
203 McLaughlin
UC Berkeley EE241 B. Nikolić
Practical Information
● Instructor: Borivoje Nikolić
570 Cory Hall , 3-9297, bora@eecs.berkeley.edu
Office hours: TuTh 2-3pm
● TA: Engling Yeo,
yeo@eecs
● Admin: Lea Barker

558 Cory Hall, 3-6683, leab@eecs
● Class Web page
http://bwrc.eecs.berkeley.edu/classes/icdesign/ee241_s01
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EE241
Class Organization
● +/- 5 assignments
● 1 term-long design project
» Phase 1: Proposal (by week 3)
» Phase 2: Study (report by week 7)
» Phase 3: Design (presentation and report
by final week)
» Report and presentations last week of
classes
● Final exam
Class Material
● Textbook: “Design of High-Performance

Microprocessor Circuits,” by A.
Chandrakasan, W. Bowhill, F. Fox
● Must be familiar with “Digital Integrated
Circuits - A Design Perspective”, by J. M.
Rabaey
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EE241
Other Books
● Other reference books:
» “High-Speed CMOS Design Styles, by K.
Bernstein, et al.
» “Digital Systems Engineering” by W. Dally
» “High-Performance System Design: Circuits and
Logic,” by V.G. Oklobdžija
» “Low-Power CMOS Design,” by Chandrakasan
and Brodersen
» “High-Speed Digital System Design,” by S.H. Hall,
G.W. Hall, J. A. McCall
» “Logical Effort: Designing Fast CMOS Circuits,” by
I. Sutherland, B. Sproull, D. Harris
Class Material
● List of background material available on
web-site
● Selected papers will be made available
on web-site
» Protected area, or linked from Inspec
● Papers on http://www.melvyl.ucop.edu
● Class-notes on web-site
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EE241
Sources
● IEEE Journal of Solid-State Circuits
(JSSC)
● IEEE International Solid-State Circuits
Conference (ISSCC)
● Symposium on VLSI Circuits (VLSI)
● Other conferences and journals
Lectures online
● The class is webcasted:
» http://bmrc.berkeley.edu/bibs/
● It is also videotaped
● So use the microphones when you ask
questions
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EE241
Class Topics
● This course aims to convey a knowledge of advanced concepts of
circuit design for digital LSI and VLSI components in state of the art
MOS technologies. Emphasis is on the circuit design, optimization, and
layout of either very high speed, high density or low power circuits for
use in applications such as micro-processors, signal and multimedia
processors, memory and periphery. Special attention will devoted to the
most important challenges facing digital circuit designers today and in
the coming decade, being the impact of scaling, deep sub-micron
effects, interconnect, signal integrity, power distribution and
consumption, and timing.
● SPECIAL FOCUS in SPRING 2001:
» high-performance low-power logic (as needed for digital radio)
» interconnect
» timing
» arithmetic circuits
» memory
Class Topics
● Fundamentals - Technology and modeling – Scaling and limits of scaling (1.5
weeks)
● Design for deep-submicron CMOS - HIGH SPEED (3 weeks)
» Static CMOS, transistor sizing, buffer design, high-speed CMOS design styles,
dynamic logic
● Design techniques for LOW POWER (2 weeks)
» analysis of power consumption sources
» power minimization at the technology, circuit, and architecture level
● Arithmetic circuits – adders, multipliers (2 weeks)
● Driving interconnect, high-speed signaling (2 weeks)
● Timing (2 weeks)
» Timing analysis, flip-flop/latch design, clock skew, clocking strategies, self-timed
design, clock generation and distribution, phase-locked loops
● Memory design (2 week)
● Design for test (0.5 weeks)
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EE241
Project Topics
● High-performance low-power logic
● Leakage suppression
● Low voltage design
● Interconnect in deep-submicron
● Arithmetic circuits
● High-speed communication
● Timing of gigascale circuits
● Flip-flops/latches
● Memory circuits
● Other important circuit topics
Suggested Reading
● Chapter 1 – Impact of physical technology on architecture (J.H.
Edmondson),
● Chapter 2 – CMOS scaling and issues in sub-0.25µm systems
(Y. Taur)
● Technology roadmap (http://public.itrs.net) - and try find some
contradictions
● Selected papers from the web:
» S. Borkar, “Design challenges of technology scaling,” IEEE Micro,
vol.19, no.4, p.23-29, July-Aug. 1999.
» J. Meindl, “Low Power Microelectronics: Retrospect and Prospect”,
Proceedings of the IEEE, April 1995.
» B. Davari et al., “CMOS Scaling for High Performance and Low
Power - The Next Ten Years,” Proceedings of the IEEE, April 1995.
» A. Masaki, “Deep-Submicron warms up to High Speed Logic,” IEEE
Cicuits and Devices Magazine, November 1992.
● This lecture is based on IC seminar by S. Borkar, October 2000.
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EE241
Tools
● HSPICE
» You need an account on cory.eecs
● 0.25µm CMOS device models
(TSMC/MOSIS)
● Other tools, schematic or layout editors
are optional
● Cadence, Synopsys, available on
mingus.eecs
Moore’s Law
In 1965, Gordon Moore noted that the

number of transistors on a chip doubled
every 18 to 24 months.
He made a prediction that semiconductor

technology will double its effectiveness
every 18 months
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EE241
Moore’s Law
16
COMPONENTS PER INTEGRATED FUNCTION

15
14
13
12
LOG2 OF THE NUMBER OF
11
10
9
8
7
6
5
4
3
2
1
0
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
Electronics, April 19, 1965.
Transistor Count
1 Billion
K
Transistors
1,000,000
100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
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EE241
Technology Evolution (1997 data)
International Technology Roadmap for Semiconductors

Year of
1997 1999 2002 2005 2008 2011 2014
Introduction
Channel length
200 140 100 70 50 35 25
[nm]
1.8- 1.5- 1.2- 0.9- 0.5-
Supply [V] 0.6-0.9 0.4
2.5 1.8 1.5 1.2 0.6
Metal layers 6 6-7 7 7-8 8-9 9 10
Max frequency
750 1250 2100 3500 6000 10000 17000
[MHz],Local
Max µP power [W] 70 90 130 160 170 175 183
http://www.sematech.org, or http://public.itrs.net
Technology Evolution (2000 data)

International Technology Roadmap for Semiconductors
Year of
1999 2000 2001 2004 2008 2011 2014
Introduction
Technology node
180 130 90 60 40 30
[nm]
Supply [V] 1.5-1.8 1.5-1.8 1.2-1.5 0.9-1.2 0.6-0.9 0.5-0.6 0.3-0.6
Wiring levels 6-7 6-7 7 8 9 9-10 10
Max frequency 14.9
1.2 1.6-1.4 2.1-1.6 3.5-2 7.1-2.5 11-3
[GHz],Local-Global -3.6
Max µP power [W] 90 106 130 160 171 177 186
Bat. power [W] 1.4 1.7 2.0 2.4 2.1 2.3 2.5
Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

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EE241
ITRS Technology Roadmap

Acceleration Continues
Some Other Scares
10
EE241
Technology Scaling
● Goals of scaling the dimensions by 30%:
» Reduce gate delay by 30% (increase operating
frequency by 43%)
» Double transistor density
» Reduce energy per transition by 65% (50% power
savings @ 43% increase in frequency
● Technology generation spans 2-3 years, but
µP speed doubles every generation (not
increased only by 43%)
S. Borkar, IEEE Micro, July 1999.

Moore’s law in Microprocessors

1000
100 2X growth in 1.96 years!

Transistors (MT)
10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
0.01 8080
8008 S. Borkar
4004
0.001
1970 1980 1990 2000 2010
Year
Transistors on Lead Microprocessors double every 2 years
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EE241
Moore’s Law - Logic Density

1000
Logic Transistors/mm2
2x trend
Logic Density
100
Pentium II (R)
486 Pentium Pro (R)
10 Pentium (R)
386
Source: Intel
i860
0.13µ
0.8µ
0.6µ
0.35µ
0.25µ
0.18µ
1.5µ
1.0µ
➊Shrinks
➊Shrinksand
andcompactions
compactions meet
meet density
densitygoals
goals
➋New micro-architectures drop density
➋New micro-architectures drop density
Die Size Growth

100
Die size (mm)
P6
10 486 Pentium ® proc
386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years
S. Borkar
1
1970 1980 1990 2000 2010
Year
Die size grows by 14% to satisfy Moore’s Law
12
EE241
Frequency
10000
Doubles every
1000
2 years
Frequency (Mhz)
P6
100
Pentium ® proc
486
10 8085 386
8086 286
1 8080
8008 S. Borkar
4004
0.1
1970 1980 1990 2000 2010
Year
Lead Microprocessors frequency doubles every 2 years
Processor Frequency Trend

10,000 100
Intel
Processor freq
IBM Power PC
scales by 2X per
DEC
generation
Gate delays/clock
21264S
Gate Delays/ Clock
1,000
21164A 21264
21064A Pentium(R)
Mhz
21164 II 10
21066 MPC750
604 604+
Pentium Pro
100 (R)
601, 603
Pentium(R)
486
386
10 1 V.De, S. Borkar
ISLPED’99
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
➊ Frequency doubles each generation

➋ Number of gates/clock reduce by 25%
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EE241
Power
100
P6
Pentium ® proc
Power (Watts)
10
486
8086 286
386
8085
1 8080
8008
4004
0.1 S. Borkar
1971 1974 1978 1985 1992 2000

Year
Lead Microprocessors power continues to increase

Obeying Moore’s Law…

10000
1.8B
1000
900M
Transistors (MT)
425M
100 200M
10
P6
Pentium ® proc
1 486
386
0.1 286
8085 8086
0.01 8080
8008 S. Borkar
0.001 4004
1970 1980 1990 2000 2010
Year
200M--1.8B transistors on the Lead Microprocessor
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EE241
If die size increases

100
36 41
Die size (mm) 28 32
P6
10 486 Pentium ® proc
386
8080 286
8086
8085 ~7% growth per year
8008 ~2X growth in 10 years
4004
S. Borkar
1
1970 1980 1990 2000 2010
Year
Die size will have to grow to 30 - 40mm
Frequency will increase

100000 30GHz
10000 14GHz
6.5GHz
Frequency (Mhz)
3 Ghz
1000
100 P6
Pentium ® proc
486
10 8085 386
8086 286
1 8080 S. Borkar
8008
4004
0.1
1970 1980 1990 2000 2010
Year
3 - 30Ghz Frequency
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EE241
Supply voltage will continue

to reduce
10.00
Supply Voltage (V)
1.00
S. Borkar
0.10
1970 1980 1990 2000 2010
Year
Only 15% Vcc reduction to meet frequency demand
Processor Power
100
Pentium II (R)
Pentium Pro ?
Max Power (Watts)
(R)
Pentium(R)
Pentium(R)
10 MMX
486 486
Source: Intel
386
386
1
1.5µ 1µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ
➊ Lead processor power increases every generation

➋ Compactions provide higher performance at lower power
16
EE241
Active power scaling

1
1 . If Vcc = 0 . 7 , and Freq = ( ),
0 .7
1 1
Power = CV 2 f = ( × 1 . 14 2 ) × ( 0 . 7 2 ) × ( ) = 1 .3
0 .7 0 .7
2 . If Vcc = 0 . 7 , and Freq = 2 ,

1
Power = CV 2 f = ( × 1 . 14 2 ) × ( 0 . 7 2 ) × ( 2 ) = 1 . 8
0 .7
3 . If Vcc = 0 . 85 , and Freq = 2 ,

1
Power = CV 2 f = ( × 1 . 14 2 ) × ( 0 . 85 2 ) × ( 2 ) = 2 . 7
0 .7
Leakage power increases

50%
100,000 8KW
0.18u 0.13u 0.1u
Drain Leakage Power
0.07u 0.05u 40%

10,000 1.7KW
Ioff (na/u)
30% 400W
1,000
88W
20%
12W
100
10%
10
0%
30 40 50 60 70 80 90 100
2000 2002 2004 2006 2008
Temp (C) Year
S. Borkar
Drain leakage will have to increase to meet freq demand

Results in excessive leakage power
17
EE241
Power will be a problem

100000
18KW
10000 5KW
1.5KW
Power (Watts)
1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004
S. Borkar
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power delivery and dissipation will be prohibitive
A closer look at the power

100,000
Will be...
18KW
Power (Watts)
10,000 5KW
Should be...
1.5KW
1,000 500W 623W
375W
225W S. Borkar
135W
100
2002 2004 2006 2008
Year
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EE241
Power density will increase

10000
Power Density (W/cm2) Rocket
Nozzle
1000
Nuclear
100
Reactor
8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
8080 286 486 S. Borkar
1
1970 1980 1990 2000 2010
Year
Power density too high to keep junctions at low temp
Power delivery challenges

1,000.00 1.E+07
1.E+06
100.00 1.E+05
1.E+04
L(di/dt)/Vdd
Icc (amp)
10.00 P6 1.E+03 P6
Pentium® proc 1.E+02
8086 1.E+01 8086 Pentium® proc
1.00 386 386
486 1.E+00 486
8080 286 1.E-01 8080 286
0.10 8085 8085
1.E-02
4004 8008
1.E-03 40048008
0.01 1.E-04
1970 1980 1990 2000 2010 1970 1980 1990 2000 2010
Year Year
S. Borkar
High supply currents at low voltage:

Challenges: IR drop and L(di/dt) noise
19
EE241
Moore’s law challenge

● Double transistors every two years
» (Obey Moore’s Law)
● Stay within the expected power trend
● Still deliver the expected performance
Expected power trend

100000
18KW
100,000
5KW
10000
1.5KW Will be...
Power (Watts)
1000 500W
18KW
Power (Watts)
100 P5 P6
286
8086 386
486 10,000 5KW
10 8085
8080
Should be...
8008
1 4004
1.5KW
0.1
1971 1974 1978 1985 1992 2000 2004 2008
1,000 500W 623W
Year
375W
225W
135W
100
2002 2004 2006 2008
Year
S. Borkar
Goal: Restrict power to the expected trend
20
EE241
Restrict transistor leakage

10000
7 GHz
5.5 GHz
4 GHz
Frequency (Mhz)
2.5 Ghz
1000
100 P6
Pentium® proc
486 S. Borkar
10 386
1985 1990 1995 2000 2005 2010
Year
Reduce leakage
Frequency will not double every 2 years
Do not increase the die size

45
40 Will be...
35 Reduce die size

Die Size (mm)
30
25
20
15
10
5
0
S. Borkar
2000 2002 2004 2006 2008
Year
Restrict die size to ~ 20 mm

21
EE241
Memory has lower power

density
1,000
Logic
Power Density (Watts/cm

2
)
Memory
100
10
S. Borkar
1
0.25µ 0.18µ 0.13µ 0.1µ 0.07µ 0.05µ
Exploit memory !
Increase memory area

70%
57%
Memory Area % of total
60% 54% 55%

50%
41%
40%
29%
30%
20%
10% S. Borkar
0%
2000 2002 2004 2006 2008
Year
Use > 50% die area in memory
22
EE241
Total memory meets trend

100000
12M
10000 2.5M
24M
1M
Memory (KB)
5.5M
1000
100 16
16
8
10
S. Borkar
0
1
1980 1990 2000 2010
Year
Power density is reduced

10000
Rocket
Power Density (W/cm2)
Nozzle
1000
Nuclear
Reactor
100
8086
10 4004 Hot Plate P6
8008 8085 386 Pentium ® proc
8080 286 486 S. Borkar
1
1970 1980 1990 2000 2010
Year
Full chip power density is reduced

But local power density will be high
23
EE241
Still obey Moore’s Law!

10,000
Actual
Moore's Law.
Transistors (MT)
1,000
100
S. Borkar
10
2000 2002 2004 2006 2008
Year
Total transistors meet Moore’s Law
Too good to be true...

● Reduced transistor leakage
● Reduced frequency
● Decreased die size
● Increased memory, but reduced logic
● Does it deliver expected performance?
24
EE241
Reduced die size causes

“Performance gap”
70%
59%
60% 53%
Performance Gap
50% 47%
40% 35%
30%
20%
10% S. Borkar
0%
0%
2000 2002 2004 2006 2008
Year
30-60% performance loss even after meeting Moore’s Law

Large caches could improve

performance
1000 100
Cache Latency (Clocks)
Relative Bandwidth
100 10
10 1
1 0
L0 L1 L2 External Mem L0 L1 L2 External Mem
800 Source: Glenn Hinton, 99
External Mem Latency
Instruction Cost
600
400 Large on die caches provide:

200 1. Increased Data Bandwidth
0
2. Reduced Latency
Pentium Pentium Pentium
Future Processors
proc Pro Proc III proc
25
EE241
Cache size trend

Cache
100% Core µ
0.18µ
Cache % of
full chip
Logic
80%
area ?
60% Cache
µ
0.13µ
Core
40%
Logic
Pentium III
20% PentiumPentium
Pro Pentium II Pentium III
0% Cache µ
0.10µ
0.7µ 0.5µ 0.35µ 0.25µ 0.18µ 0.13µ 0.10µ
Core
Logic
Cache memory area will dominate

Other design challenges

10000
Modest increase in
Logic Transistors (MT)
1000
●
100
10
P6
Logic transistors
1 Pentium® proc
486
0.1 286
386
● “Logic Core” size
8085 8086
0.01
0.001
8080
8008
4004 will decrease
1970 1980 1990 2000 2010
25
Year ● Tools/methodology
Die size will reduce...
20 But core will reduce even further... for memories
Die Size (mm)
● Interconnect RC
15
10
5
may not be that
0
big an issue
2000 2002 2004 2006 2008
UC Berkeley EE241 Year B. Nikolić
26
EE241
Productivity Trends
Logic Transistor per Chip (M)
10,000
10,000,000 100,000
100,000,000
1,000 Logic Tr./Chip 10,000
1,000,000 10,000,000
(K) Trans./Staff - Mo.

Tr./Staff Month.
100
100,000 1,000
1,000,000
Complexity
Productivity
10 58%/Yr. compounded 100
10,000 Complexity growth rate 100,000
1,0001 10
10,000
x x
0.1
100 1
1,000
xx
x
21%/Yr. compound
xx Productivity growth rate
x
0.01
10 0.1
100
0.001
1 0.01
10
1981
1983
1985
1987
1989
1991
1993
1995
1999
2001
2003
2005
2007
2009
1997
Source: Sematech
Complexity outpaces design productivity
Summary
● Moore’s Law will be obeyed
● Barrier: Power delivery, dissipation, and
density
● Exploit lower power density of memory--
creates performance gap
● Huge on die caches will help maintain
performance trend
● Design challenges are different--not
what we think they are!
27

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EE241

EE241 - Spring 2001

UC Berkeley EE241 B. Nikolić

● Admin: Lea Barker

UC Berkeley EE241 B. Nikolić

● Textbook: “Design of High-Performance

UC Berkeley EE241 B. Nikolić

UC Berkeley EE241 B. Nikolić

UC Berkeley EE241 B. Nikolić

UC Berkeley EE241 B. Nikolić

UC Berkeley EE241 B. Nikolić

UC Berkeley EE241 B. Nikolić

UC Berkeley EE241 B. Nikolić

UC Berkeley EE241 B. Nikolić

UC Berkeley EE241 B. Nikolić

In 1965, Gordon Moore noted that the

He made a prediction that semiconductor

UC Berkeley EE241 B. Nikolić

COMPONENTS PER INTEGRATED FUNCTION

UC Berkeley EE241 B. Nikolić

Technology Evolution (1997 data)

International Technology Roadmap for Semiconductors

Technology Evolution (2000 data)

Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

ITRS Technology Roadmap

UC Berkeley EE241 B. Nikolić

Some Other Scares

UC Berkeley EE241 B. Nikolić

S. Borkar, IEEE Micro, July 1999.

Moore’s law in Microprocessors

100 2X growth in 1.96 years!

Transistors on Lead Microprocessors double every 2 years

UC Berkeley EE241 B. Nikolić

Moore’s Law - Logic Density

Die Size Growth

Die size grows by 14% to satisfy Moore’s Law

UC Berkeley EE241 B. Nikolić

UC Berkeley EE241 B. Nikolić

Processor Frequency Trend

➊ Frequency doubles each generation

1971 1974 1978 1985 1992 2000

Lead Microprocessors power continues to increase

Obeying Moore’s Law…

UC Berkeley EE241 B. Nikolić

If die size increases

Die size will have to grow to 30 - 40mm

UC Berkeley EE241 B. Nikolić

Frequency will increase

Supply voltage will continue

➊ Lead processor power increases every generation

Active power scaling

2 . If Vcc = 0 . 7 , and Freq = 2 ,

3 . If Vcc = 0 . 85 , and Freq = 2 ,

Leakage power increases

0.07u 0.05u 40%

Drain leakage will have to increase to meet freq demand

UC Berkeley EE241 B. Nikolić

Power will be a problem

Power delivery and dissipation will be prohibitive

UC Berkeley EE241 B. Nikolić

A closer look at the power

UC Berkeley EE241 B. Nikolić

Power density will increase