16 W

Roll Number:
Thapar Institute of Engineering and Technology, Patiala
Department of Electronics and Communication Engineering
END SEMESTER EXAMINATION
B. E. (First Year): Semester-I (2018) Course Code:VEC001
Course Name: Electronic Engineering
Groups(A,B,C,D,E,F,G,H)
December 13, 2018 Day: Thursday
Name Of Faculty: MKR,NJ,HVR,ST,SV,
Time: 3 Hours, M. Marks: 100
AM,DG and NS

Note: Attempt all questions.

Assume missing data, if any, suitably

Q.1 (a) Show how a barrier potential is generated at the interface of a p-n
junction. Draw the energy band diagram along with the Fermi level for a
(4+9=13)
p-n junction under zero bias, forward bias and reverse bias.
Q.1 (b) Draw the output of a given clipper circuit shown in Fig.1, diode A is made
of Silicon while diode B is made of Germanium.
R

v4,0
(12)

(Fig.1)
Q.2 (a) For a BJT, establish the relation: Ic = R IB + (1+ 13) Ico in common emitter
configuration; where symbols have their usual significance and 'co is (05)
reverse saturation current of collector base junction.
Q.2 (b) For the circuit shown in Fig. 2, calculate the following parameters; Ic, VE,
Vcc, VCE, Vs and R1. Draw the load line and determine its operating point. (07)
Assume the transistor to be made of Silicon.

10.6 V

100

(Fig.2)
F(x,y,z)=xy+yz+xy-z and (5)
Q.2 (c) Find the Maxterms of the Boolean expression
realize it using NAND gates only.
Q.2 (d) Simplify the following functions using K-map in terms of SOP and (8)
P.T.0
 implement using NAND logic:
F (A, B, C, D) = m (0, 2, 4, 5, 7, 8, 10, 12, 13, 15) + d (1, 9).
Q.3 (a) Design 2- input XOR gate using 2:1 multiplexer (6)
Q.3 (b) Design a full adder using 4:1 multiplexers. (7)
Q.3 (c) Why S-R flip-flop has an indeterminate output for S=R=1? How is it
avoided in the J-K flip-flop? (6)
Q.3 (d) Draw the output timing diagram of a rising edge-triggered D Flip Flop,
given the following input (D) and clock (CLK) signals in Fig.3. (6)

D
0 r Ll
CLK
(Fig.3)
Q.4 (a) Differentiate between asynchronous and synchronous digital design. (3+2=5)
Name the asynchronous signals (with their functions) used in the flip
flops.
Q.4 (b) Construct a binary 4 bit ripple counter using D flip flops. Support your (3+4=7)
answer with appropriate timing diagrams. What is the highest modulus of
frequency that can be generated using it? Can this counter be used as a
down counter?
Q.5 (a) Describe the working operation of CMOS inverter and implement a 2- (4+3=7)
input NAND gate using CMOS logic.
Q5 (b) With a neat diagram, explain the working operation of 2 input open (6)
collector TTL logic NAND gate.

Note: The answer sheets will be shown to the students on 19th Dec'18 according to schedule
given on the following Link:
https://sites.google.com/thapar.edu/2018uec001