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3.3.1 2-bit comparator

Program Utama
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comp_2bit is
Port(
a : in std_logic_vector(1 downto 0);
b : in std_logic_vector(1 downto 0);
lt : out std_logic;
eq : out std_logic;
gt : out std_logic
);

end comp_2bit;

architecture Behavioral of comp_2bit is

begin
lt <= ((not a(1)) and (not a(0)) and b(0)) or ((not a(1)) and b(1)) or ((not a(0)) and b(1) and
b(0));
eq <= ((not a(1)) and (not a(0)) and (not b(1)) and (not b(0))) or ((not a(1)) and a(0) and (not
b(1)) and b(0)) or (a(1) and (not a(0)) and b(1) and (not b(0))) or (a(0) and a(1) and b(0) and
b(1));
gt <= (a(1) and (b(0) nor b(1))) or ((a(0) and a(1)) and (not b(1))) or (a(0) and (not b(0)));
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ROM_3x2 is
Port(
addr : in std_logic_vector(2 downto 0);
o : out std_logic_vector(1 downto 0)
);

end ROM_3x2;

architecture ROM of ROM_3x2 is

type rom is array (0 to 3) of std_logic_vector(1 downto 0);
constant ROM_3x2 : rom := (
0 => "00",
 1 => "01",
2 => "10",
3 => "11"
);

begin
process(addr)
begin
case addr is
when "000" => o <= ROM_3x2(0);
when "001" => o <= ROM_3x2(1);
when "010" => o <= ROM_3x2(2);
when "100" => o <= ROM_3x2(3);
when others => o <= ROM_3x2(0);
end case;
end process;
end ROM;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ROM_COMP is
Port(
a,b : in std_logic_vector(1 downto 0);
otp : out std_logic_vector(1 downto 0)
);
end ROM_COMP;

architecture OP of ROM_COMP is
component comp_2bit is
Port(
a : in std_logic_vector(1 downto 0);
b : in std_logic_vector(1 downto 0);
lt : out std_logic;
eq : out std_logic;
gt : out std_logic
);
end component;

component ROM_3x2 is
Port(
addr : in std_logic_vector(2 downto 0);
o : out std_logic_vector(1 downto 0)
);
end component;
signal less,equal,greater : std_logic;
begin
COMPAR : comp_2bit port map(
a => a,
b => b,
lt => less,
eq => equal,
gt => greater
);
ROMCOMP : ROM_3x2 port map(
addr(0) => less,
addr(1) => equal,
addr(2) => greater,
o => otp
);
end OP;

TestBanch

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ROM_COMP_tb is
-- Port ( );
end ROM_COMP_tb;

architecture Behavioral of ROM_COMP_tb is

component ROM_COMP
Port(
a,b : in std_logic_vector(1 downto 0);
otp : out std_logic_vector(1 downto 0)
);
end component;
signal a,b,otp : STD_LOGIC_VECTOR(1 downto 0);

begin
uut : ROM_COMP Port Map(
a => a,
b => b,
otp => otp
);
process
begin
wait for 10 ns;a <= "11";b <= "00";
wait for 10 ns;a <= "10";b <= "11";
wait for 10 ns;a <= "01";b <= "01";
end process;
end Behavioral;
[2019-05-22 13:10:38 EDT] vlib work && vcom '-2008' '-o' design.vhd testbench.vhd &&
vsim -c -do "vsim testbench tugas3; vcd file dump.vcd; vcd add -r sim:/testbench/*vcd
add -r sim:/lab3/*; run -all; exit"
VSIMSA: Configuration file changed: `/home/runner/library.cfg'
ALIB: Library `work' attached.
work = /home/runner/work/work.lib
Aldec, Inc. VHDL Compiler, build 2014.06.88
VLM Initialized with path: "/home/runner/library.cfg".
DAGGEN WARNING DAGGEN_0523: "The source is compiled without the -dbg switch. Line
breakpoints and assertion debug will not be available."
COMP96 File: design.vhd
COMP96 Compile Entity "comp_2bit"
COMP96 Compile Architecture "Behavioral" of Entity "comp_2bit"
COMP96 Compile Entity "ROM_3x2"
COMP96 Compile Architecture "ROM" of Entity "ROM_3x2"
COMP96 Compile Entity "ROM_COMP"
COMP96 Compile Architecture "OP" of Entity "ROM_COMP"
COMP96 File: testbench.vhd
COMP96 Compile Entity "ROM_COMP_tb"
COMP96 Compile Architecture "Behavioral" of Entity "ROM_COMP_tb"
COMP96 Top-level unit(s) detected:
COMP96 Entity => ROM_COMP_tb
COMP96 Compile success 0 Errors 0 Warnings Analysis time : 30.0 [ms]
# Aldec, Inc. Riviera-PRO version 2014.06.88.5387 built for Linux64 on June 25, 2014.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2014 Aldec, Inc. All rights reserved.
vsim testbench tugas3;
# VSIM: Error: Unknown library unit 'testbench' specified.
# VSIM: Error: Unknown library unit 'tugas3' specified.
# VSIM: Error: Simulation initialization failed.
Finding VCD file...
No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd");
$dumpvars;'?
Done