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6.1.1. 4-bit register with synchronous reset

Program Utama

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sync_reg_4bit is
Port(
D : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0);
load,reset,clk : in std_logic
);
end sync_reg_4bit;

architecture Behavioral of sync_reg_4bit is

begin
Process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then
Q <= "0000";
elsif (load = '1') then
Q <= D;
end if;
end if;
end Process;
end Behavioral;

TestBench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sync_reg_4bit_tb is
end sync_reg_4bit_tb;

architecture Behavioral of sync_reg_4bit_tb is

Component sync_reg_4bit
 Port(
D : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0);
load,reset,clk : in std_logic
);
end Component;

Signal Di,Qo : std_logic_vector(3 downto 0);

Signal reset1, load1, clk1 : std_logic := '0';
begin
tes_wew : sync_reg_4bit port map(
D => Di,
Q => Qo,
clk => clk1,
reset => reset1,
load => load1
);
Process
Begin
wait for 10 ns;clk1 <= '1';reset1 <= '0';Di <= "1111";load1 <= '0';
wait for 10 ns;clk1 <= '0';
wait for 10 ns;clk1 <= '1';load1 <= '1';
wait for 10 ns;clk1 <= '0';
wait for 10 ns;clk1 <= '1';Di <= "0011";load1 <= '0';
wait for 10 ns;clk1 <= '0';
wait for 10 ns;clk1 <= '1';load1 <= '1';
wait for 10 ns;clk1 <= '0';Di <= "0111";
wait for 10 ns;clk1 <= '1';
wait for 10 ns;clk1 <= '0';
 wait for 10 ns;clk1 <= '1';
wait for 10 ns;clk1 <= '0';load1 <= '0';
wait for 10 ns;clk1 <= '1';
wait for 10 ns;clk1 <= '0';Di <= "1001";
wait for 10 ns;clk1 <= '1';load1 <= '1';
wait for 10 ns;clk1 <= '0';reset1 <= '1';
end Process;
end Behavioral;

[2019-05-22 13:18:45 EDT] vlib work && vcom '-2008' '-o' design.vhd testbench.vhd &&
vsim -c -do "vsim testbench lab5; vcd file dump.vcd; vcd add -r sim:/testbench/*vcd
add -r sim:/lab5/*; run -all; exit"
VSIMSA: Configuration file changed: `/home/runner/library.cfg'
ALIB: Library `work' attached.
work = /home/runner/work/work.lib
Aldec, Inc. VHDL Compiler, build 2014.06.88
VLM Initialized with path: "/home/runner/library.cfg".
DAGGEN WARNING DAGGEN_0523: "The source is compiled without the -dbg switch. Line
breakpoints and assertion debug will not be available."
COMP96 File: design.vhd
COMP96 Compile Entity "sync_reg_4bit"
COMP96 Compile Architecture "Behavioral" of Entity "sync_reg_4bit"
COMP96 File: testbench.vhd
COMP96 Compile Entity "sync_reg_4bit_tb"
COMP96 Compile Architecture "Behavioral" of Entity "sync_reg_4bit_tb"
COMP96 Top-level unit(s) detected:
COMP96 Entity => sync_reg_4bit_tb
COMP96 Compile success 0 Errors 0 Warnings Analysis time : 30.0 [ms]
# Aldec, Inc. Riviera-PRO version 2014.06.88.5387 built for Linux64 on June 25, 2014.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2014 Aldec, Inc. All rights reserved.
vsim testbench lab5;
# VSIM: Error: Unknown library unit 'testbench' specified.
# VSIM: Error: Unknown library unit 'lab5' specified.
# VSIM: Error: Simulation initialization failed.
Finding VCD file...
No *.vcd file found. EPWave will not open. Did you use '$dumpfile("dump.vcd");
$dumpvars;'?
Done