Clock Divider

10/26/2018 (3) [Digital VLSI Topics] [1] Clock Dividers | LinkedIn
[1] Clock Dividers - PART A
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# Definitions
I assume in this topic that you know what is a Clock, Duty cycle, Falling edge and
Rising edge, Counter and T-Flip Flop and Logic!
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https://www.linkedin.com/pulse/digital-vlsi-topics-1-clock-dividers-mahmoud-abdellatif/ 1/16
# Divided Clock with 50 % Duty Cycle
>> Divide by Even Numbers
It is straight forward and can be done by many methods, to divide by N, where N is

an even number, you can make a counter which counts from 0 to N-1 and toggle the
output every (N/2) cycle.
// -- divide by even number ---
// -- 50 % duty cycle
module clock_divide_4
( input wire ref_clk, input wire rstb, output reg clk_out );
reg [1:0] cnt;
// 2-bit Counter
always @ (posedge ref_clk or negedge rstb )

if (~ rstb)
cnt <= 0;
else
cnt <= cnt + 1;
// output clock with 50% duty cycle

if (~ rstb)
clk_out <= 0;
else begin
clk_out <= 0;
if (cnt >= 2)
clk_out <= 1;
end
endmodule
Simulation Result
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>> Divide by Odd number
Dividing by an Odd number with a 50% duty cycle basic idea is to know that you
have to use the negative edge of the reference clock reference clock somewhere to
get your 50% duty cycle. You need a design that guarantees a glitch-free output
circuit, then you need to search for the design with minimal number of Flip-Flops
and Logic gates
the first idea steps are summarized in the following points
generate two clocks with half the desired

frequency with phase 90 degree between them,
then Xoring the two clocks to generate the
output clock
1. Create counter that counts from 0 to (N-1) on the rising edge of ref_clk where N is the division number
2. Create two Toggle Flip Flops one working with the positive edge and the other on the negative edge
3. Create Enable signals to the two TFFs, the first enabled when counter =0 and the other enabled when counter = (N+1)/2
4. Xor the output of the two TFFs
Let's apply this on Divide by 3 circuit where N = 3

Create Counter 0 >> 2
Create TFF_1 working on positive edge & TFF_2 working on negative edge
TFF_1_EN = 1 when Counter = 0
TFF_2_EN = 1 when Counter = 2
cllkout = TFF_1_OUT X or TFF_2_OUT
// -- divide by odd number ---
// -- 50 % duty cycle
module clock_divide_3 (
input wire ref_clk,

input wire rstb,
output wire clk_out );
reg [1:0] counter;

reg tff1_en;
reg tff2_en;
reg tff1_out;
reg tff2_out;
// Counter
always @ (posedge ref_clk or negedge rstb)

if (~rstb)
counter <= 0;
else
counter <= (counter == 2) ? 0 : counter + 1;
// TFF_1 Enable

if (~rstb)
tff1_en <= 0;
else begin
tff1_en <= 0;
if (counter == 0)
tff1_en <= 1;
end
// TFF_2 Enable

if (~rstb)
tff2_en <= 0;
else begin
tff2_en <= 0;
if (counter == 2) // (N+1)/2
tff2_en <= 1;
end
// TFF_1

if (~rstb)
tff1_out <= 0;
else if (tff1_en )
tff1_out <= ! tff1_out ;
// TFF_2 on Negative Edge
always @ (negedge ref_clk or negedge rstb)

if (~rstb)
tff2_out <= 0;
else if (tff2_en )
tff2_out <= ! tff2_out ;
assign clk_out = tff1_out ^ tff2_out ;

endmodule
Simulation Result
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# Divided Clock with non 50 % Duty Cycle

>> Divide by Odd number
This is very similar to dividing by Even number approach used to get 50% duty
cycle, but here you can't get the same result using only counters and positive edge!
// -- divide by odd number ---
// -- non 50 % duty cycle
module clock_divide_9
( input wire ref_clk, input wire rstb, output reg clk_out );
reg [3:0] cnt;
// 4-bit Counter

if (~ rstb)
cnt <= 0;
else
cnt <= (cnt == 8) ? 0 : cnt + 1;
// output clock with 77.77% duty cycle

if (~ rstb)
clk_out <= 0;
else begin
clk_out <= 0;
if (cnt >= 2)
clk_out <= 1;
end
endmodule
Simulation Result
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>> Divide by Fractional number
What if you want to divide by 1.5, or 4.5 ? In [1] and [2] many approaches are used
to generate glitch-free clock which is divided by Fractional number from a
reference clock.
Let’s start with a divide by 4.5. It means every nine reference clocks would include
two symmetrical pulses.
1. Generate a 9-bit shift register initialized by 1, the shift register is left-rotated on rising edge.
2. To generate the first pulse, first bit must be shifted by half a clock period and then OR with the first and second bit.
3. To generate the second pulse, the 4th and 5th bits must be shifted by half a clock period and then OR with the original 5th bit.
// -- divide by fractional number ---
// -- non 50 % duty cycle
module clock_divide_1p5
(
input wire ref_clk,
input wire rstb,
output wire clk_out
);
reg [8:0] cnt;

reg ps_count0;
reg ps_count4;
reg ps_count5;
// Counter on positive edge
always @ ( posedge ref_clk or negedge rstb)

if (~rstb)
cnt <= 9'b000000001;

else
cnt <= {cnt [7:0],cnt[8]};
// Generate signals on negative edge
always @ (negedge ref_clk or negedge rstb)

if (~rstb)
begin
ps_count0 <= 1'b0;
ps_count4 <= 1'b0;
ps_count5 <= 1'b0;
end
else
begin
ps_count0 <= cnt[0];
end
// Genration of output clock = (ref_clk / 4.5)
assign clk_out = (ps_count4 | ps_count5 | cnt [5]) | (cnt [0] | cnt [1] | ps_count0);
endmodule
Simulation Result
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There are many other approaches you can use

or you can modify and optimize the mentioned
approaches, check the references listed below if
you are interested to know more about Clock
Dividers, otherwise just get the idea and move to
another topic.

Clock Divider

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10/26/2018 (3) [Digital VLSI Topics] [1] Clock Dividers | LinkedIn

[1] Clock Dividers - PART A

# Divided Clock with 50 % Duty Cycle

>> Divide by Even Numbers

It is straight forward and can be done by many methods, to divide by N, where N is

// -- divide by even number ---

( input wire ref_clk, input wire rstb, output reg clk_out );

reg [1:0] cnt;

always @ (posedge ref_clk or negedge rstb )

cnt <= cnt + 1;

// output clock with 50% duty cycle

always @ (posedge ref_clk or negedge rstb )

>> Divide by Odd number

the first idea steps are summarized in the following points

generate two clocks with half the desired

4. Xor the output of the two TFFs

Let's apply this on Divide by 3 circuit where N = 3

Create Counter 0 >> 2

TFF_1_EN = 1 when Counter = 0

TFF_2_EN = 1 when Counter = 2

cllkout = TFF_1_OUT X or TFF_2_OUT

// -- divide by odd number ---

input wire ref_clk,

reg [1:0] counter;

always @ (posedge ref_clk or negedge rstb)

counter <= (counter == 2) ? 0 : counter + 1;

always @ (posedge ref_clk or negedge rstb)

always @ (posedge ref_clk or negedge rstb)

always @ (posedge ref_clk or negedge rstb)

tff1_out <= ! tff1_out ;

// TFF_2 on Negative Edge

always @ (negedge ref_clk or negedge rstb)

tff2_out <= ! tff2_out ;

assign clk_out = tff1_out ^ tff2_out ;

# Divided Clock with non 50 % Duty Cycle

>> Divide by Odd number

// -- divide by odd number ---

// -- non 50 % duty cycle

( input wire ref_clk, input wire rstb, output reg clk_out );

reg [3:0] cnt;

always @ (posedge ref_clk or negedge rstb )

cnt <= (cnt == 8) ? 0 : cnt + 1;

// output clock with 77.77% duty cycle

always @ (posedge ref_clk or negedge rstb )

>> Divide by Fractional number

// -- divide by fractional number ---

// -- non 50 % duty cycle

reg [8:0] cnt;

// Counter on positive edge

always @ ( posedge ref_clk or negedge rstb)

cnt <= 9'b000000001;

cnt <= {cnt [7:0],cnt[8]};

// Generate signals on negative edge

always @ (negedge ref_clk or negedge rstb)

// Genration of output clock = (ref_clk / 4.5)

There are many other approaches you can use

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