Course Coordinator AY 2019-2020 , Semester-1 L T P C

P Shyam Subject Name: VLSI (EC2103) 3 1 0 4

Total Contact Hours– 60

Prerequisite : Digital Logic Design, Analog Electronic Circutis

Course Objective:

This is an introductory course to VLSI Design (Very Large Scale Integrated Circuit Design).
Main emphasis is introducing various steps involved in Integrated circuit design and the course
serves as a prologue to the field of microelectronics and VLSI Design.

At the end of the course student gets familiarized with the following topics:

1. Digital System Design : Datapath Design and Control path design

2. Fabrication steps involved in IC design
3. Layout and issues connected with layout

AT/ e-Resources
Contact
L/T Topics to be covered MT/ Reference Study
hours Video Resources
EST Material
L1 Introduction to VLSI Design, VLSI MT1
1 [2] [2]
Design flow https://ocw.mit.ed
L2 ASIC vs FPGA Design Flow 1 [1] u/courses/electrica [1]
L3 Review of sequential circuits 1 [1] l-engineering-and- [1]
T1 Introduction to Xilinx Tool and
1 [4],[1] computer- [4],[1]
Verilog HDL
L4 Introduction to State Machines 1 [1] [5] science/6-111- [1] [5]
L5 State Machines : Mealy model for introductory-
D, T, JK , SR Flip flops , basic 1 [1] [5] digital-systems- [1] [5]
counters laboratory-spring-
L6 State Machines : Moore model for 2006/
D, T, JK , SR Flip flops , basic 1 [1] [5] [1] [5]
counters
T2 (Gate-Level/Structural Modeling)
Realization of Multi-bit Adders with
1 [2] [2]
the help of Module Instances and
Module Instantiation
L7 Conversion between Mealy model https://nptel.ac.in/
and Moore model, advantages, 1 [1] [5] courses/11710611 [1] [5]
disadvantages
4/
L8 Design of Serial adder using state 1 [1] [5] [1] [5]
machines: Mealy model
L9 Design of Serial adder using state
1 [1] [5] [1] [5]
machines: Moore model
T3 Data-Flow Modeling
Realization of gates, combinational 1 [2] [2]
circuits.
L10 Design of state machines for
1 [1] [5] [1] [5]
sequence detectors :Overlap
L11 Design of state machines for
1 [1] [5] [1] [5]
sequence detectors :Non-Overlap https://nptel.ac.in/
L12 Design of state machines for courses/11710609
sequence detectors (Overlap and 1 [1] [5] [1] [5]
2/
Non-Overlap), parity detectors etc
T3 Problem solving on state machines
1 [1] [5] [1] [5]
for sequence detectors
L13 Conversion of a statement into
1 [1] [5] [1] [5]
state diagram and to state machine
L14 Conversion of a statement into
state diagram and to state 1 [1] [5] [1] [5]
machines (Continued)
L15 Conversion of a statement into
state diagram and to state 1 [1] [5] [1] [5]
machines (Continued)
T4 Problem solving on state machines
1 [1] [5] [1] [5]
for any statements
L16 Datapath and Control path sub- MT2
systems of a system 1 [1] [1]
Discussion on GCD Algorithm
L17 Discussion on Controlpath
subsystem with analysis of state 1 [1] [1]
diagram.
L18 Discussion on GCD System and
Verilog HDL for Datapath, Control 1 [1] https://nptel.ac.in/ [1]
path and complete system courses/10610516
T5 Implementation of GCD System in
5/
Xilinx platform using Verilog HDL,
1 [1] [1]
implementation of Finite state
machines
L19 Hardware Design Modeling – I
1 [2] [2]
(Finite State Machines)
L20 Hardware Design Modeling – II
1 [2] [2]
(Finite State Machines) Continued
L21 Hardware Design Modeling – III
1 [2] [2]
(Finite State Machines) Continued
T6 Xilinx implementations of
1 [4] [4]
Behavioral modeling
L22 Transistor level implementations of
1 [3] [3]
digital circuits
L23 Transistor level implementations of https://ocw.mit.ed
1 [3] [3]
digital circuits continued u/courses/electrica
L24 Transistor level implementations of
digital circuits continued
1 [3] l-engineering-and- [3]
T7 Problem solving on transistor level computer-
1 [3] science/6-111- [3]
digital circuits
L25 Noise-margin definitions and timing 1 [1] introductory- [1]
parameters
L26 Timing parameters: setup time,
1 [1] [1]
hold time, clock skew, critical path
L27 Timing parameters: setup time,
1 [1] [1]
hold time, clock skew, critical path
T8 Problem solving on timing
1 [1] [1]
parameters
L28 Timing parameters: setup time,
1 [5] [5]
hold time, clock skew, critical path digital-systems-
L29 Timing parameters: setup time, laboratory-spring-
1 [5] [5]
hold time, clock skew, critical path 2006/labs/
L30 Semiconductor manufacturing,
1 [3] [3]
Silicon wafer manufacturing
T9 Problem solving on timing
1 [1][5] [1][5]
parameters
L31 Layering: Thermal oxidation,
Doping:Thermal and Ion 1 [3] [3]
Implantation
L32 Tutorials: Fabrication 1 [3] [3]
L33 Lithography, Etching and
1 [3] https://nptel.ac.in/ [3]
Deposition
T10 Process and Device evaluation courses/11310606
1 [3] [3]
L34 Clean room design and 2/
1 [3] [3]
contamination control
L35 Tutorials: Fabrication 1 [3] [3]
L36 MOSFET (PMOS, NMOS)
1 [3] [3]
Fabrication steps
T11 Stick diagrams and Layout :
1 [3] [3]
Introduction and Design rules
L37 Stick diagrams for CMOS circuits 1 [3] [3]
L38 Tutorial: Fabrication perspective of MT3
1 [3] [3]
Layout rules
L39 Euler’s model of optimization 1 [3] [3]
T12 Layout design rules 1 [3] [3]
L40 Layout optimization techniques 1 [3] [3]
L41 Tutorial 1 [3] [3]
L42 Layout for CMOS circuits 1 [3] [3]
T13 Layout for CMOS circuits 1 [3] [3]
L43 Project HDL implementation of [1][2][3]
1 [1][2][3][4]
Digital System [4]
L44 Tutorial: Layout 1 [3] [3]
L45 The complete system design [1][2][3]
1 [1][2][3][4]
perspective [4]
T14 The complete system design [1][2][3]
1 [1][2][3][4]
perspective [4]
T15 The complete system design [1][2][3]
1 [1][2][3][4]
perspective [4]

L : Lecture T: Tutorial

Learning Resources

Text Books
1. Zvonko Vranesic, ‘Fundamentals of Digital Design using Verilog’ Mc Graw Hill, Second
Edition
2.Samir Palnitkar ,’Verilog HDL’, Pearson publications
3.Douglas A.Pucknell and Kamran Eshraghian, ‘Basic VLSI Design’, PHI publications
4.Xilinx Vivado design suite user guidance
5.John F Wakerly, ‘Digital Design’, Pearson publications

References
1.Fundamentals of Microfabrication by Marc Madou, CRC Press
2.Digital Systems Design with FPGAs and CPLDs by-Ian Grout-Elsevier-2008

Web Resources

1. Prof Shankar Balachandran, NPTEL-IIT Madras, ‘Digital Circuits and Systems’

Weblink: https://nptel.ac.in/courses/117106114/

2. Prof Srinivasan, NPTEL-IIT Madras, ‘ VLSI Circuits and Systems’

Weblink: https://nptel.ac.in/courses/117106092/

3. Prof Indranil Sengupta, NPTEL – IIT Kharagpur, ‘Hardware Modeling using Verilog’
Weblink: https://nptel.ac.in/courses/106105165/

4. Prof Parasuraman Swaminathan, NPTEL – IIT Madras, ‘Electronic materials, devices

and fabrication’
Weblink: https://nptel.ac.in/courses/113106062/

5. Prof. Anantha Chandrakasan, MIT, ‘Introductory Digital Systems Laboratory’

Weblink: https://ocw.mit.edu/courses/electrical-engineering-and-computer-
science/6-111-introductory-digital-systems-laboratory-spring-2006/

Course outcomes: At the end of the course, the student will be able to

CO 1 Get expertise in Finite State Machines

CO 2 Get experitise in basic hardware modeling techniques

CO 3 Get familiarized with timing parameters in digital circuits

CO 4 Get familiarized with Fabrication steps of MOSFET circuits

CO 5 Get familiarized with Layout concepts of MOSFET circuits

CO 6 Get familiarized with transistor level implementation of digital circuits

For Theory courses only:
Course Nature Theory

Assessment Method

Assessment Assessment Monthly tests End Semester Total

Tool Tests Test

Weightage 10% 30% 60% 100%

(%)