Computer Architecture: Lecture “6”

Multicycle MIPS Implementation

• “Severe 100% midterm advisory”

• Thursday!!

1
 Single-Cycle CPU Summary
• Fairly straightforward
• Which instruction takes the longest?
By how much? Why is that a problem?
• Execution time = insts * cpi * cycle
time

Æ Most machines are not single-cycle.

2
 Evaluating Critical Path
I mem Decode, ALU PC D mem R-Write Total
R-Read update
R-type 1 1 .9 - - .8 3.7
Load 1 1 .9 - 1 .8 4.7
Store 1 1 .9 - 1 - 3.9
beq 1 1 .9 .1 - - 3

PCSrc

1
Add M
u
x
4 ALU 0
Add result
RegWrite Shift
left 2

Instruction [25–21] Read

Read register 1 Read MemWrite
PC data 1
address Instruction [20–16] Read MemtoReg
ALUSrc
Instruction register 2 Zero
1 Read ALU ALU
[31–0] Write data 2 1 Read
M result Address 1
u register M data
Instruction Instruction [15–11] x u M
memory Write x u
0 data Registers x
0
Write Data 0
RegDst data memory
Instruction [15–0] 16 Sign 32
Insight: Different extend ALU
control
MemRead

instructions have Instruction [5–0]

ALUOp 3
different critical paths!
 Multicycle design
• Problem: In single-cycle design, cycle time must be long
enough for longest instruction
• Solution: break execution into smaller tasks
- each task takes a cycle;
- different instructions require different numbers of cycles

• Another advantage: we can multiplex area-intensive datapath

components (memories, ALUs, etc) and use them multiple
times for a given instruction (as long as each use is on a
different cycle.)

This used to be one of the key desirable features of

multicycle – not so much anymore..

4
 Idea: quantize instruction execution into
smaller steps
• Five execution steps (some instructions use
fewer)
- IF: Instruction Fetch
- ID: Instruction Decode (& register fetch & add PC+immed)
- EX: Execute
- Mem: Memory access
- WB: Write-Back into registers

I cache Decode, ALU PC D R- Total

R-Read update cache Write
R-type 1 1 .9 - - .8 3.7
Load 1 1 .9 - 1 .8 4.7
Store 1 1 .9 - 1 - 3.9
beq 1 1 .9 .1 - - 3.0

5
 Will multicycle be faster?
Æ Depends on program + stage timings
Cycles Instruction
needed frequency
R-type 4 60% What is CPI assuming
Load 5 20% this instruction mix???
Store 4 10%
beq 3 10%

Single cycle design:

Clock cycle time = 4.7ns
time/inst = 1 cycle/inst * 4.7 ns/cycle = 4.7 ns/inst
Multicycle design:
Clock cycle time = 1 ns
time/inst = CPI * 1 ns/cycle
=
6
 Adding State Elements

Since execution takes place over

multiple cycles, and we reuse some
of the hardware, we need to
capture intermediate results.
Need extra registers when:
- signal is computed in one clock cycle and
used in another, AND
- the inputs to the combinational circuit
can change before the signal is written
into a state element.
• We only require them to be “held” for 1
cycle
7
 Where to add registers (more or
less)
IF ID Ex Mem WB

PCSrc

M
Add u
x
4 Add ALU
result
Shift
left 2
Registers
Read 3 ALU operation
MemWrite
Read register 1 ALUSrc
PC Read
address Read data 1 MemtoReg
register 2 Zero
Instruction ALU ALU
Write Read Address Read
register M result data
data 2 u M
Instruction u
memory Write x Data x
data memory
Write
RegWrite data
16 32
Sign
extend MemRead

8
Merging Logic from Single Cycle to MultiCycle
PCWriteCond PCSource
PCWrite ALUOp
IorD Outputs
ALUSrcB
MemRead
Control ALUSrcA
MemWrite
RegWrite
MemtoReg
Op RegDst
IRWrite [5–0]
0
M
Jump 1 u
Instruction [25–0] 26 28 address [31-0] x
Shift
left 2 2
Instruction
[31-26] PC [31-28]
PC 0 0
M Instruction Read
[25–21] register 1 M
u Address u
x Read x
Instruction Read A Zero
1 Memory
[20–16] register 2 data 1 1
0 ALU ALU ALUOut
MemData Registers
Instruction M Write result
Read B
[15–0] Instruction u register data 2 0
Write Instruction [15–11] x 4 1 M
data Write u
register 1 data 2 x
Instruction 0 3
[15–0] M
u
x
Memory 1
data 16 32 ALU
Sign Shift
register control
extend left 2

Instruction [5–0]

PCSrc

M
Add u
x
4 Add ALU
result
Shift
left 2
Registers
Read 3 ALU operation
MemWrite
Read register 1 ALUSrc
PC Read
address Read data 1 MemtoReg
register 2 Zero
Instruction ALU ALU
Write Read Address Read
register M result data
data 2 u M
Instruction u
memory Write x Data x
data memory
Write
RegWrite data
16 32
Sign
extend MemRead
9
 Multicycle Datapath – let’s figure out
basic execution model
PCWriteCond PCSource
PCWrite ALUOp
IorD Outputs
ALUSrcB
MemRead
Control ALUSrcA
MemWrite
RegWrite
MemtoReg
Op RegDst
IRWrite [5–0]
0
M
Jump 1 u
Instruction [25–0] 26 28 address [31-0] x
Shift
left 2 2
Instruction
[31-26] PC [31-28]
PC 0 0
M Instruction Read
[25–21] register 1 M
u Address u
x Read x
Instruction Read A Zero
1 Memory
[20–16] register 2 data 1 1
0 ALU ALU ALUOut
MemData Registers
Instruction M Write result
Read B
[15–0] Instruction u register data 2 0
Write Instruction [15–11] x 4 1 M
data Write u
register 1 data 2 x
Instruction 0 3
[15–0] M
u
x
Memory 1
data 16 32 ALU
Sign Shift
register control
extend left 2

Instruction [5–0]

10
 Summary of execution steps
S te p
In s tru c tio n F e tc h
In s tru c tio n D e c o d e /
re g is te r fe tc h
E x e c u tio n , a d d re s s
c o m p u ta tio n , b ra n c h
c o m p le tio n
M e m o ry a c c e s s o r R -
ty p e c o m p le tio n
W rite -b a c k
R -ty p e M e m o ry B ra n c h
IR = M e m [P C ]
PC = PC + 4
A = R e g [IR [2 5 -2 1 ]]
B = R e g [IR [2 0 -1 6 ]]
A L U o u t = P C + (s ig n -e x te n d (IR [1 5 -0 ]) < < 2 )
A LU out = A op B A LU out = A + if (A = = B ) th e n
s ig n - PC=A LU out
e x te n d (IR [1 5 -0 ])
R e g [IR [1 5 -1 1 ]] = m e m o ry -d a ta =
A LU out M e m [A L U o u t]
or
M e m [A L U o u t]=
B
R e g [IR [2 0 -1 6 ]] =
m e m o ry -d a ta

This is Register Transfer Language (RTL)

“High level” description of changes to state elements
We’ll go through these in exacting detail
And translate them to “low level” control signal settings
Modern design tools do this automatically
11
 Multicycle Datapath – let’s figure out
control logic
PCWriteCond PCSource
PCWrite ALUOp
IorD Outputs
ALUSrcB
MemRead
Control ALUSrcA
MemWrite
RegWrite
MemtoReg
Op RegDst
IRWrite [5–0]
0
M
Jump 1 u
Instruction [25–0] 26 28 address [31-0] x
Shift
left 2 2
Instruction
[31-26] PC [31-28]
PC 0 0
M Instruction Read
[25–21] register 1 M
u Address u
x Read x
Instruction Read A Zero
1 Memory
[20–16] register 2 data 1 1
0 ALU ALU ALUOut
MemData Registers
Instruction M Write result
Read B
[15–0] Instruction u register data 2 0
Write Instruction [15–11] x 4 1 M
data Write u
register 1 data 2 x
Instruction 0 3
[15–0] M
u
x
Memory 1
data 16 32 ALU
Sign Shift
register control
extend left 2

Instruction [5–0]

12
 PCWriteCond CauseWrite
CauseWrite
PCWriteCond
IntCause
IntCause
PCWrite
PCWrite EPCWrite
Outputs EPCWrite
IorD
IorD Outputs PCSource
PCSource
MemRead ALUOp
ALUOp
MemRead
Control ALUSrcB
ALUSrcB
MemWrite
MemWrite Control
ALUSrcA
ALUSrcA
MemtoReg
MemtoReg RegWrite
RegWrite
Op
Op
IRWrite
IRWrite [5–0] RegDst
RegDst
[5–0]
00

Jump 11MM
Instruction 26
26 28
28 Jump u
Instruction[25–0]
[25–0] Shift
Shift
address
address[31-0]
[31-0] x
u
left 22 x
left22
Instruction CO 33
Instruction
[31-26] CO00
0000
0000
00
[31-26] PC
PC
PC 00 00 PC[31-28]
[31-28]
M Instruction
Instruction Read
Read
M [25–21] register MM
uu Address
Address [25–21] register11 uu
xx Read xx
Memory
Memory Instruction
Instruction Read
Read Read AA Zero
11 data 1 11 Zero
[20–16]
[20–16] register22 data 1
register
ALU
MemData
MemData 00 Registers ALU ALUALU ALUOut
ALUOut EPC
Registers result EPC
Instruction
Instruction MM Write
Write Read result
[15–0] register Read BB
[15–0] u register data 00
Instruction
Instruction xu data22
Write
Write Instruction [15–11]
[15–11] x 44 11M
data Instruction Write M
data 11 Write u
register
register data
data 22 xu
x
Instruction 00 33 00 00
Instruction
[15–0]
[15–0] M MM
M uu Cause
uu Cause
xx xx
Memory 11 11 11
Memory
data
data 16
16 32
32 ALU
Sign
Sign Shift
Shift ALU
register
register control
extend
extend left
left22 control

Instruction
Instruction[5–0]
[5–0]

13
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