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Electr Eng

DOI 10.1007/s00202-017-0510-x

ORIGINAL PAPER

Modeling and simulation of a MMC-based solid-state transformer


M. Ebrahim Adabi1 · Juan A. Martinez-Velasco1 · Salvador Alepuz2

Received: 18 November 2016 / Accepted: 31 January 2017


© Springer-Verlag Berlin Heidelberg 2017

Abstract This paper presents a model of a bidirectional at both primary and secondary sides, DC and high-frequency
MV/LV solid-state transformer (SST) for distribution system ac power supply. In addition, the SST can provide some oper-
studies. A modular multilevel converter configuration is used ational benefits, namely reducing environmental concerns by
in the MV side of the STT. The LV side uses a three-phase introducing a design that does not use mineral oil or other
four-wire configuration that can be connected to both load liquid dielectrics, and efficient management of distribution
and generation. The model developed for this work has been resources by incorporating online monitoring and other dis-
implemented in MATLAB/Simulink, and its behavior has tribution automation functionalities.
been tested by carrying out several case studies under differ- A thorough revision of the topologies and control strate-
ent operating conditions. The simulation results support the gies proposed to date for configuring a three-stage SST
feasibility of the SST and its advantages in comparison to the design was presented in [4]. Readers interested in these
conventional transformer. The paper also includes a discus- aspects can also consult references [5–8].
sion of the main model limitations and the future work. Since standardized voltages used for MV distribution
grids are usually equal or higher than 10 kV [9], multilevel
Keywords Bidirectional converter · Distribution system · topologies must be considered for the MV side of the SST
Modular multilevel converter · Power quality · Solid-state if conventional Si-based semiconductors are used [10–12];
transformer that is, a realistic SST model has to consider a multilevel con-
verter representation at the MV side. Different topologies of
multilevel converters have been proposed for SST applica-
1 Introduction tions. In addition, given the required number of levels, even
for the lowest voltages, the selected topology has to face
The solid-state transformer (SST) is seen as a proper replace- some important aspects such as capacitor voltage balancing
ment of the conventional iron-and-copper transformer in the and complex control strategies [13–16].
future smart grid [1–3]. Utilities can expand traditional ser- Recently, modular multilevel converter (MMC) topolo-
vices by integrating various power requirements, monitoring, gies have attracted attention for high- and medium-voltage
and communications into a universal customer interface such (MV) applications [17,18]. MMC technology can provide an
as the SST. The SST offers several benefits that can be of effective topology for MV applications; their main advan-
paramount importance for the development of the smart grid tages are modularity and scalability [19–26]: the desired
[4–7]: enhanced power quality performance, fast voltage con- voltage level can be easily achieved by a series connection of
trol, reactive power compensation or reactive power control MMC submodules (SMs). In addition, a MMC topology can
provide high power quality and efficiency with reduced size
of passive filters, can work at lower switching frequencies,
B M. Ebrahim Adabi
ebrahim.adabi@upc.edu produce lower total harmonic distortion (THD), and place
less voltage stress on the semiconductor devices. These fea-
1 Universitat Politecnica de Catalunya, Barcelona, Spain tures made the MMC option an attractive topology for the
2 Mataró School of Technology, Mataró, Spain MV stage of the SST [27,28].

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Electr Eng

This paper proposes a three-stage SST model that uses converter, which in such case works as rectifier. The isolation
MMC technology for the MV side and a three-phase four-leg stage, which includes a high-frequency transformer (HFT)
converter for the low-voltage (LV) side. A three-phase MMC and the two corresponding MV- and LV-side converters,
topology has been considered as SST input stage, while a first converts the MV-side DC voltage into a high-frequency
single-leg MMC topology has been selected for the MV side square-wave voltage applied to the primary side of the HFT;
of the isolation stage. the secondary-side square-wave signal is then converted to a
This paper is aimed at: (1) presenting a bidirectional LV DC waveform by the LV-side converter, which also works
MV/LV SST model implemented in MATLAB/Simulink and as rectifier. Finally, the output LV-side three-phase DC/AC
whose MV side is based on a MMC configuration, (2) devel- converter, which works as inverter, provides the output power
oping a SST model with a configuration close to the actual frequency AC waveform from the LV-side DC link.
SST configuration, and (3) testing the feasibility and per- The MV side (hereinafter known as input stage) is
formance of the proposed model under various operating connected to a MV distribution grid, while the LV side (here-
conditions. inafter known as output stage) is assumed to be connected
The paper is organized as follows. The configurations to a LV grid in which both load and generation might be
and controller designs of the proposed three-stage MMC- present. When the power flows from the LV side to the MV
based SST model are presented in Sect. 2. The model has side (i.e., the LV generation is predominant), the SST behav-
been tested under severe dynamic and unbalanced conditions; ior is similar to that described above; basically, input and
Sect. 3 summarizes the main aspects of the implemented output stages swap functions. The rest of this section pro-
model and discusses the simulation results corresponding to vides a summary of the configuration selected for each stage
several case studies. These results will confirm the enhanced and the corresponding controllers.
behavior of the SST in comparison to the conventional In this paper, a three-phase MMC with half-bridge SMs is
transformer. Main conclusions and future development are used for input stage. A voltage-oriented control (VOC) strat-
summarized in Sect. 4. egy has been used to generate proper reference signals; a
level-shifted PWM method is used as modulation technique.
In addition, a sorting algorithm technique is used for balanc-
2 Configuration and control of the solid-state ing the SM capacitance voltages.
transformer The isolation stage is divided into three parts: a single-
phase MMC, a HFT, and a single-phase bidirectional PWM
2.1 General configuration of the solid-state transformer converter. An open-loop level-shifted PWM and a sorting
algorithm have been used to control the MV single-phase
Figure 1 shows the schematic configuration of the bidirec- MMC, while a proportional resonant (PR)-based control is
tional SST design selected for this work. This design consists applied to the LV single-phase bidirectional PWM converter.
of three main stages: medium-voltage stage, isolation stage, A three-phase four-leg converter is used for the output
and low-voltage stage. When the power flows from the MV stage. A VOC strategy with a three-dimensional SVM mod-
side to the LV side, the input power frequency AC voltage is ulation technique has been implemented to generate proper
converted into a MV DC voltage by the three-phase AC/DC reference signals.

Medium Voltage Stage Isolation Stage Low Voltage Stage

High Voltage Low Voltage Load


Grid Three Phase Four Leg
Line Filter Single Phase Single-phase Load Filter and/or
Voltages AC/DC Converter DC/AC Inverter
DC/AC Converter AC/DC Rectifier Generation
Vga
R1 L1
HFT R2 L2
Vgb

Vgc C2
Rn 2 Ln 2

Fig. 1 Schematic configuration of the three-stage SST design

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Electr Eng

Sa1 Da1 iua + iub + iuc + idc1


+
vc
− +
SM 1a SM 1b SM 1c
+
Sa 2 Da 2 vSM
− vdc1/2
SM 2a vua SM 2b vub SM 2c vuc

SM na SM nb SM nc
− − −
Rarm Rarm Rarm
Vga R1 L1
Larm Larm Larm
ia
Vgb va ib
vb ic
vc icirc
Vgc
Rarm Rarm Rarm

Larm Larm Larm


I la I lb I lc
+ + +
SM 1a SM 1b SM 1c
+
SM 2a vla SM 2b vlb SM 2c vlc vdc1/2

SM na SM nb SM nc

− − −
Fig. 2 Configuration of the three-phase input stage

2.2 Input stage: configuration and control 2.2.1 Mathematical model

The MV stage of the SST is connected to a three-phase To better analyze the model of the MV-side MMC, Fig. 2
AC distribution system via RL filters. Figure 2 shows the also shows the interaction of one MMC leg and the MV dc
configuration of the three-phase MMC selected for this link [29,30]. The current of the upper and lower arms of the
work. If it is assumed the power flows from the MV side phase k, (k = a, b, c), i uk and ilk , can be expressed as:
to the LV side of the SST, the MV-side MMC acts as
a rectifier that converts the AC voltage of the grid to a ik
i uk = i circ − (1)
DC voltage. A half-bridge configuration is proposed for 2
each SM; see Fig. 2. In case of power flow reversal, the ik
ilk = i circ + (2)
MMC passes to act as inverter that converts the DC volt- 2
age of the input stage DC link to AC voltage at power
where i k is the input current of phase k, and i circ is the circulat-
frequency.
ing current which can be achieved through adding (1) and (2):

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iq ωL
vdc1 id iarm vcSM
- - vd* Level Shifted
vdc* 1 + PI + PI -+ vdc1 / 2 PWM
+ dq
vd Capacitor
vk* + Voltage MMC
− + Balancing Converter
iq vq Block
- vq* abc
iq* + PI -+-

id ωL

Fig. 3 Control diagram of three-phase input stage MMC controller

equation (8) becomes:


i uk + ilk
i circ = (3)
2
di k
vgk = veq + Req i k + L eq (12)
Upper and lower voltages of the phase k, vuk and vlk can be dt
expressed as:
2.2.2 High-voltage-side control
vdc1 di uk
vuk = − vk − Rarm i uk − L arm (4)
2 dt A VOC strategy has been selected to generate proper ref-
vdc1 dilk erence signals for the modulation technique implemented
vlk = + vk − Rarm ilk − L arm (5)
2 dt in this work. The positive-sequence grid voltage is used to
obtain the grid angle for synchronization purposes by means
where vk is the voltage of phase k at the AC side of the
of a phase-locked loop (PLL). The block diagram is shown
MMC, Rarm and L arm are, respectively, the resistance and
in Fig. 3; the VOC scheme provides the reference voltage of
inductance of each MMC arm.
phase k, vk∗ [31,32].
By subtracting (5) from (4) and substituting i uk and ilk
From Eqs. (4) and (5) and upon neglecting voltage drop
from (1)–(2), the following form for vk is obtained:
across the arm impedance, the reference voltages for upper
and lower arms of phase k, vuk∗ , and v ∗ are obtained as fol-
vlk − vuk Rarm i k L arm di k lk
vk = + + (6) lows:
2 2 2 dt
As it can be seen from Fig. 2: ∗ vdc1
vuk = − vk∗ (13)
2
di k ∗ vdc1
vgk = vk + R1 i k + L 1 (7) vlk = + vk∗ (14)
dt 2

where R1 and L 1 are, respectively, the per-phase resistance 2.2.3 Level-shifted modulation
and inductance of the input filter.
Upon substituting (6) in (7) the following equation is Different modulation techniques, such as level-shifted PWM,
obtained: phase-shifted PWM, phase disposition PWM, selective har-
vlk − vuk Rarm i k L arm di k di k monic elimination, space vector modulation (SVM), or
vgk = + + + R1 i k + L 1 (8) nearest level modulation (NLM), have been developed to
2 2 2 dt dt
control MMCs [33–35]. A level-shifted PWM strategy is
An equivalent circuit of the MMC can be derived from these used in this work [36]; see Fig. 3. The reference voltages of
results. By using the following forms phase arms are compared to n triangle carriers to generate the
desired (n+1) output voltage levels. In this modulation tech-
vlk − vuk
veq = (9) nique the number of inserted SMs in upper and lower arms
2 (n u and nl ) is always controlled so that nSMs are inserted in
Rarm
Req = R1 + (10) each leg at any instant; therefore,
2
L arm
L eq = L1 + (11) n u + nl = n (15)
2

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Table 1 Switching levels for Level nu nl vko voltage balancing algorithm, based on that proposed in [36]
each MMC leg and [37].
1 6 0 − V2dc As shown in Fig. 4, the algorithm block has three inputs:
2 5 1 − V3dc SM capacitor voltages of each MMC arm (which are moni-
3 4 2 − V6dc tored and sorted in descending order), the current direction
4 3 3 0 of each MMC arm (if the arm current is positive, it is then
5 2 4 + V6dc charging SMs, which are therefore increasing their volt-
ages; if the arm current is negative, it is then discharging
6 1 5 + V3dc
SMs, which are therefore decreasing their voltages), and the
7 0 6 + V2dc
level number determined by the level-shifted PWM tech-
nique (see Table 1). Based on a sorting algorithm when
the modulator decides to insert a SM, then SMs with min-
If the MMC converter has n SMs in each arm (see Fig. 2), imum/maximum capacitor voltage will be inserted when
then n in-phase carrier waveforms are compared with the the current charges/discharges the corresponding capacitor.
reference waveform of each phase as depicted in Fig. 3. Every time the modulator decides to bypass a SM, it is the SM
Table 1 shows the different generated level for output with maximum/minimum capacitor voltage that is bypassed
phase voltage of one leg [36] when the number of SMs per when the current charges/discharges the capacitor.
arm is six. Remember that to generate a seven-level phase
voltage, the number of inserted SMs in upper and lower arms
is always six. 2.3 Isolation stage: configuration and control

2.2.4 Capacitance balancing The model implemented for representing the isolation stage
consists of three major parts (see Fig. 5): (1): a one-leg single-
Under practical conditions, the voltage of a SM capacitance phase MMC that acts as inverter and generates n+1 level
changes due to charging/discharging states, variation of cur- high-frequency input waveform to the HFT (in this work a
rent values, and different conduction times of switches. This seven-level, 1 kHz waveform); (2) the HFT, modeled as an
may lead to undesired consequences such as unbalanced volt- ideal transformer in series with its short-circuit impedance;
ages and higher harmonic distortion. Therefore, an algorithm and (3) a LV single-phase two-level full-bridge PWM con-
for proper capacitance voltage balancing must be used to keep verter that acts as a rectifier and provides the required DC link
the voltage of each arm at the desired level. The sorting algo- voltage for the output stage of the SST [38]. A short descrip-
rithm used in this work for SM capacitance voltage balancing tion of the control strategy implemented for the converters at
is that proposed in [37]. Figure 4 shows the flowchart for the each HFT side is given below.

Modulating reference generator

Determine the number of required SMs in


the upper and lower arms (nu + nl = 6)
Standby state
vcu1 vcu2 vcu6 iuk ilk vcl1 vcl2 vcl6
Add Remove
module module
Measure arm Measure arm
Sort nu nl Sort current current

Discharging state: Find Discharging state: Find


Capacitance
Switchingbalancing
functionsblock the highest-voltage off the lowest-voltage on
capacitor and connect it capacitor and bypass it
Charging state: Find the Charging state: Find the
lowest-voltage off capa- highest-voltage on capa-
citor and connect it citor and bypass it

Firing signal generator

Firing signals

Fig. 4 Control block diagram and sorting algorithm for MMC converter

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iui
+
SM 1i
+
vdc1/2
SM 2i vui

Medium Voltage MMC Converter

SM ni
-

Low Voltage Converter


High Frequency
Ri Transformer (HFT) Sa1 Da1 Sa3 Da3

Li ip +
+
is +
vtp vts vdc2
- −
Ri -
Sa2 Da2 Sa4 Da4
Li
ili +
SM 1i

+ SM 2i vli

vdc1/2
− SM ni
-

Fig. 5 Isolation stage configuration

2.3.1 Single-phase MMC The level-shifted PWM strategy is used to determine the
number of SMs to be inserted or bypassed in each arm (n u
The control strategy implemented for this single-phase con- and nl in Table 1); after that, the sorting algorithm is used
verter is similar to that discussed in the previous subsection. to balance capacitance voltages of SMs and generate gate
An open-loop level-shifted PWM and a sorting algorithm signals (as shown in Fig. 4).
have been used for controlling the single-phase MMC. The
AC reference voltage, vt∗p , can be expressed as follows:
2.3.2 Single-phase two-level full-bridge converter

vdc1
vt∗p = m a sin (2π f h t) (16) The LV single-phase two-level bridge rectifies the output cur-
2 rent of the HFT (i s ) and controls the LV-side DC link voltage
(vdc2 ) at the desired value. The diagram of the controller is
where m a is the modulation index of inverter (0.933 in this shown in Fig. 6 [39,40]. The DC link voltage vdc2 is com-
work), vdc1 is the DC link voltage at the MV side of the SST, pared to its reference value, and the resulting error is applied
and f h is the operating frequency of the HFT. to a PI controller. The output signal of PI controller is used
The upper and lower arm reference voltages, vui ∗ and v ∗ , to generate the reference current (i s∗ ).
li
are obtained as follows: The error (i s∗ − i s ) is applied to a PR controller to gen-
erate the reference value for PWM block. The PR technique
can successfully replace the typical PI-dq control scheme
∗ vdc1
vui = (1 − m a sin (2π f h t)) (17) for three-phase systems exhibiting some advantages (e.g.,
2
vdc1 improved harmonic rejection capability). In addition, a PR
vli∗ = (1 + m a sin (2π f h t)) (18) controller can provide a fast control with a structure simpler
2

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vdc 2 vs

* - is*
vdc 2 + PI + PR PWM Sa1, Sb 2
-
Sa 2 , Sb1
is

Fig. 6 Diagram of the single-phase isolation stage MMC controller

Inverter
idc2 ip2 p2

iC2 Load / Generation


ia2 R2 L2 v2agrid ia2I
a2
ib2 v2bgrid ib2I
vdc2 Cdc2 b2
ic2 v2cgrid ic2I
c2
in2 Rn2 Ln2 C2
f
N2

n2

Fig. 7 Low-voltage-side converter configuration

than other controllers such as PI control, hysteresis current The implemented model of the converter was presented
control, and predictive current control. A bidirectional PWM and detailed in some previous references of the same authors
technique is applied to generate switching pulses [39,40]. [41–43]. The switching strategy selected for this converter
is based on that proposed in [44]. For more details on the
2.4 Output stage: configuration and control control strategies and the applications of three-phase four-
leg converters, see [45–47].
The LV side of the SST uses a three-phase four-leg PWM
converter, with an RL impedance for filtering currents and a 3 Testing the performance of the SST model
capacitor bank for filtering voltages, see Fig. 7.
The converter configuration depicted in the figure may 3.1 System model and parameters
be connected to load and/or generation, and it is responsi-
ble for controlling the voltage (waveform and value) seen The model of the SST has been implemented in MAT-
by load/generation. The main task of the LV-side converter LAB/Simulink assuming lossless semiconductors and a sim-
controllers is to achieve positive-sequence capacitor volt- ple representation of the single-phase isolation transformer
ages (i.e., to obtain balanced voltages at capacitor terminals) (i.e., an ideal transformer plus the short-circuit impedance).
with stable frequency and voltage, independently of the Each lower and upper arm of the MV-side stage consists of
load/generation level and the unbalance of LV-side currents. six SMs; see Figs. 2 and 5.
The capacitor voltage has to be controlled by the regulator, The test system is that obtained when joining the three
and it is likely to have unbalanced load/generation currents. stages that form the SST plus a three-voltage source; see
Each positive, negative, and zero sequence has its corre- Fig. 1. This configuration will be used to evaluate the behav-
sponding controller. Negative- and zero-sequence capacitor ior of the SST under dynamic and unbalanced conditions
voltage references are permanently set to zero to cancel these (voltage sag at the primary MV side, load unbalance at the
components at the filter capacitor terminals, even in pres- secondary LV side, LV secondary-side short circuit), and
ence of unbalanced load/generation currents. The positive- operation conditions that could cause power flow reversal
sequence voltage controller regulates the filter capacitor (i.e., active power flowing from the LV to the MV side and
voltages. A PWM control strategy using voltage-oriented vice versa). The SST ratings and parameters are listed in
control (VOC) has been implemented to keep the harmonic Table 2; see also Fig. 1. Transformer parameter values shown
content above twice the switching frequency. in Table 2 are referred to the secondary LV side; see [41–43].

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Table 2 SST parameters 15


10
Parameters Values

Voltage (kV)
5
Line-to-line grid voltage (rms) 12 kV
0
Grid-side filter resistance (R1 ) 0.1 
-5
Grid-side filter inductance (L 1 ) 10 mH
Number of SMs per MMC arm 6 -10
Modulation index of the MMC 0.933 -15
converters 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
Time (s)
SM capacitance in MMC1&MMC2 0.4 mF
Arm resistance of MMC1 0.2  (a)
Arm inductance of MMC1 5 mH 40
MMC1 switching frequency 10 kHz
20

Current (A)
Reference signal frequency of the 50 Hz
level-shifted PWM in MMC1
0
Reference signal frequency of the 1 kHz
level-shifted PWM in MMC2
-20
MV-side DC link capacitance 1 mF
Arm resistance of MMC2 0.001
-40
Arm inductance of MMC2 0.1 mH 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
MV MMC2 and LV full-bridge 10 kHz Time (s)
converter switching frequency (b)
Transformer operating frequency 1 kHz 400
Transformer short-circuit resistance 0.005 
Transformer leakage inductance 0.03 mH 200
Voltage (V)

LV-side DC link capacitance 3 mF


LV-side converter switching 10 kHz 0
frequency
-200
Load-side filter resistance (R2 ) 0.01 
Load-side filter inductance (L 2 ) 0.9 mH
-400
Load-side filter capacitance (C2 ) 200 μF 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
Neutral resistance (Rn2 ) 0.01  Time (s)
Neutral inductance (L n2 ) 0.3 mH (c)
Fig. 8 Simulation results: Voltage sag at the primary MV terminals. a
Primary-side voltages, b primary-side currents, c secondary-side volt-
All case studies were simulated assuming the rated power ages
of the SST is 250 kVA. The MV-side MMC converter is
controlled to obtain a zero reactive power at the MV termi- MV side of the SST. Between 1200 and 1600 ms voltages
nals; that is, the SST will compensate at the MV terminals of phases A and B experiment a reduction. As observed
the reactive power irrespective of the load and/or generation from Fig. 8, the distorted voltages and currents at MV
connected to the LV terminals. side are not propagated to the LV side whose phase-
to-neutral voltages are not affected by the MV-side sag;
consequently the load currents will remain balanced as
3.2 Case studies
they were prior to the sag occurrence, and their peak mag-
nitude unaffected by the voltage sag. This behavior can
The simulation results derived from four different case stud-
be easily understood by taking into account the decou-
ies carried out to evaluate the performance of the proposed
pling provided by the DC–DC isolation stage, which will
SST model are presented below. The operating conditions
prevent the propagation of the voltage unbalance caused
for each test case are based on those considered in previous
at the primary MV side to the secondary LV side.
papers; see [41–43].
2. LV-side load unbalance (Fig. 9): A load variation occurs
to the initially balanced load connected to the LV SST ter-
1. Unbalanced voltage sag at the primary MV terminals (see minals. The variation causes a current unbalance due to
Fig. 8): A voltage sag occurs at the source that feds the an increase in the current in two load phases. Results pre-

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600 800

300 400

Current (A)
Current (A)

0 0

-300 -400

-600 -800
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
Time (s) Time (s)
(a) (a)
30 400
20
200

Voltage (V)
Current (A)

10
0 0
-10
-200
-20
-30 -400
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
Time (s) Time (s)
(b) (b)
400 30
20
200
Voltage (V)

Current (A)

10
0 0
-10
-200
-20
-400 -30
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
Time (s) Time (s)
(c) (c)
Fig. 9 Simulation results: unbalanced LV-side load. a Secondary-side Fig. 10 Simulation results: short circuit at the secondary LV terminals.
currents, b primary-side currents, c secondary-side voltages a Secondary-side currents, b secondary-side voltages, c primary-side
currents
sented in Fig. 9 prove that the secondary phase voltages
remain constant during the load variation and the cur- the phase currents are larger than before the short-circuit
rent unbalance is not propagated to the input stage where occurrence. The combination of lower voltages and larger
the three-phase currents increase simultaneously without currents causes a reduction in both the active and reac-
exhibiting any unbalance. As with the previous case, this tive powers measured at the LV terminals. This means
behavior can be understood by taking into account the that the active power measured at the MV terminals will
decoupling provided by the DC–DC isolation stage. At also be lower than before the short-circuit occurrence
the same time the load currents become unbalanced, and (remember that the reactive power is always close to
there is an increase in the power supplied from the LV zero at the MV terminals). As a consequence, the cur-
side that is also noticed at the MV side, as one can deduct rents measured at the MV terminals will be lower during
from the variation of the primary MV-side currents during the fault condition than before; that is, the SST prevents
the analyzed period. from propagating the short-circuit overcurrents to the MV
3. Short circuit at the secondary LV terminals (Fig. 10): A grid. This response is a consequence of the current limiter
three-phase short circuit occurs at the LV terminals of implemented in the LV-side converter: if the maximum
the SST. Theoretically, this should cause a large increase short-circuit current can reach a peak value much higher
in the phase currents at the LV terminals. However, the than the specified limit, then the controller decreases the
voltage drop experienced at the secondary side of the SST terminal voltage and protects the SST by limiting both
significantly reduces the short-circuit currents, although currents and powers. The current limit depends on the

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Electr Eng

300 from the MV side to the LV side, while the reactive power
P
200 measured at the MV terminals remains close to zero, irre-
Power (kW/kvar)

Q
100 spective of the reactive power measured at the LV terminals.
0
Other results not shown in Fig. 11 support the feasibility of
the SST since the secondary-side voltages are not affected
-100
by the transient due to the power flow reversal, and both
-200 MV- and LV-side currents remain balanced. Although plots
-300 do not provide too much information about voltages (except
1.2 1.4 1.6 1.8 2.0 2.2 2.4
Time (s)
in Fig. 11c), they remain constant at both sides except for the
(a) transients caused at the beginning and the end of the power
flow reversal.
300
P
200
Power (kW/kvar)

Q
3.3 Discussion
100
0 1. The behavior of the MMC-based SST can be quickly
-100 deduced from the results presented above: SST allows
-200 power flow reversal while maintaining voltages at each
-300
side to their values; unbalanced currents at any SST side
1.2 1.4 1.6 1.8 2.0 2.2 2.4 are not propagated to the other side; a close-to-unity
Time (s) power factor is maintained at the input terminals, irre-
(b) spective of the active and reactive powers measured at
20 the LV terminals (see Fig. 11).
Voltage – Current (Phase A)

2. The simulation results presented above show the SST


10 behavior seen from both MV- and LV-side terminals.
However, it is also important to analyze the response of
0
the converter models, mainly those selected for repre-
senting the MV input stage. Figures 12 and 13 show the
-10
transient response of the voltages in MV- and LV-side DC
-20 links, as well as the transient voltage of an upper arm SM
1.2 1.4 1.6 1.8 2.0 2.2 2.4 capacitance, corresponding to some of the case studies
Time (s)
analyzed in the previous subsection. A common pattern
(c) can be deduced from all these responses:
Fig. 11 Simulation results: power flow reversal. a Active and reactive • DC link voltages at both the MV and the LV sides
powers at the secondary side, b active and reactive powers at the primary
side, c primary-side current and voltage—Phase A exhibit a quick variation at the beginning and the end
of the transient, but the voltages quickly recover their
initial values at both moments.
desired performance; without this limitation and keep- • Voltage variations depend on the event being ana-
ing the present filter parameters the short-circuit currents lyzed but also on the parameters selected for repre-
would be higher and so the active power measured at the senting DC links and controllers at both SST sides.
MV side. Obviously larger DC link capacitors will suffer lower
4. Power flow reversal (Fig. 11): The SST is initially oper- voltage variations. In the cases presented in Figs. 12
ating in generation mode; that is, generation is initially and 13, the voltage variations are within the 1% of the
predominant in the secondary side and the active power selected voltage for the MV-side DC link; however,
flows from the output stage (LV side) to the input stage the variation of the output-stage DC link voltage can
(MV side) of the SST. Reactive power measured at the exceed the 15% of the reference voltage in case of
LV-side terminals is initially zero. A variation of the sec- short circuit at the LV terminals (see Fig. 13c).
ondary load causes a reversal of the active power flow • The variations of the SM capacitance voltages are
and an increment of the reactive power. within a 5% margin in all cases. On the other hand, the
differences between voltages of different SM capac-
Results presented in Fig. 11 show the response of the SST: itances or even different MMC legs (not shown in
as soon as the secondary-side power flow reversal is noticed, figures) are also very smalls; they are within a 2%
the SST controllers act and they allow active power to flow margin.

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Electr Eng

21.4 21.4

21.2 21.2
Voltage (kV)

Voltage (kV)
21 21

20.8 20.8

20.6 20.6
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
Time (s) Time (s)
(a) (a)
3.6 3.6

3.55 3.55
Voltage (kV)

Voltage (kV)
3.5 3.5

3.45 3.45

3.4 3.4
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
Time (s) Time (s)
(b) (b)
1400 1400

1200 1200
Voltage (V)
Voltage (V)

1000 1000

800 800

600 600
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
Time (s) Time (s)
(c) (c)

Fig. 12 Simulation results: voltage sag at the MV side. a MV-side DC Fig. 13 Simulation results: short circuit at the LV side. a MV-side DC
link voltage, b capacitance voltage of an MMC upper arm—Phase A, link voltage, b capacitance voltage of an MMC upper arm—Phase A,
c LV-side DC link voltage c LV-side DC link voltage

3. An important aspect to be considered is the ride-through link would not be capable of recovering its voltage after
capabilities of the SST. Just consider the case presented a quick and deep discharge caused by a bold three-phase
in Fig. 8, which presents the SST response in front of short circuit.
voltage sags at the primary side. The behavior of the SST In other words, a very important aspect of the SST design
in this case is excellent; the sag is not propagated to the is related to its ride-through capabilities; future work
secondary side whose load will not notice the event. How- should be addressed to establish a relationship between
ever, it is important to take into account that there is a limit the rated power of the SST, the parameters to be selected
to the sag severity the SST can cope with and that limit for the design of converters and controllers, and the
depends on the parameters selected for the power con- desired ride-through capabilities.
verter components and their controllers. In other words, 4. It must be assumed by default that a low harmonic dis-
the SST might not provide an adequate response if the tortion can be achieved at the SST input stage because
residual voltages during a sag at the three MV-side phases of the MMC topology: this configuration and a level-
were too low. shifted PWM modulation technique can generate a near
A similar reasoning should be followed in case of short sinusoidal voltage waveform that will exhibit a low har-
circuit. If the short-circuit currents were not limited under monic distortion. Since the MMC topology includes an
certain value and the parameters of the secondary-side inductance in both upper and lower arms that serves as fil-
converter were not adequately selected, the LV-side DC ter for its arm current, a simple RL filter at the input stage

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Electr Eng

is sufficient to achieve current waveforms with low har- concerned about reliability and availability of the apparatus
monic distortion. The output-stage three-phase four-leg but also about preventing the impact of disturbances in their
converter has high-power and low-voltage ratings which production.
lead to high rate for current; a low harmonic distortion Not much field experience is currently available about
can be achieved with a VOC strategy containing con- actual designs and real costs (including operation and main-
trollers for negative and zero sequences and 3-D SVM tenance costs). Some studies show that with the present
modulation technique. In this work RL impedance is used technology the volume, weight, and manufacturing cost of
for filtering currents and a capacitor bank for filtering a SST could exceed those of a traditional iron-and-copper
voltages; this solution can achieve a very low harmonic transformer [48].
distortion in both output currents and voltages (see Figs. 8 Future work will be addressed to obtain a more accurate
through 11) when the SST load is linear. representation of some SST components and to the optimum
5. A final aspect of the SST design is related to the design of selection of parameters (e.g., LV-side filter parameters) that
both MV- and LV-side filters. There is a close relationship could guarantee a proper behavior in front of some power
between the parameters selected for representing the fil- quality events. Aspects that are worth mentioning are the rep-
ters, the rated power that can be assigned to the SST, and resentation of semiconductors and the HFT. A more accurate
the ride-through capabilities. Future work should also be representation of semiconductor losses will produce more
addressed to an optimum design of filters to be installed realistic results of the SST efficiency and will also pro-
at both sides of the SST. vide hints for new control strategies that could improve that
efficiency. A similar conclusion can be derived from the
application of a more accurate representation of the HFT,
4 Conclusion since its behavior depends of the frequency range of volt-
ages and currents at each side; an improved representation
This paper has presented the behavior of a MMC-based bidi- could provide some light about the switching frequencies and
rectional SST model under several operating conditions. A strategies that should be applied to control converters at each
very complex model has been developed and implemented SST side.
using MATLAB/Simulink capabilities.
The proposed configuration uses MMC technology at the
MV side due to its scalability and flexibility: the design of
devices with higher rated voltages at the MV side can be References
derived from the design proposed by simply increasing the
1. Bifaretti S, Zanchetta P, Watson A, Tarisciotti L, Clare JC (2011)
number of submodules and/or selecting higher-voltage sub-
Advanced power electronic conversion and control system for uni-
modules. The control strategy implemented here has been versal and flexible power management. IEEE Trans Smart Grid
adapted to the classical three-stage SST configuration shown 2(2):231–243
in Figs. 1, 2, 5, and 7. 2. Wang J, Huang AQ, Sung W, Liu Y, Baliga BJ (2009) Smart grid
technologies. IEEE Ind Electron Mag 3:16–23
The simulation results have shown that the bidirectional
3. Lai JS (2009) Power conditioning circuit topologies. IEEE Ind
SST incorporates some advanced capabilities (e.g., fast volt- Electron Mag 3:24–34
age and power flow control, reactive power compensation, 4. Shiri A (2013) A solid state transformer for interconnection
voltage sag compensation) that support its feasibility as a between the medium and the low voltage grid design. Disserta-
tion, Delft University of Technology
fundamental component of the future smart grid. Interme- 5. She X, Burgos R, Wang G, Wang F, Huang AQ (2012) Review
diate SST DC links provide stage decoupling and prevent of solid state transformer in the distribution system: from compo-
disturbances at one side from propagating to the other side nents to field application. In: IEEE energy conversion congress and
(e.g., LV-side secondary load immunity is achieved in front exposition (ECCE)
6. Maitra A et al (2009) Intelligent universal transformer design and
of an unbalanced situation caused by a voltage sag at the applications. In: 20th international conference and exhibition on
MV-side input stage; unbalanced currents at the LV side are electricity distribution (CIRED)
not noticed at the MV side). 7. Heinemann L, Mauthe G (2001) The universal power electronics
The envisaged applications of the SST are many. Util- based distribution transformer, a unified approach. In: IEEE 32nd
annual power electronics specialists conference, vol 2, pp 504–509
ities are looking for reliable and effective components that 8. Falcones Zambrano SD (2011) A DC–DC multiport converter
could offer potential for remote supervision and control; new based solid state transformer integrating distributed generation and
grid codes and higher penetration of distributed generation storage. PhD Thesis, Arizona State University
will increase the utilities interest in voltage regulation and 9. Std IEC, 60038 (2009) IEC standard voltages. Edition 7
10. Abu-Rub H, Holtz J, Rodriguez J, Baoming G (2010) Medium-
controllability. Solar and wind power developers are other voltage multilevel converters—state of the art, challenges, and
potential customers as they are aiming at using the existing requirements in industrial applications. IEEE Trans Ind Electron
and future grid as efficiently as possible. Industries are also 57(8):2581–2596

123
Electr Eng

11. Kouro S, Malinowski M, Gopakumar K, Pou J, Franquelo LG, Wu 30. Guan M, Chen H, Xu Z (2011) Control and modulation strate-
B, Rodriguez J, Pérez MA, Leon JI (2010) Recent advances and gies for modular multilevel converter based HVDC system. In:
industrial applications of multilevel converters. IEEE Trans Ind 37th annual conference of the IEEE industrial electronics society
Electron 57(8):2553–2580 (IECON)
12. Rodríguez J, Bernet S, Wu B, Pontt JO, Kouro S (2007) Multilevel 31. Yazdani A, Iravani R (2006) A unified dynamic model and control
voltage-source-converter topologies for industrial medium-voltage for the voltage-sourced converter under unbalanced grid condi-
drives. IEEE Trans Ind Electron 54(6):2930–2945 tions. IEEE Trans Power Del 21(3):1620–1629
13. Sabahi M, Yazdanpanah Goharrizi A, Hosseini SH, Bana Sharifian 32. Xu L, Andersen B, Cartwright P (2005) VSC transmission operat-
MB, Gharehpetian GB (2010) Flexible power electronic trans- ing under unbalanced AC conditions—analysis and control design.
former. IEEE Trans Power Electron 25(8):2159–2169 IEEE Trans Power Del 20(1):427–434
14. González F, Martin-Arnedo J, Alepuz S, Martinez-Velasco JA 33. Hagiwara M, Akagi H (2009) Control and experiment of pulse
(2015) EMTP model of a bidirectional multilevel solid state trans- width modulated modular multilevel converters. IEEE Trans Power
former for distribution system studies. In: IEEE PES general Electron 24(7):1737–1746
meeting 34. Konstantinou GS, Ciobotaru M, Agelidis VG (2011) Operation of
15. Wang L, Zhang D, Wang Y, Wu B, Athab HS (2016) Power and a modular multilevel converter with selective harmonic elimination
voltage balance control of a novel three-phase solid state trans- PWM. In: 8th international conference on power electronics and
former using multilevel cascaded H-bridge inverters for microgrid ECCEA Asia (ICPE and ECCEA)
applications. IEEE Trans Power Electron 31(4):3289–3301 35. Ängquist L, Antonopoulos A, Siemaszko D, Vasiladiotis M, Nee
16. She X, Yu X, Wang F, Huang AQ (2014) Design and demonstration HP (2011) Open-loop control of modular multilevel convert-
of a 3.6-kV–120-V/10-kVA solid-state transformer for smart grid ers using estimation of stored energy. IEEE Trans Ind Appl
application. IEEE Trans Power Electron 29(8):3982–3996 47(6):2516–2524
17. Zheng Z, Gao Z, Gu C, Xu L, Wang K, Li Y (2014) Stability 36. Saeedifard M, Iravani R (2010) Dynamic performance of a mod-
and voltage balance control of a modular converter with multi- ular multilevel back-to-back HVDC System. IEEE Trans Power
winding high-frequency transformer. IEEE Trans Power Electron Electron 25(4):2903–2912
29(8):4183–4194 37. Sahoo AK, Leon R, Mohan N (2013) Review of modular mul-
18. Kumar Sahoo A, Mohan N (2014) High frequency link multi- tilevel converters for teaching a graduate-level. Course of power
winding power electronic transformer using modular multilevel electronics in power systems. University of Minnesota, Saint Paul
converter for renewable energy integration. In: 40th annual confer- 38. Shojaei A, Joos G (2013) A modular solid state transformer with
ence of the IEEE industrial electronics society (IECON) a single- phase medium-frequency transformer. In: IEEE electrical
19. Wu D, Peng L (2016) Analysis and suppressing method for the power and energy conference (EPEC)
output voltage harmonics of modular multilevel converter. IEEE 39. Lezana P, Silva CA, Rodríguez J, Pérez MA (2007) Zero-steady-
Trans Power Electron 31(7):4755–4765 state-error input-current controller for regenerative multilevel
20. Wang M, Hu Y, Zhao W, Wang Y, Chen G (2016) Application converters based on single-phase cells. IEEE Trans Ind Electron
of modular multilevel converter in medium voltage high power 54(2):733–740
permanent magnet synchronous generator wind energy conversion 40. Helin W, Qiming C, Ming L, Gen C, Liang D (2014) The study of
systems. IET Renew Power Gener 10(6):824–833 single-phase PWM rectifier based on pr control strategy. In: 26th
21. Mehrasa M, Pouresmaeil E, Zabihi S, Catalao JPS (2016) Dynamic Chinese control and decision conference (CCDC)
model, control and stability analysis of MMC-HVDC transmis- 41. Alepuz S, González F, Martin-Arnedo J, Martinez-Velasco JA
sion systems. IEEE Trans Power Del. doi:10.1109/TPWRD.2016. (2013) Solid state transformer with low-voltage ride-through and
2604295 current unbalance management capabilities. In: 39th annual con-
22. Yu F, Lin W, Wang X, Xie D (2015) Fast voltage-balancing control ference of the IEEE industrial electronics society
and fast numerical simulation model for the modular multilevel 42. Martinez-Velasco JA, Alepuz S, González-Molina F, Martin-
converter. IEEE Trans Power Del 30(1):220–228 Arnedo J (2014) Dynamic average modeling of a bidirectional solid
23. Saad H, Dennetiere S, Mahseredjian J, Delarue P, Guillaud X, state transformer for feasibility studies and real-time implementa-
Peralta J et al (2014) Modular multilevel converter models for elec- tion. Electr Power Syst Res 117:143–153
tromagnetic transients. IEEE Trans Power Del 9(3):1481–1489 43. Alepuz S, González-Molina F, Martin-Arnedo J, Martinez-Velasco
24. Solas E, Abad G, Barrena JA, Aurtenetxea S, Cárcar A, Zajac JA (2014) Development and testing of a bidirectional distribu-
L (2013) Modular multilevel converter with different submodule tion electronic power transformer model. Electr Power Syst Res
concepts—Part I: capacitor voltage balancing method. IEEE Trans 107:230–239
Ind Electron 60(10):4525–4535 44. Perales MA, Prats MM, Portillo R, Mora JL, Leon JI, Franquelo LG
25. Akagi H (2011) Classification, terminology, and application of the (2003) Three-dimensional space vector modulation in abc coordi-
modular multilevel cascade converter (MMCC). IEEE Trans Power nates for four-leg voltage source converters. IEEE Power Electron
Electron 26(11):3119–3130 Lett 99(4):104–109
26. Rohner S, Bernet S, Hiller M, Sommer R (2010) Modulation, 45. Zhang R, Prasad VH, Boroyevich D, Lee FC (2002) Three-
losses, and semiconductor requirements of modular multilevel con- dimensional space vector modulation for four-leg voltage-source
verters. IEEE Trans Ind Electron 57(8):2633–2642 converters. IEEE Trans Power Electron 17(3):314–326
27. Kumar Sahoo A, Mohan N (2014) A power electronic transformer 46. Vechiu I, Curea O, Camblong H (2010) Transient operation of
with sinusoidal voltages and currents using modular multilevel a four-leg inverter for autonomous applications with unbalanced
converter. In: International power electronics conference (IPEC- load. IEEE Trans Power Electron 25(2):399–407
ECCE-Asia) 47. Ebrahimzadeh E, Farhangi S, Iman-Eini H, Blaabjerg F (2016)
28. Shojaei A, Joos G (2013) A topology for three-stage solid Modulation technique for four-leg voltage source inverter without
state transformer. In: IEEE power and energy society general meet- a look-up table. IET Power Electron 9(4):648–656
ing 48. Huber JE, Kolar JW (2014) Volume/weight/cost comparison of
29. Debnath S, Qin J, Bahrani B, Saeedifard M, Barbosa P (2015) Oper- a 1 MVA 10 kV/400 V solid-state against a conventional low-
ation, control, and applications of the modular multilevel converter: frequency distribution transformer. In: IEEE energy conversion
a review. IEEE Trans Power Electron 30(1):37–53 congress and exposition (ECCE)

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