MC9S08QG4-8 Quick Start Tips1

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Copyright © 2005, Highlander Technologies www.highlandertech.com Revision 1.0

November 2005
Table of Contents
MC9S08QG8 INTRODUCTION ................................................................................................................ 5
MC9S08QG8 MINIMUM COMPONENT SYSTEM ............................................................................... 7
PARALLEL INPUT/OUTPUT PORTS ..................................................................................................... 8
KEYBOARD INTERRUPT MODULE.................................................................................................... 10
MC9S08QG8 SERIAL COMMUNICATION.......................................................................................... 12
ANALOG COMPARATOR MODULE ................................................................................................... 13
SIMPLE INVERTER USING THE ANALOG COMPARATOR MODULE ...................................... 15
ANALOG TO DIGITAL CONVERTER ................................................................................................. 16
USING THE ADC COMPARE FUNCTION........................................................................................... 18
WINDOW COMPARATOR USING ADC AND ACMP........................................................................ 20
IIC TO LIN SLAVE ................................................................................................................................... 22
LIN MASTER/SLAVE, IIC OR SPI INPUT ........................................................................................... 24
BRUSHLESS DC FAN/MOTOR DRIVE ................................................................................................ 25
ZERO CROSSING DETECTOR WITH TRIAC DRIVE...................................................................... 27
SMART BATTERY CONTROLLER ...................................................................................................... 28
LOW-COST IR REMOTE WITH COMPANION RECEIVER............................................................ 29
SERIAL COMMUNICATION BRIDGE/GATEWAY ........................................................................... 30
WIRELESS SENSOR APPLICATIONS ................................................................................................. 31
USING THE MC9S08QG8 AS AN IIC PERIPHERAL ......................................................................... 32
PROGRAMMING AND DEVELOPMENT ............................................................................................ 33

November 2005
List of Figures
Figure 1. MC9S08QG8/4 Packages ................................................................................................. 6

Figure 2. Minimum Configuration for MC9S08QG4...................................................................... 7
Figure 3. Parallel I/O example ......................................................................................................... 9
Figure 4. KBI flow chart................................................................................................................ 10
Figure 5. KBI module example...................................................................................................... 11
Figure 6. Serial Communications Ports ......................................................................................... 12
Figure 7. ACMP example flow chart ............................................................................................. 13
Figure 8. Analog comparator example........................................................................................... 14
Figure 9. Logic inverter ................................................................................................................. 15
Figure 10. ADC example ............................................................................................................... 17
Figure 11. Analog compare example ............................................................................................. 18
Figure 12. Window Comparator .................................................................................................... 20
Figure 13. IIC to LIN Slave ........................................................................................................... 22
Figure 14. IIC to LIN Slave Flow Chart ........................................................................................ 23
Figure 15. LIN Master/Slave ......................................................................................................... 24
Figure 16. BLDC Fan/Motor Drive ............................................................................................... 25
Figure 17. BLDC Fan/Motor Drive Flow Chart ............................................................................ 26
Figure 18. Zero-crossing detector .................................................................................................. 27
Figure 19. Zero-crossing Flow Chart............................................................................................. 27
Figure 20. Smart Battery Controller .............................................................................................. 28
Figure 21. Low-cost IR Remote..................................................................................................... 29
Figure 22. Example IR Receiver/AC switch.................................................................................. 29
Figure 23. SPI to IIC Bridge .......................................................................................................... 30
Figure 24. SPI to SCI Bridge ......................................................................................................... 30
Figure 25. SPI to SCI to IIC Gateway ........................................................................................... 30
Figure 26. MC9S08QG8 ISM Transceiver Example..................................................................... 31
Figure 27. MC9S08QG8 as A/D or KBI Peripheral ...................................................................... 32
Figure 28. BDM Tool Connector................................................................................................... 33

November 2005
MC9S08QG8 Introduction
The MC9S08QG8 is the newest member of the Freescale 8-bit family of highly integrated
microcontrollers, based on the high-performance yet low power HCS08 core. The MC9S08QG8
is an excellent solution for power-sensitive applications with extended battery life and maximum
performance down to 1.8VDC.
The MC9S08QG8 has several new features, and many enhanced peripheral functions over
previous product offerings in this size and price range. For a full description of the features,
consult the Freescale MC9S08QG8 data sheet.
The MC9S08QG8 has built-in support features, which reduce the necessity for many external
components, such as an external clock circuit, pull-up resistors on port pins, low voltage detection
circuit, and external reset components. These features, along with low-voltage operation, make
the MC9S08QG8 the ideal choice for battery operated or hand-held applications.
CPU features
• 20MHz HCS08 CPU

• 4 or 8 Kbytes FLASH with 256 or 512 bytes RAM
• Code upward compatible with M68HC05 and M68HC08 Families
• Improved! Internal clock source module, trimmable to 0.2% resolution, can eliminate the
need for external clock components
• Background debug module with breakpoints, single pin BDM interface
• On-chip in-circuit emulation (ICE), eliminates expensive external emulators/debuggers
• Support for up to 32 interrupt/reset sources
Parallel I/O
• 12 GPIO pins plus, 1 input-only, 1 output-only (16-pin package)

• Software selectable pull-up resistors
• Software selectable edge and level sensitive interrupts
• Software selectable slew rate control
• NEW! Software selectable drive strength on GPIO outputs
Peripheral Modules
• Improved! Up to 8 channels of 10-bit A/D converter (ADC) with automatic compare

function, fastest in the 8-bit controller family. ADC can operate in wait mode or stop mode 3
• Improved! Analog comparator module (ACMP) with internal reference, rail-to-rail operation
• Keyboard interrupt module (KBI) can be configured to exit low-power modes on interrupt
• Timer/PWM module with capture/compare modes
• NEW! 8-bit modulo timer module
• Serial communication interface (SCI) module
• Serial peripheral interface (SPI) module
• Inter-integrated circuit bus (IIC) module
• SCI, SPI, IIC communication modules are all mapped to separate port pins
MC9S08QG8 Quick Start Tips 5

Power Savings
• Low voltage operation 1.8 – 3.6 VDC

• Low current – 3.5 ma @ 3.0VDC typical run current at 8 MHz, 475 na in stop mode 1
• Software selectable power saving modes, 1 wait and 3 stop modes
• Numerous provisions for exiting wait or stop modes
System Protection
• Low voltage detect (LVD) module

• Computer operating properly (COP) watchdog timer
• Illegal address detection with reset
• Illegal opcode detection with reset
• FLASH block protection to prevent accidental erasure
• Protection for unauthorized access to RAM and FLASH memory
Packages
The following diagram shows the pin assignments and functions for the MCMC9S08QG4/8
devices.
Figure 1. MC9S08QG8/4 Packages

MC9S08QG8 Minimum Component System
The MC9S08QG4/8 are the latest offering in Freescale Semiconductors 8-bit HCS08 core product
family. The MC9S08QG4/8 are low-power devices, in low pin count (8 or 16 pin) packages. All
of the standard features of the HCS08 CPU core are available, with many flexible and unique
features not found in other products of this size or price range.
Figure 2 shows the basic circuit configuration of an MC9S08QG8 with minimum external
components. To realize this reduced external component count, the circuit shown takes advantage
of the following internal features of the MC9S08QG8:
• Internal clock source

• Internal reset circuit
• Software selectable internal pull-up resistors on input pins
• Slew rate control on outputs to reduce EMI
• Drive strength control on outputs
• Internal low voltage detect (LVD) circuit
Available hardware functions in this circuit include analog comparator (ACMP), 10-bit A/D
converter (ADC), keyboard interrupt module (KBI), serial communication (IIC), Timer/PWM,
GPIO.
Note that the standard header for background debugging (BDM) is shown in this circuit.
Selectabl e pull-ups, slew, drive str engt h
VCC
8
3 PTA0/KBIP0/TPMCH0/ADP0/ACMP+ 7
VDD PTA1/KBIP1/ADP1/ACMP- 6 GP IO or peripheral I/O
+ 10uf 0.1uf PTA2/KBIP2/SDA/ADP2 5
PTA3/KBIP3/SCL/ADP3 2
4 PTA4/ACMPO/BKGD/MS 1
VSS PTA5/IRQ/TCLK/RESET
9S08QG4
1 2
10k 3 O O 4 VCC
VCC O O
5 6
O O
0.1uf BDM
Optional - Optional
PTA5 configured as RESET
Figure 2. Minimum Configuration for MC9S08QG4

Parallel input/output Ports
All general purpose I/O (GPIO) port pins of the MC9S08QG8 are shared with on-chip peripheral
functions. The GPIO ports can be configured as inputs or outputs, although note that port pin
PTA4 is an output-only pin, and port pin PTA5 is an input-only pin. The GPIO ports have
selectable internal pull-up resistors, selectable slew rate control, and selectable output drive
strength.
At power-up or reset, ports A and B are configured to their default states as follows:
• Port direction set to input

• Slew rate control enabled
• Drive strength low
• Pull-up resistor disabled
The data registers for ports A and B are:
PTAD (PTBD) - port A(B) data. When port pins are inputs, reading the register returns
the logic level of the pin. When port pins are outputs, writing to the register latches the
value written and drives the pin accordingly. Reading the register returns the last value
written to the pin.
PTADD (PTBDD) - port A (B) data direction. A zero written to a register bit configures
the pin as an input, a one configures the pin as an output.
The control registers for ports A and B are:
PTAPE (PTBPE) - port A(B) internal pull-up enable. A 0 written to a register bit disables
the internal pull-up, a 1 enables the internal pull-up. If a pin is configured as an output,
the bit has no effect, and the pull-up is disabled.
PTASE (PTBSE) - port A(B) slew rate enable. A 0 written to a register bit disables the
slew rate control, a 1 enables the slew rate control. No effect if pins are configured as
inputs.
PTADS (PTBDS) - port A(B) drive strength select. A 0 written to a register bit sets low
drive strength, a 1 sets high drive strength. No effect if pins are configured as inputs.
When the MCU is in stop mode 1, all ports are powered off. When exiting stop mode 1, registers
assume their default state. In stop mode 2, pin states are latched, but the register contents must be
saved and then recalled on exit from stop mode 2. In stop mode 3, all pin states are maintained
because internal logic remains powered.
Following is a code example for setting up input and output pins on GPIO ports A and B. In this
example, port A bits 2 and 3 will be used as inputs, and port B bits 6 and 7 as outputs. Figure 3
shows the hardware connections for this example.

In this example, when an input pin is driven low, the corresponding output pin will be driven low.
This example will run on the DEMO9S08QG8 board.
/* c:\projects\freescale\gpio\ */
void main(void)
{
byte temp1 = 0;
byte temp2 = 0;
PTBDD_PTBDD7 = 1; // set PTB7 as an output, LED2 on demo board

PTBDD_PTBDD6 = 1; // set PTB6 as an output, LED1 on demo board
PTBD_PTBD6 = 1; // port b6
PTADD_PTADD2 = 0; // set PTA2 as an input

PTADD_PTADD3 = 0; // set PTA3 as an input
PTAPE_PTAPE2 = 1; // enable pullup resistor

PTAPE_PTAPE3 = 1; // enable pullup resistor
for(;;)
{
temp1 = PTAD_PTAD2; // read inputs
temp2 = PTAD_PTAD3;
PTBD_PTBD6 = temp1; // write outputs

PTBD_PTBD7 = temp2;
__RESET_WATCHDOG();
} // end main
VCC
+ 10uf 0.1uf
3
12
PTB0
VDD
16 11
15 PTA0 PTB1 10
14 PTA1 PTB2 9
Input bit 2 PTA2 PTB3
13 8
Input bit 3 PTA3 PTB4
2 7
1 PTA4 PTB5 6
PTA5 PTB6 Output bit 6
VSS
5
PTB7 Output bit 7
9S08QG8
4
Figure 3. Parallel I/O example
Note that this example uses internal pull-ups on the input ports, internal clock, and internal reset
circuit, all which eliminate the need for external components. Unused peripherals modules
should be disabled and unused port pins should be configured to a known state, to minimize
current consumption, and prevent undesired operation.

Keyboard Interrupt Module
The keyboard interrupt module (KBI) provides up to 8 independent interrupt sources, for
keyboard decoding and other applications. Each KBI pin can be configured to generate interrupts
on rising or falling edges, or both edge and level detection. One interrupt is used to for the KBI
module. Key features of the KBI module include:
• Ability to bring the MCU out of low-power modes

• Software selectable pull-up resistors
• Edge, level, or edge/level sensitive interrupt
• Pins independently configured and enabled
Registers for controlling the KBI module are:
KBISC – status flags and control bits for the interrupt and KBI mode.
KBIPE – pin enable register, a bit set high enables the pin as a keyboard interrupt
KBIES – selects the edge/level detection, a bit high selects rising edge/high level
The following code example shows the basic configuration of the KBI module. In this example,
port A bits 2 and 3 will be used as keyboard inputs, and port B bits 6 and 7 as outputs. Figure 4 is
the flow chart for this example.
When a switch is pressed, it creates a KBI interrupt, and the corresponding output is driven.
Figure 5 shows the hardware connections for this example. This example will run on the
DEMO9S08QG8 board.
Start KBI int.
Initiate MCU, Get switch,

Set up ports, Drive output,
enable ints clear int flag
Main loop, wait Return

for interrupt
Figure 4. KBI flow chart
/* c:\projects\freescale\kbi\ */
byte keypress; // receives the key pressed

…
…
KBISC_KBIE = 0; // mask kbi interrupt bit
// set up kbi
/* set pin mode and polarity if desired
KBIES_KBEDG2 = 0; // 0 = low/falling edge
KBIES_KBEDG3 = 0;

KBISC_KBIMOD = 0; // 0 = edge, 1 = level/edge
*/
PTAPE_PTAPE2 = 1; // 1 = enable pullup for kb2

PTAPE_PTAPE3 = 1; // 1 = enable pullup for kb3
KBIPE_KBIPE2 =1; // 1 = enable kb 2 interrupt
KBIPE_KBIPE3 =1; // 1 = enable kb 3 interrupt
KBISC_KBACK = 1; // 1 = clear kb interrupts
KBISC_KBIE = 1; // enable Keyboard Interrupts
// set up outputs for status indicators

PTBDD_PTBDD7 = 1; // set PTB7 as an output
PTBDD_PTBDD6 = 1; // set PTB6 as an output
EnableInterrupts; /* enable interrupts */
//KBI ISR
interrupt 18 void KBI_ISR(void)
{
keypress = PTAD; // read port A to find which key
if (keypress & 8)
PTBD_PTBD6 = ~PTBD_PTBD6; // toggle LED
else
PTBD_PTBD7 = ~PTBD_PTBD7; // toggle LED
KBISC_KBACK = 1; // clear kb interrupt

}
VCC
3
12
PTB0
VDD
11 16
10 PTB1 PTA0 15
9 PTB2 PTA1 14 Sw itch 1
8 PTB3 PTA2/KBIP2 13
7 PTB4 PTA3/KBIP3 2 Sw itch 2
6 PTB5 PTA4 1
Output 1 PTB6 PTA5
VSS
5
Output 2 PTB7
9S08QG8
4
Figure 5. KBI module example
This example does not include any de-bounce logic on the switch inputs, which may be beneficial
in some applications.

MC9S08QG8 Serial Communication
The MC9S08QG8 has unique options for designs that require multiple types of serial
communication interfaces. The MC9S08QG8 has on-chip IIC, SCI, and SPI hardware modules,
eliminating the need for creating ‘bit-banged’ serial ports in software.
What makes the MC9S08QG8 superior is that the serial ports are mapped to separate pins. This
allows all three types of serial communication to be implemented in a single application. This
allows for designing various types of serial-to-serial gateways with the MC9S08QG8. Figure 6
shows the pin assignments of the MC9S08QG8 serial ports.
VCC
3
12
PTB0/RxD
VDD 11 SCI port
16 PTB1/TxD 10
15 PTA0 PTB2/SPSCK 9
14 PTA1 PTB3/MOSI 8 SPI port
IIC port 13 PTA2/SDA PTB4/MISO 7
2 PTA3/SCL PTB5/SS 6
1 PTA4 PTB6 5
PTA5 PTB7
VSS
9S08QG8
4
Optional IIC por t mapping
Figure 6. Serial Communications Ports
For added flexibility, the IIC port can be mapped to an alternate set of port pins. This frees the
multipurpose PTA port pins, which are the default pins used for the IIC module. The following
line of code re-maps the IIC port to the alternate port B pins PTB6 and PTB7:
SOPT2_IICPS = 1; // remap IIC pins to port B

Analog Comparator Module
The analog comparator module (ACMP) provides connections for comparing two analog input
voltages, or comparing one analog input voltage to the internal reference voltage. There are two
input pins (ACMP+, ACMP-) for the ACMP, and one optional digital output pin (ACMPO).
Other features of the ACMP module include:
• Full rail-to-rail supply operation

• Less than 40 mV of input offset
• Less than 15 mV of hysteresis
• Selectable interrupt on rising edge, falling edge, or either rising or falling edges of
comparator output
• Ability to bring the MCU out of low-power modes
If the ACMP is enabled before entering wait mode, it can wake the MCU by an interrupt, if the
ACMP interrupt is enabled. The ACMP is disabled in all stop modes. When exiting from stop
mode 1 or 2, the ACMP is disabled and ACMPCS is in its reset state.
One 8-bit register (ACMPSC) is used for status and control as described below. Following is the
ACMPCS bit definition:
0,1 – ACMOD, selects the comparator mode

2 – ACOPE, a 1 enables the comparator output to drive the external pin
3 – ACO, the value of the comparator output
4 – ACIE, a 1 enables the comparator interrupt
5 – ACF, flag to indicate a compare event has occurred
6 – ACBGS, a 1 selects the internal reference voltage for the non-inverting input
7 – ACME, a 1 enables the comparator module
A flow chart for basic ACMP operation is shown in figure 7. In this configuration, when the
inverting input drops below the non-inverting input, the comparator output goes high and triggers
the interrupt (ACMOD = 1).
Start ACMP Int.

ACMP- < ACMP+
Initiate MCU, Toggle output

Set up ports, port,
enable ints clear int flag
Main loop, wait Return

for interrupt
Figure 7. ACMP example flow chart

The following code shows the basic configuration of the ACMP module. Figure 8 shows the
hardware setup for the example. This example will run on the DEMO9S08QG8 board; port
PTB7 is connected to LED2.
/* c:\projects\freescale\acmp\ */
// set up ACMP
ACMPSC_ACMOD = 1; // 1 = interrupt on rising edge of comparator output
ACMPSC_ACOPE = 0; // 0 = comparator output disabled on external pin
ACMPSC_ACIE = 1; // 1 = comparator interrupt enabled
ACMPSC_ACBGS = 1; // 1 = use internal reference on ACMP+
SPMSC1_BGBE = 1; // 1 = enable bandgap buffer for internal reference
ACMPSC_ACME = 1; // 1 = comparator enabled
ACMPSC_ACF = 1; // writing 1 clears event flag
// set up output port for an event indicator

PTBDD_PTBDD7 = 1; //set PTB.7 as an output, LED2 on demo board
PTBD_PTBD7 = 0;
EnableInterrupts; // enable interrupts
// ACMP ISR
interrupt 20 void ACMP_ISR(void)
{
PTBD_PTBD7 = ~PTBD_PTBD7; // toggle PTB.7 pin
}
VCC
+ 10uf 0.1uf
3
Not connected - using

internal refe rence 12
PTB0
VDD
11
16 PTB1 10
15 PTA0/ACMP + PTB2 9
Analog input PTA1/ACMP- PTB3
14 8
13 PTA2 PTB4 7
2 PTA3 PTB5 6
1 PTA4 PTB6 5
PTA5 PTB7 Output signal
VSS
9S08QG8
4
Figure 8. Analog comparator example
This example could use the ACMP external output on pin 2 by setting the ACOPE bit in
ACMPSC:
ACMPSC_ACOPE = 1; // comparator output enabled on external pin
To use the external ACMP+ input instead of the internal reference voltage, clear the ACBGS bit:
ACMPSC_ACBGS = 0; // disable internal reference

SPMSC1_BGBE = 0; // 0 = disable bandgap buffer for internal reference

Simple Inverter Using the Analog Comparator Module
Often during system design, there is the need for a logic gate to invert a signal. Typically, the
choice is to add logic components, which will also add cost and real estate. The internal analog
comparator of the MC9S08QG8 provides a simple method to invert a logic signal.
Figure 9 shows the pins used on the MC9S08QG4 for the logic inverter. The ACMP+ pin is not
connected in this example, as the internal reference is used for the ACMP+ input. When the
signal on ACMP- rises above the level of ACMP+, the output on ACMPO will switch to logic 0.
In this configuration, an interrupt is triggered by a rising or falling edge of the comparator output.
On an ACMP interrupt, the ACO bit is checked, and if high pin PTB7 is set high. Note that the
comparator can work without using interrupts. This example will run on the DEMO9S08QG8
board; port PTB7 is connected to LED2.
The code example for configuring ACMP as a logic inverter:
/* c:\projects\freescale\inverter\ */
ACMPSC_ACMOD = 11; // 1 = comparator output on rising or falling edge

ACMPSC_ACOPE = 1; // 1 = comparator output enabled on external pin
SOPT1_BKGDPE = 0; // 0 = disable bgdb mode on ACMPO pin
//ACMP ISR
{
if (ACMPSC_ACO)
PTBD_PTBD7 = 1; // set PTB.7 pin on compare event
else
PTBD_PTBD7 = 0; // clear PTB.7 pin on compare event
}
VCC Ex ampl e uses external reference voltage

3
12
PTB0
VDD
11 16
10 PTB1 PTA0/ACMP+ 15
PTB2 PTA1/ACMP- Logic signal in
9 14
8 PTB3 PTA2 13
7 PTB4 PTA3 2
PTB5 PTA4/ACMPO Inverted logic signal out
6 1
PTB6 PTA5
VSS
5
Output signal PTB7
9S08QG8
4
Figure 9. Logic inverter

Analog to Digital Converter
The enhanced analog to digital module (ADC) in the MC9S08QG8 is a 10-bit successive
approximation converter. A conversion can be initiated by hardware (not on all devices) or
software command, and can provide an interrupt when the conversion is complete. The ADC can
operated in wait or stop mode 3, and can wake the MCU on a conversion complete interrupt.
Other features of the ADC module include:
• Automatic compare feature with interrupt

• Output formatted in 10- or 8-bit right-justified format
• Single or continuous conversion
• Selectable sample time and conversion speed/power
• Input clock selectable from up to 4 sources
• 10-bit conversion time 3.5 us with 8 MHz clock
• Option to select internal bandgap voltage as input channel
The analog power and ground, and the voltage reference high and low are connected internally to
the logic power supply. The ADC module indicates support of up to 28 analog inputs. The
hardware pin availability limits the number in this product.
The ADCSC1 register is used for status and control of the ADC module. To initiate a software
conversion, write the channel to be converted to the ADCH bits. The bit structure of ADCSC1 is:
0-4 – ADCH, channel selection, all 1’s disables the ADC module.
5 – ADCO, a 1 enables continuous conversion once a conversion is initiated
6 – AIEN, a 1 enables the conversion complete interrupt
7 – COCO, conversion complete flag, a 1 indicates the conversion is complete
The ADCSC2 register is used to control the compare function. The bit structure of ADCSC2 is:
0,1 – reserved, must always be written as 0’s

2,3 – not implemented
4 – ACFGT, 1 enables compare function greater than
5 – ACFE, 1 enables the compare function
6 – ADTRG, a 1 selects hardware conversion triggering, 0 for software triggering
7 – ADACT, a 1 indicates a conversion is in progress
ADCRL and ADCRH are the conversion low and high results. ADCRL contains the lower 8 bits
of the result, ADCRH contains the upper 2 bits.
ADCCVL and ADCCVH are the compare value low and high registers. ADCCVL contains the
lower 8 bits of the compare value, ADCCVH contains the upper 2 bits.
ADCCFG is used to select the mode, clock source, clock divide, and configure for low power or
long sample time. The bit structure of ADCCFD is:
0,1 – ADICLK, selects the input clock source for the ADC, 00 is bus clock source
2,3 – MODE, selects the ADC conversion mode, 00 is 8-bit mode, 10 is 10-bit mode
4 – ADLSMP, 1 selects long sample conversion time

5,6 – ADIV, clock divide select, 00 is input clock, 01 is input clock/2, etc.
7 – ADLPC, 1 selects low power configuration
APCTL1 is used is used to control the pins associated with channels 0–7 of the ADC module.
Setting a bit to 1 disables I/O control of that pin.
The following code example shows the basic configuration of the ACMP module. In this
example, an ADC conversion is triggered by toggling a KBI pin low. The KBI ISR starts a
software conversion on an analog channel, and the ADC ISR reads the results when the
conversion is complete. Figure 10 shows the hardware setup for the example.
/* c:\projects\freescale\adc\ */
// set up adc
ADCSC1_ADCH = 0x1f; // disables the ADC
ADCSC1_AIEN = 1; // enable ADC interrupt
ADCSC1_ADCO = 0; // enable single conversion, 1 is continuous conversion
ADCSC2_ADTRG = 0; // select software trigger

ADCSC2_ACFE = 0; // disable the compare function
ADCCFG_ADICLK = 0; // bus clock

ADCCFG_ADIV = 1; // input clock/2
ADCCFG_MODE = 0x02; // 10 bit mode
ADCCFG_ADLSMP = 1; // long sample time
APCTL1 – 0x03; // disable I/O control on channel 0, 1
//KBI ISR
{
keypress = PTAD; // read port a to find which key
if (keypress & 8)
ADCSC1_ADCH = 0; // start conversion on channel 0
else

}
interrupt 19 void ADC_ISR(void)

{
ADC_val_H = ADCRH; // get the high bits
ADC_val_L = ADCRL; // get the lower byte
}
VCC
3 8
VDD PTA0/ADP0 Analog Input 0
7
PTA1/ADP1 Analog Input 1
+ 10uf 0.1uf 6
PTA2/KBIP2 5
4 PTA3/KBIP3 2
VSS PTA4 1
PTA5
9S08QG4
Figure 10. ADC example

Using the ADC Compare Function
This example uses the compare function of the ADC to monitor an analog input, and interrupt the
MCU when the input value becomes greater than the compare value setting. In this example, the
ADC is set up for continuous conversions. A digital input interrupt starts the conversion.
The analog compare function can be configured to trigger when the analog input is either greater
than or less than the compare value. There are many options for configuring the clock and power
savings modes; this example demonstrates only one method.
The ADC module and compare function can operate from wait or stop mode 3. The ADC
interrupt will wake the MCU from either of these low-power modes when the compare condition
is met.
A real world application that uses these features could be a low-power application to monitor an
analog sensor or other analog signal. When the analog input crosses the compare threshold, the
ADC will interrupt and wake the MCU, which will then process some specific action.
Figure 11 shows the flowchart for this example:
Continuous sample
Start KBI Int. Input >

setpoint
?
Initiate MCU, Start ADC, Y

Set up ports, clear int flag
enable ints
ADC Int.
Main loop, wait Return Get AD value

for interrupt clear int flag
Return
Figure 11. Analog compare example
Following is the code for this example:
/* c:\projects\freescale\adc_comp\ */
// set up adc
ADCSC1_ADCH = 0x1f; // all channels selected disables the ADC during config
ADCCFG_ADICLK = 0; // clock source, 00=bus clock, 11 = async. clock
ADCCFG_MODE = 0b10; // conversion mode, 00 = 8 bit, 10 = 10 bit mode
ADCCFG_ADLSMP = 1; // sample time, 1 = long sample time
ADCCFG_ADIV = 1; // clock divide, 1 = input clock/2
ADCCFG_ADLPC = 1; // low power config, 1 = low power
ADCSC2_ADTRG = 0; // trigger select, 0 = software trigger

ADCSC2_ACFE = 1; // compare function, 1 = enable compare function
ADCSC2_ACFGT = 1; // 1 = compare function greater than

ADCSC1_ADCO = 1; // enable continuous conversion, 1 = continuous, 0 = single
ADCSC1_AIEN = 1; // unmask ADC interrupt
APCTL1_ADPC0 = 1; // disable I/O control on pin on ADC channel 0
ADCCVL = 0x80; // set a compare value low 8-bits

ADCCVH = 0x01; // set a compare value upper 2-bits
// set up kbi
PTAPE_PTAPE2 = 1; // enable pullup for kb2
KBIPE_KBIPE2 =1; // enable kbi 2 function
KBISC_KBACK = 1; // clear kb interrupts
KBISC_KBIE = 1; // unmask kbi interrupt

{
}

{
ADC_val_H = ADCRH; // read the ADC
ADC_val_L = ADCRL;
ADCSC1_ADCH = 0x1f; // disable the ADC
}

Window Comparator Using ADC and ACMP
The MC9S08QG8 ADC module is a 10-bit successive approximation analog to digital converter.
The ADC can run single or continuos conversions, and has configurable sample time and
conversion speed. There is a conversion complete flag and interrupt available for software. The
ADC also has an automatic compare feature, which is necessary for this example. To complete
the window comparator, this example will also use the ACMP module.
The goal is to measure an analog input voltage, and signal the application when the analog input
goes outside the high or low limits. The lower limit will be tested using the ACMP module, and
the upper limit will be tested with an ADC channel using the compare function.
If the analog input falls below the low threshold, the ACMP will signal the software with an
interrupt. If the analog input rises about the high threshold, the ADC will signal the software with
an interrupt.
The start switch initiates monitoring of the analog input. Output 1 and Output 2 signal when the
analog input goes above or below the limits.
The principal advantage of this example is that when the analog input is within the limits, nothing
occurs in the software. For power savings, limit checking can be initiated, and then the MCU can
be put in wait mode. When the analog input goes out of the limits, an interrupt wakes the MCU.
Figure 12 shows the pins used on the MC9S08QG8.
VCC
Us ing internal reference voltage

3
12
PTB0
VDD
11 16
10 PTB1 PTA0/ACMP+ 15
PTB2 PTA1/ACMP- Analog signal in
9 14
8 PTB3 PTA2/ADP2 13
7 PTB4 PTA3/KBIP3 2 St art
6 PTB5 PTA4 1
Output 1 PTB6 PTA5
VSS
5
Output 2 PTB7
9S08QG8
4
Figure 12. Window Comparator
The code for configuring this example:
/* c:\projects\freescale\window comp\ */
// set up adc
ADCSC1_ADCH = 0x1f; // disables the ADC during config
ADCCFG_ADICLK = 0; // clock source, 00=bus clock, 11 = async. clock

ADCCFG_MODE = 2; // conversion mode, 00 = 8 bit, 10 = 10 bit mode
ADCCFG_ADLSMP = 1; // sample time, 1 = long sample time
ADCCFG_ADIV = 0; // clock divide, 0 = input clock
ADCCFG_ADLPC = 0; // low power config, 1 = low power

ADCSC2_ADTRG = 0; // trigger select, 0 = software trigger
ADCSC2_ACFE = 1; // compare function, 1 = enable compare function
ADCSC2_ACFGT = 1; // 1 = compare function greater than
ADCSC1_ADCO = 1; // enable single conversion, 1 is continuous conversion

ADCSC1_AIEN = 1; // enable ADC interrupt
APCTL1_ADPC2 = 1; // disable I/O control on pin
ADCCVL = 0x90; // set a compare value

ADCCVH = 0x01; // set a compare value
// set up comparator
ACMPSC_ACMOD = 1; // 1 = comparator output on falling edge
ACMPSC_ACOPE = 0; // 0 = output pin disabled
ACMPSC_ACF = 1; // writing 1 clears ACMP event flag
// set up output port for an indicator

PTBDD_PTBDD6 = 1; // set PTB.6 as an output
PTBD_PTBD7 = 0;
PTBDD_PTBDD7 = 1; // set PTB.7 as an output
PTBD_PTBD7 = 0;
// set up kbi
PTAPE_PTAPE3 = 1; // enable pullup for kb3
KBIPE_KBIPE3 =1; // enable kb 3
KBISC_KBACK = 1; // clear kb interrupts
KBISC_KBIE = 1; // enable Keyboard Interrupts
//KBI ISR
{
PTBD_PTBD6 = 1;
PTBD_PTBD7 = 1;
ADCSC1_ADCH = 2;
}
// ADC ISR
{
ADC_val_H = ADCRH;
ADC_val_L = ADCRL;
PTBD_PTBD6 = 0; // toggle PTB.6 pin
ADCSC1_ADCH = 0x1f; // disable the ADC when done
}
//ACMP ISR
{
PTBD_PTBD7 = 0; // toggle PTB.7 pin
}

IIC to LIN Slave
LIN (Local Interconnect Network) is a UART-base single-wire communication protocol, used

extensively in automotive networking and diagnostics. The LIN bus in automotive applications
will typically have one master node, which initiates all communication to the slave nodes on the
bus. LIN is typically used in automotive devices that do not require the higher speed capabilities
(and cost) of CAN, or other high-speed in-vehicle networks.
Automotive devices have strict current limitations when they are to maintain some type of
operating state when the vehicle is not running, such as power door locks or remote keyless entry.
The MC9S08QG4/8 power-save modes make it an excellent choice for these applications. The
IIC can SCI modules of the MC9S08QG4/8 can operate in wait mode, and wake the MCU when
activity occurs.
This application uses the circuit shown in Figure 13 as a LIN slave peripheral to another
microcontroller. The MC9S08QG4 connects to the host microcontroller through a standard two-
wire IIC bus. The host microcontroller can then communicate on a LIN bus through IIC, and
potentially reduce it’s CPU time by off-loading the handling of the LIN bus tot the MC9S08QG4.
The MC9S08QG8 may be configured to automatically process keep-alive messages on LIN,

which again reduces the host microcontroller overhead. The MC9S08QG8 can also process
incoming LIN messages automatically, and filter out messages that are not intended for this
device.
This application will use the MC33661 LIN Transceiver from Freescale. The MC33661 is able to
operate with logic power down to 3.3VDC, which allows the device to connect directly to the
CPU, without any logic level shifting.
A flow chart for the initialization and general flow of this application is shown in figure 14. For
complete LIN Driver examples, see Freescale documents AN2503 and AN2599.
VCC
+ 10uf 0.1uf +12

8 7
2 INH VSUP
U12 EN
3
6
LIN LIN
12 1 3
PTB0/RxD RxD WAKE
VDD
11 4 5
16 PTB1/TxD TxD GND
15 PTA0 10 MC33661 100k
14 PTA1 PTB2 9
IIC port SDA PTA2/SDA PTB3
13 8
SCL PTA3/SCL PTB4
2 7
1 PTA4 PTB5/TPMCH1
PTA5/RESET 6
PTB6
VSS
5
PTB7 Us ed to measure LIN bit time
MC9S08QG8
4
Figure 13. IIC to LIN Slave

Start Sleep
Wake from SCI
Initialize MCU
registers and
ports pins Wake
from Valid break
IIC? no received?
no
yes
Configure IIC for
yes
host Trim internal clock
communication for LIN
Convert IIC to
SCI and send LIN
message
Configure SCI for
LIN no
This
communication nodes
Start LIN receive message
timeout timer
Set MCU to wait yes

mode, IIC and
SCI active
LIN Receive no
message Timeout?
received
no
Sleep
yes yes
Stop timer
This no
nodes
message
Send timeout
message to host
yes
Stop timer
Convert SCI to
IIC and send to
host
Figure 14. IIC to LIN Slave Flow Chart

LIN Master/Slave, IIC or SPI Input
Similar to the previous application, this circuit use the MC9S08QG8 to act as a LIN peripheral,
using either IIC or SPI as the link to the host controller, and the SCI to handle LIN
communication. This circuit can also behave as a LIN slave or master node. Figure 15 shows the
circuit for the application.
The host microcontroller offloads much of the LIN bus control to the MC9S08QG8, reducing its
processing load. The MC9S08QG8 may be configured to automatically process keep-alive, and
filter out messages that are not intended for this device.
This application will use the MC33661 LIN Transceiver from Freescale. The MC33661 is able to
operate with logic power down to 3.3VDC, which allows the device to connect directly to the
CPU, without any logic level shifting.
VCC 1k
+ 10uf 0.1uf +12

8 7
2 INH VSUP
U8 EN
3
6
LIN LIN
12 1 3
PTB0/RxD RxD WAKE
VDD
11 4 5
16 PTB1/TxD TxD GND
15 PTA0 10 MC33661 100k
PTA1 PTB2/SPSCK SPSCK
14 9
IIC port SDA PTA2/SDA PTB3/MOSI MOSI
13 8
SCL PTA3/SCL PTB4/MISO MISO SPI port
2 7
PTA4 PTB5/SS ~SS
1
PTA5/RESET 6
PTB6/XTAL
VSS
5
PTB7/EXTAL
MC9S08QG8
4
Figure 15. LIN Master/Slave
A flow chart for the initialization and general operation of this application is shown in figure 14
above. This hardware can use SPI or IIC for host communication, and can be a LIN master or
slave. For complete LIN Driver examples, see Freescale documents AN2503 and AN2599.

Brushless DC Fan/Motor Drive
This example shows a demo circuit for driving a brushless DC fan or motor with the
MC9S08QG8. In this example, a variable-speed motor drive is created using the PWM function
that varies the motor speed, and a logic output that handles the switching between coil 1 and 2. A
logic input is used for a hall sensor, common on many brushless DC fans or motors.
For cooling fan applications, an optional temperature sensor can be connected to an ADC input
channel. There is also an internal temperature sensor on the MC9S08QG8.
The IIC module in this example can used for optional remote monitoring or control. Using IIC,
the MC9S08QG8 could serve as a slave peripheral device. Figure 16 shows the circuit for this
example.
V+
PWM
Hall Motor
VCC
8
PTA0/TPMCH0 Ext temp
3 7
VDD PTA1/ADP1 6
PTA2/SDA SDA
+ 10uf 0.1uf 5
PTA3/SCL SCL
2 VCC
4 PTA4 1 Coil1
VSS PTA5
9S08QG8 Coil2
Figure 16. BLDC Fan/Motor Drive
The flow chart for the motor drive example is shown in figure 17. The flow of the temperature
and IIC monitoring are not detailed, but are assumed to be part of the software main loop. If
desired, the PWM output may be varied to adjust motor speed based on the temperature input.

Start B
Initialize MCU,
Setup ports and
peripherals
Stop
Y Stop motor,
event
? clear run flag
A
N
A
Monitor temp
sensor and IIC Hall
Y
bus for start change
?
Toggle coil
N drive, update
Start hall, reset timer
N
event
?
Timer
expired
N C
?
Y
Start timer, Toggle coil

start PWM Y drive, reset
output timer, set flag
Stop motor,
clear run flag,
set error flag
Hall Hall
Y Y
change Error change
? handler ?
Timer Timer
N N
expired expired
? Set hall state, Set hall state, ?
set run flag, set run flag,
reset timer reset timer
Y Y
Error
C B B handler
Figure 17. BLDC Fan/Motor Drive Flow Chart

Zero crossing detector with triac drive
This example shows a method of implementing a low component count zero-crossing detector
and triac drive with the MC9S08QG8. In this circuit, a digital input port with interrupt is used
detect the zero-crossing point of the AC line. A digital output port with high drive enabled is
used to fire the triac.
An optional potentiometer is connected to an analog input. This is to provide a variable voltage

that the software can interpret, and provide changes triac on-time. A typical use of this function
would be for a light dimmer.
Some triacs may require more drive current on the gate than can be provided directly by a port
pin. If available, several port pins may be paralleled to increase the drive current to the triac. Use
caution to insure that the total package current of the MC9S08QG8 is not exceeded.
Figure 18 shows the circuit for this example. Figure 19 is the flow chart for the zero crossing
function.
VCC AC Line
1M
VCC
8 LOAD
3 PTA0/KBIP0 7
VDD PTA1/ADP1 6
+ 10uf 0.1uf PTA2 5
PTA3 2
4 PTA4 1
VSS PTA5/RESET TRIAC
9S08QG4
1M
High-driv e en abled AC Neut
Figure 18. Zero-crossing detector
Start Zero x-ing

interrupt
Initialize MCU, Re-check pin to

Setup ports verify interrupt
Enable zero Delay Y

firing
crossing
?
interrupt
Wait delay time
N
Main loop –
Read analog in
Fire triac
Wait for zero x
Figure 19. Zero-crossing Flow Chart

Smart Battery Controller
The MC9S08QG8 is an ideal microcontroller for battery charge and smart battery applications.
The ADC provides for fast and accurate battery measurements, along with the ability to operate
from low-power modes and wake the MCU when a voltage threshold is crossed. The IIC module
allows for communication on the SMBus, and the internal temperature sensor provides for battery
temperature monitoring.
Differing battery technologies provide large variations in capacity and performance. A battery
profile must be created for each specific battery before implementing the charging algorithm.
Smart batteries typically provide critical battery information over the SMBus, such as charge
state, battery status, and the batteries charging algorithm. Additional features could be
implemented, such as disconnecting a battery from its load to prevent over-discharging the
battery.
In this example, two analog channels are used to monitor the battery voltage and current. Three
digital outputs are used, one to switch on a constant current charging source, one to switch on a
constant voltage source, and one to disconnect the battery from the load. The IIC signals are used
to communicate on the SMBus. The internal temperature sensor is used to sense excessive
temperature in the battery.
Figure 20 shows the configuration of the MC9S08QG8 for this example. The specific circuits for
monitoring and controlling the charging voltage and current are not shown since the requirements
vary greatly, depending on the type and number of batteries being controlled.
BATTERY
Ext_power Ch arge Sense Load LOAD
Co ntro l Disconnec t
V_Sense
VCC VCC I_Sense
3
Constant_current 12
PTB0
VDD
Constant_voltage11 16
10 PTB1 PTA0/ADP0 15
9 PTB2 PTA1/ADP1 14 Load Off
8 PTB3 PTA2 13
7 PTB4 PTA3 2
6 PTB5 PTA4 1
IIC/SM Bus SDA PTB6/SDA PTA5
VSS
5
SCL PTB7/SCL
9S08QG8
4
Figure 20. Smart Battery Controller

Low-cost IR Remote with Companion Receiver
The small size and low power operation of the MC9S08QG8 make it the ideal microcontroller for
battery operated devices, such as key fobs and hand-held remote controls. This example, shown
in figures 21 and 22, illustrates two circuits using the MC9S08QG8. One circuit is a low-cost IR
remote control, and the other is a companion IR receiver powered directly from an AC line.
In the IR remote, the on and off switches use the KBI to wake the MCU, which will send a data
pulse out to the IR and red indicator LED specific to the switch pressed. In the receiver, the
phototransistor detects the IR data, and then drives the triac on or off as appropriate.
To simplify the design, a single switch could be used in the remote. The receiver would then
toggle the triac at each data pulse in. The software could be expanded to make the devices
function as a dimmer, rather than an on/off switch.
Typical applications for these examples would include lighting control, remote fan or motor
control, garage door opener, alarm system enable/disable.
VCC
VCC
3 8
VDD PTA0 7
Coin Cell 0.1uf PTA1/ADP1 6
PTA2/KBIP2 5 On IR Rem ote
4 PTA3/KBIP3 2 Red IR
VSS PTA4 1
PTA5 Off
9S08QG4
Figure 21. Low-cost IR Remote
AC Line
510k 510k
AC Line VCC LOAD

8 VCC
3 PTA0/KBIP0 7
VDD PTA1/ADP1 6
Light Control + 470uf 0.1uf PTA2 5
PTA3 2
4 PTA4 1 TRIAC
VSS PTA5/RESET
9S08QG4
Ph oto NPN
AC Neut
Figure 22. Example IR Receiver/AC switch

Serial Communication Bridge/Gateway
The MC9S08QG8 features on-chip IIC, SPI, and SCI communication modules. The unique
feature of the MC9S08QG8 serial ports is that they are all mapped to separate pins, allowing all
of the serial modules to be used in parallel. This allows for the following serial communication
applications to be implemented.
VCC
3
12
PTB0/RxD
VDD
11
16 PTB1/TxD
15 PTA0 10
14 9
SDA PTA2/S DA PTB3/MOSI MOSI
13 8
SCL PTA3/S CL PTB4/MISO MISO
2 7
PTA4 PTB5/S S ~SS
1
PTA5/RESET 6
PTB6
VSS
5
PTB7
MC9S08QG8
4
Figure 23. SPI to IIC Bridge
VCC
3
12
PTB0/RxD RxD
VDD
11
PTB1/TxD TxD
16
15 PTA0 10
14 9
PTA2/SDA PTB3/MOSI MOSI
13 8
PTA3/SCL PTB4/MISO MISO
2 7
PTA4 PTB5/SS ~SS
1
PTA5/RESET 6
PTB6
VSS
5
PTB7
MC9S08QG8
4
Figure 24. SPI to SCI Bridge
VCC
3
12
PTB0/RxD RxD
VDD
11
PTB1/TxD TxD
16
15 PTA0 10
PTA1 PTB2/SPSCK SP SCK
14 9
SDA PTA2/SDA PTB3/MOSI MOSI
13 8
SCL PTA3/SCL PTB4/MISO MISO
2 7
PTA4 PTB5/SS ~SS
1
PTA5/RESET 6
PTB6
VSS
5
PTB7
MC9S08QG8
4
Figure 25. SPI to SCI to IIC Gateway

Wireless Sensor Applications
With its low-power, small footprint, and low cost, the MC9S08QG8 is ideal for battery operated
wireless applications. Increasingly, wireless applications are chosen over traditional wired
networks and application, because the associated wiring and installation costs are greatly reduced.
The proliferation of wireless networks and devices make the potential applications almost
unlimited.
Figure 26 shows the pins necessary to connect the MC9S08QG8 to a Freescale MC13191 Low-
power ISM Transceiver. The pin compatible MC13192/3 support 802.15.4 and the Zigbee
protocol. This combination of MCU and Transceiver can be applied to many different wireless
applications, such as remote sensing, remote meter reading, asset management, wireless
keyboards and mice, and factory or home automation.
VCC
3
20
12 12 IRQB
PTB0 RSTB
VDD
11
Sensor inputs 16 PTB1 10 16
Analog 15 PTA0 PTB2/SPSCK 9 17 SPICLK
Digital 14 PTA1 PTB3/MOSI 8 18 MOSI
Timer 13 PTA2 PTB4/MISO 7 19 MISO
2 PTA3 PTB5/SS 6 CEB
1 PTA4 PTB6 5 13
PTA5 PTB7 RXTZEN
VSS
14
ATTNB
9S08QG8 10
4
11 GPIO2
GPIO1
MC13191
Figure 26. MC9S08QG8 ISM Transceiver Example

Using the MC9S08QG8 as an IIC Peripheral
There are many great features in the MC9S08QG8 that make it a cost-effective solution for
peripheral applications, such as an A/D converter, keyboard controller, or discrete I/O device.
With low power and programming flexibility, the MC9S08QG8 may even outperform peripheral
devices designed for one specific function.
An excellent example of the cost and performance advantage of the MC9S08QG8, is to apply it
as an 8 channel 10-bit A/D converter. With its internal clock, internal reference voltage, and low-
power modes, the MC9S08QG8 can perform as well or better than dedicated A/D converters that
are of ten 2 to 4 times more expensive. Using the automatic compare function, and operating in
wait or stop mode 3 increase the benefit of using the MC9S08QG8.
Figure 27 shows the pin configuration for using the MC9S08QG8 as an A/D or keyboard
peripheral. This example shows the IIC module mapped to the alternate set of port pins. The
analog and other pin functions can be set on a pin by pin basis.
VCC
3
VDD
16 2
A/D 0-3 15 PTA0/ADP0 PTA4 1
or 14 PTA1/ADP1 PTA5
KBI 0-3 13 PTA2/ADP2 8
PTA3/ADP3 PTB4 7
12 PTB5
A/D 4-7 11 PTB0/ADP4 6
or PTB1/ADP5 PTB6/SDA SDA IIC po rt
10 5
PTB2/ADP6 PTB7/SCL SCL
VSS
KBI 4-7 9
PTB3/ADP7
MC9S08QG8
4
Figure 27. MC9S08QG8 as A/D or KBI Peripheral

Programming and Development
Many cost-effective tools are available from Freescale Semiconductor and its third party partners
to support development on the MC9S08QG8. The MC9S08QG8 features a background debug
controller (BDC) that is accessed through a single port pin. The BDC does not use any MCU
memory or peripheral resources, and does not interfere with resource operation.
The BDC has its own set of registers, which are separate from the MC9S08QG8 memory map.
The BDC supports typical debug functions, including setting breakpoints, trace and go
commands. The internal COP watchdog is disable in active debug mode.
The MC9S08QG8 uses the standard single-wire BDM interface common to all HCS08 MCUs.
The BDM interface provides quick and efficient access to the MCU for programming the on-chip
Flash memory. The BDM is also the primary interface for accessing the on-board in-circuit
emulator (ICE). The BDM interface makes field or factory programming quick and easy.
Figure 28. BDM Tool Connector

MC9S08QG4-8 Quick Start Tips1

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Copyright © 2005, Highlander Technologies www.highlandertech.com Revision 1.0

MC9S08QG8 INTRODUCTION ................................................................................................................ 5

MC9S08QG8 MINIMUM COMPONENT SYSTEM ............................................................................... 7

PARALLEL INPUT/OUTPUT PORTS ..................................................................................................... 8

KEYBOARD INTERRUPT MODULE.................................................................................................... 10

MC9S08QG8 SERIAL COMMUNICATION.......................................................................................... 12

ANALOG COMPARATOR MODULE ................................................................................................... 13

SIMPLE INVERTER USING THE ANALOG COMPARATOR MODULE ...................................... 15

ANALOG TO DIGITAL CONVERTER ................................................................................................. 16

USING THE ADC COMPARE FUNCTION........................................................................................... 18

WINDOW COMPARATOR USING ADC AND ACMP........................................................................ 20

IIC TO LIN SLAVE ................................................................................................................................... 22

LIN MASTER/SLAVE, IIC OR SPI INPUT ........................................................................................... 24

BRUSHLESS DC FAN/MOTOR DRIVE ................................................................................................ 25

ZERO CROSSING DETECTOR WITH TRIAC DRIVE...................................................................... 27

SMART BATTERY CONTROLLER ...................................................................................................... 28

LOW-COST IR REMOTE WITH COMPANION RECEIVER............................................................ 29

SERIAL COMMUNICATION BRIDGE/GATEWAY ........................................................................... 30

WIRELESS SENSOR APPLICATIONS ................................................................................................. 31

USING THE MC9S08QG8 AS AN IIC PERIPHERAL ......................................................................... 32

PROGRAMMING AND DEVELOPMENT ............................................................................................ 33

Copyright © 2005, Highlander Technologies www.highlandertech.com Revision 1.0

Figure 1. MC9S08QG8/4 Packages ................................................................................................. 6

Copyright © 2005, Highlander Technologies www.highlandertech.com Revision 1.0

• 20MHz HCS08 CPU

• 12 GPIO pins plus, 1 input-only, 1 output-only (16-pin package)

• Improved! Up to 8 channels of 10-bit A/D converter (ADC) with automatic compare

MC9S08QG8 Quick Start Tips 5

• Low voltage operation 1.8 – 3.6 VDC

• Low voltage detect (LVD) module

Figure 1. MC9S08QG8/4 Packages

MC9S08QG8 Quick Start Tips 6

• Internal clock source

Selectabl e pull-ups, slew, drive str engt h

Figure 2. Minimum Configuration for MC9S08QG4

MC9S08QG8 Quick Start Tips 7

• Port direction set to input

The data registers for ports A and B are:

The control registers for ports A and B are:

MC9S08QG8 Quick Start Tips 8

PTBDD_PTBDD7 = 1; // set PTB7 as an output, LED2 on demo board

PTADD_PTADD2 = 0; // set PTA2 as an input

PTAPE_PTAPE2 = 1; // enable pullup resistor

PTBD_PTBD6 = temp1; // write outputs

Figure 3. Parallel I/O example

MC9S08QG8 Quick Start Tips 9

• Ability to bring the MCU out of low-power modes

Registers for controlling the KBI module are:

Start KBI int.

Initiate MCU, Get switch,

Main loop, wait Return

Figure 4. KBI flow chart

byte keypress; // receives the key pressed

MC9S08QG8 Quick Start Tips 10

PTAPE_PTAPE2 = 1; // 1 = enable pullup for kb2

// set up outputs for status indicators

EnableInterrupts; /* enable interrupts */

KBISC_KBACK = 1; // clear kb interrupt

Figure 5. KBI module example

MC9S08QG8 Quick Start Tips 11

Optional IIC por t mapping

Figure 6. Serial Communications Ports