Beruflich Dokumente
Kultur Dokumente
net/publication/329959460
CITATION READS
1 243
4 authors:
Some of the authors of this publication are also working on these related projects:
All content following this page was uploaded by Shubham Sahay on 30 December 2018.
Abstract — In this paper, we propose a misaligned double- in the ON-state is still a bottleneck. Moreover, ambipolar
gate p-i-n impact ionization MOS (MIMOS) with a deliber- conduction makes it unsuitable for various digital circuit oper-
ate misalignment between the top and bottom gates. The ations [5]. Although various solutions have been proposed to
presence of a misaligned bottom gate leads to band-to-
band-tunneling of electrons at the source-intrinsic region improve the drive current [9]–[14] and to reduce the ambipolar
interface and increases the number of carriers for impact conduction [15], [16] in TFET, a high ON-state current compa-
ionization. The electric field redistribution provides a longer rable to MOSFET with a sub-60-mV/dec SS is yet to be real-
transport path for the carriers. Therefore, carriers gain ized experimentally [4], [5], [17], [18]. The feedback FET [19]
higher kinetic energy, and the impact ionization rate is and negative capacitance field-effect transistor [20], [21]
enhanced in the MIMOS. This results in a significantly lower
avalanche breakdown voltage compared to conventional also show very steep SS compared to the conventional
single-gate IMOS structure. Using calibrated 2-D simula- MOSFET.
tions, we demonstrate that MIMOS exhibits a steep sub- The impact ionization MOSFET (IMOS), which relies on
threshold slope ( ∼6 mV/dec) at a significantly low-supply the impact ionization phenomena in reverse biased p-i-n struc-
voltage of (VDS = 0.59 V), which is ∼48% lower than that of ture, is considered as one of the most promising candidates
the corresponding single-gate IMOS (VDS = 1.15 V).
to realize low SS devices [22], [28]. However, the con-
Index Terms — Avalanche breakdown, impact ionization, ventional p-i-n IMOS requires a large operating voltage for
low power, MOSFET, misaligned gate, steep subthreshold generating and sustaining charge carriers through an impact
slope.
ionization mechanism. Therefore, several solutions were pro-
I. I NTRODUCTION posed to reduce the operating voltage of the conventional
p-i-n IMOS such as depletion IMOS [28], enhanced electric
T HE modern-day integrated circuits require MOSFETs
which can simultaneously offer a low-power dissipation
and a high speed. The low-power operation of the MOSFETs
(E2) IMOS [27], and bipolar IMOS [29], [30]. The use of
heterostructure of two different bandgap materials enhances
the electric field at the interface and leads to an increased
is limited by the inability to scale the subthreshold swing (SS)
impact ionization in the E2-IMOS. The bipolar IMOS uses
below 60 mV/dec [1]. However, several device architectures
the internal current gain mechanism of the parasitic bipo-
with different turn on mechanisms such as band-to-band tun-
lar junction transistor to lower the breakdown voltage. The
neling (BTBT) or impact ionization were proposed to reduce
impact ionization occurs in the bulk in the depletion mode
the SS below the conventional limit of 60 mV/dec.
IMOS where the impact ionization coefficients are higher as
Although the tunneling field-effect transistor (TFET) based
compared to the surface. Therefore, a lower drain voltage
on the carrier injection via BTBT [2]–[8] provides subthresh-
is required for avalanche breakdown. However, despite these
old slope lower than the theoretical limit, the low drive current
innovations, the voltage required for impact ionization in
Manuscript received September 28, 2018; revised November 13, 2018; silicon-based IMOS is too high to be considered for low-
accepted December 13, 2018. The review of this paper was arranged by power (sub-1.0 V) applications according to the ITRS roadmap
Editor R. M. Todi. (Corresponding author: Gaurav Musalgaonkar.)
G. Musalgaonkar is with the Solid-State Physics Laboratory, for the sub-7-nm technology nodes [31]. Germanium, on the
DRDO, New Delhi 110054, India, and also with the Depart- other hand, can offer a lower breakdown voltage for IMOS
ment of Electrical Engineering, IIT Delhi, New Delhi 110016, India devices owing to its lower bandgap, lower critical fields
(e-mail: gaurav.musalgaonkar7@gmail.com).
S. Sahay is with the California NanoSystems Institute, University of for avalanche breakdown, and nearly symmetrical impact-
California at Santa Barbara, Santa Barbara, CA 93106, USA (e-mail: ionization coefficient (αn , α p ) for both electrons and holes.
shubham.sahay.ece10@iitbhu.ac.in). Recently, FETs without any metallurgical junction known
R. S. Saxena is with the Solid-State Physics Laboratory, DRDO, New
Delhi 110054, India (e-mail: rs_saxena@yahoo.com). as junctionless FETs (JLFETS) were proposed [32]–[36].
M. J. Kumar is with the Department of Electrical Engineering, IIT Delhi, The JLFETs exhibit a lower avalanche breakdown voltage
New Delhi 110016, India (e-mail: mamidala@ee.iitd.ac.in). as compared to the conventional MOSFETs owing to the
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. bulk conduction and occurrence of peak electric field within
Digital Object Identifier 10.1109/TED.2018.2887168 the drain region [32]. Several device architectures such as
0018-9383 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
2 IEEE TRANSACTIONS ON ELECTRON DEVICES
TABLE I
D EVICE PARAMETERS
Fig. 6. 2-D contour plot (at the onset of breakdown) of electron and hole
current density, respectively. (a) and (b) Conventional IMOS. (c) and (d)
Proposed MIMOS.
Fig. 3. Output characteristics of the conventional IMOS and proposed
MIMOS.
result, avalanche breakdown is most likely to be initiated in the
intrinsic region. Once the avalanche breakdown occurs, gener-
ated electrons (holes) drift toward the drain (source) terminal,
respectively, as shown in Fig. 6. Therefore, the motion of
the charge carriers before gaining the required kinetic energy
and initiating avalanche multiplication is limited to L I region
where the electric field is very high. On the other hand, in the
proposed MIMOS, at the middle of the germanium film, in the
region common to the top and bottom gates, the electric field
is minimum and increases on either side as shown in Fig. 5(b).
This electric field redistribution enables the carriers to
Fig. 4. Energy band profiles of (a) conventional IMOS and (b) proposed traverse along a longer inclined path as shown in Fig. 6(c)
MIMOS just before the avalanche breakdown. For conventional IMOS in contrast to the horizontal conduction path in conventional
VDS = 0.9 V and VGD = 0.2 V and for MIMOS VDS = 0.4 V and
VGD = 0.15 V IMOS. Therefore, the carriers move a longer distance in
MIMOS gaining more kinetic energy and momentum before
impact ionization leading to an increased impact ionization
rate.
Also, in the MIMOS, the inversion layer is formed under
both gates. Therefore, the entire channel potential drops across
the intrinsic regions (L I 1 and L I 2 ) away from the gates.
This increases the lateral electric field in the intrinsic regions
(L I 1 and L I 2 ). At the source-channel interface near the bot-
tom gate, the large electric field induces sharp band bending
and facilitates BTBT of carriers from source to intrinsic region
increasing the impact ionization rate further. All these factors
Fig. 5. Lateral electric field of (a) conventional IMOS and (b) proposed result in a higher impact ionization in MIMOS leading to a
MIMOS at the onset of avalanche breakdown. lower breakdown voltage.
Although the placement of the bottom gate near to the
in the MIMOS, a sharp band bending is observed at the source- source side can significantly reduce the breakdown voltage
channel interface just before breakdown voltage along the of an IMOS device, as shown in Fig. 3, the OFF-state current
cutline B–B’. This band bending aligns the valence band of increases considerably for the MIMOS. It may be noted that
the source with the conduction band of the intrinsic region the OFF-state current is defined as the drain current at the
(L I ). Carriers are injected into the channel region via BTBT zero-gate voltage (VGS ) for a fixed value (near the breakdown
from the source region due to this band alignment. The BTBT voltage) of the drain-to-source voltage (VDS ) and the ON-
increases the number of carriers available for impact ionization state current is defined as the drain current when VGS =
in the intrinsic region. This enhances the impact ionization VDS = VDD .
rate in the MIMOS. Fig. 5 shows the electric field profile for The OFF-state current of the conventional IMOS comprises
both the conventional and MIMOS structure at the onset of of p-i-n diode reverse leakage current and tunneling current.
avalanche breakdown. As can be observed from Fig. 7(a), a higher BTBT rate near the
As can be observed in Fig. 5(a), in the conventional IMOS, source-channel interface adjacent to the bottom gate, which is
most of the electric fields drop across the intrinsic region (L I ). responsible for reduced breakdown voltage also increases the
The electric field peaks at the gate edge and source-channel OFF -state current. Therefore, there is a tradeoff between the
junction and is minimum under the gate region (L G ). As a OFF -state current and the breakdown voltage in MIMOS.
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
4 IEEE TRANSACTIONS ON ELECTRON DEVICES
TABLE II
D EVICE PARAMETERS AT VARIOUS G EOMETRIES
Fig. 11. (a) Proposed MIMOS with both bottom and top gate lengths
fixed at 25 nm. (b) Bottom gate length variation keeping top gate length
fixed at 25 nm. (c) Top gate length variation keeping bottom gate
length fixed at 25 nm.
Fig. 9. (a) Output curve of proposed MIMOS with bottom gate shifted
toward the source. (b) Energy band profiles along B–B just before the
avalanche breakdown. (c) Output curve of proposed MIMOS with bottom
gate shifted toward the drain. (d) Energy band profiles along B–B just
before the avalanche breakdown.
Fig. 12. Output characteristics of the proposed MIMOS for the different
top gate to bottom gate lengths. (a) Top gate is fixed at 25 nm and bottom
gate length is varied. (b) Bottom gate is fixed at 25 nm and top gate length
is varied.
i.e., from source end to drain end. Also, this reduction in the
electric field is compensated by an increased electric field in
Fig. 10. (a) Output curve of the proposed MIMOS with complete
bottom gate between the source and drain. (b) Lateral electric field of
the ungated region L I 1 . This compensation ensures that the
the proposed MIMOS and complete bottom gate IMOS at the onset of breakdown voltage does not change significantly.
avalanche breakdown. The impact of gate length scaling on the breakdown voltage
of MIMOS is analyzed by scaling the top gate and the
increased toward the drain side keeping one edge fixed at the bottom gate length as shown in Fig. 11. Fig. 12(a) shows
source-channel interface. This is because the electric field at the output characteristic of the MIMOS for different bottom
the source-channel interface above the bottom gate remains gate lengths (L G2 ) while keeping the top gate length (L G1 )
nearly the same even when the bottom gate length is increased fixed at 25 nm. The electric field in the intrinsic region (L I 1 )
as shown in Fig. 10(b). There is only a slight reduction in the and at the source-channel interface increases when the length
peak electric field at the source-bottom gate interface when of the bottom gate is reduced below the top gate length.
the bottom gate extends below the entire active device layer, A higher electric field at the source-channel interface results
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
6 IEEE TRANSACTIONS ON ELECTRON DEVICES
multiplication induced breakdown. Using TCAD simulation [19] A. Padilla, C. W. Yeung, C. Shin, C. Hu, and T.-J. K. Liu, “Feed-
for Ge-MIMOS, a breakdown voltage of 0.59 V has been back FET: A novel transistor exhibiting steep switching behav-
ior at low bias voltages,” in IEDM Tech. Dig., Dec. 2008,
demonstrated. Although we have analyzed the performance pp. 1–4, doi: 10.1109/iedm.2008.4796643.
improvement for germanium devices targeting subunity break- [20] A. I. Khan, C. W. Yeung, C. Hu, and S. Salahuddin, “Fer-
down voltages, in this paper, the breakdown voltage is reduced roelectric negative capacitance MOSFET: Capacitance tuning &
antiferroelectric operation,” in IEDM Tech. Dig., Dec. 2011,
by 1.4 V when this architecture is employed in the silicon pp. 11.3.1–11.3.4., doi: 10.1109/iedm.2011.6131532.
IMOS. Therefore, the proposed MIMOS could be a lucrative [21] K.-S. Li et al., “Sub-60 mV-swing negative-capacitance FinFET with-
alternative to the conventional IMOS. Our results may provide out hysteresis,” in IEDM Tech. Dig., Dec. 2015, pp. 22.6.1–22.6.4.,
doi: 10.1109/iedm.2015.7409760.
the incentive for its experimental realization. [22] K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, “Impact ionization
MOS (I-MOS)-part I: Device and circuit simulations,” IEEE Trans.
Electron Devices, vol. 52, no. 1, pp. 69–76, Jan. 2005, doi: 10.1109/
R EFERENCES ted.2004.841344.
[23] W. Y. Choi, J. Y. Song, J. D. Lee, Y. J. Park, and B.-G. Park,
[1] M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, and “100-nm n-/p-channel I-MOS using a novel self-aligned structure,”
K. Bernstein, “Scaling, power, and the future of CMOS,” in IEDM Tech. IEEE Electron Device Lett., vol. 26, no. 4, pp. 261–263, Apr. 2005,
Dig., Dec. 2005, pp. 1–7, doi: 10.1109/IEDM.2005.1609253. doi: 10.1109/led.2005.844695.
[2] A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy- [24] F. Mayer, C. Le Royer, G. L. Carval, L. Clavelier, and S. Deleonibus,
efficient electronic switches,” Nature, vol. 479, no. 7373, pp. 329–337, “Static and dynamic TCAD analysis of IMOS performance: From the
Nov. 2011. single device to the circuit,” IEEE Trans. Electron Devices, vol. 53,
[3] A. C. Seabaugh and Q. Zhang, “Low-voltage tunnel transistors for no. 8, pp. 1852–1857, Aug. 006, doi: 10.1109/ted.2006.877372.
beyond CMOS logic,” Proc. IEEE, vol. 98, no. 12, pp. 2095–2110, [25] S. Ramaswamy and M. J. Kumar, “Junctionless impact ionization MOS:
Dec. 2010, doi: 10.1109/jproc.2010.2070470. Proposal and investigation,” IEEE Trans. Electron Devices, vol. 61,
[4] M. J. Kumar, R. Vishnoi, and P. Pandey, Tunnel Field-Effect Transistors no. 12, pp. 4295–4298, Dec. 2014, doi: 10.1109/ted.2014.2361343.
(TFET): Modelling and Simulation. Chichester, U.K.: Wiley, 2017. [26] N. Kannan and M. J. Kumar, “Dielectric-modulated impact-ionization
[5] S. Saurabh and M. J. Kumar, Fundamentals Of Tunnel Field-Effect MOS transistor as a label-free biosensor,” IEEE Electron Device
Transistors. Boca Raton, FL, USA: CRC Press, 2017. Lett., vol. 34, no. 12, pp. 1575–1577, Dec. 2013, doi: 10.1109/
[6] R. Asra, M. Shrivastava, K. V. R. M. Murali, R. K. Pandey, led.2013.2283858.
H. Gossner, and V. R. Rao, “A tunnel FET for VDD scaling below [27] D. Sarkar, N. Singh, and K. Banerjee, “A novel enhanced electric-field
0.6 V with a CMOS-comparable performance,” IEEE Trans. Electron impact-ionization MOS transistor,” IEEE Electron Device Lett., vol. 31,
Devices, vol. 58, no. 7, pp. 1855–1863, Jun. 2011, doi: 10.1109/ no. 11, pp. 1175–1177, Nov. 2010, doi: 10.1109/led.2010.2066541.
ted.2011.2140322. [28] C. Onal, R. Woo, H.-Y. S. Koh, P. B. Griffin, and J. D. Plummer,
[7] U. E. Avci, D. H. Morris, and I. A. Young, “Tunnel field-effect “A novel depletion-IMOS (DIMOS) device with improved reliability
transistors: Prospects and challenges,” IEEE J. Electron Devices Soc., and reduced operating voltage,” IEEE Electron Device Lett., vol. 30,
vol. 3, no. 3, pp. 88–95, May 2015, doi: 10.1109/jeds.2015.2390591. no. 1, pp. 64–67, Jan. 2009, doi: 10.1109/led.2008.2008029.
[8] S. Saurabh and M. J. Kumar, “Novel attributes of a dual material gate [29] M. J. Kumar, M. Maheedhar, and P. P. Varma, “Bipolar I-MOS—
nanoscale tunnel field-effect transistor,” IEEE Trans. Electron Devices, An impact-ionization MOS with reduced operating voltage using the
vol. 58, no. 2, pp. 404–410, Feb. 2011, doi: 10.1109/TED.2010.2093142. open-base BJT configuration,” IEEE Trans. Electron Devices, vol. 62,
[9] D. Mohata et al., “Barrier-engineered arsenide–antimonide heterojunc- no. 12, pp. 4345–4348, Dec. 2015, doi: 10.1109/ted.2015.2492358.
tion tunnel FETs with enhanced drive current,” IEEE Electron Device [30] A. Lahgere and M. J. Kumar, “The charge plasma n-p-n impact
Lett., vol. 33, no. 11, pp. 1568–1570, Nov. 2012, doi: 10.1109/ ionization MOS on FDSOI technology: proposal and analysis,” IEEE
led.2012.2213333. Trans. Electron Devices, vol. 64, no. 1, pp. 3–7, Jan. 2017, doi: 10.1109/
[10] M. S. Ram and D. B. Abdi, “Dopingless PNPN tunnel FET with ted.2016.2622741.
improved performance: Design and analysis,” Superlattices Microstruct., [31] (2013). International Technology Roadmap for Semiconductors.
vol. 82, pp. 430–437, Jun. 2015, doi: 10.1016/j.spmi.2015.02.024. [Online]. Available: http://public.itrs.net
[11] D. B. Abdi and M. J. Kumar, “In-built N+ pocket p-n-p-n tunnel [32] C.-W. Lee et al., “Low subthreshold slope in junctionless multigate
field-effect transistor,” IEEE Electron Device Lett., vol. 35, no. 12, transistors,” Appl. Phys. Lett., vol. 96, no. 10, p. 102106, Feb. 2010,
pp. 1170–1172, Dec. 2014, doi: 10.1109/led.2014.2362926. doi: 10.1063/1.3358131.
[12] D. B. Abdi and M. J. Kumar, “PNPN tunnel FET with control- [33] M. Gupta and A. Kranti, “Steep-switching germanium junctionless
lable drain side tunnel barrier width: Proposal and analysis,” Super- MOSFET with reduced OFF-state tunneling,” IEEE Trans. Electron
lattices Microstruct., vol. 86, pp. 121–125, Oct. 2015, doi: 10.1016/ Devices, vol. 64, no. 9, pp. 3582–3587, Sep. 2017, doi: 10.1109/
j.spmi.2015.07.045. ted.2017.2727543.
[13] M. J. Kumar and S. Janardhanan, “Doping-less tunnel field effect tran- [34] M. S. Parihar and A. Kranti, “Back bias induced dynamic and steep sub-
sistor: Design and investigation,” IEEE Trans. Electron Devices, vol. 60, threshold swing in junctionless transistors,” Appl. Phys. Lett., vol. 105,
no. 10, pp. 3285–3290, Oct. 2013, doi: 10.1109/ted.2013.2276888. no. 3, p. 033503, Jul. 2014, doi: 10.1063/1.4890845.
[14] S. Ramaswamy and M. J. Kumar, “Double gate symmetric tunnel FET: [35] S. Sahay and M. J. Kumar, “Nanotube junctionless FET: Proposal,
Investigation and analysis,” IET Circuits, Devices Syst., vol. 11, no. 4, design, and investigation,” IEEE Trans. Electron Devices, vol. 64, no. 4,
pp. 365–370, Jul. 2017, doi: 10.1049/iet-cds.2016.0324. pp. 1851–1856, Apr. 2017, doi: 10.1109/ted.2017.2672203.
[15] S. Sahay and M. J. Kumar, “Controlling the drain side tunneling [36] M. Gupta and A. Kranti, “Transforming gate misalignment into a unique
width to reduce ambipolar current in tunnel FETs using heterodielectric opportunity to facilitate steep switching in junctionless nanotransistors,”
BOX,” IEEE Trans. Electron Devices, vol. 62, no. 11, pp. 3882–3886, Nanotechnology, vol. 27, no. 45, p. 455204, Oct. 2016, doi: 10.1088/
Nov. 2015, doi: 10.1109/ted.2015.2478955. 0957-4484/27/45/455204.
[16] T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, [37] M. Gupta and A. Kranti, “Raised source/drain germanium junctionless
“Double-gate strained-ge heterostructure tunneling FET (TFET) MOSFET for subthermal off-to-on transition,” IEEE Trans. Electron
with record high drive currents and 60 mV/dec subthreshold Devices, vol. 65, no. 6, pp. 2406–2412, Jun. 2018, doi: 10.1109/
slope,” in IEDM Tech. Dig., Dec. 2008, pp. 1–3, doi: 10.1109/ ted.2018.2823752.
iedm.2008.4796839. [38] J. Widiez et al., “Experimental evaluation of gate architecture influence
[17] W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, “Tunneling field- on DG SOI MOSFETs performance,” IEEE Trans. Electron Devices,
effect transistors (TFETs) with subthreshold swing (SS) less than 60 vol. 52, no. 8, pp. 1772–1779, Aug. 2005, doi: 10.1109/ted.2005.851824.
mV/dec,” IEEE Electron Device Lett., vol. 28, no. 8, pp. 743–745, [39] ATLAS Device Simulation Software, Silvaco Int., Santa Clara, CA, USA,
Aug. 2007. doi: 10.1109/LED.2007.901273. 2014.
[18] H. Lu and A. Seabaugh, “Tunnel field-effect transistors: State-of-the- [40] G. Hellings et al., “Electrical TCAD simulations of a germanium
Art,” IEEE J. Electron Devices Soc., vol. 2, no. 4, pp. 44–49, Jul. 2014, pMOSFET technology,” IEEE Trans. Electron Devices, vol. 57, no. 10,
doi: 10.1109/jeds.2014.2326622. pp. 2539–2546, Oct. 2010, doi: 10.1109/ted.2010.2060726.
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
8 IEEE TRANSACTIONS ON ELECTRON DEVICES
[41] T. Mikawa, S. Kagawa, T. Kaneda, Y. Toyama, and O. Mikami, “Crystal Shubham Sahay (S’16) received the Ph.D.
orientation dependence of ionization rates in germanium,” Appl. Phys. degree in electrical engineering from IIT Delhi,
Lett., vol. 37, no. 4, pp. 387–389, Jul. 1980, doi: 10.1063/1.91932. New Delhi, India, in 2018.
[42] K. Gopalakrishnan, R. Woo, C. Jungemann, P. B. Griffin, and He is currently a Post-Doctoral Associate with
J. D. Plummer, “Impact ionization MOS (I-MOS)-part II: Experimental the University of California at Santa Barbara,
results,” IEEE Trans. Electron Devices, vol. 52, no. 1, pp. 77–84, Santa Barbara, CA, USA. His current research
Jan. 2005, doi: 10.1109/TED.2004.841345. interests include semiconductor device design
[43] M. Gupta and A. Kranti, “Variation of threshold voltage with temper- and modeling.
ature in impact ionization-induced steep switching Si and Ge junc-
tionless MOSFETs,” IEEE Trans. Electron Devices, vol. 64, no. 5,
pp. 2061–2066, May 2017, doi: 10.1109/ted.2017.2679218.
[44] E.-H. Toh, G. H. Wang, L. Chan, G. S. Samudra, and Y.-C. Yeo,
“Device physics and performance optimization of impact-ionization
metal–oxide–semiconductor transistors formed using a double-spacer
fabrication process,” Jpn. J. Appl. Phys., vol. 47, no. 4s, pp. 3077–3080,
Apr. 2008, doi: 10.1143/jjap.47.3077.
[45] D. J. Massey, J. P. R. David, and G. J. Rees, “Temperature dependence
of impact ionization in submicrometer silicon devices,” IEEE Trans. Raghvendra Sahai Saxena received the Ph.D.
Electron Devices, vol. 53, no. 9, pp. 2328–2334, Sep. 2006, doi: 10.1109/ degree from IIT Delhi, New Delhi, India, in 2012.
ted.2006.881010. Since 1998, he has been a Scientist with the
[46] R. Narang, M. Saxena, R. S. Gupta, and M. Gupta, “Impact of tempera- Solid-State Physics Laboratory (SSPL), DRDO,
ture variations on the device and circuit performance of tunnel FET: New Delhi. His current research interests include
A simulation study,” IEEE Trans. Nanotechnol., vol. 12, no. 6, nanoscale very large scale integration devices
pp. 951–957, Nov. 2013, doi: 10.1109/tnano.2013.2276401. and circuits.
[47] Y. Li, C.-H. Hwang, and T.-Y. Li, “Random-dopant-induced variability Dr. Saxena is an Editor of the IETE Technical
in Nano-CMOS devices and digital circuits,” IEEE Trans. Electron Review and the SSPL Technical Bulletin-Crystal.
Devices, vol. 56, no. 8, pp. 1588–1597, Aug. 2009, doi: 10.1109/ He is an American Society for Quality Certified
ted.2009.2022692. Reliability Engineer.
[48] S. Singh and P. N. Kondekar, “A novel dynamically configurable
electrostatically doped silicon nanowire impact ionization MOS,” Super-
lattices Microstruct., vol. 88, pp. 695–703, Dec. 2015, doi: 10.1016/
j.spmi.2015.10.033.
Gaurav Musalgaonkar (S’18) is currently pur- Mamidala Jagadesh Kumar (SM’98) is a Pro-
suing the Ph.D. degree with the Department fessor (on lien) with IIT Delhi, New Delhi, India.
of Electrical Engineering, IIT Delhi, New Delhi, He is currently the Vice-Chancellor of Jawahar-
India. lal Nehru University, New Delhi.
His current research interests include nano- Mr. Kumar was an Editor of the IEEE Trans-
electronics, semiconductor device modeling, and actions on Electron Devices. He is currently the
CMOS image sensors. Editor-in-Chief of the IETE Technical Review and
an Editor of the IEEE Journal of the Electron
Devices Society.