UNIT - 1

DIGITAL LOGIC & SEMICONDUCTOR DIODES

Digital Logic:
Boolean Algebra, Basic and Universal Logic gates, Half adder, Full adder, Simplification of logic
expressions using K-maps, Multiplexer, De-multiplexer, Encoder and Decoder.

BOOLEAN ALGEBRA
George Boole in 1854 invented a new kind of algebra known as Boolean algebra. It is sometimes
called switching algebra. Boolean algebra is the mathematical frame work on which logic design
based. It is used in synthesis & analysis of binary logical function.
Laws of Boolean Algebra:
1. 0’=1
2. 1’=0
3. If A=0, A’=1
4. IF A=1, A’=0
5. A’’=A
6. A.0=0
7. A.1=A
8. A.A=A
9. A.A’=0
10. A+0=A
11. A+1=1
12. A+A=A
13. A+A’=1
14. A+AB=A(1+B)=A
15. A+A’B=A+AB+A’B=A+B(A+A’)=A+B

LOGIC GATES
• It is an electronic circuit which makes logic decisions. A logic gate is a digital circuit with
 one or more input signal and only one output signal. All input or output signals either low
voltage or high voltage. A digital circuit is referred to as logic gate for simple reason i.e.
it can be analyzed on the basis of Boolean algebra.
• To make logical decisions, three gates are used. They are OR, AND and NOT gate. These
logic gates are building blocks which are available in the form of IC.
• The input and output of the binary variables for each gate can be represented in a tabular
column or truth table.
1. OR Gate: The OR gate performs logical additions commonly known as OR function. The OR
gate has two or more inputs and only one output. The operation of OR gate is such that a
HIGH(1) on the output is produced when any of the input is HIGH. The output is LOW(0) only
when all the inputs are LOW.
• If A & B are the input variables of an OR gate and c is its output, then A+B. similarly for
more than two variables, the OR function can be expressed as Y=A+B+C.

• Logical Symbol:

A
Y
B

 Truth table

Input Output

A B Y= A+B
0 0 0
0 1 1
1 0 1
1 1 1

Realization of OR gate using diodes

• Two input OR gate using "diode-resistor" logic is shown in figure below. Where X, Y are
 the inputs and F is the output.

D 1
X
F

Y
R L
D 2

Fig 5.1: OR gate using diodes

2. AND Gate : The AND gate performs logical multiplication, commonly known as AND
function. The AND gate has two or more inputs and a single output. The output of an AND gate
is HIGH only when all the inputs are HIGH. Even if any one of the input is LOW, the output will
be LOW. If a & b are input variables of an AND gate and c is its output, then Y=A.B

Logic Symbol

A
Y
B
Truth table

Input Output
A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1
Realization of AND gate using diodes
• Two input AND gate using "diode-resistor" logic is shown in figure below. Where X, Y
are inputs and F is the output.
+Vcc
+Vcc
R L
D 1
R L
X D 1 F
X F
Y

Y D 2

D 2
Fig 5.2AND gate using diodes

3. Not Gate ( Inverter): The NOT gate performs the basic logical function called inversion or
complementation. The purpose of this gate is to convert one logic level into the opposite logic
level. It has one input and one output. When a HIGH level is applied to an inverter, a LOW level
appears at the output and vice-versa.
4.NAND Gate: The output of a NAND gate is LOW only when all inputs are HIGH and
output of the NAND is HIGH if one or more inputs are LOW.

A
Y
B

5. NOR Gate: The output of the NOR gate is HIGH only when all the inputs are LOW.

A
Y
B
6.XOR Gate or Exclusive OR gate: In this gate output is HIGH only when any one of the
input is HIGH. The circuit is also called as inequality comparator, because it produces
output when two inputs are different. When both the inputs are high, then the output is
low.

A
Y
B
 7. XNOR Gate or Exclusive NOR Gate: An XNOR gate is a gate with two or more inputs
and one output. XNOR operation is complimentary of XOR operation. i.e. The output of
XNOR gate is High, when all the inputs are identical; otherwise it is low.

A
Y
B

Universal Logic Gate

NAND and NOR gates are called Universal gates or Universal building blocks, because both
can be used to implement any gate like AND,OR an NOT gates or any combination of these
basic gates.

• NAND gate as Universal gate

NOR gate as Universal gate:
De Morgan’s Theorems:
It is one of the important properties of Boolean algebra. It is extensively useful in simplifying
complex Boolean expression.
Theorem 1: It states that “the compliments of product of two variables equal to sum of the
compliments of individual variable”.
X Y  X Y

Theorem 2: It states that compliment of sum of two variables is equal to product of compliment
of two individual variables.

X Y  X Y
1. RealizeEXOR Gate using only minimum NAND Gates

2. RealizeEXOR Gate using only NOR Gates

XNOR + NOR = XOR i.e. Add NOR gate to the ouptut of XNOR gate. Here is
the boolean algebra for XOR gate:

3. RealizeEX-NOR Gate using only minimum NOR Gates

4. RealizeEX-NOR Gate using only NAND Gates
XOR + NAND Inverter(NOT) = XNOR i.e. Add NOT Gate to the output of XOR
gate as shown in the image above. Here is the boolean algebra for XNOR
gate:
Half Adder:
A combinational circuit which performs the arithmetic addition of two binary digits is called Half
Adder. In the half adder circuit, there are two inputs, one is addend and augends and two outputs
are Sum and Carry.

A Sum
H a lf A d d e r
C arry
B

Logic Expression :

Circuit Symbol of Half adder:

Full Adder: The full adder is a combinational circuit that performs the arithmetic sum of three
input bits.
• It consists of three inputs and two outputs. Two of the inputs are variables, denoted by A
and B, represent the two significant bit to be added. The third input C in represents carry
form the previous lower significant position.

A Sum
B F u ll A d d e r
C arry
C in
Truth Table for Full Adder

Full adder Circuit

using two Half adders:
 Fig 5.4:Full adder Circuit using two Half adders

SIMPLIFICATION USING BOOLEANALGEBRA

A simplified Boolean expression uses the fewest gates possibleto
implement a givenexpression.

Example
Using Boolean algebra techniques, simplify thisexpression:

AB + A(B + C) + B(B +C)

Solution
Step 1: Apply the distributive law to the second and third terms inthe
expression, asfollows:
AB + AB + AC + BB +BC
Step 2: Apply rule 7 (BB = B) to the fourthterm.
AB + AB + AC + B +BC
Step 3: Apply rule 5 (AB + AB = AB) to the first twoterms.
AB + AC + B +BC
Step 4: Apply rule 10 (B + BC = B) to the last twoterms.
 AB + AC +B
Step 5: Apply rule 10 (AB + B = B) to the first and thirdterms.
B+AC
At this point the expression is simplified as much aspossible.

Boolean Algebra Practice Problems

1) a 0 yyy

14) xyx y

2) a0

15)
3) aa 16 xyx
)


4) aa 17) (w x y z) y

5) a ab
18) (x y)(x y)
6) a ab
19) w [w (wx)]
7) a(a b) 20) x[x (xy)]

8) abab 21) (x x)

22) (x x)


9) (ab)(a b) 

10) a(a b c ...) 23) w (wxyz)

For (11),(12),(13),
f(a,b,c)abc 24) w(wxyz)
11) f(a, b, ab) 25) xzxyzy
12) f(a,b,ab) 26) (x z)(x y)(z y)
13)f[a,b,(ab)] 27) x y xyz

Solutions to the Boolean Algebra PracticeProblems

1) a0 a
2) a0 0
3) aa 1
1) a a a
5) aaba(1 b) a
6)aab(aa)(ab)ab
7) a(a b) aaabab
8) ababb(a a) b
9) (ab)(ab)aaabbabbaababa(1bb)a
10) a(a b c ...) aaabac ... a abac ... a
11) f(a, b, ab) a b aba b
12) f(a,b,ab)abababa1
13) f[a,b,(ab)]ab(ab)abab 1
14) y yy y
15) xyx y x( y y) x
16) xyxx(1 y) x
17) (wx y z) y
y18) (x y)(x y)
x19)w[w(wx)]w
20) x[x (xy)] x
21) (x x) x
22) (x x) 0
23) w(wxyz)w(1xyz)w
24) w(wxyz)w(wxyz)w
25) xzxyzyxzxy
26)(xz)(xy)(zy)(xz)(xy)xyxz
27) xy xyz x y z
 Draw a logic circuit for (A + B)C.
 Soln:

 Draw a logic circuit for A + BC + D.

Soln:

 Draw a logic circuit for AB + AC.

Soln:

 Draw a logic circuit for (A + B)(C + D)C.

Soln:
MULTIPLEXER (MUX)

 A MUX is a digital switchthat has multiple inputs(sources) and a singleoutput

(destination).

 The select linesdetermine which input is connected to the output

 MUXTypes
2-to-1(1selectline)
4-to-1(2selectlines)
8-to-1(3selectlines)
16-to-1(4selectlines)

 Normally there are 2n input lines and n select lines

 The basic multiplexer has several data input lines and a single output line and hence the
name ‘Many to One’.
 2:1 Mux
 2:1 Mux contains 2 input lines, 1 select line and one output line

Fig 5.8: 2:1 MUX

 4:1 MUX
 4:1 MUX contains 4 input lines, 2 select lines and one input line

Logic Symbol
Truth Table

S0 S1 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

S0 S1
Logic Expression:

Y= S0’ S1’D0 +S0’ S1 D1 +S0 S1’ D2+ S0 S1 D3

No of AND Gates : 04
No of NOT Gates : 02
No of OR Gates : 01
Total Gates : 07
DEMULTIPEXER (De-MUX)

• A DEMUX is a digitalswitch with a single input(source) and a multiple outputs

(destinations).

• The select linesdetermine which output the inputisconnectedto. The selection of

specific output is controlled by the values of ‘n’ select lines.

• DEMUXTypes
1-to-2(1selectline)
1-to-4(2selectlines)
1-to-8(3selectlines)
1-to-16(4selectlines)
1:4 DEMUX:

Input = 01
Select lines ‘n’= 2
Outputs = 2n = 4

Logic symbol:

Truth Table:
S0 S1 D0 D1 D2 D3
0 0 X 0 0 0
0 1 0 X 0 0
1 0 0 0 X 0
1 1 0 0 0 X
Logic Expression:

D0=S0’ S1’ X
D1= S0’ S1 X
D2= S0 S1’ X
D3= S0 S1 X
1: 4 DEMUX Circuit:

S0 S1

 No of Gates for 1:4 DEMUX

AND Gates= 04
NOT Gates = 02
ENCODERS:

 Device which converts one binary code to another

 Multiple inputs , multiple outputs
 Converts complex to simplest form
 More inputs, less outputs

DECODER

 Device which transforms the coded bits to generate the original data again
 Multiple inputs multiple output logic circuit
 It converts coded inputs into coded outputs, where the inputs and outputs are different
 Less inputs with more outputs
 It takes in ‘n’ input and gives out 2n outputs

2 to 4 Decoder Logic symbol and Truth table:

3 to 8 decoder: (Binary to Octal Converter)

A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0
 1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

Circuit diagram for 3 to 8 decoder:

Semiconductor Diode:
 The Semiconductor diode is created by simply joining the n-type and p-type material
together. It is nothing but joining of one material with a majority carrier of electrons to
one with a majority carries of holes.

 In below figure1.1 p-type and n-type semiconductor materials are shown side by side
representing a PN- junction

Fig1.1: At an pn-junction, electrons cross from the n-side to fill the holes in a layer of the p-
side close to the junction.
 Since holes and electrons are close together at the junction, some free electrons from the
n-side are attracted across the junction from a region of higher carrier concentration.

 The free electrons crossing the junction create negative ions on the p-side by giving some
atoms one more electron than their total number of protons.

 The electrons also leave positive ions(atoms with one fever electron than the number of
protons)behind them on n-side.

Barrier Voltage:
 Before the diffusion process the n-type and p-type materials will be electrically neutral.

 When the negative ions are created on the p-side, the portion of the p-side close to the
junction acquires a negative voltage. Similarly the positive ions created on the n-side give
the n-side a positive voltage close to the junction.
  The negative voltage on the p-side tends to repel additional electrons crossing from the n-
side and the positive voltage on the n-side tends to repel additional holes from the p-side.

 The initial diffusion of charge carriers creates a barrier voltage at the junction which is
positive on n-side and negative on p-side.

 The magnitude of the barrier voltage for germanium is 0.3V and for silicon is 0.7V.

Depletion Region:
 Depletion region is also called space charge region.

 The movement of charge carriers across the junction leaves a layer on each side that is
depleted of charge carriers.

 On the n-side, the depletion region consists of donor impurity atoms that having lost the
free electron associated with them have become positively charged.

 On the p-side, the depletion region consists of acceptor impurity atoms that have become
negatively charged by losing the hole associated with them.

 If the two blocks of semiconductor material have equal doping densities ,the depletion
layer on each side have equal widths.

 If the p-side is more heavily doped than n-side the depletion region penetrates more
deeply into the n-side in order to include an equal number of impurity atoms on each side
of the junction.

 When the n-side is more heavily doped, the depletion region penetrates more deeply into
the p-side.

 In equilibrium condition, the depletion region gets widened upto a point where further
electrons or holes can cross the junction.

PN Junction diode operation and its V-I characteristics

PN Junction diode operation:
 The below figure1.2 shows the schematic arrangement of a PN junction diode and figure
1.3 shows the symbol of a diode.
 Fig1.2:Schematic arrangement of PN junction diode

Fig1.3:Symbol of of PN junction diode

 The term Bias refers to the application of external voltage across the two terminals of the
device to extract the response.

 We have two different biasing conditions:

1. Forward Bias

2. Reverse Bias

 If a voltage applied across the diode has the same polarity across the diode it is
considered as Forward Biasing.

 If a voltage applied across the diode has the reverse polarity across the diode it is
considered as Reverse Biasing.

Forward Bias condition:

 A forward bias or ON condition is established by applying the positive potential to the p-
type material and negative potential to the n-type material.

 The forward bias condition is shown in below fig 1.4.

 Fig1.4: Forward biased PN junction: Internal distribution of charge
carriers under forward-bias condition
 The application of a forward biased potential will pressurize electrons in the n-type
material and holes in the p-type material to recombine with the ions near the boundary
and reduce the width of the depletion region.

 The minority flow of carrier flow of electrons from the p-type material to the n-type
material and of holes from n-type material to p-type material has not changed in
magnitude but the reduction in the width of the depletion region has resulted in a heavy
majority flow across the junction

 An electron of the n-type material now experiences reduced barriers at the junction due to
the reduced depletion region and a strong attraction for the positive potential applied to
the p-type material.

 As the applied bias increase in magnitude the depletion region will continue to decrease
in width until a flood of electrons can pass through the junction resulting in a exponential
rise in current.

 Typically the voltage across the forward biased diode will be less than 1V.

 It is important to remember that in the forward biased condition, conduction is by

majority current carriers(i.e. holes in p-type material and electrons in n-type material.)

 Increasing the battery voltage will increase the number of majority carriers arriving the
junction and therefore increases the current flow.

 If the battery voltage is increased to the point where the barrier is greatly reduced a heavy
current will flow and the junction may be damaged from the resulting heat.

Reverse Bias condition:

 A reverse bias or OFF condition is established by applying the positive potential to the n-
type material and negative potential to the p-type material.

 The forward bias condition is shown in below fig1.5.

.
Fig1.5:Reverse biased PN junction: Internal distribution of charge
carriers under reverse-bias condition

 The number of uncovered positive ions in the depletion region of the n-type material will
increase due to the large number of free electrons drawn to the positive potential of the
applied voltage

 Similarly the number of uncovered negative ions will increase in the p-type material. The
net effect therefore is a widening of depletion region.

 This widening of the depletion region will establish a great barrier for the majority
carriers to overcome effectively reducing the majority carrier flow to zero.

 The number of minority carriers, however entering the depletion region will not change,
resulting in minority carrier flow.

 The current that exists under reverse bias conditions is called the reverse saturation
current represented by Is or Io.

 when the reverse bias on the PN junction is increased, there is only a negligible increase
in the reverse saturation current.

 Further increase in the reverse bias voltage reduces a special phenomenon called
“Junction Breakdown”.
 Diode Current Equation:
 When a diode is subjected to bias there will be a current flow through the diode
depending on bias conditions.

 Diode conducts when it is forward biased and there will be a large majority charge
carriers crossing the junction resulting in large current.

 Diode stops conduction when it is reverse biased and there will be only minority charge
carriers crossing the junction resulting in a reverse saturation current.

 The equation relating pn junction current and voltage levels is called Shockley equation
and is represented as

ID= Io[eVD/ηVT -1]

Where
Io - Reverse Saturation Current
VD - Applied bias voltage across the diode
η -
Constant that depends on material
V
T - Thermal voltage called voltage equivalent of temperature
V
T =KT/q

where
K-Boltzman’s constant=1.38*10-23 J/K
T- Absolute Temperature=(273+Tºc)K
q-change of electron=1.6*10-19 C
By substituting the above values VT can be obtained as
V
T =T/11600

V-I characteristics of PN junction Diode:

 A complete analysis of PN junction shows that in the forward biased condition , the diode
current ID varies exponentially with applied voltage V

 Where as in the reverse biased condition, the diode current ID is almost constant
irrespective of the applied voltage and is almost equal to Io.

 The relation between the current through the diode and the voltage across the diode is
given by diode equation.

 The diode behavior based on the diode current equation is illustrated in below fig 1.6.
 Fig1.6: V-I Characteristics of PN junction diode
 The figure1.6 indicates the VI characteristics for a germanium diode and a silicon diode.

 From the curve it is clear that cut-in voltage Vγ for a germanium diode is 0.3V and for a
silicon diode is 0.7V.

 It is evident from the diode current equation that diode current is sensitive to the device
temperature.

 In the forward bias region for a given voltage ,diode current reduces with increase in
temperature and the current shifts to the left.

 In reverse bias condition, the diode current increases i.e. I0 doubles for every 10º c rise in
temperature.

Diode Parameters:
The diode parameters of greatest interest are listed below:
1. VF ----- Forward voltage drop/ Cut-in voltage

2. Is or Io----- Reverse Saturation Current

3. RD----- Static or DC resistance

4. rd-----Dynamic or AC resistance

5. VBR-----Reverse breakdown voltage

6. Trr----- Reverse recovery time

7. Pd-----Maximum power dissipation

1. Forward Voltage drop VF:

 It is the voltage drop across the diode when it conducts.
 The forward bias voltage must exceed this voltage before the diode begins to conduct
large currents
 It is also called as cut-in voltage vγ or knee voltage.

2. Reverse Saturation Current IS:

 The reverse saturation current IS is the nominal current which flows through the diode
when it is reverse biased.
 The term saturation comes from the fact that it reaches its maximum level quickly and
does not change significantly with increasing reverse bias potential.
 Reverse saturation current will be few nA for silicon and µA foe germanium.
 IS Varies with temperature, IS doubles for every 10º rise in temperature. When the
temperature of a semiconductor material is raise, increasing the number of electrons
break away from their atoms. This Generates additional minority carriers causing I S to
increase as temperature rises.
 The new IS at temperature T2 is given as

IS(T2)= IS(T1)(2 T2- T1/10)

3. Static or DC resistance RD:

 The application of a DC voltage to a circuit containing a diode will result in an operating
point on the characteristics curve that will not change with time.
 This is a static quantity i.e. it is constant for a specific current.
 The resistance of the diode at the operating point can be found by finding the
corresponding levels of VD and ID as shown in below figure1.7.

RD= VD/ ID
Fig 1.7:Determining the DC resistance of a diode at a particular operating
point
 The resistance levels in the reverse bias region will naturally be quite high.
 In general, the higher the current through the diode the lower is the dc resistance levels.

4. Dynamic or AC resistance rd:

 Suppose in addition to a dc current a small ac signal is super imposed in a diode circuit.
The resistance that the diode offers to this signal is called AC resistance.
 The varying input will move the operating point up and down and thus defines a specific
change in current and voltage.
 If there is no varying signal the point of operation would be the Q-point appearing on
figure determined by the applied dc levels.
 The term Q-point is derived from the word “Quiescent” which means “Still or
unvarying”.
 Fig1.8: Defining the dynamic or AC resistance
 A straight line drawn tangent to the curve through the Q-point as shown on figure will
define a particular change in voltage and current that can be used to determine the AC or
dynamic resistance.
 rd is given as

rd =ΔVD/Δ ID
where Δ signifies the finite change in the quantity.

Expressing rd in terms of VT and ID

WKT ID= Io[eVD/ηVT -1]
Differentiate ID w.r.t VD
d ID/ d VD=d (Io[eVD/ηVT -1])/ d VD
d ID/ d VD= Io[eVD/ηVT *1/ ηVT-0]
d ID/ d VD= IoeVD/ηVT * 1/ ηVT
d ID/ d VD= ID/ ηVT
WKT r=V/I
Therefore d VD/ d ID= ηVT/ ID
put η =1 &VT=26mV, we get
rd=26mv/ID=VT/ ID
5. Reverse breakdown voltage VBR:
 If the reverse bias applied to a PN junction diode is increased, points is reached where the
junction breaks down and reverse current shoots up to a value only by the external
 resistance connected in series with the junction, This critical value of the voltage is called
the reverse breakdown voltage.

For silicon it is greater than 80V

For germanium, the typical value is 100V

6. Power dissipation Pd:

 The diode power dissipation is given by

Pd= Vf *If W
 To avoid overeating and damage of the device, the maximum safe value of power
dissipation is specified which is denoted as Pd(max).
 At higher temperatures, as the device junction temperature is higher it can dissipate
less power. Thus maximum power dissipation of the device must be derated at higher
temperature.

Fig 1.9: Power derated at high temperature

 the above figure 1.9 shows derating graph for a particular device, up to 30ºC it is
rated for Pd(max) of 80mW but at higher temperature it is derated as it cannot dissipate
same amount of maximum power.
 The new power P2 at new temperature T2 can be obtained from initial temperature T1
as

P2=( P1 at T1)-[ΔT* Derating factor]

ΔT=( T2- T1)
 Derating factor is also given by ΔP/ΔT.
7. Reverse recovery time:

 Ideally, a diode is (a) a perfect conductor when it isforward biased, (b) a perfect insulator.
when reverse biased, and (c) the transition from conductor to insulator is instantaneous
upon a forward bias/reverse bias switch.
  Practical diodes don’t display these ideal characteristics, and this question is related to the
transition (switching) time from conduction to open circuit when the bias is reversed. The
figure below shows what happens when the diode bias is switched from forward to
reverse. At the switch time, the current reverses and stays at a constant level for a period
of time called the storage time, ts.
 During this time the diode acts essentially as a short circuit. Then the current decreases to
the reverse leakage current value. This latter time is called the transition time
 The sum of the storage and trasition times is the reverse recovery time. It depends on the
forward current, and data sheets give the reverse recovery time along with the test
conditions.

Fig 1.10:Reverse recovery time

 When pn junction is forward biased, a large number of electrons are injected into the p-
material, and a large number of holes are injected into the n-material of the pn junction.
 When the diode is then reverse biased, these stored minority carriers must return to the
opposite material. The time it takes for the electrons to move from the p-material back to
the n-material and the holes to move from the n-material to the p-material is the storage
time, and is determined by the geometry of the pn junction.
 The reverse recovery times for pn junction diodes are a few microseconds for general-
purpose rectifier diodes such as the 1N4001.

Diode Equivalent Circuits:

 For general performance analysis of any device or a system, an equivalent circuit may be
used which is an alternate representation of the device or the system.
 An equivalent circuit contains alternate components that best corresponds the actual
characteristics of a device or the system under the given operating conditions.
1. Piecewise Linear Equivalent circuit:
  In order to obtain more precise and an excellent equivalent circuit for a diode
approximations for the device characteristics by using straight line segments can be made
 Nonlinear waveforms are often approximated by a number of linear segments in order to
simplify the analysis.
 The more the number of linear segments, the more will be the approximations close to the
actual waveform such an approximation is called Piecewise Linear approximation.

Fig 1.11: Defining the piecewise-linear equivalent circuit using straight-line

segments to approximate the characteristic curve.

Fig 1.12:Components of piecewise-linear equivalent circuit.

 It should be obvious from the figure1.12 that the straight line segments do not result in
exact duplication of the actual characteristics especially in the knee region however, the
resulting segments are sufficiently close to the actual curves that establish an equivalent
circuit that will provide an excellent first approximation to the actual behavior of the
device.
 The ideal diode is included to establish that there is only one direction of conduction
through the device and a reverse bias condition will result in the open circuit state for the
device.
 We know that the semiconductor diode does not reach the conduction state until V D
reaches 0.7V with a forward bias, a battery V K opposing the conduction direction must
appear in the equivalent circuit.

2. Simplified Equivalent Circuit:

 For most of the applications, the resistance rav represented in the equivalent circuit is
sufficiently small order of few ohms and hence can be ignored in comparison to the other
elements in the network such as source resistance Rs and load resistance RL
 By eliminating the resistance rav from the equivalent circuit of above fig, a simplified
equivalent is obtained and it is represented in below figure.
 This approximation can be employed in all semiconductor diode circuit analysis.
 Below figure states that a forward biased silicon diode in an electronic system under dc
conditions has a drop of 0.7V across it in the conduction state at different levels of diode
current but resistance is zero.


Fig 1.13: Simplified equivalent circuit for silicon semiconductor diode.

3. Ideal Equivalent Circuit:
 For all practical purposes, the voltage Vk represented in the equivalent circuit is
negligible compared to the applied voltage and is eliminated from the equivalent circuit
resulting in an ideal diode as shown below.
 As shown in figure the forward current for the diode starts at the origin itself, even for a
small positive forward bias current shoots up implying that Vk and r=0.
 An ideal diode therefore contains zero forward resistance, zero cut-in voltage and infinite
reverse resistance.
 Fig 1.14:Ideal diode and its characteristics.

DC Load Line Analysis:

E VD

Fig 1.15:Diode circuit

Fig 1.16:Diode characteristics

 The above diode circuit in figure 1.15 is used to describe the analysis of a diode circuit
using its actual characteristics.
  The above circuit is solved to find the current and voltage levels that will satisfy both the
characteristics of the diode and the chosen network parameters.
 The conventional direction of current has the same direction as the arrow in the diode
symbol reveals that the diode is in the ON state and will conduct a high level of current,
 The intersection of the load line characteristics can be determined by first applying KVL
to the above circuit.

+E-VD-VR=0
E=VD+ ID VR--------------------(1)
 The intersection of load line on the characteristics can easily be determined if one simply
employs the fact that anywhere on the horizontal axis ID=0 and anywhere on the vertical
axis VD=0 and

 If we set VD=0 in eqn(1) and solve for ID we get

E=VD+ ID VR
E=0+ ID VR
ID=E/R| VD=0
If we set ID=0 in eqn (1) and solve for VD we get
E=VD+ ID VR
E=VD
VD =E| ID=0
 Plotting these points on the diode characteristics and joining the points will give the load
line.
 The below figure 16 shows the load line and the point of operation.

E/R

E
Fig 1.17: Drawing the load line and finding the point of operation.
 The diode characteristics are placed on the same set of axes as a straight line defined by
the parameters of the network.
 The straight line is called load line because the intersection on the vertical axis is defined
by the applied load R. the analysis to follow is therefore called load line analysis.
 The intersection of two curves will define the solution for the network and define the
current and voltage levels for the network.
 Changing the level of R (the load) will change the intersection on the vertical axis; the
result will be a change in slope of the load line. So we get a different point of intersection
between the load line and the device characteristics.
 The point of intersection of the load line and the device characteristics will give the point
of operation for the circuit.
 The point of operation is usually called the quiescent point or Q point which is nothing
but still unmoving.

Temperature Effects:
1. Effect of Temperature on the forward voltage drop across a Diode:
 Most of the times, the drop across the diode is assumed to be constant. But in few
situations it is necessary to consider the effect of temperature on forward voltage
drop.
 The diode voltage drop decreases with increase in temperature.
 A diode forward voltage drop at any temperature can be calculated from a
knowledge of VF at the starting temperature(VF1 @ T1) the temperature change (ΔT)
and the voltage per temperature co-efficient(Δ VF/ºc)
 VF2= VF1 @ T1 + [ΔT Δ VF/ºc]
 Fig 1.18: Effect of temperature on VF
2. Effect of temperature on dynamic resistance :
 WKT, the dynamic resistance is expressed as

r`=26mV/IF = VT/ IF= KT/ IF

 As temperature increases the value of VT changes in fact it increases.

r`= KT`/ IF
 Where T` is the new temperature
 New dynamic resistance can be expressed as

r`=26mV/IF[Tº in K/300 K]
 As temperature increases VT increases hence dynamic resistance increases.
3. Effect of temperature on reverse saturation current:
 IS Varies with temperature, IS doubles for every 10º rise in temperature. When the
temperature of a semiconductor material is raise, increasing the number of electrons
break away from their atoms. This Generates additional minority carriers causing I S to
increase as temperature rises.
 The new IS at temperature T2 is given as

IS(T2)= IS(T1)(2 T2- T1/10)

Temperature Dependence of PN Diode characteristics:

 Fig 1.19: Effect of temperature on diode.

AC Equivalent circuits:
Junction capacitances:
 The depletion region of a PN junction is a layer depleted of charge carriers situated
between two blocks of low resistance material which is similar to a capacitor. The
junction depletion region clearly has a capacitance.
 Depending on the biasing conditions, 2 types of capacitance effects exists in the diode.
They are
i. Transition capacitance (CT) in reverse biased condition.
ii. Diffusion capacitance (CD) in forward biased condition.

1. Transition capacitance(CT or Cpn):

 Fig 1.20: capacitance in reverse biased region
 The above figure1.20 shows the capacitance in reverse biased region.
 When a diode is reverse biased, the width of the depletion region increases. So there
are more positive and negative charges present in the depletion region.
 This depletion region acts like di-electric, the p-region and n-region acts like plates of
capacitor. Thus there exists a capacitance at the pn junction called transition
capacitance or junction capacitance or space charge capacitance or barrier capacitance
or depletion region capacitance which is denoted as CT.
 It is given by the expression
 ɛ
CT= A/W.
 ɛ - Permittivity of semiconductor.
 A - area of cross section
 W – Width of depletion region.

Fig 1.21: Variation of CT with respect to applied reverse bias

  As the reverse bias applied to the Diode increases the width of the depletion region
increases, thus the transition capacitance CT decreases.
 In short, the capacitance can be controlled by the applied voltage.
 Variation of CT with respect to the applied reverse bias is shown in the above figure.
 In the above figure 1.21 CT varies from 80Pf to 10 Pf, as reverse voltage varies from
5V to 20V.

2. Diffusion capacitance(CD)
 During forward biased condition another capacitance comes into existence called
Diffusion capacitance or storage capacitance.
 In forward biased condition, the width of the depletion region decreases. Holes from
P side get diffused into N side while electrons from N side moves into the P side.
 As the applied voltage increases, concentration of injected charged particles
increases.
 This rate of change of the injected charge with the applied voltage is defined as
diffusion capacitance.
 CD=dQ/dV or CD=ΓI/ηVT
 Usually CD will be in the order of nF to µF and CT will be pF.
 Therefore CD >> CT
 CD is very significant when we are considering the fast signals.
 Variation of CD with respect to applied forward bias is shown in below figure 21

.
Fig 1.22: Variation of CD with respect to applied forward bias
3. AC Equivalent Circuits:
 Reverse biased condition:
a. The equivalent circuit of a reverse biased diode is shown below:
b. It consists of large reverse resistance RR in parallel with depletion layer
capacitance CD .
 Fig 1.23: Reverse biased condition
 Forward biased condition:
a. The forward biased diode is represented by two parallel circuits as shown
below.
b. The first circuit comprises of forward voltage drop VF in series with dynamic
resistance RD.While the second circuit contains diffusion capacitance CD.

Fig 1.24: Forward biased condition

c. The AC equivalent circuit can be obtained by shorting the DC source as
shown below.

Fig 1.25: AC equivalent circuit