PD-95020A

IRFR9120NPbF
IRFU9120NPbF
HEXFET® Power MOSFET
l Ultra Low On-Resistance
l P-Channel D
l Surface Mount (IRFR9120N) VDSS = -100V
l Straight Lead (IRFU9120N)
l Advanced Process Technology RDS(on) = 0.48Ω
l Fast Switching G
l Fully Avalanche Rated ID = -6.6A
l Lead-Free S

Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
known for, provides the designer with an extremely efficient
and reliable device for use in a wide variety of applications.
D-Pak I-Pak
The D-Pak is designed for surface mounting using vapor TO-252AA TO-251AA
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU series) is for through-hole mounting
applications. Power dissipation levels up to 1.5 watts are
possible in typical surface mount applications.

Absolute Maximum Ratings

Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ -10V -6.6
ID @ TC = 100°C Continuous Drain Current, VGS @ -10V -4.2 A
IDM Pulsed Drain Current  -26
PD @TC = 25°C Power Dissipation 40 W
Linear Derating Factor 0.32 W/°C
V GS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy‚ 100 mJ
IAR Avalanche Current -6.6 A
EAR Repetitive Avalanche Energy 4.0 mJ
dv/dt Peak Diode Recovery dv/dt ƒ -5.0 V/ns
TJ Operating Junction and -55 to + 150
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )

Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 3.1
RθJA Junction-to-Ambient (PCB mount)** ––– 50 °C/W
RθJA Junction-to-Ambient ––– 110
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IRFR/U9120NPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage -100 ––– ––– V VGS = 0V, ID = -250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– -0.11 ––– V/°C Reference to 25°C, ID = -1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 0.48 Ω VGS = -10V, I D = -3.9A „
VGS(th) Gate Threshold Voltage -2.0 ––– -4.0 V VDS = VGS, ID = -250µA
gfs Forward Transconductance 1.4 ––– ––– S VDS = -50V, ID = -4.0A†
––– ––– -25 VDS = -100V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– -250 VDS = -80V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
Qg Total Gate Charge ––– ––– 27 ID = -4.0A
Qgs Gate-to-Source Charge ––– ––– 5.0 nC VDS = -80V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 15 VGS = -10V, See Fig. 6 and 13 „†
td(on) Turn-On Delay Time ––– 14 ––– VDD = -50V
tr Rise Time ––– 47 ––– ID = -4.0A
ns
td(off) Turn-Off Delay Time ––– 28 ––– RG = 12 Ω
tf Fall Time ––– 31 ––– RD =12 Ω, See Fig. 10 „†
Between lead, D
LD Internal Drain Inductance ––– 4.5 –––
6mm (0.25in.)
nH
from package G

LS Internal Source Inductance ––– 7.5 –––

and center of die contact… S

Ciss Input Capacitance ––– 350 ––– VGS = 0V

Coss Output Capacitance ––– 110 ––– pF VDS = -25V
Crss Reverse Transfer Capacitance ––– 70 ––– ƒ = 1.0MHz, See Fig. 5†

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current MOSFET symbol D

––– ––– -6.6

(Body Diode) showing the
A
ISM Pulsed Source Current integral reverse G
––– ––– -26
(Body Diode)  p-n junction diode. S

V SD Diode Forward Voltage ––– ––– -1.6 V TJ = 25°C, IS = -3.9A, VGS = 0V „

t rr Reverse Recovery Time ––– 100 150 ns TJ = 25°C, IF = -4.0A
Qrr Reverse Recovery Charge ––– 420 630 nC di/dt = 100A/µs „†
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Repetitive rating; pulse width limited by „ Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature. ( See fig. 11 ) …This is applied for I-PAK, LS of D-PAK is measured between
‚ Starting TJ = 25°C, L = 13mH lead and center of die contact
RG = 25Ω, IAS = -3.9A. (See Figure 12)
ƒ ISD ≤ -4.0A, di/dt ≤ 300A/µs, VDD ≤ V(BR)DSS, † Uses IRF9520N data and test conditions.
TJ ≤ 150°C
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
 IRFR/U9120NPbF
100 100 VGS
VGS
TOP -15V TOP -15V
-10V -10V

-I D , Drain-to-Source Current (A)

-8.0V
-I D , Drain-to-Source Current (A)

-8.0V
-7.0V -7.0V
-6.0V -6.0V
-5.5V -5.5V
-5.0V -5.0V
BOTTOM -4.5V BOTTOM -4.5V
10 10

1 1

-4.5V
-4.5V
20µs PULSE WIDTH 20µs PULSE WIDTH
TJ = 25 °C TJ = 150 °C
0.1 0.1
0.1 1 10 100 0.1 1 10 100
-VDS , Drain-to-Source Voltage (V) -VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

100 2.5
ID = -6.7A
R DS(on) , Drain-to-Source On Resistance
-I D , Drain-to-Source Current (A)

2.0

10 TJ = 25 °C
(Normalized)

1.5
TJ = 150 ° C

1.0
1

0.5

V DS = -50V
20µs PULSE WIDTH
V GS = -10V
0.1 0.0
4 5 6 7 8 9 10 -60 -40 -20 0 20 40 60 80 100 120 140 160
-VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature ( °C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

Vs. Temperature
 IRFR/U9120NPbF
800 20
VGS = 0V, f = 1MHz ID = -4.0 A
VDS =-80V
Ciss = Cgs + Cgd , Cds SHORTED
VDS =-50V

-VGS , Gate-to-Source Voltage (V)

Crss = Cgd
VDS =-20V
Coss = Cds + Cgd 16
600
C, Capacitance (pF)

Ciss
12

400 Coss
8
Crss
200
4

FOR TEST CIRCUIT

SEE FIGURE 13
0 0
1 10 100 0 5 10 15 20 25
-VDS , Drain-to-Source Voltage (V) QG , Total Gate Charge (nC)

Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs.

Drain-to-Source Voltage Gate-to-Source Voltage

100 100
OPERATION IN THIS AREA LIMITED
BY RDS(on)
-ISD , Reverse Drain Current (A)

10us
-IID , Drain Current (A)

TJ = 150 ° C
10 10
TJ = 25 ° C 100us

1ms

1 1
10ms

TC = 25 °C
TJ = 150 °C
V GS = 0 V Single Pulse
0.1 0.1
0.2 0.8 1.4 2.0 2.6 1 10 100 1000
-VSD ,Source-to-Drain Voltage (V) -VDS , Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
 IRFR/U9120NPbF
8.0 RD
VDS

VGS
D.U.T.
6.0 RG -
-ID , Drain Current (A)

+ VDD

-10V
Pulse Width ≤ 1 µs
4.0 Duty Factor ≤ 0.1 %

Fig 10a. Switching Time Test Circuit

2.0
td(on) tr t d(off) tf
VGS
10%
0.0
25 50 75 100 125 150
TC , Case Temperature ( °C)
90%
VDS

Fig 9. Maximum Drain Current Vs.

Case Temperature Fig 10b. Switching Time Waveforms

10
Thermal Response (Z thJC )

D = 0.50

1
0.20

0.10
0.05
0.02 P DM
SINGLE PULSE
0.1 0.01 (THERMAL RESPONSE)
t1
t2

Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

IRFR/U9120NPbF
VDS L
250
ID

EAS , Single Pulse Avalanche Energy (mJ)

D.U.T - V TOP -1.7A
RG
V DD -2.5A
+ DD 200
IAS A BOTTOM -3.9A
-20V DRIVER
tp 0.01Ω

150

15V 100

Fig 12a. Unclamped Inductive Test Circuit

50
I AS

0
25 50 75 100 125 150
Starting TJ , Junction Temperature ( °C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current
tp
V(BR)DSS

Fig 12b. Unclamped Inductive Waveforms

Current Regulator
Same Type as D.U.T.

50KΩ
QG 12V .2µF

-10V
.3µF
-
QGS QGD D.U.T. +VDS

VGS
VG
-3mA

IG ID
Charge Current Sampling Resistors

Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit
 IRFR/U9120NPbF
Peak Diode Recovery dv/dt Test Circuit

+ Circuit Layout Considerations

D.U.T* • Low Stray Inductance
• Ground Plane
ƒ
• Low Leakage Inductance
Current Transformer
-

+
‚
„
- +
-


RG • dv/dt controlled by RG +
• ISD controlled by Duty Factor "D" VDD
-
• D.U.T. - Device Under Test
VGS

* Reverse Polarity of D.U.T for P-Channel

Driver Gate Drive

P.W.
Period D=
P.W. Period

[VGS=10V ] ***

D.U.T. ISD Waveform

Reverse
Recovery Body Diode Forward
Current Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
[VDD]
Re-Applied
Voltage Body Diode Forward Drop
Inductor Curent

Ripple ≤ 5% [ISD ]

*** VGS = 5.0V for Logic Level and 3V Drive Devices

Fig 14. For P-Channel HEXFETS

IRFR/U9120NPbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)

D-Pak (TO-252AA) Part Marking Information

EXAMPLE: THIS IS AN IRFR120
PART NUMBER
WITH ASSEMBLY INTERNATIONAL
LOT CODE 1234 RECTIFIER IRFU120 DATE CODE
ASSEMBLED ON WW 16, 1999 LOGO 916A YEAR 9 = 1999
IN THE ASSEMBLY LINE "A" 12 34 WEEK 16
LINE A
Note: "P" in assembly line position ASSEMBLY
indicates "Lead-Free" LOT CODE

OR
PART NUMBER
INTERNATIONAL
RECTIFIER IRFU120 DATE CODE
LOGO P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
12 34
YEAR 9 = 1999
ASSEMBLY WEEK 16
LOT CODE
A = ASSEMBLY SITE CODE
 IRFR/U9120NPbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

EXAMPLE: T HIS IS AN IRF U120 PART NUMBER
INT ERNAT IONAL
WIT H AS SEMBLY
RECT IF IER IRF U120 DAT E CODE
LOT CODE 5678
LOGO 919A YEAR 9 = 1999
ASS EMB LED ON WW 19, 1999
56 78 WEEK 19
IN T HE AS S EMBLY LINE "A"
LINE A
AS SEMBLY
Note: "P" in assembly line
LOT CODE
position indicates "Lead-F ree"

OR
PART NUMBER
INT ERNAT IONAL
RECT IFIER IRF U120 DAT E CODE
LOGO P = DES IGNAT ES LEAD-FREE
56 78 PRODUCT (OPT IONAL)
YEAR 9 = 1999
ASS EMB LY WEEK 19
LOT CODE A = AS SEMB LY S IT E CODE
IRFR/U9120NPbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)

TR TRR TRL

16.3 ( .641 ) 16.3 ( .641 )

15.7 ( .619 ) 15.7 ( .619 )

12.1 ( .476 ) 8.1 ( .318 )

FEED DIRECTION FEED DIRECTION
11.9 ( .469 ) 7.9 ( .312 )

NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.

Data and specifications subject to change without notice.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/