TECHNOLOGICAL UNIVERSITY OF THE PHILIPPINES-TAGUIG

CAMPUS

Bachelor of Science in Information Technology

Digital Clock

Rating: ____________

BSIT – 1B DATE:
ARBOLEDA, Jose Angelo C. April 11, 2019
LACBAYEN, Ezekiel Clyde P.
SALES, Keir M.
VELEZ, Clariz D.

___________________
MR. NESTOR R. VALDEZ
Professor
OBJECTIVES:
1. To create Digital Clock using 74LS293.

2. To design a logical circuit for the Digital Clock.

3. To construct a counter for each part of the digital clock.

4. To create a Digital Clock that has indicator if it is a.m. or p.m.

5.

MATERIALS:
 Seven-Segment Display

 Decoder (74LS47)

 74LS293 Integrated Circuit

 555 Timer

 100-ohm Capacitor

 Resistors

 Solid Wires

 LED
THEORIES AND PRINCIPLES

The 74LS293 Integrated Circuit is high-speed 4-bit ripple type

counters partitioned into two sections. Each counter has a divide-by-
two section and either a divide-by-five (LS290) or divide-by-eight
(LS293) section which are triggered by a HIGH-to-LOW transition on
the clock inputs. Each section can be used separately or tied together
(Q to CP) to form BCD, Bi-quinary, or Modulo-16 counters. Both of the
counters have a 2-input gated Master Reset (Clear), and the LS290 also
has a 2-input gated Master Set (Preset 9).

The J-K flip-flop is the most versatile of the basic flip-flops. It

has the input- following character of the clocked D flip-flop but has two
inputs, traditionally labeled J and K. If J and K are different then the
output Q takes the value of J at the next clock edge. The inputs are
labeled J and K in honor of the inventor of the device, Jack Kilby. If J
and K are both low, then no change occurs. If J and K are both high at
the clock edge, then the output will toggle from one state to the other. It
can perform the functions of the set/reset flip-flop and has the
advantage that there are no ambiguous states. It can also act as a T
flip-flop to accomplish toggling action if J and K are tied together. This
toggle application finds extensive use in binary counters.

The 74LS47 Integrated Circuit accepts four lines of BCD (8421)

input data, generates their complements internally and decodes the
data with seven AND/OR gates having open-collector outputs to drive
indicator segments directly. Each segment output is guaranteed to sink
24 mA in the ON (LOW) state and withstand 15V in the OFF (HIGH)
state with a maximum leakage current of 250 µA. Auxiliary inputs
provided blanking, lamp test and cascadable zero-suppression
functions.

The 555 Timer is a highly stable device for generating. Additional

terminals are provided for triggering or resetting if desired. In the time
delay mode of operation, the time is precisely controlled by one external
resistor and capacitor. For a stable operation as an oscillator, the free
running frequency and duty cycle are accurately controlled with two
external resistors and one capacitor. The circuit may be triggered and
reset on falling waveforms, and the output circuit can source or sink up
to 200 mA or drive TTL circuits.
DATA AND RESULTS

Seconds Section
We used JK FLIP FLOP IC (74Ls293) We use four flip flop which
give 0 to 5 outputs and remaining other 4 flip flop give 0 to 9. The circuit
will Display Successfully 5 & 9 in each seven segments display with the
help of driver IC 7447 then it gives pulse to minute section.
Minutes Section
Repeating the same circuit operation which we had previously used for
the second section. We used JK FLIP FLOP IC (74Ls293) We use four
flip flop which give 0 to 5 outputs and remaining other 4 flip flop give 0
to 9. The circuit will Display Successfully 5 & 9 in each seven segments
display with the help of driver IC 7447 then it gives pulse to minute
section.
Hours Section
Designing the circuit in such a way so that the output resets to 0 0
0automatically displaying 11.59.59. The counting proceeds with a
frequency of one pulse per hour coming from minute section. We used
J-K flip flop IC (74LS293). We know that hour would show 1&2 in each
seven segment display not great than that number. So we need 0 to 1
displays count on first segment and 0 to 2 counts on other segment. In
hour section same as previous section we used J-k Flip flop to connect
all needy component we need 0 to 1 display on single seven segment
due to prevent it from exceeding we similarly as usual used NAND gate
to clear the two flip flop which they want to show 0 to 2 count but our
requirement is to only want to display 0 to 1.
 PIN CONFIGURATION

Seven-segment Display 74LS47 Decoder

74LS293 Integrated Circuit 555 Timer

OBSERVATION

CONCLUSION