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Design and Performance analysis of CMOS

Manasa Iyer1*
1
Vidyalankar Institute Of Technology,Mumbai,
India

I. INTRODUCTION

The current trends in the enlargements and improvements in the domain of low power VLSI design does examined
in this paper. This paper focuses to expand on the modern aims in the low power design. Multi-threshold CMOS is
an efficient standby leakage control low power method. Multi-threshold logic makes use of low Vth and high
Vth MOS transistors to satisfy both low power and high-performance requirements. Minimizing supply
voltages devoid compromise of speed are mainly useful mode to diminish power consumption. To achieve
this aim, numerous low voltage circuits with low- threshold MOSFET’s, power gating and SVL has
been proposed.

A. CMOS Technique

CMOS is called as “Complementary Metal Oxide Semiconductor” [4]. CMOS technique is one of the
most well- known technique in the computer chip design industry and widely used today to compose
integrated circuits in several miscellaneous applications. CMOS technology uses of both PMOS and NMOS
transistors i.e. pull up and pull-down network that’s why it is called as complementary Metal Oxide
Semiconductor. CMOS is quite suitable technique for various components such as microprocessors,
microcontrollers, and memories- RAM, ROM and ASICs. A Complementary MOS circuits has negligible static
power dissipation like NMOS or BIPOLAR circuits.

Fig.1: a) CMOS b) MTCMOS basic Circuit

Most of the time, power is exhausted when switching takes place in the circuit. More number of gates can be
integrated on an IC by CMOS technology than NMOS or bipolar technology.
so lowering the power consumption. Power consumption is a critical concern in the VLSI circuits due to regular
decrease in feature size of CMOS circuits and a subsequent increase in chip density and operating frequency.

B. MTCMOS Technique

MTCMOS is called as “Multi-threshold Complementary Metal Oxide Semiconductor” [4]. Scaling the supply
voltage is an effective way to handle power dissipation. MTCMOS is a robust circuit-level technique which
gives high-performance and low-power consumption by using sleep transistors as shown in Fig.1. Basically,
these low-power techniques help in maintaining the circuit performance while reducing the sub- threshold
currents in standby mode. Power management is unavoidable especially as technology scales down, so low-
power techniques must be devised to reduce power dissipation and accurately estimate the power
consumption [5-6]. Normally, there are three sources of power dissipation in digital CMOS circuits, first is
switching activities i.e. signal transition, second comes from short circuit current and the last is due to leakage
currents. Besides, leakage power is also the critical concern. As high leakage current is also transformed into an
important contributor to power dissipation of CMOS circuits. Basically, MTCMOS is the low power technique i.e. is
used to minimize power consumption. To reduce the power dissipation in CMOS circuit, numerous sources must be
identified. Standby currents, an important cause of power dissipation can be reduced by using CMOS and
MTCMOS technique. It can be used to improve speed at low supply voltage and low power consumption. More
power consumption in VLSI circuits requires more costly packaging and cooling technologies that enhance the
cost and decrease system reliability. This is one of the main reasons for low power cell design. The most important
reason for low power research and design is our convergence to a mobile society for that we require long battery life
and this can be done by using low power cells.

C. Power gating technique

Transistor based power gating is a technique used to reduce power consumption in integrated circuit. This
technique uses the sleep transistors which work as a headers and footers is shown in fig 2. In this technique
when numerous power areas or an independent modifiable voltage regulator is used, Headers find their applications
in most commercial designs as they are easy to design and analyze. On the other hand, less number of footers is
needed due to their high n-type mobility, thus making them more area efficient. Leakage problem in header is
slightly reduced during standby mode. The width of the headers act as controlling factors, which is responsible for
leakage reduction and increasing delay on power network.

Fig.2: a) Power gating b) SVL Basic Circuit


Due to large variations in the size of header, the leakage power during active mode is reduced but not increased
during large ideal mode remaining leakage power encourages energy consumption. The additional
capability of power getting technique is to enable Iddq testing which enhances the testing speed in CMOS
circuits. The selected ideal period can be controlled by Temporal Granularity and the number of distinct power
gating regions is controlled by Regional Granularity. The most granular approach can be achieved by an
independent modifiable regulator. On chip leakage will be completely removed by switching off the voltage
regulator. But it achieves high granularity in both ways. First, the distinct power supply pins will be required by
every power gated area. Second, the high capacitance of switched power network would consume considerable
amount of energy and time to energize. As compared to coarse-grained approach, the fine-grained
approach is achieved by advanced low-power microprocessors.

II. Functional Description Of CMOS

A. Technical Details

"CMOS" refers to both a particular style of digital circuitry design and the family of processes used to implement
that circuitry on integrated circuits (chips). CMOS circuitry dissipates less power than logic families with resistive
loads. Since this advantage has increased and grown more important, CMOS processes and variants have come to
dominate, thus the vast majority of modern integrated circuit manufacturing is on CMOS processes. [5] As of 2010,
CPUs with the best performance per watt each year have been CMOS static logicsince 1976
CMOS circuits use a combination of p-type and n-type metal–oxide–semiconductor field-effect
transistor (MOSFETs) to implement logic gates and other digital circuits. Although CMOS logic can be
implemented with discrete devices for demonstrations, commercial CMOS products are integrated circuits
composed of up to billions of transistors of both types, on a rectangular piece of silicon of between 10 and
400 mm2.
CMOS always uses all enhancement-mode MOSFETs (in other words, a zero gate-to-source voltage turns the
transistor off).

B Inversion

CMOS circuits are constructed in such a way that all P-type metal-oxide-semiconductor (PMOS) transistors must
have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must
have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates
low resistancebetween its source and drain contacts when a low gate voltage is applied and high resistance when a
high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance
between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied.
CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both
gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET
not to conduct, while a low voltage on the gates causes the reverse. This arrangement greatly reduces power
consumption and heat generation. However, during the switching time, both MOSFETs conduct
briefly as the gate voltage goes from one state to another. This induces a brief spike in power
consumption and becomes a serious issue at high frequencies.
The adjacent image shows what happens when an input is connected to both a PMOS transistor (top of diagram) and
an NMOS transistor (bottom of diagram). When the voltage of input A is low, the NMOS transistor's channel is in a
high resistance state. This limits the current that can flow from Q to ground. The PMOS transistor's channel is in a
low resistance state and much more current can flow from the supply to the output. Because the resistance between
the supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current drawn from Q is
small. The output, therefore, registers a high voltage.
On the other hand, when the voltage of input A is high, the PMOS transistor is in an OFF (high resistance) state so it
would limit the current flowing from the positive supply to the output, while the NMOS transistor is in an ON (low
resistance) state, allowing the output from drain to ground. Because the resistance between Q and ground is low, the
voltage drop due to a current drawn into Q placing Q above ground is small. This low drop results in the output
registering a low voltage.
In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the
output is high, and when the input is high, the output is low. Because of this behavior of input and output, the CMOS
circuit's output is the inverse of the input.

C. Power supply pins


The power supply pins for CMOS are called VDD and VSS, or VCC and Ground(GND) depending on the
manufacturer. VDD and VSS are carryovers from conventional MOS circuits and stand for
the drain and source supplies.[6] These do not apply directly to CMOS, since both supplies are really
source supplies. VCC and Ground are carryovers from TTL logicand that nomenclature has been
retained with the introduction of the 54C/74C line of CMOS.

D. Logic

More complex logic functions such as those involving AND and OR


gates require manipulating the paths between gates to represent the logic.
When a path consists of two transistors in series, both transistors must have low resistance to the corresponding
supply voltage, modelling an AND. When a path consists of two transistors in parallel, either one or both of the
transistors must have low resistance to connect the supply voltage to the output, modelling an OR.
Shown on the right is a circuit diagram of a NAND gate in CMOS logic. If both of the A and B inputs are high, then
both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will
conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low. If
both of the A and B inputs are low, then neither of the NMOS transistors will conduct, while both of the PMOS
transistors will conduct, establishing a conductive path between the output and Vdd (voltage source), bringing the
output high. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS
transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the
output high. As the only configuration of the two inputs that results in a low output is when both are high, this circuit
implements a NAND (NOT AND) logic gate.
An advantage of CMOS over NMOS logic is that both low-to-high and high-to-low output transitions are fast since
the (PMOS) pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In
addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly
symmetric response also makes CMOS more resistant to noise.

D. Power Switching and Leakage


CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when
switching ("dynamic power"). On a typical ASIC in a modern 90 nanometer process, switching the output might
take 120 picoseconds, and happens once every ten nanoseconds. NMOS logic dissipates power whenever the
transistor is on, because there is a current path from Vdd to Vss through the load resistor and the n-type network.
Static CMOS gates are very power efficient because they dissipate nearly zero power when idle. Earlier, the power
consumption of CMOS devices was not the major concern while designing chips. Factors like speed and area
dominated the design parameters. As the CMOS technology moved below sub-micron levels the power
consumption per unit area of the chip has risen tremendously.
Broadly classifying, power dissipation in CMOS circuits occurs because of two components, static and dynamic:
III. Advantages of CMOS over BJT

BJT CMOS

 Higher switching speed  It offers high noise margins.


 It offers high current drive per unit area and high gain  It has low static power dissipation compare to other
technologies.
 Generally better noise performance and better high
frequency characteristics  It offers high packing density
 It has better analogue capability compare to others.  It offers high yield along with large integrated complex
functions.
 Improved I/O speed.
 It has low manufacturing cost per device.
 It offers high power dissipation.
 Scalable threshold voltage
 Lower input impedance (high drive current)
 It has High input impedance and low drive current.
 Low packing density.
 It offers higher delay sensitivity to load (i.e. it has fan out
 Low voltage swing logic. limitation.)
 It offers lower delay sensitivity to load.  It has lower trans-conductance, here trans-conductance gm
 High gm (gm α Vin) α Vin

 It offers high unity gain bandwidth at low current  It has lower output drive current (This will have issue while
 They are basically unidirectional devices. driving higher capacitive loads)
 A near ideal switching device
 Bi-directional capability (drain & source are
interchangeable)

III. Fabrication Of CMOS

Simplified process of fabrication of a CMOS inverter on p-type substrate in semiconductor microfabrication.


Note: Gate, source and drain contacts are not normally in the same plane in real devices, and the diagram is
not to scale.
IV. Applications
CMOS transistors are used for all high density transistor applications such as microprocessors that we
find in our home computers and smartphones.
V. References

1. COS-MOS was an RCA trademark, which forced other manufacturers to find another name – CMOS
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March 2013.

3. ^ Fairchild. Application Note 77. "CMOS, the Ideal Logic Family" Archived 2015-01-09 at the Wayback
Machine. 1983.

4. ^ "Intel® Architecture Leads the Microarchitecture Innovation Field". Intel. Archivedfrom the original on
29 June 2011. Retrieved 2 May 2018.

5. ^ Baker, R. Jacob (2008). CMOS: circuit design, layout, and simulation (Second ed.). Wiley-IEEE.
p. xxix. ISBN 978-0-470-22941-5.

6. ^ "Archived copy" (PDF). Archived (PDF) from the original on 2011-12-09. Retrieved 2011-11-25.

7. ^ K. Moiseev, A. Kolodny and S. Wimer, "Timing-aware power-optimal ordering of signals", ACM


Transactions on Design Automation of Electronic Systems, Volume 13 Issue 4, September 2008, ACM

8. ^ A good overview of leakage and reduction methods are explained in the book Leakage in Nanometer
CMOS Technologies Archived 2011-12-02 at the Wayback Machine ISBN 0-387-25737-3.

9. ^ Edwards C, "Temperature control", Engineering & Technology 26 July – 8 August 2008, IET

10. ^ Patrick Moorhead (January 15, 2009). "Breaking Records with Dragons and Helium in the Las Vegas
Desert". blogs.amd.com/patmoorhead. Archived from the original on September 15, 2010. Retrieved 2009-
09-18.

11. ^ Prati, E.; De Michielis, M.; Belli, M.; Cocco, S.; Fanciulli, M.; Kotekar-Patil, D.; Ruoff, M.; Kern, D. P.;
Wharam, D. A.; Verduijn, J.; Tettamanzi, G. C.; Rogge, S.; Roche, B.; Wacquez, R.; Jehl, X.; Vinet, M.;
Sanquer, M. (2012). "Few electron limit of n-type metal oxide semiconductor single electron
transistors" (PDF). Nanotechnology. 23 (21):
215204. arXiv:1203.4811. Bibcode:2012Nanot..23u5204P. doi:10.1088/0957-4484/23/21/215204. PMID
22552118. Archived (PDF) from the original on 2014-10-04.