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PART
Introduction
There is no doubt that the microcomputer revolution will continue into the future
and many will be required to specify and integrate microprocessors into products or systems
Interfaces are the last items to be seriously considered in the race of new
technology, and it deals with the systematic study of microprocessor interfaces and their
applications in many diversified fields. In this subject students learn how to interface
history. Since the introduction of the first microcomputer chip in 1971, there have been
four generations of microprocessors, and the number of devices per chip has increased by a
factor of 2000, the clock frequency by a factor of 1000, and the overall throughput of the
capabilities are forcing changes in development systems and the ways in which they develop
microcode instructions. Also, all μP architectures are not created equal when it comes to
providing designers with the tools they need for effective systems resource management.
Therefore, well designed flexible interfaces will be required to ensure compatibility and
Definitions:
Microprocessor - The central unit of a microcomputer that contains logical elements for
manipulating data and performing arithmetic or logical operations. A single chip may contain
RAM, ROM, and PROM memories, clocks, and interfaces for memory and I/O device.
Microprogramming- A method for controlling the operation of the CPU in which each
units under integrated control. Although this definition may be correct, it is not complete
There are other important features that include both hardware and software. A
multiprocessor will be defined as a system with: a) two , or more processing units, b)shared
Interface Definitions
Interface -A shared boundary between system elements defined by common physical
signals.
Interface Device -A device that meets the interface specifications on one side of an
interface. The term is usually applied to a device through which a system or equipment
equipment and data processing terminal equipment. Has been generally accepted by most
Direct memory access -A technique that permits a peripheral device to enter or extract
blocks of data from the memory without involving the central processing unit. In some
cases, the CPU can perform other functions while the data transfers occur.
Components of Interface
signals. Interfacing of two IDs require the following components. Processing the interfacing
signals normally based on the type of devices that are used. Most of the time if the IDs are
computer terminals RS-232 standard is used. RS-232 standard uses a totally different
signal representation. This uses high positive voltage for binary ‘0’ and high negative voltage
for binary ‘1’. These signals are called as standard CMOS signals. But most of the other
motherboard signals and interfacing circuit signals use TTL signals. So it is mandatory to
make use of a CMOS to TTL converter at these interfaces. Also based on the type of
devices to be interfaced, various ADC and DAC devices are required. Some of the complex
interfaces need to be controlled by stored program circuits. This makes use of EPROM
The interfacing devices should make use of standard data transfer schemes for the
efficient exchange of data. Following discussion will give the detailed analysis on the
The data transfer schemes refers to the method of data transfer between the
processor and peripheral devices. In a typical microcomputer, data transfer takes place
between any two devices: microprocessor and memory; microprocessor and I/O devices;
memory and I/O devices. For effective data transfer between these devices, the timing
parameters of the devices should be matched. But most of the devices have incompatible
timings.
For example, an I/O device may be slower than the processor due to which, it cannot send
The semiconductor memories are available with compatible timings. Moreover, slow
memories can be interfaced using additional hardware to introduce wait states in machine
cycles. The microprocessor system designer often face difficulties while interfacing I/O
devices & magnetic memories (like floppy or hard disk) to achieve effective data transfer to
or from microprocessor. Several data transfer schemes have been developed to solve the
The data transfer schemes have been broadly classified into the following two categories.
In programmed data transfer, a memory resident routine (subroutine) requests the device
Programmed data transfer scheme is used when a relatively small amount data are to
be transferred. In these schemes, usually one byte or word of data is transferred at a time.
Examples of devices using parallel data transfer are ADC,DAC, Hex-keyboard, 7-segment
LED's, etc.
The programmed data transfer scheme can be further classified into the following
three types.
In DMA data transfer, the processor is forced to hold state by an I/O device until the data
The processor does not execute any instructions during the hold period. The DMA data
transfer is used for large block of data transfer between I/O device and memory. Typical
examples of devices using DMA are CRT controller, floppy disk, hard disk, high speed line
printer, etc.
The fig below shows the various types of data transfer schemes.
All the data transfer schemes discussed above requires both software and hardware for
their implementation. Within a microcomputer, more than one scheme can be used for
interfacing different I/O devices. However, some of these schemes require specific
In this scheme, the transfer of data is completely under the control of the
microprocessor program. i.e an i/o operation takes place only when an i/o instruction is
Synchronous transfers mean transfers occurring at the same time. The sender and
the receiver are synchronized to operate at the same clock speed. This is preferred when
the speeds of both the sender and the receiver match. Synchronous transfers are used in
high-speed transmission.
Data transfers between the microprocessor and the peripherals are primarily
asynchronous.
Program controlled data transfers can take place under several conditions. They
are:-
Polling: The microprocessor is kept in a loop to check whether data are available. The
KYCLO loop in the matrix keyboard program is an example of polling the input device for
data availability.
program, & branches to service the interrupt. After completing the I/O transfer, the
microprocessor returns to the main program and continues. This scheme eliminates the need
for the microprocessor to wait in a loop until the device gets ready and hence is more
efficient.
With ready signal: When peripheral response time is slower than the microprocessor
execution time, READY signal is used. The microprocessor samples this signal during T2 of
every Read/ writes machine cycle. If it is high, The I/O device is ready and the
microprocessor goes ahead with transfer. If READY is low, it means that the peripheral is
not ready and additional T –states will be inserted in the, execution cycle by external
hardware. These T -states are called WAIT states. They prolong the instruction execution;
With handshake Signals: Handshake signals are signals exchanged prior to data transfer.
Their purpose is ensure readiness of the peripheral and to synchronize timing of data
transfer For example the IBF, STB, OBF signals in mode 1 operation of 8255 - A are
handshake signals. These are called STATUS CHECK signals. INTR is an interrupt signal,
8255 -A generates in response to .STB, and IBF. This can be used to interrupt the
In this scheme the processor does not check the readiness of the device. The I/O device or
peripheral should have matched timing parameters. Whenever data is to be obtained from
the device or transferred to the device, the user program can issue a suitable instruction
At the end of the execution of this instruction, the transfer would have been
completed.
The synchronous data transfer scheme can also be implemented with small delay (if the
The sequence of operations for synchronous data transfer scheme is shown in figure below.
The mode-O input or output in 8155 or 8255 is an example of synchronous data transfer.
In this scheme the processor ends a request to the device for read/write operation.
Then the processor keeps on polling the status of the device. Once the device is ready, the
processor executes a data transfer instruction to complete the process. To implement this
scheme, the device should provide a signal which may be tested by the processor to
The sequence of operations for asynchronous data transfer is shown in the figure
below. The handshake data transfer without interrupt (mode-l and mode-2) of8155 or 8255
Fig (a): Synchronous Data Transfer Scheme (b): Asynchronous Data Transfer Scheme
for effectively utilizing the processor time. In this scheme, the processor first initiates
the I/O device for data transfer. After initiating the device, the processor will continue
the execution of instructions in the program. Also at the end of an instruction the
processor will check for a valid interrupt signal. If there is no interrupt then the processor
interrupt sigt1al the processor will complete the current instruction execution and saves
the processor status in stack. Then the processor call an interrupt service routine (ISR) to
service the interrupted device. At the end of ISR the processor status is retrieved from
stack and the processor starts executing its main program. The sequence of operations for
Fig (a) Main Program Execution Sequence Fig (b): ISR Execution Sequence
In polled and status check I/O, the microprocessor is kept in a loop to check for
data availability at the I/O Port. This scheme is inefficient because the microprocessor is
unnecessarily tied up in a loop. Instead, it is more efficient to let the microprocessor carry
on with its main job of executing programs without having concern for the I/O device
readiness, and let the I/O device send a signal o the microprocessor as and when it gets
On receiving the interrupt signal, the microprocessor takes the following sequence
of steps to process the requirement of the VO device, which sent the signal.
routine and at the end, retrieves the status of the main program and the
return address from the stack and returns to the point in the main
In programmed data transfer, a memory resident routine requests the device for
In DMA transfer, the microprocessor is forced to hold on by an I/O device until the
Programmed data are used when relatively small amounts of data are transferred using
relatively slow I/O devices such AID, D/A converters, and peripheral floating point
arithmetic unit.
generally employed for transferring data between the microprocessor and peripheral mass
Programmed transfer schemes are further classified into synchronous, asynchronous and
interrupt driven transfers. All these schemes require both hardware and software for their
implementation.
8085
The 8085 has FIVE pins on the chip for implementing the interrupt process. The pin
numbers and the names of these interrupt signals are given below.
PIN NO Name
6 TRAP
7 RST 7.5
8 RST 6.5
9 RST 5.5
10 INTR.
On these five lines, 8085 can receive signals from the peripheral devices, requesting
the microprocessor to attend to data transfers from them or send data to them. These are
called HARDWARE INTERRUPTS. Pin No 11 on the chip is an active low signal, sent by the
In addition 8085 has an internal flip-flop called INTERRUPT ENABLE flip flop, This
should be set, in order for the ~p to be interrupted. 8085 has the following instructions the
-This sets the IE flip -flop and enables the interrupt process.
-This resets the IE flip -flop and disables the interrupt process.
-It should be included in a program segment where an interrupt from an external source can
nut be tolerated.
These Interrupts are called VECTORED INTERRUPTS. What it means is that each of the
interrupts except INTR is associated with a branch address on page OOH in ROM. On
respective location.
In case of INTR, the lNTA signal issued in response to the signal on INTR lines is used to
insert a RST instruction lone byte CALL) on the data bus. The branch addresses is
I/O devices can interrupt the ~p on any of the 5 pins. The nature of the interrupt
SIM : Set Interrupt Mask. This is a 1 -byte instruction, used to mask or unmask the
interrupts RST 7.5, 6.5 & 5.5. To use this instruction, the accumulator is to be loaded with a
data byte whose bits have the purposes shown in figure below
D7 D6 D5 D4 D3 D2 D1 D0
MSE Mask set enable: IfO, bits Do, Dl, D2 are ignored;
This is also 1 -byte instruction; this instruction is used to identify finding interrupts, when
multiple devices interrupt the processor. When this instruction is written in a program and
is executed by the microprocessor, the accumulator is loaded with a byte, whose bits
Example Problems:
1. Design data transfer scheme using Interrupts which will enable the data transfer of
a block of data from memory locations 2045H - 2056H to the memory locations
starting at 2091H. ( Block Transfer). This has to implemented thorough the RST 7.5
interrupts.
system.
T1 Pressure Transducer
T2 Temperature Transducer
T3 Humidity Transducer
Assume that the driver circuit and instrumentation amplifier circuits are available
for processing the transducers signals. All these transducers have to be connected
Each instrumentation amplifier circuits output is connected to RST 7.5, RST 6.5
Design the program in such a way that the M1 has to be switched ON for 5 Seconds
Else if
Else if
After serving a request the program has to search for the pending interrupts.
3. Design an interfacing scheme to interface a eight LED display to the out put port of
the 8255 port A. The LEDs has to be switched ON alternately if the RST 7.5 is
activated, else if RST 6.5 is activated All LEDs should be switched ON and it the
RST 5.5 is activated the LEDs should read AAH. After serving a request the
8086
Broadly, there are two types of interrupts. The first out of them is external
interrupt and the second is internal interrupt. In external interrupt, an external device or a
signal interrupts the processor from outside or, in other words, the interrupt is generated
outside the processor, for example, a Keyboard Interrupt. The Internal Interrupt, on the
interrupt instruction. The examples of this type are divide by zero interrupt, overflow
Suppose an external device interrupts the CPU at the interrupt pin, either NMI or
INTR of 8086, while the CPU is executing an instruction of a program. The CPU first
completes the execution of the current instruction. The IP is then incremented to point to
the next instruction. The CPU then acknowledges the requesting device on its INTA pin
CPU checks the IF flag. If the IF is set, the interrupt request is acknowledged using the
OOA pin. If the IF is not set, the interrupt requests are ignored. Note that the responses
to the NMI, TRAP and Divide-by-Zero interrupt requests are independent of the IF flag.
After an interrupt is acknowledged, the CPU computes the vector address from the type of
the interrupt that may be passed to the interrupt structure of the CPU internally (in case
of software interrupts, NMI, TRAP and Divide by Zero interrupts) or externally, i.e. from
an interrupt controller in case of external interrupts. (The contents of IP and CS are next
pushed to the stack. The contents of IP and CS now point to the address of the next
instruction of the main program from which the execution is to be continued after
executing the ISR. The PSW is also pushed to the stack). The interrupt flag (IF) is cleared.
The TF is also cleared, after every response to the single step interrupt. The control is
then transferred to the interrupt service routine for serving the interrupting device. The
new address of ISR is found out from the interrupt vector table. The execution of the ISR
starts. If further interrupts are to be responded to during the time the first interrupt is
being serviced, the IF should again be set to 1 by the ISR of the first interrupt. If the
interrupt flag is not set, the subsequent interrupt signals will not be acknowledged by the
processor, till the current one is completed. The programmable interrupt controller is used
for managing such multiple interrupts based on their priorities. At the end of ISR the last
instruction should be IRET. When the CPU executes IRET , the contents of flags, IP and CS
which were saved at the start by the CALL instruction are now retrieved to the respective
registers. The execution continues onwards from this address, received by IP and CS.
At the end of each instruction cycle. the 8086 checks to see if any interrupts have
been requested. If an interrupt has been requested, the 8086 responds to the interrupt by
It decrements the stack pointer by 2 and pushes the flag register on the stack.
It disables the 8086 INTR interrupt input by clearing the interrupt flag (IF) in the
flag register.
It decrements the stack pointer by 2 and pushes the current code segment register
It decrements the stack pointer again by 2 and pushes the current instruction
It does an indirect far jump to the start of the procedure you wrote to respond to
the Interrupt.
Following figure summarizes these steps in diagram form. As you can see, the 8086
pushes the flag register on the stack disables the INTR input and the single-step function,
and does essentially an indirect far call to the interrupt service procedure. An IRET
instruction at the end of the interrupt service procedure returns execution to the main
program.
We now discuss about how the 8086/88 finds out the address of an ISR. Every
external and internal interrupt is assigned with a type (N), that is either implicit (in case of
NMI, TRAP and divide by zero) or specified in the instruction INT N (in case of internal
external hardware like programmable interrupt controller. In the zeroth segment of physical
address space, i.e. CS = 0000, Intel has reserved 1024 locations for storing the interrupt
vector table. The 8086 supports a total of256 types of the interrupts, i.e. from 00 to FFH.
Each interrupt requires 4 bytes, i.e. two bytes each for IP and CS of its ISR. Thus a total
of 1024 bytes are required for 256 interrupt types, hence the interrupt vector table starts
at location 0000:0000 and ends at 0000:03FFH. The interrupt vector table contains the IP
and CS of all the interrupt types stored sequentially from address 0000:0000 to 0000 :
03FF H. The interrupt type N is multiplied by 4 and the hexadecimal multiplication obtained
gives the offset address in the zeroeth code segment at which the IP and CS addresses of
the interrupt service routine (lSR) are stored. The execution automatically starts from the
new CS:IP.
The processor 8086/88 has a non-maskable interrupt input pin (NMI) that has the
highest priority among the external interrupts. TRAP (Single Step-Type 1) is an intern al
interrupt having the highest priority amongst all the interrupts except the Divide By Zero
(Type 0) exception. The NMI is activated on a positive transition (low to high voltage). The
assertion of the NMI interrupt is equivalent to an execution of instruction INT 02, i.e.
The NMI pin should remain high for at least two clock cycles and is no need to be
synchronized with the clock for being sensed. When NMI is activated, the current
instruction being executed is completed, and then the NMI is served. In case of string type
instructions, this interrupt will be served only after the complete string has been
manipulated.
Another high going edge on the NMI pin of 8086, during the period, in which the
first NMI is served, triggers another response. The signal on the NMI pin must be free of
The processor 8086/88 also provides a pin INTR, that has lower priority as
compared to NMI. Further the priorities, within the INTR types are decided by the type of
the INTR signal, that is to be passed to the processor via data bus by some external device
like the programmable interrupt controller. The INTR signal is level triggered and can be
masked by resetting the interrupt flag. It is internally synchronized with the high transition
of CLK. For the INTR signal, to be responded to in the next instruction cycle, it must go
high in the last clock cycle of the current instruction or before that. The INTR requests
appearing after the last clock cycle of the current instruction will be responded to after
the execution of the next instruction. The status of the pending interrupts is checked at
If the IF is reset, the processor will not serve any interrupt appearing at this pin. If the IF
is set, the processor is ready to respond to any INTR interrupt. Once the processor
responds to an INTR signal, the IF is automatically reset. If one wants the processor to
further respond to any type of INTR signal, the IF should again be set.