Lecture Schedule 2007

Date Time Place Topic

wed 29.8.2007 14-16 TB104 Course info, Overview of digital design (Chapt. 1,3)
Combinatorial Systems – Specification, description
tue 4.9.2007 12-14 TB109
and analysis (Chapt. 2,4)
Combinatorial Systems – Design (Chapt.. 5,6)
wed 5.9.2007 14-16 TB104
EDA Tools demonstration
tue 11.9.2007 12-14 TB109 Sequential Systems –Specification (Chapt. 7)
Sequential Systems – Specification continued
wed 12.9.2007 14-16 TB104
Sequential Systems – Design (Chapt. 8)
tue 18.9.2007 12-14 TB109 State Machine Design (Extra material)
wed 19.9.2007 14-16 TB104 Sequential Systems – Modules (Chapt. 11)
wed 26.9.2007 14-16 TB104 Combinatorial Systems – Modules (Chapt. 9)
wed 3.10.2007 14-16 TB104 Arithmetic Modules (Chapt. 10)
wed 10.10.2007 - - No lectures
Register Transfer Level, Data and control
wed 17.10.2007 14-16 TB104
subsystems (Chapt. 13,14)
wed 24.10.2007 14-16 K1702 Programmable logic (Chapt. 5.7, 12)
1
wed 31.10.2007
12.9.2007 12:07
14-16 TB104 Review
Sequential Systems
Implementation of Sequential Networks
Timing Constraints
 Outline
 Implementation of sequential systems
 State transition timing
 State register implementation and timing
 Sequential network timing
 System clock speed

3 12.9.2007 12:07
 Implementation of Sequential
Systems
 Sequential networks implement sequential systems
 General term for all kinds of sequential systems
 Just like combinational networks implement combinational
systems
 Most often implementations are for state machines
 Only synchronous implementations are considered
 Requires clocked components in the implementation
 State changes are related to clock signal

 Canonical sequential network is general

implementation model

4 12.9.2007 12:07
 Canonical Sequential Network
 State register stores the current state
 Combinational network performs functions G and H
s(t+1) = G(s(t);x(t))
z(t) = H(s(t);x(t))
 Initializing initialize
next
Combi national
sets s(0) state

State Register
s(t+1) present
s(t) state
present Network
input
x(t)
CLK present
z(t) output
5 12.9.2007 12:07
 Mealey State Machine
 Mealey state machine can be implemented as
canonical sequential network

State Register
s(t+1)
C1
x(t) s(t) z(t)
C2

state transition function G CLK

output function H
6 12.9.2007 12:07
 Moore State Machine
 Note that output function is not dependent on input
 Output function might be omitted (if state register
output = output)

State Register
s(t+1) z(t)
C1 C2
x(t) s(t)

CLK
state transition function G output function H
7 12.9.2007 12:07
 State Machine with Binary
Variables
 To simplify functions, denote s(t+1) = Y, s(t)=y

Initialize

Combinational Network
x0 z0
Inputs Outputs
x m-1 z n-1
Y0 y
0

Y1 y
1
State Register
y (binary cells)
Y k-1 k-1

Next state Present state

variables Yi Next state variables yi
8 12.9.2007 12:07 Present state CLK
 Example FSM Binary Specification
 Specification Input: x(t)=(x1;x 0); xi 2f0;1g
Output: z(t)2f0;1g
State: y(t)=(y3;y 2;y 1;y 0); yi(t)2f0;1g
Initial state: y(0)=(0;0;0;0)
 State transition and output functions are given for each
state vector element as function of input and current
state vector elements
0 Present state
Y3 = y2x1x0 variables yi
Next state 0
variables Yi Y2 = (y1 y2)x0 y3x1
Y1 = (y0 y3)x01x0 (y0 y1)x1 Input
Y = (y y )x0 y x0 x y x variables xi
0 0 3 0 1 1 0 2 1
z = y3 y2 y1 y0
9 12.9.2007 12:07
Mealey or Moore?
 Example FSM Implementation

x0
Initialize
Combinational
x1
Y0 y
Network
0
Y1 y z
1
Y2 y
2
Y3 y
3

CLK

10 12.9.2007 12:07
 Most Known Problems Part 1
 What is the whole
system output?
Initialize
 What is the output of

Combinational Network
x0 z0
the state register?
z n-1
 What is the input of the x m-1 Y0 y
0
whole system
Y1 y
 What is the input of 1

combinational network y
inside? Y k-1 k-1

 What is the input to

state register?
CLK
 What internal signal
affects to the next state
and what to the output?
11 12.9.2007 12:14
State Transition Timing
 Timing
 State changes (ideally) at clock pulse

Ideal clock pulse

PRESENT NEXT
STATE STATE
s(t) s(t+1)
t

Ideal t
clock 0 1 2 3 4 5 6 7
13 12.9.2007 12:15
 Ideal Timing (Mealey)
PS x(t)=a x(t)=b Notes:
1. All signals including
even even,1 odd,0 input changes sharply
odd odd,0 even,1 at clock edge
NS; z(t)

 Example ideal timing

Input b b
State EVEN ODD
Output 1 0
Clock
Present state Next state
14 12.9.2007 12:15
 Real Timing (Mealey)
Notes:
PS x(t)=a x(t)=b 1. Delays depend on
even even,1 odd,0 combinatorial networks and
odd odd,0 even,1 state register delays
NS; z(t) 2. Output depends on state and
input
3. If input changes during clock
 Example real timing period, also output changes

Input b b
State EVEN ODD
Output 1 0
Clock
Present state Next state
15 12.9.2007 12:15
 Input Effect on Output (Mealey)
 Current output depends on current state and current
input –even if input changes during the clock cycle
 Moore is more robust in this sense!

Input a b a b
State EVEN ODD
Output 1 0 1 0
Clock
Present state Next state

16 12.9.2007 12:15
 Real Timing (Moore)
PS x(t)=a x(t)=b Notes:
1. Output follows only
even even odd 1 state (with a delay)
odd odd even 0 2. Input changes during
NS z(t) clock period does not
affect output
 Example real timing

Input b b
State EVEN ODD
Output 1 0
Clock
Present state Next state
17 12.9.2007 12:16
 What is the Input at Clock Edge?
 The input present at the input just before the edge
always dictates the next state
 Always assume real timing model, even if the input is
drawn as ideally changing sharply at clock edge!

a b

Input a b
State EVEN ODD
Output 1 0
Clock
18 12.9.2007 12:17
State Register
Implementation and
Timing
 Implementation of State Register
 Any clocked component can be used in principle
 Gated latch (level sensitive cell)
 Edge triggered cell (rising or falling edge)
 Flip Flops (edge sensitive)

 Canonical network uses D-flip flops

 Also called binary cell in textbook

 Set of D-FFs form binary state register

 In practice, use only D-FFs

20 12.9.2007 12:17
 Timing Basics: Clock
 Clock has finite duration – pulse width defined as signal
being ”1”
 Pulse width should not be smaller than required by
system components
 Duty cycle is the ratio between 1 and 0 durations within
clock period

CLK

tw Clock pulse width

Clock period T
time
21 12.9.2007 12:18
 Level-Sensitive Cells
 Example: gated latch D
0
Q(t+t p)=D(t) E(t) Q(t)E (t)
Q
 tp is propagation delay
 Level sensitive: E
when E=1 then Q=D and latches when E=0
follow input latch
E

22
tp tp
12.9.2007 12:18
 Edge-triggering Cell: D-Flip Flop
 Specification (note: state is same as output)
Inputs : d (t ) {0,1}
PR {0,1} D (t)
PS=Q(t)
CLR {0,1} 0 1
0 0 1
CLK {0,1}
1 0 1
Outputs : Q(t ) {0,1} NS=Q(t+1)
Q (t ) {0,1}
Function : Q(t 1) D(t )
Q(t ) 0, if CLR 1 (asynchronous reset)
Q(t ) 1, if PR 1 (asynchronous set)
23 12.9.2007 12:18
 D-Flip Flop Block and State Diagram
PR (preset)
INPUT D(t) D Q Q(t)
OUTPUTS
CLK
Q’ Q’(t) (optional)

CLR (clear)
1

0 Q=0 Q=1 1

0
24 12.9.2007 12:18
 D-Flip Flop Timing Input
D
CLK input inverted in State
 Input must be FF symbol = falling Q
stable: edge triggered! CLK
 Before edge –
setup time
CLK tw
 After edge –
hold time
 Pulse width has tsu th
minimum set-up time hold time
duration
 Propagation Input
delay is the time
from clock
edge to change State
in output
propagation delay
25 12.9.2007 12:19
tp
 Physical Characteristics of D-FF
 Propagation delays depend on the output loading L
 Note minimum clock pulse width, setup and hold times
for proper operation

Input
Delays
factor Size
tpLH tpHL tsu th tw [std. [equiv.
[ns] [ns] [ns] [ns] [ns] loads] gates]
0:49+0:038L 0:54+0:019L 0:30 0:14 0.2 1 6

26 12.9.2007 12:19
Sequential Network
Timing
 Timing of Sequential Network
 Consider Moore state machine
 C1: combinational network for next state transition
 C2: combinational network for output function

Delay from current delay d1 y

state y to

State Register
next state Y
Y z
C1 C2
x y

Delay from input x to delay d1 x delay d2

next state Y CLK
Delay from current
28 12.9.2007 12:19
state y to output z
 Sequential Network as
Part of Larger System
 Determine what are the timing constraints for the system
 Sequential network set-up and hold times
 Propagation delay through sequential network

 What timing parameters depend on the system and what

on neighbor system parts
System S
y
delay d1

State Registe r
Y z
System A C1 C2 System B
x y

x delay d2
delay d1

CLK CLK CLK

29 12.9.2007 12:19
 Sequential Network Set-up Time
 When network input delay d1 y

State Register
should be stabilized? Y z
C1 C2
x y

delay d1 x delay d2
CLK

Clock CLK

Network input x

Register (cell) input Y

d1x tsu (cell)

tsu (net)

30 12.9.2007 12:20
txsu(net)=d1x +t su(cell)
 Sequential Network Hold Time
 How long after delay d1 y

State Register
clock edge network Y z
input should keep C1 C2
x y
stable?
delay d1 x delay d2
CLK

Clock CLK

Network input x

Register (cell) input Y

 th(cell) must be fulfilled d1x
t th(net)=th(cell)
 Worst case: d1x delay h (cell)
is zero t (net)
h
31 12.9.2007 12:21
 Sequential Network
Propagation Delay
 When the output is delay d1 y

State Register
stabilized after Y z
clock edge? C1 C2
x y

delay d1 x delay d2
CLK

Clock CLK

Cell output y

Network output z
t (cell) d2
p
tp(net)=tp(cell)+d2
t (net)
p
32 12.9.2007 12:22
 Example –Part 1
 One flip-flop forms state register of the system under
consideration
 What are input(s) and output(s)?
system under study
SET SET SET
D Q D Q D Q

U1 U3 U4 U6 U7
CLR Q CLR Q CLR Q

F1 F2 F3
U2
U5

tsu (net ) tsu ( F 2) t p (U 3) t p (U 1)

th (net ) th ( F 2)
t p (net ) t p ( F 2)
33 12.9.2007 12:23
 Example –Part 2

SET SET SET

D Q D Q D Q

U1 U3 U4 U6 U7
CLR Q CLR Q CLR Q

F1 F2 F3
U2
U5

system under study

tsu (net ) tsu ( F 3) t p (U 7) t p (U 6) t p (U 4)

th (net ) th ( F 3)
t p (net ) t p ( F 3)

34 12.9.2007 12:23
 Example –Part 3
 State register consists of FFs F1,F2 and F3
 But not drawn as in canonical networks example diagram!

SET SET SET

D Q D Q D Q

U1 U3 U4 U6 U7
CLR Q CLR Q CLR Q

F1 F2 F3
U2
U5
system under study

 Obviously
tsu (net ) tsu ( F1), th (net ) th ( F1), t p (net ) t p ( F 3)
 Should this system operate correctly if these timing
constraints are fulfilled?
 No, must also consider what is the max clock speed!
35 12.9.2007 12:24
System Clock Speed
 Maximum Clock Speed
 Minimum clock period dictates maximum clock speed
System S
y
delay d1

State Registe r
Y z
System A C1 C2 System B
x y

x delay d2
delay d1

CLK CLK CLK

 Consider timing constraints between two clock edges:
 State transition –affected by network input and internal logic
 Network output – affected by state transition and internal logic
 Constraints that neighbor systems must fulfill
37 12.9.2007 12:25
 Clock & Signal System S

Delays delay d1
y

State Register
Y z
System A C1 C2 System B
x y

x delay d2
delay d1

CLK CLK CLK

Network input stabilized Next state

Clock CLK stabilized

Input x t p ( A) Margin for state transition

x
Cell input from Sys A Y t p ( A) d1 tsu
Cell input from PS Y tp d 1y tsu Cell set-up
Network output z tp d2 tsu ( B ) System B set-up
Margin for output

38 12.9.2007 12:25
 Maximum Clock Frequency –
Minimum Clock Perdiod
Clock CLK

Input x t p ( A)
x
Cell input from Sys A Y t p ( A) d1 tsu
Cell input from PS Y tp d 1y tsu Cell set-up
Network output z tp d2 tsu ( B ) System B set-up

T netin min t p ( A) d1x t su With respect to network input

T regout min tp d1y tsu With respect to register output
T netout min tp d 2 tsu ( B ) With respect to network output

 The maximum value of these is taken as the minimum clock

period
39 12.9.2007 12:27
 Example
 Operation is bounded by internal state transition logic
 Consider with respect to state register (= F1,F2, F3) output

SET SET SET

D Q D Q D Q

U1 U3 U4 U6 U7
CLR Q CLR Q CLR Q

F1 F2 F3
U2
U5

 Find longest route from FF output to input –critical path

 Here assumed that all similar parts have same delays

T regout min t p (U 7) t p (U 6) tsu ( F 3)

max[(t p (U 4) t p ( F1)),(t p (U 5) t p ( F 3))]
40 12.9.2007 12:27
 Clock Skew
 Synchronous system requires that clock arrives at the
same time to all components
 Clock skew takes place when the physical route length
from source to different destinations varies
 Causes time difference
 The higher clock speeds the worse problem

41 12.9.2007 12:28
 Example of Clock Skew
CLK Correct
 Two FF-s connected
 Skew causes x

malfunction Q1

Q1 Q2
x D Q
CLK
CLK Incorrect
FF1

delay
x
Q2
CLK* D Q z Q1
FF2 CLK*

Q2

42 12.9.2007 12:30 clock skew

 Solutions to Clock Skew
 Balanced clock trees
 Special clock signal delivery networks

 Partition the design into smaller sections each having

independent clocks
 Clock speed can be same but phase not
 First-in-First-out memories often used to interface such blocks
 GALS -Globally asynchronous locally synchronous method

 Student exercises: do not worry…

 But never, never use clock signal as part of system function –
keep it only to synchronize FFs.

43 12.9.2007 12:30