DIGITAL LOGIC DESIGN

PRACTICE PROBLEMS – SEQUENTIAL CIRCUITS

1) Write the state table for a BCD (modulo-10) synchronous counter. From the state table, design the
complete sequential circuit using J-K flip-flops.

2) Construct a 4-bit Johnson counter. List the eight unused states of the counter. Determine the next state
for each of these states, and show that if the counter finds itself in an invalid state, it does not recover to
a valid state. How will you modify the circuit to avoid this problem?

3) Design a 3-bit counter which counts in the sequence: 001, 011, 010, 110, 111, 101, 100, (repeat) 001, . . .
(a) Use J-K flip-flops (b) Use D flip-flops.

4) A sequential circuit has one input (X) and one output (Z). The circuit examines groups of four consecutive
inputs and produces an output Z = 1 if the input sequence 0101 or 1001 occurs. The circuit resets after
every four inputs. Find the Mealy state diagram.

5) Design the sequential circuit specified by the state diagram below using T-flip-flops.

6) Design a 3-bit synchronous binary counter with a control signal C. When C = 0, the counter has to count
up by ones in a normal fashion and when C = 1, the counter has to count by twos. When C changes to one,
if the counter is at an odd number, the counter will count in odd numbers. Similarly when C changes to
one, if it been at an even number, it would then count in even numbers. In either case, when C returns to
zero, it will resume counting by ones from the current value. Implement your design using J-K flip-flops.

7) Design a sequential circuit that will detect a serial input sequence of 10110. The detection of the required
bit pattern can occur in a longer data string and the correct pattern can overlap with another pattern.
When the input pattern has been detected, it causes an output Z to be asserted to high. The circuit
should not take more than 3 flip flops.
8) A new clocked X-Y flip flop is defined with two inputs, X and Y in addition to the clock input. The flip flop
functions as follows.
If XY=00, the flip flop changes state with each clock pulse
If XY=01, the flip flop state Q becomes ‘1’ with the next clock pulse
If XY=10, the flip flop state Q becomes ‘0’ with the next clock pulse
If XY=11, the flip flop changes state with each clock pulse
(i) Write the characteristic table and excitation table for the XY flip flop.
(ii) Draw a circuit to show how you will implement XY flip flop using JK flip flop.

9) Analyze the following sequential circuit and derive the state table and state diagram.

10) For a negative edge triggered J-K flip flop with the inputs as show in Figure below, develop the Q output
waveform relative to the clock. Assume that Q is initially LOW.