BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani

Pilani Campus
AUGS/ AGSR Division

FIRST SEMESTER 2019-20

COURSE HANDOUT
Date: 02.07.2019

In addition to part I (General Handout for all courses appended to the Time table) this portion gives further
specific details regarding the course.
Course No : CS F215/ EEE F215/ INSTR F215
Course Title : DIGITAL DESIGN
Instructor-in-Charge : S. GURUNARAYANAN
Instructor(s) : S. GURUNARAYANAN, PAWAN K. AJMERA
Tutorial/Practical Instructors:
For Tutorial Devesh Samaiya, Jahagirdar Ankush Chandrakant, Ashish Patel, Tejasvi Alladi, Pawan
K Ajmera
For Practical Poonam Poonia, Ankita Dixit , Punit Khari, Kanika, Teena Gakhar, Prateek Bindra,
Abheek Gupta, Sambhavi Shukla, Rahul Sharma
1. Course Description: This course covers the topics on logic circuits and minimization, Combinational and
sequential logic design, Programmable Logic devices, Finite state machines, Digital ICs, Arithmetic
operations and algorithms, Introduction to Computer organization, Algorithmic State Machines, RTL level
realization of Digital systems
2. Scope and Objective of the Course: The objective of the course is to impart knowledge of the basic tools
for the design of digital circuits and to provide methods and procedures suitable for a variety of digital design
applications. The course also introduces fundamental concepts of computer organization. Laboratory exercises
on Combination and Sequential logic design will be given as a part of the course.

3. Text Books:
T1: M.Moris Mano and Michael D. Ciletti “Digital Design”, PHI, 5th Edition, 2013
T2: G Raghurama. S Gurunarayanan, Sudeept Mohan, Karthik, “Laboratory Manual”, EDD notes 2007.
4. Reference Books:
R1: Donald D.Givonne, “Digital Principles and Design” TMH, 2003
R2: W. Stallings, “Computer Organization and Architecture” PHE, 10th Edition, 2015
5. Course Plan:
Module Lecture Session Reference Learning outcomes
No.
1 Digital Systems, Digital ICs 1.1; 1.9; 2.9, 10.1,2 Introduction to Digital
Systems and Characteristics of Digital
ICs.

2-4 Binary codes, K-Maps (4,5 1.7; 2.6; 3.1 to 3.8 Different forms of Representation of
variables), QM Method Digital functions, simplification
techniques

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 BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani
Pilani Campus
AUGS/ AGSR Division

5-8 Adders, Subtracters Multipliers, 4.1 - 4-7, R2 Combinational Logic, Design of

Arithmetic circuits, Multiplication
Booth Multiplier
division algorithms

9 Hardware Description 3.11 Simulation and synthesis basics using

Languages HDL

10-12 Flip-Flops & Characteristic tables, 5.1 to 5.4 Sequential Logic

Latches.

13-16 TTL, MOS Logic families and their 10.3, 10.5, 10.7 to Digital Integrated Circuits
characteristics 10.9

17-20 Comparators, Decoders, Encoders, 4.8 to 4.11 MSI Components

MUXs, DEMUXs

21 HDL for Combinational Logic 4.12 Simulation of Combinational Logic

Functions.

22-25 Analysis of clocked sequential 5.5, 5.7 Clocked Sequential Circuits

circuits, state diagram and reduction

26 HDL for Sequential Logic 5.6 Simulation of Sequential Logic

Functions.

27-29 ROM, PLA, PAL 7.1, 7.5 to 7.7 Memory and PLDs

30-32 Shift registers, Synchronous & 6.1 to 6.5 Registers & Counters
Asynchronous counters, clock skew
& Clock Jitter

33-35 Algorithmic State Machines R1. Chapter 8 Design of Digital Systems

36 Memory Hierarchy R2 Memory Organization

37-40 RTL, HDL description 8.1,8.2, 8.4 to 8.8 Modular approach for CPU Design

6. Evaluation Scheme:
Nature of component
Component Duration MM Date & Time
(Close Book/ Open Book)
Mid-Semester Test 90 Min. 80 <TEST_1> CLOSE BOOK
Comprehensive CLOSE BOOK /
180 Min 120 <TEST_C>
Examination OPEN BOOK
Assignments/Tutorials 10 Min 50 Continuous CLOSE BOOK
Practical:
Lab Session + Lab 120 Min 50 Continuous OPEN BOOK
exam

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 BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani
Pilani Campus
AUGS/ AGSR Division

(b) Practicals
S.No. Name of experiment
1. BOOLEAN FUNCTIONS IMPLEMENTATION
2. DESIGN OF ARITHMATIC CIRCUITS
3. IMPLEMENTATION OF BCD ADDER
4. LATCHES & FLIP-FLOPS
5. DECODERS, MULTIPLEXERS AND DEMULTIPLEXERS
6-7 DESIGN OF COUNTERS
8. COMPARATORS & ARITHMETIC LOGIC UNIT
9. SHIFT REGISTERS
10. DESIGN OF SEQUENCE DETECTOR

Assignments: Assignment sheets will be given in tutorial classes. There will be evaluation based on these
assignments in the tutorial classes. There will also be Simulation based assignments, which will be given as
take home assignments.

7. Chamber Consultation Hour: To be announced in class

8. Notices: All notices will be displayed on the CS and EEE notice boards
9. Make-up Policy:
10. Note (if any):

Instructor-in-charge
Course No. F215