Beruflich Dokumente
Kultur Dokumente
AIM ‐ Design and simulate RC Phase Shift Oscillator of 10kHz using Op‐Amp
and also check performance with respect to gain of the circuit
Software Used‐ Orcad
CIRCUIT DIAGRAM
Barkhausen condition for sustaining oscillations and total loop gain of this circuit
is greater than or equal to 1, this condition used to generate the sinusoidal
OUTPUT WAVEFORM
EXPERIMENT 2
AIM‐ Design and simulate the Narrow Band Pass and Narrow band Notch filter.
The input voltage source is Vac with 1V magnitude .Obtain a plot V versus
frequency (AC analysis)
THEORY:
Narrow bandpass filters are designed to isolate a narrow region of the infrared
spectrum. This is accomplished using a complex process of constructive and
destructive interference.
Narrow band pass filters have bandwidths (measured at half‐peak transmittance
levels) less than 6 percentage of the center of wavelength value. When ordering,
the bandwidth can be expressed as a percentage of the center wavelength, or can
be given in microns.
The filters exhibit high peak transmission (typically greater than 60 percentage) combined
with high attenuation levels outside the passband (typically less than
0.1 percentage).
NARROW BAND NOTCH FILTER CIRCUIT DIAGRAM
THEORY:
A Notch Filter is also known as a Band Stop filter or Band Reject Filter. These
filters reject/attenuate signals in a specific frequency band called the stop band
frequency range and pass the signals above and below this band. For example, if
a Notch Filter has a stop band frequency from 1500 MHz to 1550 MHz, it will pass
all signals from DC to 1500 MHz and above 1550 MHz. It will only block those
signals from 1500 MHz to 1550 MHz.
OUTPUT WAVEFORM NARROW BAND NOTCH FILTER
EXPERIMENT 3
AIM‐Design and simulate variable power supply using 78XX
Software Used‐ Orcad
EXPERIMENT 4
AIM‐Design a 2‐to‐4‐line decoder and simulate
Software Used‐ Orcad
In the above example, you can observe that each o/p of the decoder is truly a minterm,
resulting from an assured inputs combination, that is:
D0 =A1 A0, ( minterm m0) which corresponds to input 00 D1 =A1 A0, ( minterm
m1) which corresponds to input 01 D2 =A1 A0, ( minterm m2) which corresponds
to input 10 D3 =A1 A0, ( minterm m3) which corresponds to input 11
The circuit is implemented with AND gates, as shown in the figure. In this circuit,
the logic equation for D0 is A1/A0, and so on. Thus, each output of the decoder
will be generated to the input combination.
OUTPUT WAVEFORM
EXPERIMENT 5
AIM‐Design D Flip‐Flop and simulate
Software Used‐ Orcad
D Flip‐Flop CIRCUIT DIAGRAM
THEORY: D Flip‐Flop are used as a part of memory storage elements and data
processors as well. D flip‐flop can be built using NAND gate or with NOR gate. Due
to its versatility they are available as IC packages. The major applications of D flip‐
flop are to introduce delay in timing circuit, as a buffer, sampling data at specific
intervals. D flip‐flop is simpler in terms of wiring connection compared to JK flip‐
flop. Here we are using NAND gates for demonstrating the D flip flop
Whenever the clock signal is LOW, the input is never going to affect the output
state. The clock has to be high for the inputs to get active. Thus, D flip‐flop is a
controlled Bi‐stable latch where the clock signal is the control signal. Again, this
gets divided into positive edge triggered D flip flop and negative edge triggered D
flip‐flop.
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EXPERIMENT 6
PCB LAYOUTS
AIM‐ PCB layout of RC Phase Shift Oscillator
Software used‐ Eagle
RC Phase Shift Oscillator PCB layout
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AIM‐ PCB layout of NARROW BAND PASS FILTER
Software used‐ Eagle
NARROW BAND PASS FILTER PCB layout
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AIM‐ PCB layout of NARROW BAND NOTCH FILTER
Software used‐ Eagle
NARROW BAND NOTCH FILTER PCB layout
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