RC7017-datasheet-V3 6 5

100M Ethernet & 8xE1 merging multiplexer
RC7017
Datasheet
V3.6.5
Mar. 2011
Raycom CO.,LTD.
RC7017 Datasheet V3.6.5 Page 1 of 48
Revision History
Revision Date Alteration remarks

Document created.
V1.0 2003-Mar-1
ECO version
Local loop of line port is added, namely LINE_LOOPI
V2.0 2003-Apr-1 (pin 33);
Forced reception by line port is added, namely
FORCEAI (pin 21) and FORCEBI (pin 22).
V2.1 2003-May-10 Errors in the line port connection diagram are corrected.
E1 alarm output sequence in Fig. 7-2-4-4 is changed.
V2.2 2004-Jul-2
Errors in naming pins in Fig. 3-1 are changed and pin 21
V2.3 2004-July-15
is FORCEAI and pin 22 is FORCEBI.
Regulate the contents of Chapter 4.2.5~4.2.7
Add optical Automatic Protection Switching time
V3.0 2004-Sep-25 parameter.
Modify Fig. 4-2-2-1 and Fig. 4-2-2-1 for reading
convenience.
Add optical line scramble mode pin.
V3.1 2005-May-12
Modify the description of the customer channels and
add two figures “Asynchronous Serial Channel
Transmission” and “Asynchronous Serial Channel
V3.2 2005-Jun-10
Receiving” in 4.2.6 for easy comprehension.
Modify the Ethernet MII Timing and E1 Interface Timing
(NRZ Mode) to be compatible with most customers.
Supplement Table5-1: Maximum Ratings
V3.3 2006-Jan-10 Correct Fig.7-2-3 Connection between the RC7017 and
Fiber Transceiver with tx_dis.
V3.4 2006-Mar-21 Document optimized.
V3.6 2006-Jun-05 Document optimized.
Page 16, Table 3-2-7, Pin 49 CLK9MI should be
V3.6.1 2006-Oct-24
9.375MHz, not 9MHz.
Modify Fig. 7-2-4-4.
Modify “the control bit 5.4” in 7.2.1 is changed to “the
control bit 4.1”.
V3.6.2 2007-Nov-29
Add “, and connect the E1NI and E1PI to high or low
level.” after “(3) Bypass the HDB3 Coder/Decoder
through HDB3_NRZ_SELI” in 7.2.1
V3.6.3 2008-May-5 Modify the 4.2.7.1 about the ” Sign” description
Page 27, “1 start bit, 8 data bits, 1 odd parity bit and 1
V3.6.4 2009-Jan-15
stop bit” and the packet should be 11-bit.
Add description about the connection mathod of the
V3.6.5 2011-Mar-17
input pins without pull-up/pull-down in 3.2.
Copyright notice
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and clients of Raycom during their usage of relevant products. Without written
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Copyright @ 2000~2006 Raycom CO., LTD. All rights reserved.

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Contents
1. GENERAL DESCRIPTION
DESCRIPTION--------------------------------------------------------------------------------
-------------------------------------------------------------------------------- 5
2. FEATURES
FEATURES----------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------- 5
3. PIN ASSIGNMENTS AND DESCRIPTIONS

DESCRIPTIONS----------------------------------------------------------
---------------------------------------------------------- 6
3.1 PIN ASSIGNMENTS---------------------------------------------------------------------------------------------6

3.2 SIGNAL DESCRIPTIONS--------------------------------------------------------------------------------------- 7
3.2.1 100BASE-FX MII--------------------------------------------------------------------------------------- 7
3.2.2 E1 Interface---------------------------------------------------------------------------------------------- 8
3.2.3 Optical Line Interface--------------------------------------------------------------------------------10
3.2.4 EOW Interface-----------------------------------------------------------------------------------------12
3.2.5 Alarm and Configuration----------------------------------------------------------------------------13
3.2.6 Management and Customer Channels Interface------------------------------------------- 15
3.2.7 Reset and Clock-------------------------------------------------------------------------------------- 16
3.2.8 Power Supply------------------------------------------------------------------------------------------ 16
4. FUNCTIONAL DESCRIPTION
DESCRIPTION--------------------------------------------------------------------------
-------------------------------------------------------------------------- 17
4.1 INTRODUCTION----------------------------------------------------------------------------------------------- 17
4.2 FUNCTIONAL DETAILS--------------------------------------------------------------------------------------- 18
4.2.1 Optical Interface Processing---------------------------------------------------------------------- 18
4.2.2 PDH-------------------------------------------------------------------------------------------------------20
4.2.3 100BASE-FX MII------------------------------------------------------------------------------------- 22
4.2.4 EOW------------------------------------------------------------------------------------------------------22
4.2.5 Alarm Output------------------------------------------------------------------------------------------- 23
4.2.6 Customer Channels----------------------------------------------------------------------------------23
4.2.7 Management UART----------------------------------------------------------------------------------27
5. TECHNICAL PARAMETERS
PARAMETERS----------------------------------------------------------------------------
---------------------------------------------------------------------------- 36
5.1 MAXIMUM RATINGS------------------------------------------------------------------------------------------36

5.2 DC CHARACTERISTICS--------------------------------------------------------------------------------------37
5.2.1 Recommended Operating Conditions----------------------------------------------------------37
5.2.2 DC Characteristics----------------------------------------------------------------------------------- 38
5.2.3 P-CML DC Characteristics-------------------------------------------------------------------------39
5.2.4 Power Consumption--------------------------------------------------------------------------------- 39
5.3 AC CHARACTERISTICS-------------------------------------------------------------------------------------- 40
5.3.1 I/O Pin Capacitance--------------------------------------------------------------------------------- 40
5.3.2 Interface Timing Characteristics----------------------------------------------------------------- 40
6. PACKAGE
PACKAGE----------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------- 42
----------------------------------------------------------------------------------------------------42
7. APPLICATION GUIDE
GUIDE------------------------------------------------------------------------------------
------------------------------------------------------------------------------------ 43
7.1 TYPICAL APPLICATIONS------------------------------------------------------------------------------------- 43

7.2 TIPS FOR HARDWARE DESIGN---------------------------------------------------------------------------- 44

7.2.1 Mask Non-used E1 Tributaries------------------------------------------------------------------- 44
7.2.2 Unused Input Pins------------------------------------------------------------------------------------44
7.2.3 Optical Connection-----------------------------------------------------------------------------------44
7.2.4 Serial Pins Connection------------------------------------------------------------------------------45
Figure Index
FIG. 3-1 RC7017 PIN ASSIGNMENTS................................................................................................. 6

FIG. 4-1 RC7017 BLOCK DIAGRAM..................................................................................................17
FIG. 4-2-1-1 PROTECTION SWITCHING TIMING................................................................................. 19
FIG. 4-2-2-1 E1 TRIBUTARIES LOS DETECT.................................................................................... 20
FIG. 4-2-2-2 E1 TRIBUTARY LOOP-BACK..........................................................................................21
FIG. 4-2-3 THE PIN-TO -PIN MAP BETWEEN THE RC7017 AND THE SWITCH KS8993............... 22
FIG 4-2-6-1 ASYNCHRONOUS SERIAL CHANNEL TRANSMISSION.................................................... 25
FIG 4-2-6-2 ASYNCHRONOUS SERIAL CHANNEL RECEIVING.......................................................... 25
FIG. 4-2-6-3 CONNECTION OF CLK2MO AND FS8KO................................................................... 26
FIG. 4-2-6-4 SERIAL OUTPUT TIMING............................................................................................... 26
FIG. 4-2-6-5 SERIAL INPUT TIMING................................................................................................... 27
FIG. 4-2-7-1-1 CONNECTION BETWEEN THE MANAGEMENT UART PORT AND A PC.................... 27
FIG. 4-2-7-1-2 MANAGEMENT UART FRAME STRUCTURE..............................................................28
FIG. 4-2-7-2 CONFIGURATION FRAME STRUCTURE......................................................................... 28
FIG. 4-2-7-3 QUERY FRAME STRUCTURE........................................................................................ 32
FIG. 4-2-7-4 LOW-SPEED ASYNCHRONOUS SERIAL PORT ACCESS FRAME STRUCTURE..............34
FIG. 5-3-2-1-1 RC7017 ETHERNET MII OUTPUT TIMING............................................................... 40
FIG. 5-3-2-1-2 RC7017 ETHERNET MII INPUT TIMING................................................................... 40
FIG. 5-3-2-2-1 RC7017 E1 INTERFACE OUTPUT TIMING (NRZ MODE).........................................41
FIG. 5-3-2-2-2 RC7017 E1 INTERFACE INPUT TIMING (NRZ MODE)............................................ 41
FIG. 6 RC7017 144-PIN LQFP PACKAGE DIAGRAM...................................................................... 42
FIG. 7-1 RC7017 TYPICAL APPLICATION.......................................................................................... 43
FIG. 7-2-3: CONNECTION BETWEEN THE RC7017 AND FIBER TRANSCEIVER WITH TX_DIS.......... 44
FIG. 7-2-4-1 ADDRI CONNECTION DIAGRAM.................................................................................. 45
FIG. 7-2-4-2 MASK_ENI, HDB3_NRZ_SELI AND E1_LOOPI CONNECTION DIAGRAM............ 45
FIG. 7-2-4-3 HJBLI CONNECTION DIAGRAM....................................................................................46
FIG. 7-2-4-4 E1ASDO CONNECTION DIAGRAM.............................................................................. 46
FIG. 7-2-4-5 HJBLO CONNECTION DIAGRAM..................................................................................47

Table Index
TABLE 3-2-1: RC7017 MII SIGNAL DESCRIPTIONS----------------------------------------------------------- 7

TABLE 3-2-2: RC7017 E1 SIGNAL DESCRIPTIONS------------------------------------------------------------ 8
TABLE 3-2-3: OPTICAL LINE SIGNAL DESCRIPTIONS---------------------------------------------------------10
TABLE 3-2-4: EOW SIGNAL DESCRIPTIONS-------------------------------------------------------------------12
TABLE 3-2-5: RC7017 ALARM AND CONFIGURATION SIGNAL DESCRIPTIONS-------------------------13
TABLE 3-2-6: MANAGEMENT AND CUSTOMER CHANNELS SIGNAL DESCRIPTIONS--------------------15
TABLE 3-2-7: RC7017 RESET AND CLOCK SIGNAL DESCRIPTIONS------------------------------------- 16
TABLE 3-2-8: RC7017 POWER SUPPLY SIGNAL DESCRIPTIONS----------------------------------------- 16
TABLE 4-2-6: SERIAL CHANNEL BUS CONFIGURATIONS---------------------------------------------------- 24
TABLE 4-2-7-2-1: CONFIGURATION FRAME--------------------------------------------------------------------29
TABLE 4-2-7-2-2: AUTOMATIC PROTECTION SWITCHING CONFIGURATION------------------------------ 31
TABLE 4-2-7-2-3: THRESHOLD SETTING FOR AUTOMATIC PROTECTION SWITCHING----------------- 31
TABLE 4-2-7-3: RESPOND FRAME WHEN TYP IS 0X0------------------------------------------------------ 32
TABLE 4-2-7-4-1: LOW-SPEED ASYNCHRONOUS SERIAL PORT ACCESS FRAME--------------------- 34
TABLE 4-2-7-4-2: RESPOND FRAME WHEN TYP IS 0X2--------------------------------------------------- 35
TABLE 5-1: MAXIMUM RATINGS---------------------------------------------------------------------------------- 36
TABLE 5-2-1: RECOMMENDED OPERATING CONDITIONS--------------------------------------------------- 37
TABLE 5-2-2: DC CHARACTERISTICS----------------------------------------------------------------------------38
TABLE 5-2-3: P-CML DC CHARACTERISTICS----------------------------------------------------------------- 39
TABLE 5-3-1: I/O PIN CAPACITANCE---------------------------------------------------------------------------- 40
TABLE 5-3-2-1: RC7017 ETHERNET MII TIMING PARAMETERS------------------------------------------ 41
TABLE 5-3-2-2: RC7017 E1 INTERFACE INPUT TIMING PARAMETERS (NRZ MODE)---------------- 42

1. General Description
The RC7017 is a mixed multiplexer, which integrates a PDH optical terminal

and a 100BASE-FX Ethernet PHY transceiver. The RC7017 provides two
Pseudo-CML (PCML) interfaces that can be directly connected to optical
transceivers, an Engineering Order Wire (EOW) interface, customer auxiliary
interfaces, and other useful interfaces. With this featured chip, it is easy to
realize the optical terminal with multi E1 and a wire speed fast Ethernet.
2. Features
� Multiplexes 8 E1 signal and a full-speed 100M Ethernet frame.

� Supplies dual optical ports with built-in CDR and supports connection
with optical transceiver directly.
� 1+1 line protection with ALS facility for eye safety.
� Built-in E1 CDR, HDB3 CODEC and DPLL for jitter attenuation at E1
interface to allow simple LIU adopted.
� Supports 64Kb/s interface to directly connect with PCM CODEC for
order wire function.
� Management UART for configuring and monitoring the chip at 9600bps
or 19200bps.
� Supports local and remote E1 loop-back.
� Supports optical port local loop-back.
� Masks alarm automatically when no LIU installed.
� Supports configured customer channels: up to 4 asynchronous serial
channels or 2 serial channels + one E1.
� 32 low-speed asynchronous sampling channels, which can be accessed
through management UART or pins.
� LQFP144 package and 3.3 Voltage power supply.

3. Pin Assignments and Descriptions
3.1 Pin Assignments
Fig. 3-1 RC7017 Pin Assignments

3.2 Signal Descriptions
3.2.1 100BASE-FX MII
Table 3-2-1: RC7017 MII Signal Descriptions
Pin No. PIN NAME I/O Signal Description

79 MRXDV O, 4mA Output Data Valid.
High level = The RC7017 drives valid data
on the MRXD.
The RC7017 drives this signal on the rising
edge of the MRXC.
78 MRXD3 O, 4mA Output Data.

77 MRXD2 O, 4mA The RC7017 drives these signals on the
76 MRXD1 O, 4mA rising edge of the MRXC.
75 MRXD0 O, 4mA
74 MRXC O, 4mA Output Data Driving Clock.
The 25MHz clock provides reference for
MRXD, MRXDV.
69 MTXEN I, PD Input Data Valid.

High level = The MAC drives valid data on
the MTXD.
This signal must be synchronized to the
MTXC and the RC7017 samples this signal
on the rising edge of the MTXC.
68 MTXD3 I, PD Input Data.

67 MTXD2 I, PD These signals must be synchronized to the
65 MTXD1 I, PD MTXC and the RC7017 samples these
64 MTXD0 I, PD signals on the rising edge of the MTXC
72 MTXC O, 4mA Input Data Sampling Cloc

Clock.
The 25MHz clock provides reference for
MTXD, MTXEN.

3.2.2 E1 Interface
Table 3-2-2: RC7017 E1 Signal Descriptions
Pin No. Pin Name I/O Signal Description

118 E1PO7 O, 4mA E1 tributary output port 7.
In HDB3 mode, positive rail
data is provided on E1PO7
and the negative on E1NO7;
in NRZ mode, the 2.048MHz
clock is provided on E1NO7
119 E1NO7 O, 4mA and the NRZ Signal on the
E1PO7 is clocked out on the
falling edge of the 2.048MHz
clock. See Fig. 5-3-2-2-1 for
timing details.
120 E1PO6 O, 4mA

E1 tributary output port 6.
121 E1NO6 O, 4mA
122 E1PO5 O, 4mA
123 E1NO5 O, 4mA
124 E1PO4 O, 4mA
125 E1NO4 O, 4mA
128 E1PO3 O, 4mA
129 E1NO3 O, 4mA
130 E1PO2 O, 4mA
131 E1NO2 O, 4mA
132 E1PO1 O, 4mA
133 E1NO1 O, 4mA
134 E1PO0 O, 4mA
135 E1NO0 O, 4mA
104 E1PI7 I, 5V Tol E1 tributary input port 7.
In HDB3 mode, positive rail
data should be provided on
E1PI7 and the negative on
E1NI7; in NRZ mode, a
2.048MHz clock should be
provided on E1NI7 and the
NRZ data on E1PO7. The
input NRZ data is sampled
105 E1NI7 I, 5V Tol
on rising edge of the
2.048MHz clock. See Fig.
5-3-2-2-2 for timing details.
If the E1 input port is not
used, it can not be left float
and it should be connected
to 3.3V via a 1KΩ resistance.

106 E1PI6 I, 5V Tol

E1 tributary input port 6.
107 E1NI6 I, 5V Tol
109 E1PI5 I, 5V Tol
110 E1NI5 I, 5V Tol
111 E1PI4 I, 5V Tol

112 E1NI4 I, 5V Tol
140 E1PI3 I, 5V Tol
141 E1NI3 I, 5V Tol
142 E1PI2 I, 5V Tol
143 E1NI2 I, 5V Tol
2 E1PI1 I, 5V Tol
3 E1NI1 I, 5V Tol
4 E1PI0 I, 5V Tol E1 tributary input port 0.
5 E1NI0 I, 5V Tol
E1 Line Port Local or
Remote Loop-back
Selection.
High level = Remote
27 LOOP_FN_SELI I, PD
loop-back enable.
Low level = Local loop-back
enable.
Serial E1 Line Port

Loop-back Enable.
Serial input shares by 8 E1
line ports and drives by
parallel-in/serial-out shift
registers.
28 E1_LOOPI I, PD High level = Loop-back
enable.
Low level = Loop-back
disable.
See Fig. 7-2-4-2 for
connection details.
Serial E1 Line Format

Selection.
Serial input shares by 8 E1
line ports and drives by
parallel-in/serial-out shift
registers.
31 HDB3_NRZ_SELI I, PD High level = HDB3
Coder/Decoder is bypassed
and the E1 line port is in
NRZ format.
Low level = The E1 line port
is in rail format.

3.2.3 Optical Line Interface
Table 3-2-3: Optical Line Signal Descriptions

93 TSDPAO O, PCML Optical Line Input Port A, Positive
94 TSDNAO O, PCML and Negative.
Differential PCML driver pair
compatible with standard fiber
transceiver for 150MHz data
transmission.
98 OS_ENAO O, 2mA Fiber Transceiver A Transmission

Enable.
High level = Transmission disable.
Low level = Transmission enable.
In ALS mode (high level on
ALS_ENI), the RC7017
automatically drives OS_ENAO to
reduce the laser if necessary; in
customer control mode (low level on
ALS_ENI), the OS_ENAO is driven
by control bit 5.7 of the configuration
frame on the management UART.
96 RSDPAI I, PCML Optical Line Input Port A, Positive

95 RSDNAI I, PCML and Negative.
transceiver for receiving data at
150MHz.
97 OSDAI I, A Loss of Signal on Input Fiber A.

High level = The optical transceiver
detects the loss of signal on input
fiber A.
When high level occurs on OSDAI,
the RC7017 inserts Alarm Indication
Signals (AIS) on optical line input
port A.
If the optical input port A is not used,
the OSDAI can not be left float and

it should be connected to 3.3V via a

1KΩ resistance.
87 BIASEI I, A Bias Control Input.

Connects to 1.6V via an external
100Ω resistor. See Fig. 7-2-3 for
details.

89 BIASEO O Bias Control Output.
Connects to 3.3V via an
external 110Ω resister and
Connects to ground via an external
1μ capacity. See Fig. 7-2-3 for
details.
84 TSDNB O, PCML Optical Line Output Port B,
83 TSDPBO O, PCML Positive and Negative.
80 OS_ENBO O, 2mA Fiber Transceiver B
Transmission Enable.
In ALS mode (high level on
ALS_ENI), the RC7017
automatically drives OS_ENBO to
reduce the laser if necessary; in
customer control mode (low level
on ALS_ENI), the OS_ENBO is
driven by control bit 5.6 of the
configuration frame on the
management UART.
86 RSDPBI I, PCML Optical Line Input Port B,
85 RSDNBI I, PCML Positive and Negative.
transceiver for receiving data at
150MHz.
82 OSDBI I, A Loss of Signal on Input Fiber B.
If the optical input port B is not
used, the OSDBI can not be left
float and it should be connected to
3.3V via a 1KΩ resistance.
61 CRNT_WORKO O, 2mA Active Optical Line Input Port
Indication.
High level = The data from port A is
selected for deframer and all the
optical line alarms come from fiber

A.
Low level = The data from port B is
selected for deframer and all the
optical line alarms come from fiber
B.
21 FORCEAI I, PD Automatic Protect Switching
Configuration.
22 FORCEBI I, PD See Table 4-2-7-2-2 for details.

34 SCRAM_MODI I,PD Optical Line Scramble Mode
Low level = Scramble mode which
is compatible with the RC7010(the
RC7010 is the last generation of
the merging multiplexer)
High level = New scramble mode
New scramble mode is
recommended.
26 ALS_ENI I, PU Automatic Leaser
Shutdown/Reduction Enable.
High level = The RC7017
automatically drives OS_ENAO to
reduce the laser if necessary.
Low level = The OS_ENAO and
OS_ENBO are driven by control
bits 5.7 and 5.6 of the configuration
frame on the management UART.
3.2.4 EOW Interface
Table 3-2-4: EOW Signal Descriptions

58 CLK2MO O, 4mA PCM Clock.
This 2.048MHz clock is provided to drive
bit clock and master clock of the PCM
CODEC for synchronous operation.
59 FS8KO O, 4mA PCM Frame Sync Pulse.
This 8KHz pulse is 8 bit clock period long
for long frame sync operation.
57 TD64KO O, 4mA PCM Data Output.
56 RD64KI I, 5V Tol PCM Data Input.

If the EOW port is not used, the RD64KI

can not be left float and it should be
connected to GND via a 1KΩ resistance.
52 HOOKI I, 5V Tol Hook Status Input.
Low level = Off-hook.
High level = Hook.
If the EOW port is not used, the HOOKI
can not be left float and it should be
connected to 3.3V via a 1KΩ resistance.
10 RINGO O, 4mA Alarm and Phone Bell Tone Output.
Low level is output when there is nothing.
This signal can drive a speaker or a
buzzer.
60 PHONE_L O, 2mA EOW Status Indication.
EDO High level = On talking.
Low level = Line in free.
Toggle = Other status.
3.2.5 Alarm and Configuration
Table 3-2-5: RC7017 Alarm and Configuration Signal Descriptions

39 ALMO O, 2mA Global Alarm.
High level = Local alarm.
Toggle = Remote alarm.
Low level = No alarm.
If both local alarm and remote alarm occur,
high level is output.
40 NOPO O, 2mA Optical Line Alarm.
41 LOFO O, 2mA Active high. When low level is on ALM_SELI,
42 ALE3O O, 2mA local alarms of the active optical line are
43 ALE6O O, 2mA output; otherwise remote alarms are output.
NOPO: Loss of Optical Line Signal.
LOFO: Loss of Optical Line Frame.
ALE3O: Optical Line Bit Error Rate (BER)
Alarm.
If the equivalent BER exceeds the threshold
of 10-3, high level is on ALE3O.
ALE6O: Optical Line Bit Error Rate (BER)
Alarm.
If the equivalent BER exceeds the threshold
of 10-6, high level is on ALE6O.
44 E1ASDO O, 4mA E1 Tributary Alarm Serial Output.

Active high. This output is shared by 8 E1

tributaries and contains Loss of E1 Line
Signal and HDB3 Coding Violation. The
serial-in/parallel-out shift register is needed.
See Fig. 7-2-4-4 for connection details.
When low level is on ALM_SELI, local alarms
are output; otherwise remote alarms are
output.
High level = Alarm is detected.
46 ALM_SE I, PD Local or Remote Alarm Output Selection.
LI Low level = Local alarms output enable.
High level = Remote alarms output enable.
48 MUTE_E I, PD Alarm Tone Mask.
NI High level = Alarm tone output disable; only
the phone bell tone is output.
Low level = Both alarm tone and phone bell
tone are output.
47 MASK_E I, PD E1 Tributary Alarm Serial Mask.
NI This input is shared by 8 E1 tributaries and
the parallel-in/serial-out shift registers are
needed. See Fig. 7-2-4-2 for connection
details.

3.2.6 Management and Customer Channels Interface
Table 3-2-6: Management and Customer Channels Signal Descriptions

103 ADDRI I, PD Management UART Address Serial
Input.
Each RC7017 is assigned a 6-bits
management UART address, ranging
from 0 to 63, which allows the
controller to communicate with multiple
RC7017.
See Fig. 7-2-4-1 for connection details.
7 SIBUSI I, PU Management UART Port, Input and
8 SIBUSO O, 4mA Output.
When there is no data to output,
SIBUSO is forced to high impedance
(tri-state).
SPD_SELI I, PD Management UART Baud Rate
Selection.
Low level = 9600bps.
High level = 19200bps.
32 HJBLI I, PD Low-speed Asynchronous
38 HJBLO O, 4mA Channels Serial Port, Input and
Output.
See 4.2.6 Customer Channels for
details.
99 TS_MODE0I I, PD Serial Channel Bus Mode
100 TS_MODE1I I, PD Configuration.
See 4.2.6 Customer Channels for
details.
11 TD232_0O O, 4mA Serial Channel Bus, Inputs and
12 RD232_0I I, 5V Tol outputs.
13 TD232_1O O, 4mA See 4.2.6 Customer Channels for
14 RD232_1I I, 5V Tol details.
15 TD232_2O O, 4mA If the serial channel bus is not used,
16 RD232_2I I, 5V Tol the input
17 TD232_3O O, 4mA pins(RD232_0I/RD232_1I/RS232_2I/
20 RD232_3I I, 5V Tol RS232_3I) can not be left float and
they should be connected to 3.3V via a
1KΩ resistance.

3.2.7 Reset and Clock
Table 3-2-7: RC7017 Reset and Clock Signal Descriptions

29 RESETI I, Smt Hardware Reset.
Low level = Hardware reset.
High level = Normal operation.
24 CLK65MI I, 5V Tol System Clock.
This clock is mainly used for E1 line
operation. Its frequency must be
65.536MHz (± 50ppm) and the clock duty
cycle must be (50 ± 10) %.
49 CLK9MI I, 5V Tol System Clock.
This clock is mainly used for optical line
and Ethernet operation. Its frequency
must be 9.375MHz (± 30ppm) and the
clock duty cycle must be (50 ± 10) %.
3.2.8 Power Supply
Table 3-2-8: RC7017 Power Supply Signal Descriptions
Pin No. Pin Name Signal Description

1,18,37,54,73,90,116,126 Digital Supply (3.3V)
VDD
6,9,19,25,30,33,36,45,50,55,66,70,71,81,9 Digital Ground
GND
1,101,102,108,117,127,137,138,144
51 Analog Supply (3.3V) for
AVD optical line operation.
53 Analog ground for optical
AVS line operation.
35,62,63,88,92,113,114,115,136,139 No Connection. Leave

NC
open.
Note: I/O Type Coding.

I = Input
O = Output
PD = Pull-Down
PU = Pull-Up
5V Tol = 5V Tolerant
Smt = Schmidt
PCML = Pseudo-CML
A = Analog

4. Functional Description
4.1 Introduction
PHONE_LEDO
CLK2MO
TD64KO
RD64KI
FS8KO
HOOKI
RINGO
HJBLI RESETI
CLK65MI
RD232I[0:3] RX232 EOW
BIASEI
B IA S E O
E1NI[0:7]
E1 RX OS_ENAO
E1PI[0:7]
TSDPAO
TSDNAO
MTXD[3:0] Framer Scrambler P /S
OS_ENBO
M TXEN ETH
TSDPBO
RX
M TXC TSDNBO
SCRAM_MODI
CLK9MI APLL FORCEAI
FORCEBI
CRNT_W ORKO
MRXD[3:0]
M RXDV ETH OSDAI
TX S /P RSDPAI
MRXC
DeFramer DeScrambler & RSDNAI
CDR
RSDPBI
E1NO[0:7]
E1 TX RSDNBI
E1PO[0:7]
OSDBI
TD232O[0:3] TX232
UART CONTROL ALARM
H JB LO
HDB3_NRZ_SELI
E1_LOOPI
MUTE_ENI
MASK_ENI
SPD_SELI
LOOP_FN_SELI
ALM_SELI
ADDRI
SIBUSO
NOPO
SIBUSI
TS_MODEI[0:1]
E1ASDO
ALMO
LERR3O
LERR6O
LOFO
Fig. 4-1 RC7017 Block Diagram
With the process of clock recovery and HDB3 decoding 8 E1 signals enter
the chip and are then merged with the data stream from the MII interface. They
are then sent out through the dual PCML interfaces in a special frame after being
scrambled.
From the other direction, by monitoring the quality, the RC7017 selects one
data stream from the two PCML interfaces, abstracts the line clock and recovers
the data. After de-scrambling and frame alignment, each type of data is
separated. Meanwhile, the line bit rate is supervised and the result is reported.
All alarms and performance records are gathered and filtered according to
their priority. Then they are sent to the UART interface and some to pins for
direct display.

4.2 Functional Details
4.2.1 Optical Interface Processing
4.2.1.1 Automatic Protect Switching
The RC7017 possesses two PCML interfaces. The data to be transmitted is

sent to the two PCML interfaces simultaneously for 1+1 backup. For receiving,
the two data streams coming from the PCML interfaces are inspected and the
better one is selected. If any fault occurs on the selected data stream, the other
is switched to replace the bad one immediately. The trigger conditions for the
protection switch are NOP (No Optical signal), LOF (Loss of Frame alignment),
and a bit error rate of 10-3, 10-6, that can be configured by UART. There are two
control bits (4.3, 4.2 in the configuration frame) to determine the trigger condition.
By default, either Loss of Optical Line Signal Alarm or Loss of Optical Line
Frame Alarm will trigger the switching operation. Please refer to the Table 13 for
details.
The selection of coming data from the two PCML can be performed by both
pins and setting the UART. There are two control pins (FORCEAI, FORCEBI)
and two control bits (5.7 and 5.6 in configuration frame) for optical line input port
selection. If none of them are configured, the RC7017 decides automatically.
Please note that user can disable the functions of the PIN FORCEAI and
FORCEBI through UART instructions. See Table 4-2-7-2-2 for configuration
details.
The RC7017 samples the alarms from the selected incoming data of the
optical line every 125 μs. If any effective alarm has been declared, the protection
switching will be initiated. The time of the switching operation itself is almost zero.
So the delay is less than 125μs from alarm detection to the protection switching
operation.
When line switching operation occurs, the RC7017 stops the fault sampling
for 1s to prevent the system from the repeatedly switching due to some unstable
status.

Switching Point
P o rt A P o rt B
Optical Line
Input Data
Alarm Confirmation
Optical Line
A la r m
Re-Synchronization
S can
Sleep after Switching

S can
Point
Fig. 4-2-1-1 Protection Switching Timing

Correlative time parameter:
The Loss of Optical Signal detection depends on the optical device.
The Loss of Optical Line Frame can be detected in 400μs (Max.).
The defect of BER exceeding 10-3 can be detected in 10 ms (Max.).
The defect of BER exceeding 10-6 can be detected in 500 ms (Max.).
The active optical line port can be observed on CRNT_WORKO pin. Active
port A drives CRNT_WORKO high and active port B drives low.
No matter which optical line input port is active, the two optical line output
ports are all active and the RC7017 always sends the same data stream on both
output ports.
4.2.1.2 Automatic Laser Shutdown/Reduction
For eye safety considerations, the RC7017 provides the capability of

Automatic Laser Shutdown (ALS) capability in case of optic fiber disconnection.
When the optical fiber is disconnected, a continuous pulse with a certain duty
cycle is output on OS_ENAO or OS_ENBO to control the operation of the optical
transmitter, and the luminous power of the transmitter will be 20 db lower on
average than normal. The RC7017 can automatic restart after the optical fiber
revalidation.
The pulse duty cycle on the Pins OS_ENAO and OS_ENBO determines how
much the laser power will decrease. If 20dB reduction is not satisfactory, the
RC7017 allows the user to modify this parameter by asserting bit 5.6 and 5.7 in
the configuration frame through the UART interface while setting high on PIN
ALS_ENI. Note that a pull up resistor is connected with PIN ALS_ENI internally
to make 20dB ALS default.

4.2.2 PDH
4.2.2.1 Advanced E1 Line Transceiver
The RC7017 integrates advanced E1 line transceivers that contain digital

smoothing Phase Locked Loop (PLL), Clock and Data Recovery (CDR), and an
HDB3 Coder/Decoder. Therefore, only simple E1 Line Interface Unit (LIU) is
needed.
The HDB3 Coder/Decoder can be bypassed through pin HDB3_NRZ_SELI,
so both HDB3 and NRZ format are supported on the E1 tributary.
The 8 bits to be serially captured through the PIN HDB3_NRZ_SELI,
correspond to 8 E1 tributaries for HDB3 and NRZ selection. So external
parallel-in/serial-out shift registers as 74HC165 are needed. These external shift
registers are clocked by the PIN CLK2MO at the frequency of 2.048MHz, and
loaded in parallel by the pulse on the PIN FS8KO at the rate of 8KHz. With the
internal pull down resistor attached on PIN HDB3_NRZ_SELI, HDB3 set by
default, in case of no external logics existing. See Fig. 7-2-4-2 for connection
and timing details.
The E1 transceiver has the logics to detect Loss Of Signal (LOS) and Coding
Violation on the input of HDB3 rail. When LOS is effective, AIS is inserted into
the E1 channel. If the HDB3 Coder/Decoder is bypassed, the LOS alarm and CV
alarm are not generated.
Sometimes, users just need 4 E1s, leaving the other 4 E1s floating. That will
cause the un-wanted LOS alarm. Thus, the external pull up resistors are
recommended to connect to the unused E1 input pins to eliminate those LOS
alarms. The RC7017 can mask these alarms automatically by identifying the
high level input. See Fig. 4-2-2-1.
+ 3 .3 V E1 LO S Alarm Collect
Detect Block B lo c k
E1 LO S
LED
R
non-use port E1ASDO
1
port with LOS
1
normal port
0
G lo b a l A L M
R C 7017
Fig. 4-2-2-1 E1 Tributaries LOS Detect
By setting PIN MASK_ENI high, all current E1 LOS alarms due to cable
disconnection can be masked. It also can be realized by configuring certain bits

in the frame of the UART.

Even with PIN MASK_ENI asserted high, and all LOS alarms masked, a
new E1 LOS alarm can still be triggered if a new event of E1 signal loss is
detected.
The high level on PIN MASK_ENI will take effect again when power
restored from the accidental power down.
4.2.2.2 E1 Tributary Loop-back
The RC7017 provides local and remote loop-back capability for each of the
E1 tributaries.
Corresponding to 8 E1 tributaries, there are 8 control bits designed for E1
loop-back. They are serially input through the PIN E1_LOOPI and clocked by the
PIN CLK2MO with the load pulse of FS8KO. So external parallel-in /
serial-output shift registers are needed.
These 8bits can also be set through the UART. Non-loop back is the default
if the internal pull down resistor is floated.
Another PIN LOOP_FN_SELI is used to select where the loop back will
occur. When high level is on LOOP_FN_SELI, the instruction is transmitted to
remote chip and the E1 tributary loop-back is enabled there. Otherwise, local E1
tributary loop-back is enabled. See Fig. 4-2-2-2 for E1 tributary loop-back
position and direction.
Remote RC7017 Local RC7017
Framer DeFramer
E1 Optical E1
DeFramer Framer
UART
E1_LOOPI
LOOP_FN_SELI
Local Loopback
Remote RC7017 Local RC7017
Framer DeFramer
E1 Optical E1
DeFramer Framer
UART
E1_LOOPI
LOOP_FN_SELI
Remote Loopback
Fig. 4-2-2-2 E1 Tributary Loop-back

4.2.3 100BASE-FX MII
The RC7017 provides a 100BASE-FX MII like a PHY. A SWITCH is needed

to perform the Media Access Controller (MAC) operation and connect with a LAN.
The RC7017 does not limit the Ethernet frame length, and the features of
Ethernet are mostly determined by the SWITCH.
In order to facilitate the design of schematic diagram and PCB, Fig. 4-2-3
provides a pin-to-pin map between the RC7017 and the SWITCH KS8993.
R C 7017 K S 8993
No. Nam e I/O I/O Nam e No.
P79 MRXDV O I M TXEN P57
P78 MRXD3 O I M TX D 3 P58
GND I M TXER P62
P74 MRXC O I M R X C LK P71
P69 M TXEN I O MRXDV P64
P68 M TX D 3 I O MRXD3 P65
P72 M TXC O I M TX C L K P63
Fig. 4-2-3 The Pin-to-Pin Map Between the RC7017 and the SWITCH
KS8993
4.2.4 EOW
The RC7017 provides point-to-point EOW function and the 64Kbps interface
can be connected with CODEC directly. The RC7017 performs signaling
procedure and generates ringing back tones, engaged tones, howling tones and
bell tones. The bell tones output and alarm tones output share the pin RINGO.
Unlike other alarms, the ring bell can’t be muted by the PIN MUTE_ENI.
The status of EOW is indicated by the PIN PHONE_LEDO. The low is for idle,
the high for engaged, and the toggle is for others.

4.2.5 Alarm Output
All alarm outputs are active when high.

There is the pin ALMO for the two global alarms, the local and the remote,
both of which are from the active optical line and the E1 tributaries in use. Any
fault detected from the local chip asserts the ALMO a constant high, and any
remote alarm drives the ALMO toggle at 0.5sec high and 0.5sec low. The local
global alarm enjoys the priority.
Note that pin ALM_SELI cannot affect the ALMO display.
Except ALMO, the pin ALM_SELI determines whether the local or remote
terminal working status will be displayed on the alarm pins. When ALM_SELI is
set to logic low, local alarms are output; otherwise remote alarms drive these
pins.
Either the local global alarm or the remote global alarm is declared. The
toggle is provided on the pin RINGO, which is used to connect with the circuit of
a buzzer or speaker driver. When MUTE_ENI is logic high, the alarm tones are
disabled.
The optical line alarms have the priority NOP > LOF > ALE3 > ALE6 from
high to low. For example, when the NOP is declared, the other three lower
priority alarms are shielded.
When the RC7017 detects NOP or LOF, the Alarm Indication Signals (AIS)
are inserted in all of the E1 tributaries of the de-multiplexing side, all-zero
patterns are inserted in Ethernet data stream out of the MII, high level is on the
serial channel bus output pins TD232 (3:0) O and low level is on low-speed
asynchronous serial channel output pin HJBLO.
The RC7017 detects Loss of E1 tributary rail signals and HDB3 coding
violation. The alarm of signal loss has the higher priority than coding violation.
When an E1 tributary channel is regarded as non-use or in NRZ mode (HDB3
Coder/Decoder bypassed), the alarm of this channel will not be output.
All the E1 tributary alarms share the pin E1ASDO to output, so the external
serial-in/parallel-out shift register logics like 74HC595 is required.
4.2.6 Customer Channels
The RC7017 provides abundant customer channels for functional

expansion.
The pins RS232I (0:3) and RS232O (0:3) are defined as serial channel bus,
which supports asynchronous or synchronous reception and transmission. The
mode is determined by TS_MODEI (0:1). See Table 4-2-6 for serial channel bus
configurations details.

Table 4-2-6: Serial Channel Bus Configurations
TS_MODEI (0) TS_MODEI (1) Serial Bus Mode

0 X RS232I (0), RS232O (0): Customer
UART port 0, and sampling rate is 2MHz.
RS232I (1), RS232O (1): Not used.
RS232I (2), RS232O (2): Customer
RS232I(3), RS232O(3):Not used.
1 0 RS232I(0), RS232O(0):Customer
RS232I(1), RS232O(1):Customer
1 1 RS232I(0), RS232O(0):Customer
RS232I(2):Customer Synchronous
Receiver and Transmitter port, NRZ data
input. The NRZ data is sampled on the
rising edge of 2.048MHz clock provided on
RS232I (3).
RS232I(3):Customer Synchronous
Receiver and Transmitter port, 2.048MHz
clock input.
RS232O(2):Customer Synchronous
Receiver and Transmitter port, NRZ data
output. The NRZ data is clocked out on the
falling edge of 2.048MHz clock occurred on
RS232O (3).
RS232O(3):Customer Synchronous
Receiver and Transmitter port, 2.048MHz
clock output.
In the asynchronous mode, the data is sampled asynchronously and

transmitted transparently. When the sampling rate is 1 MHz, the recommended
maximum baud rate is 125K, which can support the RS232 transmission of
115.2Kbps; when the sampling rate is 2 MHz, the recommended maximum baud
rate is 250K.
The RC7017 provides 32 low-speed asynchronous serial channels with the
internal sampling rate of 10KHz. These 32 channels share the pin HJBLI as

input and HJBLO as output, so an external parallel-in/serial-output shift registers

and serial-in/parallel-out shift registers are needed. These shift registers must
use reversed CLK2MO (2.048MHz) as their shift clock and reversed FS8KO as
their parallel loading pulse. See Fig. 4-2-6-3 to Fig. 4-2-6-5 for connection and
timing details. 54HC/74HC165 is recommended as the parallel-in/serial-output
device and 54HC/74HC595 as the serial-in/parallel-out.
6 5 .5 3 6 M 9 .3 7 5 M
CLK2M O TX
ECO
FS8KO Tim er
Tim er
Framer
74HC165 S /P Optical
HJBLI P ort
A syn
S am ple
RD232_I E1
S ync
TS_MODEI[1:0]
Fig 4-2-6-1 Asynchronous Serial Channel Transmission
During the transmission, these 32 bits of data are retrieved from the signal
on the HJBLI according to the timing of 74/54HC165, synchronously sampled by
the 9.375MHz clock and filled in the overhead of the optical frame.
6 5 .5 3 6 M
RX CLK2M O
CDR ECO
Tim er FS8KO
Tim er
H JB LO
D e fra m P /S 74HC595
Optical er
P ort A syn
S am ple
E1
D esync
T D 232_O
TS_MODEI[1:0]
Fig 4-2-6-2 Asynchronous Serial Channel Receiving

While receiving, 32 bits of data are picked from the optical frame, sampled to
be synchronous with the 65.536MHz domain and transformed into a serial signal
according to the timing of 74/54HC595.
In fact the 32 low-speed channels are asynchronous although the HJBLI
and HJBLO both look like the synchronous interface. The recommended
maximum baud rate is 1K for one channel, which is designed for low-speed
signal such as Link, TX, RX indications of the Ethernet switch and other
environment variables.
These 32 channels can also be accessed as registers through the
management UART.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
H G F E D C B A H G F E D C B A
MC54/74HC165 MC54/74HC165
Serial Shift/ Serial Shift/
Parallel Load C lo c k Parallel Load C lo c k
FS8KO
R C 7017
CLK2M O
L a tc h Shift L a tc h Shift
C lo c k C lo c k C lo c k C lo c k
MC54/74HC595 MC54/74HC595
A B C D E F G H A B C D E F G H
CODEC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Fig. 4-2-6-3 Connection of CLK2MO and FS8KO
CLK2M O
FS8KO
Not
CLK2M O
Not
FS8KO
HJBLO HJBLO(8) HJBLO(7) HJBLO(6) HJBLO(5) HJBLO(4) HJBLO(3) HJBLO(2) HJBLO(1) HJBLO(0) e m p ty
Shift Load
Fig. 4-2-6-4 Serial Output Timing

CLK2M O
FS8KO
Not
CLK2M O
Not
FS8KO
HJBLI HJBLI(0) HJBLI(1) HJBLI(2) HJBLI(3) HJBLI(4) HJBLI(5) HJBLI(6) HJBLI(7) HJBLI(8) HJBLI(9)
Shift
Fig. 4-2-6-5 Serial Input Timing
4.2.7 Management UART
4.2.7.1 General Description
The management UART protocol defines the three types of frames: the
configuration frame, the alarm query frame and the low-speed asynchronous
serial channel access frame (serial channel access frame). Each frame consists
of several 11-bit packets and each packet contains 1 start bit, 8 data bits, 1 odd
parity bit and 1 stop bit.
The baud rate of the management UART is configurable. When high level is
on pin SPD_SELI, the baud rate is 19200bps; otherwise the baud rate is
9600bps.
If there is no effective data to be output, the management UART output pin
SIBUSO is forced to high impedance (tri-state). See Fig. 4-2-7-1-1 for
connection details. This allows the system designers to use one processor to
control multi-RC7017 through UART interface.
TX SIBUSI ADDRI
PC M A X 232 RC7017(0)
RX S IB U S O 0
SIBUSI ADDRI
RC7017(0)
S IB U S O 1
SIBUSI ADDRI
RC7017(0)
S IB U S O 2
.
.
.
Fig. 4-2-7-1-1 Connection Between the Management UART Port and a PC

Each frame contains header, body and end. The header includes three bytes
as following: 0x7E, 0x82, 6-bit Address and 2-bit Sign, which indicates frame
types (10 represents query frame, 11 represents configuration frame, and 01
represents serial channel access frame). The end byte should be 0x33. Only
when the end mark is received successfully, a frame is seen as valid.
MSB LSB
0x7E
0x82 Header
Sign(2bit) Address(6bit)
Content Body
0x33 End
Fig. 4-2-7-1-2 Management UART Frame Structure
4.2.7.2 Configuration Frame
MSB LSB MSB LSB

0x7E 0x7E
Header Header
0x82 0x82
(3Byte) (3Byte)
S ig n Address S ig n Address
CMD1 CMD1
CMD2 CMD2
CMD3 Body CMD3 Body
CMD4 (7Byte) CMD4 (7Byte)
CMD5 CMD5
CMD6 CMD6
CMD7 End CMD7 End
0x33 (1Byte) 0x33 (1Byte)
Configuration Frame Configuration Frame
(PC to RC7017) (Sent Back)
Fig. 4-2-7-2 Configuration Frame Structure
For safety considerations, one configuration frame is demanded to be sent

two times continuously. It will be valid, only the two continuously received frames
are exactly the same, and then, the RC7017 will send back the result of the
configuration. Since the configurations can be performed through both
management UART and control pins, the RC7017 sends back the current result
of the configurations. Thus, when the control pin MUTE_ENI is high, the
corresponding control bit in the back frame is 1 no matter what the configuration
frames are.
Writing 1 to the control bit 5.5 can disable all the control pins, and the input
data on the HJBLI can be canceled by control bits 5.2, 5.1, 5.0.

Table 4-2-7-2-1: Configuration Frame
Bit Description
Frame Header
0.7:0 0x7E
1.7:0 0x82
Sign & Address
2.7:6 Configuration Frame Sign = 11
2.5:0 Address Assigned by ADDRI
CMD1
3.7:0 Instruction to make E1 tributary remote Loop-back.
3.7~3.0 control E1 channel 7~ 0 respectively.
1 = Loop-back enable;
0 = Loop-back disable.
These control bits provide the same capability as the control pin
E1_LOOPI.
CMD2
4.7 Reserved
4.6:5 Automatic Protect Switching Configuration.
See Table 4-2-7-2-2 for details.
4.4 Hook.
1 = Hook.
0 = Off-Hook.
This control bit provides the same capability as control pins
HOOKI without reference to control bit 5.5.
4.3:2 Setting threshold for Automatic Protect Switching.
If 4.6:5 is 00 and both FORCEI and FORCEBI are low level,
these two control bits determine the threshold, at which auto protect
switching will start. See Table 4-2-7-2-3 for details.
4.1 E1 Tributary Alarm Mask.
1 = Mask enable;
0 = Mask disable.
This control bit provides the same capability as control pin
MASK_ENI.
4.0 Alarm Sound MaskMask.
1 = Mask enable;
0 = Mask disable.
This control bit provides the same capability as control pin
MUTE_ENI.
CMD3
5.7 Unit A transmission enable for ALS.
In customer protection switching mode (low level is on
ALS_ENI), this control bit drives OS_ENAO directly.

Bit Description
5.6 Unit B transmission enable for ALS.
In customer protection switching mode (low level is on
ALS_ENI), this control bit drives OS_ENBO directly.
5.5 Configuration Control Pins Mask.
1 = All the configuration control pins are disabled and the
configuration depends on management UART.
0 = Both configuration control pins and management UART are
enabled.
5.4 Reserved.
5.3 Reserved.
5.2 Low-speed Asynchronous channel Input Pin Mask.
1 = Data of channel 0 to 7 from the pin HJBLI is disabled. The data
only comes from management UART.
0 = Data of channel 0 to 7 from the pin HJBLI is enabled. The
data only comes from the pin HJBLI.
5.1 Low-speed Asynchronous Channel Input Pin Mask.
1 = Data of channel 8 to 15 from the pin HJBLI is disabled. The data
only comes from management UART.
5.0 Low-speed Asynchronous Channel Input Pin Mask.
1 = Data of channel 16 to 31 from the pin HJBLI is disabled. The
data only comes from management UART.
CMD4
6.7:0 E1 Tributary Local Port Loop-back.
6.7~6.0 control port 7~port 0 respectively.
1 = Loop-back enable;
0 = Loop-back disable.
These control bits provide the same capability as control pins
E1_LOOPI.
CMD5~CMD7
7.7:0 Reserved.
8.7:0 Reserved.
9.7:0 Reserved.
End
10.7:0 0x33

Table 4-2-7-2-2: Automatic Protection Switching Configuration
FORCEAI FORCEBI
Description
(4.6) (4.5)
Low (0) Low (0) Performing Automatic Protection Switching
operations.
Low (0) High (1) Forced selection of data stream from the
input of the optical line B.
High (1) Low (0) Forced selection of data stream from the
input of the optical line A.
Table 4-2-7-2-3: Threshold Setting for Automatic Protection Switching
4.3:2 Description
00 Perform Automatic Protection Switching operation when Loss of
Optical Line Signals is detected.
01 Perform Automatic Protection Switching operation when either
Loss of Optical Line Signals or Loss of Line Frame is detected.
(Default)
Optical Line Signals, Loss of Optical Line Frame or BER exceeding
10-3 is detected.
Optical Line Signals, Loss of Optical Line Frame, BER exceeding
10-3 or BER exceeding 10-6 is detected.

4.2.7.3 Query Frame
MSB LSB MSB LSB

0x7E Header 0x7E
(3Byte) Header
0x82 0x82
(3Byte)
S ig n Address Body S ig n Address
0x0 TYP (1Byte) EOW
0x33 End E1LOS
(1Byte) DETCV
Query Frame
ALM
(PC to RC7017)
R_E1LO S Body
R_DETCV (11Byte)
R_ALM
RESERVED1
RESERVED2
RESERVED3
RESERVED4
End
0x33
(1Byte)
Query Frame
(Alarms Sent Back)
Fig. 4-2-7-3 Query Frame Structure
There are three types of query frame differentiated by the 4-bit TYP. When
the TYP is 0x0, the RC7017 sends back the frame defined in Table 4-2-7-3;
when the TYP is 0x1, the RC7017 sends back the frame defined in Table
4-2-7-2-1; when the TYP is 0x2, the RC7017 sends back the frame defined in
Table 4-2-7-4-2.
In the alarm query frame sent back by the RC7017, a 1 always indicates
that the corresponding alarm is detected.
Table 4-2-7-3: Respond Frame when TYP is 0X0
Bit Description
Frame Header
0.7:0 0x7E
1.7:0 0x82
Sign & Address
2.7:6 Alarm Query Frame Sign = 10
2.5:0 Address assigned by ADDRI
EOW
3.7:3 Reserved
3.2 Hook status at remote.
1 = Remote off-hook;
0 = Remote hook.
3.1 Active Fiber Input Indication.
1 = The data from fiber A is selected for deframer;

0 = The data from fiber B is selected for deframer.
Bit Description
3.0 EOW Status.
1 = On talking;
0 = Other Status.
E1LOS
4.7:0 Loss of Local E1 Tributary Port Signal
Signal.
4.7 is for E1 tributary 7 and 4.0 is for E1 tributary 0.
DETCV
5.7:0 HDB3 Coding Violation of Local E1 Tributary Port.
ALM
6.7 Local Global Alarm.
6.6 Loss of Local Optical Signal.
6.5 Loss of Local Optical Line Frame.
6.4 Local Line Bit Error Rate (BER) exceeding 10-3.
6.3 Local Line Bit Error Rate (BER) exceeding 10-6.
6.2:0 Reserved.
R_E1LOS
7.7:0 Loss of Remote E1 Tributary Port Signal Signal.
R_DETCV
8.7:0 HDB3 Coding Violation of Remote E1 Tributary Port.
R_ALM
9.7 Remote Global Alarm.
9.6 Loss of Remote Optical Signal Alarm.
9.5 Loss of Remote Optical Line Frame Alarm.
9.4 Remote Line Bit Error Rate (BER) exceeding 10-3.
9.3 Remote Line Bit Error Rate (BER) exceeding 10-6.
9.2:0 Reserved.
RESERVED1- RESERVED4
10.7:0 Reserved.
11.7:0 Reserved.
12.7:0 Reserved.
13.7:0 Reserved.
End
14.7:0 0x33

4.2.7.4 Low-speed Asynchronous Serial Port Access Frame
MSB LSB MSB LSB

0x7E 0x7E
Header Header
0x82 0x82
(3Byte) (3Byte)
S ig n Address S ig n Address
0x0 (2 ) (1 ) REG1
REG1 REG2
REG2 Body REG3
0x0 (4 ) (3 ) (6Byte) REG4
Body
REG3 R_REG 1
(8Byte)
REG4 End R_REG 2
0x33 (1Byte) R_REG 3
R_REG 4 End
Low-speed Channels Access Frame 0x33 (1Byte)
(PC to RC7017)
Low-speed Channels Access Frame
(1) R/W1 ; (2) R/W2 (Sent Back)
(3) R/W3 ; (4) R/W4
11 means Write
others means Read
Fig. 4-2-7-4 Low-Speed Asynchronous Serial Port Access Frame Structure
Table 4-2-7-4-1: Low-speed Asynchronous Serial Port Access Frame
Bit Description
Frame Header
0.7:0 0x7E
1.7:0 0x82
Sign & Address
RW12
3.7:4 Reserved
3.3:2 R/W1.
11 = Writing operation of low-speed asynchronous serial channel
0~7;
Others = Reading operation of low-speed asynchronous serial
channel 0~7.
3.1:0 R/W2.
8~15;
channel 8~15.
REG1
4.7:0 Data written to low-speed asynchronous serial channel 0~7 if
R/W1 is 11.
4.7 is for channel 0 and 4.0 is for channel 7.

Bit Description
REG2
R/W2 is 11.
RW34
6.7:4 Reserved
6.3:2 R/W3.
16~23;
channel 16~23.
6.1:0 R/W4.
24~31;
channel 24~31.
REG3
R/W3 is 11.
REG4
R/W4 is 11.
End
9.7:0 0x33
Table 4-2-7-4-2: Respond Frame when TYP is 0X2
Bit Description
Frame Header
0.7:0 0x7E
1.7:0 0x82
Sign & Address
REG1
3.7:0 Data written to low-speed asynchronous serial channel 0~7.
REG2
REG3
REG4

Bit Description
R_REG1
7.7:0 Received data of low-speed asynchronous serial channel 0~7.
R_REG2
8.7:0 Received data of low-speed asynchronous serial channel 8~15.
R_REG3
9.7:0 Received data of low-speed asynchronous serial channel
16~23.
R_REG4
10.7:0 Received data of low-speed asynchronous serial channel
24~31.
End
11.7:0 0x33
5. Technical Parameters
5.1 Maximum Ratings
The maximum ratings are threshold values that must not be exceeded even
momentarily. Any exceeding may cause permanent damage to the device.
Table 5-1: Maximum Ratings
Parameter Symbol Ratings Unit

Power supply voltage VDD VSS-0.5~+4.0 V
Input voltage VI VSS -0.5~VDD+0.5 V
VSS -0.5~VDD+4.0(≤6.0, 5V tolerant)
Output voltage VO VSS -0.5~ VDD +0.5 V
VSS -0.5~ VDD +4.0(≤6.0, 5V tolerant)
Power supply pin current ID Per VDD pin 95 mA
(Constantly) Per VSS pin 95
Output current (Constantly) IO CMOS output +/-14 mA
IOL=2mA, 4mA, 8mA
Overshoot (50 ns or less) - VDD+1.0 V
Undershoot (50 ns or less) - VSS-1.0 V
Storage temperature TST Plastic package –55~+125 °C
Junction temperature Tj -40~+125
(VSS=0V)

5.2 DC Characteristics
5.2.1 Recommended Operating Conditions
Table 5-2-1: Recommended Operating Conditions
Ratings
Parameter Symbol Unit
Min. Typ. Max.
Supply voltage VDD 3.0 3.3 3.6 V
High 3V Normal VIH VDDx0.65 - VDD+0.3 V
level CMOS Schmitt VDDx0.80
Input 5V Normal VDDx0.65 - 5.5
voltage Tolerant Schmitt VDDx0.80
3V Normal VIL VDD - VDDx0.25 V
CMOS Schmitt VDDx0.20
5V
Tolerant
Junction Temperature Tj 0 - 100 °C
(VDD=3.3V+/-0.3V, VSS=0V)

5.2.2 DC Characteristics
DC characteristics specify the extreme values of static characteristics of I/O

buffers guaranteed within the range of recommended operating conditions.
Table 5-2-2: DC Characteristics
Value
Parameter Symbol Condition Unit
Min. Typ. Max.
Supply IDDS Static state (VIH=VDD, - - 300 uA
Current VIL=VSS)
High level VOH 2mA IOH=-2mA VDD-0.5 - VDD V
output buffer IOH=-4mA
voltage 4mA
buffer
Low level VOL 2mA IOL=2mA VSS - 0.4 V
output buffer IOL=4mA
voltage 4mA
buffer
Output IOS 2mA VO=0V or VDD - - +/-30 mA
short-circuit buffer +/-60
Current 4mA
buffer
Input ILI Input VI=0V~VDD -5 - 5 uA
leakage cell
current ILZ BUS
input
Input RP Typical type VI=VDD 25 50 100 KΩ
pull-down Tolerant type VI=5V 200
resistance
Input Typical type VI=0V 25 50 100
pull-up Tolerant type VI=0V 200
resistance
(VDD=3.3V+/-0.3V,VSS=0V,Tj=0~100 ºC)

5.2.3 P-CML DC Characteristics
Table 5-2-3: P-CML DC Characteristics
Paramete Value
Symbol Condition Unit
r Min. Typ. Max.
Center VC VC=1.3V V
level VC=1.6V
VC=2.0V
High level VIH Differential VIL+0.3 - VDD V
input input pin
voltage VIH Single REF+0.3
input pin
Low level VIL Differential VSS - VIL-0.3 V
input input pin
voltage VIL Single REF-0.3
input pin
High level VOH Output pin Vt-0.05 Vt Vt+0.05 V
output
voltage
Low level VOL Output pin Vr-0.05 Vr Vr+0.05 V
output
voltage
BIAS Low Vr VC=1.3V Vt*-0.85 - Vt-0.35 V
level input VC=1.6V
voltage VC=2.0V
Reference REF Single VC-0.05 VC VC+0.05 V
level input
(VDD=3.3V+/-0.3V, VSS=0V,Tj=0~100 ºC)

Note: * Vt = Termination voltage
5.2.4 Power Consumption
The maximum power consumption is less than 500mW under the

recommended operating conditions.

5.3 AC Characteristics
5.3.1 I/O Pin Capacitance
Table 5-3-1: I/O Pin Capacitance
Parameter Symbol Value Unit

Input pin CIN Max 16 pF
Output pin IOL=2mA, 4mA COU Max 16
I/O pin IOL=2mA, 4mA CI/O Max 16
(Tj=+25 ºC ,VDD=VI=0V,F=1MHz)
5.3.2 Interface Timing Characteristics
5.3.2.1 Ethernet MII Timing
M RXC
MRXDV
M RXD3~0
Teod
Fig. 5-3-2-1-1 RC7017 Ethernet MII Output Timing
M TXC
M TXEN
M TXD3~0
T e is T e ih
Fig. 5-3-2-1-2 RC7017 Ethernet MII Input Timing

Table 5-3-2-1: RC7017 Ethernet MII Timing Parameters
Value
Symbol Parameter Unit
Min. Typ. Max.
Teod MRXDV, 10 - 22 ns
MRXD
Output
Delay to
MRXC
rising edge
Teis MTXEN, 5 - -
MTXD
Setup to
MTXC
rising edge
Teih MTXEN, 5 - -
MTXD
Hold to
MTXC
rising edge
5.3.2.2 E1 Interface Timing (NRZ Mode)
E1N O
E1PO
Tpod
Fig. 5-3-2-2-1 RC7017 E1 Interface Output Timing (NRZ Mode)
E1NI
E1PI
T p is T p ih
Fig. 5-3-2-2-2 RC7017 E1 Interface Input Timing (NRZ Mode)

Table 5-3-2-2: RC7017 E1 Interface Input Timing Parameters (NRZ Mode)
Value
Symbol Parameter Unit
Min. Typ. Max.
Tpod E1PO Output - 0 - ns
Delay to E1NO
falling edge
Tpis E1PI Setup to 10 - -
E1NI rising edge
Tpih E1PI Hold to 10 - -
E1NI rising edge
6. Package
144-pin plastic LQFP

u n it : m m
22
20
108 73
109 72
20
22
RC7017
144 37
1 36
0 .5 0 .2 2
0 .4 0 .6
Fig. 6 RC7017 144-Pin LQFP Package Diagram

7. Application Guide
7.1 Typical Applications
1~32xLow 1~4x S uch as

UART
Speed Data 232 V .3 5
MC54/
Conver
74H C 1 M A X 232
te r
65
1xE1
(NRZ)
L IU 1~8xE 1
Optical
Transceiver
R C 7017
Optical
Transceiver SW I
M II
TCH
MC54/
CODE
74H C 5
C
95
Phone A la r m
Fig. 7-1 RC7017 Typical Application
The RC7017 integrates PDH and Ethernet operations in a single chip with
two optical line ports and abundant auxiliary channels. It is easy to design an
optical terminal device series with the following features:
One PCB suitable for all devices with different numbers of E1 ports.
Devices with both a PDH interface and a full-speed Ethernet interface.
Safe optical terminal with capability of point-to-point 1+1 optical line
protection switching and Automatic Leaser Shutdown/Reduction.
Abundant auxiliary channels for some special conditions.

7.2 Tips for Hardware Design
7.2.1 Mask Non-used E1 Tributaries
The RC7017 provides three ways to mask the alarms of non-used E1

tributaries.
(1) External pull-up to high level(3.3V) on both E1NI and E1PI via resistors
when there are no LIU circuits connected to these pins.
(2) Driving high level on MASK_ENI or writing 1 to the control bit 4.1 in
configuration frame when E1 signal loss occurs.
(3) Bypass the HDB3 Coder/Decoder through HDB3_NRZ_SELI, and
connect the E1NI and E1PI to high or low level.
7.2.2 Unused Input Pins
All the 5V tolerance input pins have no pull-up or pull-down resistors

internally. It is strongly recommended to connect the 5V tolerance input pins to
VDD or VSS when these pins are not in use.
7.2.3 Optical Connection
In order to support ALS, a fiber transceiver with tx_dis is needed. See the
figure below for connection details.
OSDAI
100
1 .6 V 3 .3 V
BIASEAI
B IA S E B O
3 .3 V LM
110 510
1u 0 .0 1 u 358
33 rd +
RSDAPI
rd -
RSDANI
1
820 620 18
RX
RC7017 0 .1 u 0 .1 u 1 0 u
tx_ d is sd
1 .2 u H
OS_ENAO VCC
3 .3 V 5V
5V 1 .2 u H
TX
0 .1 u 0 .1 u 1 0 u
200 10
82 9
75 td -
TSDANO
td + T o p V ie w
TSDAPO
0 .0 1 u
510 510
Fig. 7-2-3: Connection between the RC7017 and Fiber Transceiver with
tx_dis

7.2.4 Serial Pins Connection
7.2.4.1 ADDRI Connection
FS8KO(P60) 1
S H /L D
GND 15 16 VCC
C L K IN H VCC
2
C LK
CLK2MO(P58)
GND 10
SER
GND 11
A
GND 12
B 74HC165
13
C
14 9 ADDRI(P103)
D QH
3 7
E nQ H
4
F
5
G
6 8 GND
H GND
5 4 3 2 1 0
MSB LSB
Fig. 7-2-4-1 ADDRI Connection Diagram
7.2.4.2 MASK_ENI, HDB3_NRZ_SELI and E1_LOOPI Connection
FS8KO(P60) 1
S H /L D
GND 15 16 VCC
C L K IN H VCC
2
CLK
CLK2MO(P58)
GND 10
SER
11
A
12
B 74HC165
13
C HDB3_NRZ_SELI(P31)
14 9
D QH E1_LOOPI(P28)
3 7
E nQH MASK_ENI(P47)
4
F
5
G
6 8 GND
H GND
7 6 5 4 3 2 1 0
MSB LSB
Fig. 7-2-4-2 MASK_ENI, HDB3_NRZ_SELI and E1_LOOPI Connection

Diagram

7.2.4.3 HJBLI Connection
GND
SER QH SER QH
74HC165 74HC165
3130292827262524 2322212019181716
MSB
HJBLI(P32)
SER QH SER QH
74HC165 74HC165
151413121110 9 8 7 6 5 4 3 2 1 0
LSB
Fig. 7-2-4-3 HJBLI Connection Diagram
7.2.4.4 E1ASDO Connection
15 14 E1A S D O (P4 4 )
Q0 DS
1 16 VCC
Q1 VCC
2 8 GND
Q2 GND
3 13 GND
Q3 OE
4 7 4 H C 595 12 F S 8K O (P6 0 )
Q4 STCP
5 11
Q5 SHCP
6 10 VCC
Q6 MR
7 9
Q7 Q7~
C L K 2M O (P5 8 )
0 1 2 3 4 5 6 7
LSB MSB
E1 L O S
15 14
Q0 DS
1 16 VCC
Q1 VCC
2 8 GND
Q2 GND
3 13 GND
Q3 OE
4 7 4 H C 595 12 F S 8K O (P6 0 )
Q4 STCP
5 11
Q5 SHCP
6 10 VCC
Q6 MR
7 9
Q7 Q7~
C L K 2M O (P5 8 )
0 1 2 3 4 5 6 7
LSB MSB
E1 H D B 3 Code Violation
Fig. 7-2-4-4 E1ASDO Connection Diagram

7.2.4.5 HJBLO Connection
Q7~ DS Q7~ DS
74HC595 74HC595
QQ Q QQQQ Q Q QQQQ Q QQ
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
3130292827262524 2322212019181716
MSB
HJBLO(P38)
Q7~ DS Q7~ DS
74HC595 74HC595
QQ Q QQQQ Q Q QQQQ Q QQ
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
151413121110 9 8 7 6 5 4 3 2 1 0
LSB
Fig. 7-2-4-5 HJBLO Connection Diagram


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100M Ethernet & 8xE1 merging multiplexer

Revision Date Alteration remarks

Copyright @ 2000~2006 Raycom CO., LTD. All rights reserved.

3. PIN ASSIGNMENTS AND DESCRIPTIONS

3.1 PIN ASSIGNMENTS---------------------------------------------------------------------------------------------6

5.1 MAXIMUM RATINGS------------------------------------------------------------------------------------------36

7.1 TYPICAL APPLICATIONS------------------------------------------------------------------------------------- 43

Copyright @ 2000~2006 Raycom CO., LTD. All rights reserved.

7.2 TIPS FOR HARDWARE DESIGN---------------------------------------------------------------------------- 44

FIG. 3-1 RC7017 PIN ASSIGNMENTS................................................................................................. 6

Copyright @ 2000~2006 Raycom CO., LTD. All rights reserved.

TABLE 3-2-1: RC7017 MII SIGNAL DESCRIPTIONS----------------------------------------------------------- 7

Copyright @ 2000~2006 Raycom CO., LTD. All rights reserved.

The RC7017 is a mixed multiplexer, which integrates a PDH optical terminal

� Multiplexes 8 E1 signal and a full-speed 100M Ethernet frame.

Copyright @ 2000~2006 Raycom CO., LTD. All rights reserved.

3. Pin Assignments and Descriptions

3.1 Pin Assignments

Fig. 3-1 RC7017 Pin Assignments

Copyright @ 2000~2006 Raycom CO., LTD. All rights reserved.

3.2 Signal Descriptions

3.2.1 100BASE-FX MII

Table 3-2-1: RC7017 MII Signal Descriptions

Pin No. PIN NAME I/O Signal Description

78 MRXD3 O, 4mA Output Data.

69 MTXEN I, PD Input Data Valid.

68 MTXD3 I, PD Input Data.

72 MTXC O, 4mA Input Data Sampling Cloc

Copyright @ 2000~2006 Raycom CO., LTD. All rights reserved.

Table 3-2-2: RC7017 E1 Signal Descriptions

Pin No. Pin Name I/O Signal Description

120 E1PO6 O, 4mA

Copyright @ 2000~2006 Raycom CO., LTD. All rights reserved.

106 E1PI6 I, 5V Tol

111 E1PI4 I, 5V Tol

Serial E1 Line Port

Serial E1 Line Format

Copyright @ 2000~2006 Raycom CO., LTD. All rights reserved.

3.2.3 Optical Line Interface

Table 3-2-3: Optical Line Signal Descriptions

Pin No. PIN NAME I/O Signal Description

98 OS_ENAO O, 2mA Fiber Transceiver A Transmission

96 RSDPAI I, PCML Optical Line Input Port A, Positive

97 OSDAI I, A Loss of Signal on Input Fiber A.

Copyright @ 2000~2006 Raycom CO., LTD. All rights reserved.

it should be connected to 3.3V via a

87 BIASEI I, A Bias Control Input.

Pin No. PIN NAME I/O Signal Description

Copyright @ 2000~2006 Raycom CO., LTD. All rights reserved.

Pin No. PIN NAME I/O Signal Description

3.2.4 EOW Interface

Table 3-2-4: EOW Signal Descriptions

Pin No. PIN NAME I/O Signal Description

Copyright @ 2000~2006 Raycom CO., LTD. All rights reserved.

If the EOW port is not used, the RD64KI

3.2.5 Alarm and Configuration

Table 3-2-5: RC7017 Alarm and Configuration Signal Descriptions

Pin No. PIN NAME I/O Signal Description

Copyright @ 2000~2006 Raycom CO., LTD. All rights reserved.

Active high. This output is shared by 8 E1

Copyright @ 2000~2006 Raycom CO., LTD. All rights reserved.

3.2.6 Management and Customer Channels Interface

Table 3-2-6: Management and Customer Channels Signal Descriptions