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SEMICONDUCTOR TECHNICAL DATA



    
 
High–Performance Silicon–Gate CMOS J SUFFIX
CERAMIC PACKAGE
20
The MC54/74HC373A is identical in pinout to the LS373. The device CASE 732–03
inputs are compatible with standard CMOS outputs; with pullup resistors, 1
they are compatible with LSTTL outputs.
N SUFFIX
These latches appear transparent to data (i.e., the outputs change PLASTIC PACKAGE
asynchronously) when Latch Enable is high. When Latch Enable goes low, 20 CASE 738–03
data meeting the setup and hold time becomes latched. 1
The Output Enable input does not affect the state of the latches, but when DW SUFFIX
Output Enable is high, all device outputs are forced to the high–impedance 20 SOIC PACKAGE
state. Thus, data may be latched even when the outputs are not enabled. 1 CASE 751D–04
The HC373A is identical in function to the HC573A which has the data
inputs on the opposite side of the package from the outputs to facilitate PC SD SUFFIX
20 SSOP PACKAGE
board layout.
1 CASE 940C–03
The HC373A is the non–inverting version of the HC533A.
• Output Drive Capability: 15 LSTTL Loads DT SUFFIX
20 TSSOP PACKAGE
• Outputs Directly Interface to CMOS, NMOS and TTL 1 CASE 948E–02
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA ORDERING INFORMATION
MC54HCXXXAJ Ceramic
• High Noise Immunity Characteristic of CMOS Devices
MC74HCXXXAN Plastic
• In Compliance with the Requirements Defined by JEDEC Standard
MC74HCXXXADW SOIC
No. 7A
MC74HCXXXASD SSOP
• Chip Complexity: 186 FETs or 46.5 Equivalent Gates MC74HCXXXADT TSSOP

LOGIC DIAGRAM
PIN ASSIGNMENT
3 2 OUTPUT 1 20 VCC
D0 Q0 ENABLE
4 5 Q0 2 19 Q7
D1 Q1
7 6 D0 3 18 D7
D2 Q2
8 9 D1 4 17 D6
DATA D3 Q3 NONINVERTING Q1 5 16 Q6
INPUTS 13 12
D4 Q4 OUTPUTS
Q2 6 15 Q5
14 15
D5 Q5 D2 7 14 D5
17 16
D6 Q6 D3 8 13 D4
18 19
D7 Q7 Q3 9 12 Q4
GND 10 11 LATCH
11 PIN 20 = VCC ENABLE
LATCH ENABLE
1 PIN 10 = GND

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
OUTPUT ENABLE
FUNCTION TABLE

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Design Criteria Value Units
Output
Inputs
Latch
Output

ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Internal Gate Count* 46.5 ea Enable Enable D Q

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
L H H H
Internal Gate Propagation Delay 1.5 ns
L H L L

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
L L X No Change
Internal Gate Power Dissipation 5.0 µW

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
H X X Z
Speed Power Product 0.0075 pJ X = Don’t Care
* Equivalent to a two–input NAND gate. Z = High Impedance

3/97

 Motorola, Inc. 1997 1 REV 7


MC54/74HC373A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Parameter
DC Supply Voltage (Referenced to GND)
Value
– 0.5 to + 7.0
Unit
V
This device contains protection
circuitry to guard against damage

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
due to high static voltages or electric
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vout

ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Iin
ÎÎÎ
DC Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ
ÎÎÎ
DC Input Current, per Pin
– 0.5 to VCC + 0.5
± 20
V
mA
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 35 mA

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vout should be constrained to the
ICC DC Supply Current, VCC and GND Pins ± 75 mA v
range GND (Vin or Vout) VCC. v
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic or Ceramic DIP† 750 mW

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
tied to an appropriate logic voltage
SOIC Package† 500 level (e.g., either GND or VCC).

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
SSOP or TSSOP Package† 450
Unused outputs must be left open.

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds _C
(Plastic DIP, SOIC, SSOP or TSSOP Package) 260

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
(Ceramic DIP) 300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
SSOP or TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎ
ÎÎÎ Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout
ÎÎÎ ÎÎÎ
ÎÎÎ
DC Supply Voltage (Referenced to GND)

ÎÎÎ
ÎÎÎ
DC Input Voltage, Output Voltage (Referenced to GND)
2.0
0
6.0
VCC
V
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
TA
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf
ÎÎÎ ÎÎÎ
ÎÎÎ
Operating Temperature, All Package Types

ÎÎÎ
ÎÎÎ
Input Rise and Fall Time VCC = 2.0 V
– 55
0
+ 125
1000
_C
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
(Figure 1) VCC = 4.5 V 0 500
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
v ÎÎÎÎ
v ÎÎÎ VCC – 55 to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
VIH Minimum High–Level Input Vout = VCC – 0.1 V 2.0 1.5 1.5 1.5 V
v Voltage |Iout| 20 µA 3.0 2.1 2.1 2.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
6.0 4.2 4.2 4.2
VIL Maximum Low–Level Input Vout = 0.1 V 2.0 0.5 0.5 0.5 V
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
Voltage
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ |Iout| 20 µA 3.0 0.9 0.9 0.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎ
4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VOH

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Minimum High–Level Output

ÎÎÎÎÎÎÎÎÎ ÎÎÎ
Vin = VIH 2.0 1.9 1.9 1.9 V

v ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎ
Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
6.0 5.9 5.9 5.9
Vin = VIH |Iout| 2.4 mA 3.0 2.48 2.34 2.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ |Iout| 6.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
|Iout| 7.8 mA 6.0 5.48 5.34 5.2

MOTOROLA 2 High–Speed CMOS Logic Data


DL129 — Rev 6
MC54/74HC373A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v
ÎÎÎÎÎÎÎÎ
v ÎÎÎ
ÎÎÎÎ
Parameter

ÎÎÎ
Test Conditions
VCC
V
– 55 to
25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
VOL Maximum Low–Level Output Vin = VIL 2.0 0.1 0.1 0.1 V
v
Voltage |Iout| 20 µA 4.5 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
6.0 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIL |Iout| 2.4 mA 3.0 0.26 0.33 0.4
v
ÎÎÎÎ Î
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
|Iout| 6.0 mA 4.5 0.26 0.33 0.4
|Iout| 7.8 mA 6.0 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
IOZ

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Input Leakage Current

ÎÎÎÎ
ÎÎÎ
Maximum Three–State Leakage
Vin = VCC or GND
Output in High–Impedance State
6.0
6.0
± 0.1
± 0.5
± 1.0
± 5.0
± 1.0
± 10
µA
µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Current Vin = VIL or VIH
Vout = VCC or GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Quiescent Supply

ÎÎÎÎ
ÎÎÎ
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0 4.0 40 160

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
S b l
Symbol ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ
v ÎÎÎ
ÎÎÎÎ
ÎÎÎ
P
Parameter
VCC
V
– 55 to
25_C 85_C 125_C U i
Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
tPLH Maximum Propagation Delay, Input D to Q 2.0 125 155 190 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
tPHL (Figures 1 and 5) 3.0 80 110 130
4.5 25 31 38

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
6.0 21 26 32

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
tPLH Maximum Propagation Delay, Latch Enable to Q 2.0 140 175 210 ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
tPHL (Figures 2 and 5) 3.0 90 120 140
4.5 28 35 42

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
6.0 24 30 36

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
tPLZ Maximum Propagation Delay, Output Enable to Q 2.0 150 190 225 ns
tPHZ (Figures 3 and 6) 3.0 100 125 150

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
4.5
6.0
30
26
38
33
45
38

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
tPZL Maximum Propagation Delay, Output Enable to Q 2.0 150 190 225 ns
tPZH (Figures 3 and 6) 3.0 100 125 150

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
4.5 30 38 45

ÎÎÎ
6.0 26 33 38

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
tTLH Maximum Output Transition Time, Any Output 2.0 60 75 90 ns
tTHL (Figures 1 and 5) 3.0 23 27 32

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
4.5 12 15 18

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
6.0 10 13 15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Cin Maximum Input Capacitance 10 10 10 pF

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Cout Maximum Three–State Output Capacitance 15 15 15 pF
(Output in High–Impedance State)
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V


CPD P
Power Di
Dissipation
i i C Capacitance
i (P
(Per E
Enabled
bl d O
Output)*
)* 36 pF
F
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).

High–Speed CMOS Logic Data 3 MOTOROLA


DL129 — Rev 6
MC54/74HC373A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
v v ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎ – 55 to 25_C
Guaranteed Limit
85_C 125_C

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC
Symbol
S b l Parameter
P Fig.
Fi Volts Min Max Min Max Min Max Unit
U i

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
tsu
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Minimum Setup Time, Input D to Latch Enable

ÎÎ
ÎÎÎ
4 2.0
3.0
25
20
30
25
40
30
ns

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
4.5 5.0 6.0 8.0
6.0 5.0 6.0 7.0

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
th
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Minimum Hold Time, Latch Enable to Input D

ÎÎ
ÎÎÎ
4 2.0
3.0
5.0
5.0
5.0
5.0
5.0
5.0
ns

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
4.5 5.0 50 5.0
6.0 5.0 5.0 5.0

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
tw
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Minimum Pulse Width, Latch Enable

ÎÎ
ÎÎÎ
2 2.0
3.0
60
23
75
27
90
32
ns

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
4.5 12 15 18
6.0 10 13 15

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Maximum Input Rise and Fall Times 1 2.0 1000 1000 1000 ns

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
3.0 800 800 800
4.5 500 500 500

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ ÎÎ
ÎÎÎ 6.0 400 400 400

SWITCHING WAVEFORMS

tr tf tw
VCC VCC
90%
INPUT D 50% LATCH ENABLE 50%
10% GND GND
tPLH tPHL tPLH tPHL
90%
Q 50%
10%
Q 50%
tTLH tTHL

Figure 1. Figure 2.

VCC
OUTPUT
50%
ENABLE
GND VALID
tPZL tPLZ VCC
HIGH
INPUT D 50%
IMPEDANCE
Q 50% GND
10% VOL tsu th
tPZH tPHZ VCC
VOH LATCH ENABLE 50%
90%
Q 1.3 V GND
HIGH
IMPEDANCE

Figure 3. Figure 4.

MOTOROLA 4 High–Speed CMOS Logic Data


DL129 — Rev 6
MC54/74HC373A

TEST CIRCUITS

TEST POINT
TEST POINT

OUTPUT CONNECT TO VCC WHEN


OUTPUT 1 kΩ
TESTING tPLZ AND tPZL.
DEVICE
DEVICE CONNECT TO GND WHEN
UNDER
CL* UNDER TESTING tPHZ AND tPZH.
TEST CL*
TEST

* Includes all probe and jig capacitance


* Includes all probe and jig capacitance

Figure 5. Figure 6.

EXPANDED LOGIC DIAGRAM

D0 D1 D2 D3 D4 D5 D6 D7
3 4 7 8 13 14 17 18
D Q D Q D Q D Q D Q D Q D Q D Q

LE LE LE LE LE LE LE LE

11

2 5 6 9 12 15 16 19
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

High–Speed CMOS Logic Data 5 MOTOROLA


DL129 — Rev 6
MC54/74HC373A

OUTLINE DIMENSIONS

J SUFFIX
CERAMIC PACKAGE NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
20 11 CASE 732–03 POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
ISSUE E 2. DIMENSION L TO CENTER OF LEADS WHEN
1 10
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
B
MILLIMETERS INCHES
A DIM MIN MAX MIN MAX
A 23.88 25.15 0.940 0.990
B 6.60 7.49 0.260 0.295
C L C 3.81 5.08 0.150 0.200
F D 0.38 0.56 0.015 0.022
F 1.40 1.65 0.055 0.065
G 2.54 BSC 0.100 BSC
H 0.51 1.27 0.020 0.050
N J 0.20 0.30 0.008 0.012
J K 3.18 4.06 0.125 0.160
H K L 7.62 BSC 0.300 BSC
D G M M 0_ 15 _ 0_ 15_
N 0.25 1.02 0.010 0.040
SEATING
PLANE

N SUFFIX
–A– PLASTIC PACKAGE
CASE 738–03 NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
20 11 ISSUE E Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
B 3. DIMENSION L TO CENTER OF LEAD WHEN
1 10 FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
C L
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 1.010 1.070 25.66 27.17
B 0.240 0.260 6.10 6.60
–T– C 0.150 0.180 3.81 4.57
K D 0.015 0.022 0.39 0.55
SEATING
PLANE M E 0.050 BSC 1.27 BSC
F 0.050 0.070 1.27 1.77
E N G 0.100 BSC 2.54 BSC
J 0.008 0.015 0.21 0.38
G F K 0.110 0.140 2.80 3.55
J 20 PL
L 0.300 BSC 7.62 BSC
D 20 PL 0.25 (0.010) M T B M M 0_ 15 _ 0_ 15_
0.25 (0.010) M T A M N 0.020 0.040 0.51 1.01

DW SUFFIX
–A– PLASTIC SOIC PACKAGE NOTES:
1. DIMENSIONING AND TOLERANCING PER
CASE 751D–04 ANSI Y14.5M, 1982.
20 11 ISSUE E 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
–B– 10X P (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
0.010 (0.25) M B M
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
1 10 (0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.

20X D MILLIMETERS INCHES


J DIM MIN MAX MIN MAX
0.010 (0.25) M T A S B S A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
F D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
R X 45 _ J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 10.05 10.55 0.395 0.415
C R 0.25 0.75 0.010 0.029

–T– SEATING
PLANE
18X G M
K

MOTOROLA 6 High–Speed CMOS Logic Data


DL129 — Rev 6
MC54/74HC373A

OUTLINE DIMENSIONS
SD SUFFIX
PLASTIC SSOP PACKAGE
CASE 940C–03
NOTES:
ISSUE B 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20X K REF 2. CONTROLLING DIMENSION: MILLIMETER.
0.25 (0.010) 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
0.12 (0.005) M T U S V S PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
N GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
L/2 20 11 M FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER
N SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
L B F PROTRUSION/INTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
DETAIL E EXCESS OF K DIMENSION AT MAXIMUM MATERIAL
PIN 1 1 10 CONDITION. DAMBAR INTRUSION SHALL NOT
IDENT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002)
AT LEAST MATERIAL CONDITION.

ÉÉÉ
ÇÇÇ
K 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE
ONLY.
–U–

ÇÇÇ
ÉÉÉ
A 7. DIMENSION A AND B ARE TO BE DETERMINED AT
–V– J J1 DATUM PLANE –W–.
MILLIMETERS INCHES
0.20 (0.008) M T U S K1 DIM MIN MAX MIN MAX
A 7.07 7.33 0.278 0.288
B 5.20 5.38 0.205 0.212
SECTION N–N C 1.73 1.99 0.068 0.078
D 0.05 0.21 0.002 0.008
F 0.63 0.95 0.024 0.037
–W– G 0.65 BSC 0.026 BSC
C H 0.59 0.75 0.023 0.030
0.076 (0.003)
J 0.09 0.20 0.003 0.008
–T– SEATING J1 0.09 0.16 0.003 0.006
PLANE D G DETAIL E
K 0.25 0.38 0.010 0.015
K1 0.25 0.33 0.010 0.013
H L 7.65 7.90 0.301 0.311
M 0_ 8_ 0_ 8_

DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
20X K REF ISSUE A NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
0.15 (0.006) T U S 0.10 (0.004) M T U S V S Y14.5M, 1982.

ÍÍÍÍ
2. CONTROLLING DIMENSION: MILLIMETER.
K 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,

ÍÍÍÍ
K1 PROTRUSIONS OR GATE BURRS. MOLD FLASH
20 11 OR GATE BURRS SHALL NOT EXCEED 0.15
2X L/2 (0.006) PER SIDE.

ÍÍÍÍ
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
B J J1 FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
L –U– PER SIDE.
PIN 1 5. DIMENSION K DOES NOT INCLUDE DAMBAR
IDENT SECTION N–N PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
1 10 EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
N 0.25 (0.010) 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
0.15 (0.006) T U S 7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
A M
MILLIMETERS INCHES
–V– DIM MIN MAX MIN MAX
A 6.40 6.60 0.252 0.260
N B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
F D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
DETAIL E G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
–W– J1 0.09 0.16 0.004 0.006
C K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
G
D H M 0_ 8_ 0_ 8_
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE

High–Speed CMOS Logic Data 7 MOTOROLA


DL129 — Rev 6
MC54/74HC373A

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◊ MC74HC373A/D
MOTOROLA 8 High–Speed CMOS Logic Data
DL129 — Rev 6

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