Routing

Contents:
● Basic terminologies
● Introduction
● Routing in a Nutshell
● Global Routing
● Congestion map
● Congestion Analysis Table
● Detailed Routing
● Left-Edge Algorithm
● Horizontal Constraints
● Vertical constraints
● Horizontal constraint Graph
● Vertical constraint Graph
● Routing procedure
● Reference
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Basic terminologies:
● Congestion: If the number of available routing tracks for routing in a
particular area is lesser than the number of required routing tracks, then
that particular area is said to be congested.

Congestion creates shorts and DRCs

which makes functionality fail in a design.

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Basic terminologies:
● Metal Layers: Based on technology node, there are different metal layers
involved for routing. Each metal layer is designated with a name say M1 or
M3 and each metal layer has preferred and non-preferred directions with
well-defined width, pitch, offset and tracks.

Ex: M2 can have preferred direction as vertical and

non-preferred direction as horizontal, while M3 can
have preferred direction as horizontal and non-
preferred direction as vertical.

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Basic terminologies:
● NDR (Non-Default Rule): Non-Default Rule is a routing rule applied for a
single net or a group of nets that is not default. Default routing rule have
defined width and spacing for each metal layer and via. Using Non-Default
Rules, one can create an NDR rule with double or triple the width with
double or triple the spacing.

NDRs are used for clock nets and critical nets (high-
frequency nets) in a design to avoid Signal Integrity (SI)
issues such as crosstalk and noise.

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Basic terminologies:
● Shorts: When two or more wires or vias of different nets in the same metal
layer cross each other, then it is termed as a short. Shorts are the number
one concern after detail routing a block.

These overlapping wire segments must be corrected for proper functioning

of the design.

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Introduction :
As ASIC designs are getting more complex and larger (e.g. sea of cells), routing
is becoming more difficult and challenging.

It is possible for routing to fail to complete, or to take an unacceptable amount

of execution run time besides the routing algorithms, the factors which
influence the routability of a given ASIC are the layout of standard cells style, a
well-prepared floorplan, and the quality of standard cell placement.

Routing algorithms are mainly classified as channel or over-the-cell based

routers.

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Routing in a Nutshell:

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 Global Routing :
The first step of the global routing algorithm is to
identify routing regions or cells (a rectangular area with
terminals on all sides) and calculate their corresponding
routing density.
These routing regions or cells are known as Global
Routing Cells or G cells, as shown in the following
figure.

The global router attempts to find the shortest path

through the g-cells, but does not make actual
connections or assign nets to specific tracks within the
g-cells. It tries to avoid assigning more nets to a gcell
than the tracks can accommodate. The detailed router
uses the global routing paths as a routing plan.
A Global Routing Cell 9
Global Routing :
So the paths obtained in global routing, detailed routing assigns actual tracks and vias for
nets.

We provide netlist that describes a list of connections by indicating which pins or pads
should be electrically connected to form a set of nets.

Figure (c) shows a result of detailed routing, which determines the exact route for each
net by searching within the tile-to-tile path. Here, the exact route means a path
specified by the actual geometric layout such as metal wires and vias.

Placement with fixed Detailed routing 10

Global routing
locations of blocks and pins
Congestion map: No congestion Markers

In global routing stage it generate a

map of the g-cells, called a
congestion map.

From that map we can see the

approximate number of nets assigned
to the g-cells.

The congestion map uses colors to

indicate whether there are too few,
too many, or the correct number of The vertical lines in the middle of the area and other sides showing congestion region

nets assigned to the g-cells. If the

router assigns too many nets to a
gcell, it marks the g-cell as over
congested.
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Congestion map:

Zoomed view of
previous figure
congestion markers density is high congestion markers density is almost 0 12
Congestion Analysis Table:
The congestion analysis table shows the distribution and severity of congestion in global routing cells
(gcells) on each routing layer.

Following is an example of a Congestion Analysis table:

● The first column (Layer) lists the metal layers that have over-congested g-cells. Tool marks a g-cells
as over congested if the global router has assigned more nets to the g-cell than the g-cell has
available tracks. 13
Congestion Analysis Table:
● The second through fifth columns, labeled OverCon #Gcell, list the number and percentage of g-cells on each
layer that are over-congested.
● The numbers in parentheses after OverCon #Gcell indicate how many additional tracks within the g-cell are
needed to accommodate the global routing assignments. For example, OverCon #Gcell (1 - 2) means that one or
two additional tracks are needed to accommodate all the nets that the global router has assigned the g-cells
listed in the column. As you move from left to right in the table, congestion increases because the difference
between the number of nets assigned to the gcell by the global router and number of available tracks within
the g-cell increases.
● The number of columns in the table is determined by the number of additional tracks needed by the g-cells
with the worst congestion. For example, if the most over-congested g-cells need only four additional tracks,
the table would include columns for 1-2 and 3-4 tracks, but not for 5-6 or more tracks.
● Tool creates only one column for g-cells that need seven or more additional tracks. In the example, all g-cells
that need seven to 12 additional tracks are listed in the column labelled OverCon #Gcell (7 - 12).
● The NanoRoute router displays the maximum number of tracks needed in the last OverCon #Gcell column. In
the example, the maximum number of tracks needed is 12. If some g-cells needed 14 more tracks, the column
would be labelled OverCon #Gcell (7-14). If the maximum number of tracks needed were only eight, the column
would be labelled OverCon #Gcell (7-8).
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Congestion Analysis Table:

● The last column, %Gcell OverCon, lists the percentage of all gcells on the layer that are
overcongested.In the example, on layer Metal 1, only 0.01% of the gcells are over-congested.
● The last row of the table, Total, lists the total number and percentage of over-congested gcells in
each column. In the example, 1,850 gcells in the design, or 0.13% of all gcells, need three or
four more tracks.
● The last row of the last column displays the overall percentage of over-congested gcells in the
design. In the example, 1.39% of all cells are over-congested.
● Following the table NanoRoute summarizes a few key values. The maximum number of tracks
any Gcell needed, the total over congestion number for all layers, and the worst layers Gcell
congestion rate.
● The worst layer Gcell overcon rate is intended to report the routing congestion so the pin access
layer or the layer below the pin access layer is not reported even if it is higher.

Summary : There is no specific number that determines whether the design is routable. In general,
the more columns, and the more the percentages increase toward the right side of the table, the worse
the congestion. 15
Detailed Routing:
After given global routing paths, detailed routing determines the exact tracks
and vias for nets & perform the actual physical interconnections of ASIC design.

It use both vertical and horizontal tracks for actual routing. Those tracks are
defined in the technology file for all layers that are being used.

The detailed router creates shorts or spacing violations rather than leave
unconnected nets.

You can run detailed routing on the entire design, a specified area of the design,
or on selected nets. In addition, you can run incremental detailed routing on a
database that has already been detail routed.

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Detailed Routing:
The router runs continuously search and repair routing during detailed routing.
During search and repair, it locates shorts and spacing violations and again route
the affected areas to eliminate as many of the violations as possible. The
primary goal of detailed routing is to complete all of the required interconnect
without leaving shorts or spacing violations.

The router also runs post route optimization as part of detailed routing. During
post route optimization, it runs more rigorous search and repair steps.

Detailed routing stops automatically if it cannot make further progress on

routing the design

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Detailed Routing:
There are many types of algorithm for detailed routing. We will discuss two most
popular types of detailed routing.

1. Channel routing
2. Full-chip routing
3. Switchbox routing

We will discuss Here only Channel routing in details.

Channel Routing:

Channel routing seeks to minimize the number of tracks required to complete

routing. In gate-array designs, channel height is typically fixed, and algorithms
are designed to pursue 100% routing completion.
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Left-Edge Algorithm:
An early channel routing algorithm was
developed by Hashimoto and Stevens.

Their simple and widely used left-edge

heuristic, based on the VCG (vertical
constraint graph) and the zone
representation, greedily maximizes the
usage of each track.

The former identifies the assignment order

of nets to tracks, and the latter
determines which nets may share the same
track. Each net uses only one horizontal
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segment (trunk).
Left-Edge Algorithm:

Terminology Related to channel routing for a horizontal channel.

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Horizontal Constraints:
● Horizontal Constraint exists between two nets if their trunk overlap each
other.
● In figure given below includes one horizontal and one vertical routing layer,
with nets B and C being horizontally constrained. If the two nets in
horizontal segments do not overlap, then they can both be assigned to the
same track (nets A & B) and are horizontally unconstrained.

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Vertical constraints:
● The vertical constraints can be exist between two nets if they have pins in
same column.
● The vertical net coming from either one side need to be stop before
overlapping the other vertical net.
● In the Figure (a) , net A and B do not have a vertical conflict because
without this combination routing can’t be possible.
● In the Figure (b) , net A and B have a vertical conflict because we are
splitting the vertical segment of one net and using an additional third track.

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Horizontal constraint Graph:
This graphs are used :

For horizontal constraint graph indicate the minimum number of tracks require and the
vertical constraint graph indicates the potential routing conflicts.

We can represent the graph by two type of representation. One is zone and other one is
graphical representation.

1. Zone representation: In a channel, all horizontal wire segments must span at least
the leftmost and rightmost pins of their respective nets. Let S(x) denote the set of
nets that pass through column x . In other words, S(x) contains all nets that either
● Are connected to a pin in column x or
● Have pin connections to both the left and right of column x. Since horizontal
segments cannot overlap, each net in S(x) must be assigned to a different track
in column x.
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Horizontal constraint Graph:
This figure represents a
channel routing problem and
its corresponding zone
representation (green color
box).

Maximum column

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Horizontal constraint Graph:
2. Graphical representation: Figure represents horizontal constraint graph and
the lower bound on the number of tracks is five.

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Vertical constraint Graph:
A directed edge e(i,j) connects nodes i and j if net i must be located above net j.

0 B D E B F G 0 D 0 0
B D F

C E A
A C E C E A F H 0 H G
However, an edge that can be derived by transitivity is not included. In above figure edge (B,C) is not
included because it can be derived from edges (B,E) and (E,C).

G
B D

E F
The Vertical constraint Graph for channel routing

H C A 26
Routing procedure:
● The algorithm is applied on We will take both left edge order and VCG and
together their constraints will be assigned on the tracks and minimizes the
number of tracks required used this algorithm and graph will check if two
nets can be assigned the same track.
● Each net will use one horizontal track

Steps:

1. Sort the nets according to the x coordinate of the left most terminal of the
net.Hence the name of this algorithm is left edge
2. Then we route that nets that order by assigning the first possible track to
each net while honor VCG simultaneously.

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 0 A D E A F G 0 D I J J
Example :
Solve the routing problem.

B C E C E B F H I H G I

Soln : 1st ,find the lowest number of trucks using HCG

1 2 3 4 5 6 7 8 9 10 11 12
0 A D E A F G 0 D I J J S{1} = {B}
B S{2} = {A,B,C}
C S{3} = {A,B,C,D,E} Highest
E S{4} = {A,B,C,D,E} number 5
F S{5} = {A,B,D,E}
G S{6} = {B,F,D}
H S{7} = {F,G,D}
I S{8} = {H,G,D}
D S{9} = {H,I,G,D}
S{10} = {H,I,G}
A J S{11} = {G,I,J}
S{12} = {I,J}
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B C E C E B F H I H G I
 Procedure : A D
J

E i G
2nd, after doing VCG find the order.

Left Edge order= {B,A,C,D,E,F,G,H,I,J }

F
C H

1 2 3 4 5 6 7 8 9 10 11 12
0 A D E A F G 0 D I J J
B

Track 1

Track 2

Track 3

Track 4

Track 5

B C E C E B F H I H G I

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Procedure:
The left-edge algorithm works as follows. Start with the topmost track . For all
unassigned nets, generate the VCG and the zone representation . Then, in
left-to-right order, for each unassigned net n, assign it to the current track if

● n has no predecessors in the VCG and

● it does not cause a conflict with any nets that have been previously
assigned. Once n has been assigned, remove it from nets_unassigned. After
all unassigned nets have been considered, increment the track index.
Continue this process until all nets have been assigned to routing tracks.

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Reference:

[1] VLSI Physical Design : From Graph Partitioning to Timing Closure by Andrew
B.Kahng, Jens Lienig , Igor L. Markov , Jin Hu

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