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List of integrated circuit packaging types

Integrated circuits are put into protective packages to allow easy handling and assembly onto printed
circuit boards and to protect the devices from damage. A very large number of different types of
package exist. Some package types have standardized dimensions and tolerances, and are registered
with trade industry associations such as JEDEC and Pro Electron. Other types are proprietary
designations that may be made by only one or two manufacturers. Integrated circuit packaging is the
last assembly process before testing and shipping devices to customers.

Occasionally specially-processed integrated circuit dies are prepared for direct connections to a
substrate without an intermediate header or carrier. In flip chip systems the IC is connected by solder
bumps to a substrate. In beam-lead technology, the metallized pads that would be used for wire A standard-sized 8-pin dual in-line
bonding connections in a conventional chip are thickened and extended to allow external connections package (DIP) containing a 555 IC.
to the circuit. Assemblies using "bare" chips have additional packaging or filling with epoxy to protect
the devices from moisture.

Contents
Through-hole packages
Surface mount
Chip carrier
Pin grid arrays
Flat packages
Small outline packages
Chip-scale packages
Ball grid array
Transistor, diode, small-pin-count IC packages
Dimension reference
Surface-mount
Through-hole
Package dimensions
Dual row
Quad rows
LGA
Multi-chip packages
See also
References
External links

Through-hole packages
Through-hole technology uses holes drilled through the PCB for mounting the components. The component has leads that are soldered to pads on the
PCB to electrically and mechanically connect them to the PCB.
Acronym Full name Remark
Single in-line
SIP
package
Dual in-line 0.1 in (2.54 mm) pin spacing, rows 0.3 in (7.62 mm) or
DIP
package 0.6 in (15.24 mm) apart.

CDIP Ceramic DIP[1]


Glass-sealed
CERDIP
ceramic DIP[1]
Quadruple in-line
QIP Like DIP but with staggered (zig-zag) pins.[1] Three 14-pin (DIP14) plastic dual in-
package
line packages containing IC chips.
Standard DIP with 0.1 in (2.54 mm) pin spacing, rows
SKDIP Skinny DIP
0.3 in (7.62 mm) apart.[1]
Non-standard DIP with smaller 0.07 in (1.78 mm) pin
SDIP Shrink DIP
spacing.[1]
Zig-zag in-line
ZIP
package

MDIP Molded DIP[2]

PDIP Plastic DIP[1]

Surface mount
Acronym Full name Remark

CCGA Ceramic column-grid array (CGA)[3]

CGA Column-grid array[3] Example

CERPACK Ceramic package[4]

CQGP[5]

LLP Lead-less lead-frame package A package with metric pin distribution (0.5–0.8 mm pitch)[6]

LGA Land grid array[3]

LTCC Low-temperature co-fired ceramic[7]

MCM Multi-chip module[8]

MICRO SMDXT Micro surface-mount device extended technology[9] Example

Chip carrier
A chip carrier is a rectangular package with contacts on all four edges. Leaded chip carriers have metal leads wrapped around the edge of the package,
in the shape of a letter J. Leadless chip carriers have metal pads on the edges. Chip carrier packages may be made of ceramic or plastic and are usually
secured to a printed circuit board by soldering, though sockets can be used for testing.

Acronym Full name Remark

BCC Bump chip carrier[3] -

CLCC Ceramic lead-less chip carrier[1] -

LCC Lead-less chip carrier[3] Contacts are recessed vertically.

LCC Leaded chip carrier[3] -

LCCC Leaded ceramic-chip carrier[3] -

DLCC Dual lead-less chip carrier (ceramic)[3] -

PLCC Plastic leaded chip carrier[1][3] -

Pin grid arrays


Acronym Full name Remark
OPGA Organic pin-grid array -

FCPGA Flip-chip pin-grid array[3] -

PAC Pin array cartridge[10] -

PGA Pin-grid array Also known as PPGA[1]

CPGA Ceramic pin-grid array[3] -

Flat packages
Acronym Full name Remark
- Flat-pack Earliest version metal/ceramic packaging with flat leads

CFP Ceramic flat-pack[3] -

CQFP Ceramic quad flat-pack[1][3] Similar to PQFP

BQFP Bumpered quad flat-pack[3] -

DFN Dual flat-pack No lead[3]

ETQFP Exposed thin quad flat-package[11] -

PQFN Power quad flat-pack No-leads, with exposed die-pad[s] for heatsinking[12]

PQFP Plastic quad flat-package[1][3] -

LQFP Low-profile quad flat-package[3] -

QFN Quad flat no-leads package Also called as micro lead frame (MLF).[3][13]

QFP Quad flat package[1][3] -

MQFP Metric quad flat-pack QFP with metric pin distribution[3]


HVQFN Heat-sink very-thin quad flat-pack, no-leads -

SIDEBRAZE[14][15]

TQFP Thin quad flat-pack[1][3] -

VQFP Very-thin quad flat-pack[3] -

TQFN Thin quad flat, no-lead -


VQFN Very-thin quad flat, no-lead -
WQFN Very-very-thin quad flat, no-lead -
UQFN Ultra-thin quad flat-pack, no-lead -
ODFN Optical dual flat, no-lead IC packaged in transparent packaging used in optical sensor

Small outline packages


Acronym Full name Remark

SOP Small-outline package[1]


Ceramic small-outline
CSOP
package
Thermally-enhanced
HSOP
small-outline package
mini- Mini small-outline
SOIC integrated circuit
Mini small-outline
MSOP
package
Plastic small-outline
PSOP
package[3]
Plastic small-outline no-
PSON
lead package
Quarter-size small-
QSOP The pin spacing are width of 0.635 mm.[3]
outline package
Small-outline integrated
SOIC Also known as SOIC NARROW and SOIC WIDE
circuit
Small-outline J-leaded
SOJ
package
Shrink small-outline
SSOP
package[3]
Thin small-outline
TSOP Example
package[3]
Thin shrink small-outline
TSSOP
package[3]
Thin very-small-outline
TVSOP
package[3]
Similar to a SOIC. (A Maxim trademark example (https://web.archive.org/web/201107140534
µMAX
31/http://datasheets.maxim-ic.com/en/ds/MAX9716-MAX9717.pdf))
Very-very-thin small-
WSON
outline no-lead package

Chip-scale packages

Example WL-CSP devices sitting


on the face of a U.S. penny. A
SOT-23 device is shown for
comparison.
Acronym Full name Remark
Beam lead
BL Bare silicon chip, an early chip-scale package
technology
Chip-scale
CSP Package size is no more than 1.2× the size of the silicon chip[16][17]
package
True chip-
TCSP size Package is same size as silicon[18]
package
True die-
TDSP size Same as TCSP[18]
package
WCSP or Wafer-
WL-CSP level chip-
or scale
WLCSP package
MICRO
- Chip-size package (CSP) developed by National Semiconductor[19]
SMD
Bare silicon chip, that is usually an integrated circuit, is supplied without a package. It can often be
Chip-on-
COB identified by having a blob of black Epoxy instead of a square package. Also used for LEDs. In LEDs, the
board
epoxy is poured into a mold which forms part of the package.
Chip-on-
COF Variation of COB, where a chip is mounted directly to a flex circuit.
flex
Chip-on-
COG Variation of COB, where a chip is mounted directly to a piece of glass - typically an LCD.
glass

Ball grid array


Ball Grid Array BGA uses the underside of the package to place pads with balls of solder in grid pattern as connections to PCB.[1][3]

Acronym Full name Remark

FBGA Fine-pitch ball-grid array A square or rectangular array of solder balls on one surface[3]

LBGA Low-profile ball-grid array Also known as laminate ball-grid array[3]


TEPBGA Thermally-enhanced plastic ball-grid array -

CBGA Ceramic ball-grid array[3] -

OBGA Organic ball-grid array[3] -

TFBGA Thin fine-pitch ball-grid array[3] -

PBGA Plastic ball-grid array[3] -

Mold array process - ball-grid array [2] (http://


MAP-
www.freescale.com/files/dsp/doc/eng_bulleti -
BGA
n/EB362.pdf)
Similar to a BGA (A Maxim trademark example (https://web.archive.org/
UCSP Micro (μ) chip-scale package web/20110714053431/http://datasheets.maxim-ic.com/en/ds/MAX9716-
MAX9717.pdf))[17]
μBGA Micro ball-grid array Ball spacing less than 1 mm

LFBGA Low-profile fine-pitch ball-grid array[3] -

TBGA Thin ball-grid array[3] -

SBGA Super ball-grid array[3] Above 500 balls

UFBGA Ultra-fine ball-grid array[3]

Transistor, diode, small-pin-count IC packages


MELF: Metal electrode leadless face (usually for resistors and diodes)
SOD: Small-outline diode.
SOT: Small-outline transistor (also SOT-23, SOT-223, SOT-323).
TO-XX: wide range of small pin count packages often used for discrete parts like transistors or
diodes.

TO-3: Panel-mount with leads


TO-5: Metal can package with radial leads
TO-18: Metal can package with radial leads
TO-39
TO-46
TO-66: Similar shape to the TO-3 but smaller
TO-92: Plastic-encapsulated package with three leads
TO-99
TO-100
TO-126: Plastic-encapsulated package with three leads and a hole for mounting on a heat
sink
TO-220: Through-hole plastic package with a (usually) metal heat sink tab and three leads
TO-226[20]
TO-247:[21] Plastic-encapsulated package with three leads and a hole for mounting on a heat
sink
TO-251:[21] Also called IPAK: SMT package similar to the DPAK but with longer leads for
SMT or TH mounting
TO-252:[21] (also called SOT428, DPAK):[21] SMT package similar to the DPAK but smaller A drawing of a ZN414 IC in
a TO-18 package
TO-262:[21] Also called I2PAK: SMT package similar to the D2PAK but with longer leads for
SMT or TH mounting
TO-263:[21] Also called D2PAK: SMT package similar to the TO-220 without the extended tab
and mounting hole
TO-274:[21] Also called Super-247: SMT package similar to the TO-247 without the mounting hole

Dimension reference

Surface-mount

C
Clearance between IC body and PCB
H
Total Height
T
Lead Thickness
L
Total carrier length
LW
Lead width
LL
Lead length
P
Pitch

Through-hole

C
Clearance between IC body and board
H
Total height
T
Lead thickness
L
Total carrier length
LW
Lead width
LL
Lead length
P
Pitch
WB
IC body width
WL
Lead-to-lead width

Package dimensions
All measurements below are given in mm. To convert mm to mils, divide mm by 0.0254 (i.e., 2.54 mm / 0.0254 = 100 mil).

C
Clearance between package body and PCB.
H
Height of package from pin tip to top of package.
T
Thickness of pin.
L
Length of package body only.
LW
Pin width.
LL
Pin length from package to pin tip.
P
Pin pitch (distance between conductors to the PCB).
WB
Width of the package body only.
WL
Length from pin tip to pin tip on the opposite side.

Dual row
Image Family Pin Name Package WB WL H C L P LL T LW

6.2– 9.2– 2.54 3.05– 1.14–


8-DIP 7.62 7.7
Dual inline 6.48 9.8 (0.1 in) 3.6 1.73
DIP Y
package 2.54
32-DIP 15.24
(0.1 in)
Lead-frame
LFCSP N chip-scale 0.5
package
0.17–
8-MSOP 3 4.9 1.1 0.10 3 0.65 0.95 0.18
0.27
Mini small-
10- 0.17–
MSOP Y outline 3 4.9 1.1 0.10 3 0.5 0.95 0.18
MSOP 0.27
package
16- 0.17–
3 4.9 1.1 0.10 4.04 0.5 0.95 0.18
MSOP 0.27
5.8– 0.10– 4.8– 0.19– 0.39–
8-SOIC 3.9 1.72 1.27 1.05
6.2 0.25 5.0 0.25 0.46

Small- 5.8– 0.10– 8.55– 0.19– 0.39–


SO 14-SOIC 3.9 1.72 1.27 1.05
outline 6.2 0.25 8.75 0.25 0.46
SOIC Y
integrated 5.8– 0.10– 9.9– 0.19– 0.39–
SOP 16-SOIC 3.9 1.72 1.27 1.05
circuit 6.2 0.25 10 0.25 0.46
10.00– 0.10– 10.1– 0.23– 0.38–
16-SOIC 7.5 2.65 1.27 1.4
10.65 0.30 10.5 0.32 0.40

Small-
SOT-23- 0.22–
SOT Y outline 1.6 2.8 1.45 2.9 0.95 0.6
6 0.38
transistor

Shrink
small-
SSOP Y 0.65
outline
package
Thin dual 0.7– 0.19–
TDFN N 8-TDFN 3 3 3 0.65 N/A
flat no-lead 0.8 0.3
Thin small-
TSOP Y outline 0.5
package
Thin shrink
small- 8- 0.09– 0.19–
TSSOP Y 4.4 6.4 1.2 0.15 3 0.65
outline TSSOP 0.2 0.3
package
Micro
small-
µSOP Y µSOP-8 4.9 1.1 3 0.65
outline
package[22]
US8
US8[23] Y 2.3 3.1 .7 2 0.5
package

Quad rows
Image Family Pin Name Package WB WL H C L P LL T LW

Plastic
PLCC N leaded chip- 1.27
carrier

Ceramic
48-
CLCC N leadless 14.22 14.22 2.21 14.22 1.016 N/A 0.508
CLCC
chip-carrier
Low-profile
LQFP Y Quad Flat 0.50
Package

Thin quad TQFP- 0.35– 0.09– 0.30–


TQFP Y 10.00 12.00 0.80 1.00
flat-package 44 0.50 0.20 0.45

Thin quad
TQFN N
flat no-lead

LGA

Package x y z
52-ULGA 12 mm 17 mm 0.65 mm
52-ULGA 14 mm 18 mm 0.10 mm
52-VELGA ? ? ?

Multi-chip packages
A variety of techniques for interconnecting several chips within a single package have been proposed and researched:

SiP (system in package)


PoP (package on package)
3D-SICs, Monolithic 3D ICs, and other three-dimensional integrated circuits
WSI (wafer-scale integration)
proximity communication[24]

See also
Surface-mount technology
Three-dimensional integrated circuit
Interposer
IPC (electronics)
List of chip carriers
List of electronics package dimensions
Redistribution layer
Surface-mounted package sizes
Wafer-level packaging

References
1. "CPU Collection Museum - Chip Package Information" (http://www.cpushack.com/Packages.html). The CPU Shack. Retrieved
2011-12-15.
2. "Archived copy" (https://web.archive.org/web/20110815143522/http://www.national.com/ms/PA/PACKING_CONSIDERATIONS__ME
THODS__MATERIALS_AND_REC.pdf) (PDF). Archived from the original (http://www.national.com/ms/PA/PACKING_CONSIDERATI
ONS__METHODS__MATERIALS_AND_REC.pdf) (PDF) on 2011-08-15. Retrieved 2011-02-03.
3. "Integrated Circuit, IC Package Types; SOIC. Surface Mount Device Package" (http://www.interfacebus.com/Design_Pack_Type_SO
IC.html). Interfacebus.com. Retrieved 2011-12-15.
4. "National Semiconductor CERPACK Package Products" (https://web.archive.org/web/20120218205030/http://www.national.com/pac
kaging/parts/CERPACK.html). National.com. Archived from the original (http://www.national.com/packaging/parts/CERPACK.html) on
2012-02-18. Retrieved 2011-12-15.
5. "National Semiconductor CQGP Package Products" (https://web.archive.org/web/20071021023517/http://www.national.com/packagi
ng/parts/CQGP.html). National.com. Archived from the original (http://www.national.com/packaging/parts/CQGP.html) on 2007-10-21.
Retrieved 2011-12-15.
6. "National's LLP Package" (https://web.archive.org/web/20110213050709/http://www.national.com/analog/packaging/llp).
National.com. Archived from the original (http://www.national.com/analog/packaging/llp) on 2011-02-13. Retrieved 2011-12-15.
7. "LTCC Low Temperature Co-fired Ceramic" (http://www.minicaps.com/ltcc.html). Minicaps.com. Retrieved 2011-12-15.
8. Frye, R.C.; Gabara, T.J.; Tai, K.L.; Fischer, W.C.; Knauer, S.C. (1993). "Performance evaluation of MCM chip-to-chip
interconnections using custom I/O buffer designs" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=410760). IEEE Xplore -
Performance evaluation of MCM chip-to-chip interconnections using custom I/O buffer designs. Ieeexplore.ieee.org. pp. 464–467.
doi:10.1109/ASIC.1993.410760 (https://doi.org/10.1109%2FASIC.1993.410760). ISBN 978-0-7803-1375-0. Retrieved 2011-12-15.
9. "National Semiconductor Launches New Generation of Ultra-Miniature, High Pin-Count Integrated Circuit Packages" (https://web.arc
hive.org/web/20120218205131/http://www.national.com/news/item/0,1735,1116,00.html). National.com. Archived from the original (h
ttp://www.national.com/news/item/0,1735,1116,00.html) on 2012-02-18. Retrieved 2011-12-15.
10. Meyers, Michael; Jernigan, Scott (2004). Mike Meyers' A+ Guide to PC Hardware (https://books.google.com/?id=mvo5rpAX3RsC&p
g=PT94&lpg=PT94&dq=PAC+%22Pin+Array+Cartridge%22#v=onepage&q=PAC%20%22Pin%20Array%20Cartridge%22&f=false).
The McGraw-Hill Companies. ISBN 978-0-07-223119-9.
11. [1] (http://ir.conexant.com/releasedetail.cfm?ReleaseID=431800) Archived (https://web.archive.org/web/20110818161952/http://ir.co
nexant.com/releasedetail.cfm?ReleaseID=431800) August 18, 2011, at the Wayback Machine
12. "Press Releases - Motorola Mobility, Inc" (http://www.motorola.com/mediacenter/news/detail.jsp?globalObjectId=2791_2269_23).
Motorola.com. Retrieved 2011-12-15.
13. "Xilinx new CPLDs with two I/O banks" (http://www.eetasia.com/ART_8800353559_480100_NP_9b8d1426.HTM). Eetasia.com.
2004-12-08. Retrieved 2011-12-15.
14. "Packages" (http://www.chelseatech.com/packages.htm). Chelseatech.com. 2010-11-15. Retrieved 2011-12-15.
15. "Archived copy" (https://web.archive.org/web/20081120103405/http://cpu.linuxmania.net/liste/cpuinfo/chip-package/SIDEBRAZE_DI
P/chip-package-sidebraze.htm). Archived from the original (http://cpu.linuxmania.net/liste/cpuinfo/chip-package/SIDEBRAZE_DIP/chi
p-package-sidebraze.htm) on 2008-11-20. Retrieved 2009-10-24.
16. "CSP - Chip Scale Package" (http://www.siliconfareast.com/csp.htm). Siliconfareast.com. Retrieved 2011-12-15.
17. "Understanding Flip-Chip and Chip-Scale Package Technologies and Their Applications - Maxim" (http://www.maxim-ic.com/appnote
s.cfm/an_pk/4002). Maxim-ic.com. 2007-04-18. Retrieved 2011-12-15.
18. "Chip Scale Review Online" (http://www.chipscalereview.com/issues/ES/issues/0301/packagingFoundries.html).
Chipscalereview.com. Retrieved 2011-12-15.
19. "Packaging Technology | National Semiconductor – Package Drawings, Part Marking, Package Codes, LLP, micro SMD, Micro-
Array" (https://web.archive.org/web/20100801065223/http://www.national.com/analog/packaging/appnote_msmd). National.com.
Archived from the original (http://www.national.com/analog/packaging/appnote_msmd) on 2010-08-01. Retrieved 2011-12-15.
20. http://www.siliconfareast.com/to226.htm
21. http://www.irf.com/package/
22. http://pdfserv.maximintegrated.com/package_dwgs/21-0036.PDF
23. "Fairchild's TinyLogic family overview" (https://web.archive.org/web/20150108015729/https://www.fairchildsemi.co.jp/collateral/produ
ct_overview/TinyLogic-Device-Product-Overview.pdf) (PDF). March 22, 2013. Archived from the original (https://www.fairchildsemi.c
o.jp/collateral/product_overview/TinyLogic-Device-Product-Overview.pdf) (PDF) on January 8, 2015.
24. Proximity Communication - the Technology (https://web.archive.org/web/20090718081900/http://research.sun.com/spotlight/2004-09
-20.feature-proximity.html), 2004, archived from the original (http://research.sun.com/spotlight/2004-09-20.feature-proximity.html) on
2009-07-18

External links
JEDEC JEP95 (http://www.jedec.org/category/technology-focus-area/jc-10/registered-outlines-jep95) official list of all (over 500)
standard electronic packages
Fairchild Index of Package Information (https://www.fairchildsemi.com/get-help/package-information/)
An illustrated listing of different package types, with links to typical dimensions/features of each (https://web.archive.org/web/201312
15133813/http://www.siliconfareast.com/ic-package-types.htm)
JEDEC JEP95 (https://www.jedec.org/category/technology-focus-area/jc-10/registered-outlines-jep95) official list of all (over 500)
standard electronic packages
Intersil packaging information (http://www.intersil.com/design/packages/)
ICpackage.org (http://www.icpackage.org)
Solder Pad Layout Dimensions (http://catalog.tycoelectronics.com/catalog/common/images/PartImages/chip_res_padsz.jpg)
International Microelectronics And Packaging Society (http://www.imaps.org)

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