INSTRUCTION SET OF

MICROPROCESSOR 8086
 Data Flow

Instructions
 Binary Codes Microprocessor Processed
 Hexadecimal Programs
(Data Processor) Data
Codes
 Mneumonics
 Low Level
Language/Machine
Language
 Hexadecimal Code
language
 Assembly Language Input Data
 High Level Language • Memory
• IO Device
 Assembler, Linker and Loader

Assembly Language
Machine Language
program ASSEMBLER MEMORY
Modules

Object Code:
machine Language
Module 1

Executable:
Object Code: LINKER Machine Language LOADER
machine Language Program
Module 2

Object Code: Object Code:

machine Language machine Language
Library 1 Library 2
Instruction format and sample program
LABEL: OPERANDS (If ; Comments
MNEUMONIC
required) (Optional)
Example: Program to add a series of five words present in memory from address 5000H:2005H
MOV AX, 5000H
MOV DS, AX ; Initialize Data memory segment
MOV CX, 05H
XOR DX, DX
MOV BX, 2005H
XOR AX, AX
CONTINUE_ADD: ADD AX, [BX] ;Adds content of AX with content of memory location
JNC SKIP_CARRY_ACCUM
INC DX
SKIP_CARRY_ACCUM: INC BX
INC BX
DEC CX
JNZ CONTINUE_ADD
MOV [BX], AX
MOV [BX+2], DX
MOV AX, 4C00H
INT 21H
List file: Assembler outputs
===================================================================================================
[LINE] LOC: MACHINE CODE SOURCE
===================================================================================================

[ 1] 0000: B8 00 50 MOV AX, 5000H

[ 2] 0003: 8E D8 MOV DS, AX
[ 3] 0005: B9 05 00 MOV CX, 05H
[ 4] 0008: 33 D2 XOR DX, DX
[ 5] 000A: BB 05 20 MOV BX, 2005H
[ 6] 000D: 33 C0 XOR AX, AX
[ 7] 000F: 03 07 CONTINUE_ADD: ADD AX, [BX]
[ 8] 0011: 73 01 JNC SKIP_CARRY_ACCUM
[ 9] 0013: 42 INC DX
[ 10] 0014: 43 SKIP_CARRY_ACCUM: INC BX
[ 11] 0015: 43 INC BX
[ 12] 0016: 49 DEC CX
[ 13] 0017: 75 F6 JNZ CONTINUE_ADD
[ 14] 0019: 89 07 MOV [BX], AX
[ 15] 001B: 89 57 02 MOV [BX+2], DX
[ 16] 001E: B8 00 4C MOV AX, 4C00H
[ 17] 0021: CD 21 INT 21H
Status Flag Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X OF DF IF TF SF ZF X AF X PF X CF

Status X Undefined
Flags CF Carry Flag, set if carry generated from msb
PF Parity Flag, Set if result has Even Parity
AF Auxiliary Flag set from lower nibble, used for BCD operation
ZF Zero Flag, set if result is zero
SF Sign Flag set is msb is copied (i.e. result is negative)
OF Over flow Flag for signed result, if result is out of range
Control TF Trap Flag; for single stepping Mode
Flags IF Interrupt Flag, set to recognize maskable interrupt request for enabling
interrupt
DF Direction flag for string operation
 Instructions

Function Size Addressing modes

1. One Byte 1. Implicit

1. Data Transfer
(NOP, HLT, WAIT, STI, AAA, DAA, XLAT) (CMA, DAS, AAM, AAA, AAD)
2. Arithmetic
2. Two Byte 2. Register Direct
3. Logical/ Bit
manipulation (MOV CX, BX; MOV DX, [BX]) (MOV Rd,Rs)
4. Branching 3. Three Byte 3. Immediate
5. Stack (MOV CX, 05H; MOV [1234H], AX) (MOV AX, 0105H; MOV R8/R16, IMMD8/IMMD16)
6. Machine Control 4. FOUR Byte 4. Direct
7. Input Output MOV [1234H], CX; (MOV BX, [3456H], MOV [1234H], CL)
8. Flags control MOV DX, [BX+85H]; 5. Register Indirect
9. Iteration Control MOV CX, [BX+1235H]; (MOV DX, [BX/SI/DI])
10. String MOV SP, 3135H 6. Register Relative
Instructions (MOV [BX/BP/SI/DI+8/16 bit disp.], CL)
5. FIVE Byte
(JMP EA16 SBA16; ADD [SI+90H],0AH; 7. Base Index addressing mode
ADD [SI+1290H], 0AH) (MOV [BX/BP+SI/DI], DX)
6. SIX Bytes 8. Relative Base Index addressing Mode
(MOV [BX+9505H], 0BA15H) (MOV DL, [BX/BP+SI/DI+8/16 bit disp])
Addressing Modes:
Addressing Instruction Format
Register MOV AX, BX
Aggressing

Immediate MOV BX, 0F123H

Addressing
Direct MOV CX, [1234h]
Addressing

Register MOV CX, [MOV DX, DS:[BX/SI/DI]

Indirect
Addressing
Addressing Instruction Format
Register MOV CX, DS:[BX/BP/SI/DI+ 8/16
Relative bit disp.]
Addressing

Register Base MOV CX, DS: [BX/BP+SI/DI]

Indexed
Addressing

Register MOV DX, DS: [BX/BP+SI/DI+8/16

Relative Base bit disp]
Indexed
Addressing
Different ways to access memory in 8086
DIRECT AND REGISTER REGISTER RELATIVE REGISTER RELATIVE
INDIRECT ADDRESSING AND REGISTER BASE AND REGISTER BASE
MODE INDEX ADDRESSING INDEX ADDRESSING
MODE WITH 8 BIT MODE WITH 16 BIT
DISPLACEMENT DISPLACEMENT
[EA] [BP+8 bit] [BP+16 bit]
[BX] [BX+8 bit] [BX+16 bit]
[SI] [SI+8 bit] [SI+16 bit]
[DI] [DI+8 bit] [DI+16 bit]
[BX+SI] [BX+SI+8 bit] [BX+SI+16 bit]
[BX+DI] [BX+DI+8 bit] [BX+DI+16 bit]
[BP+SI] [BP+SI+8 bit] [BP+SI+16 bit]
[BP+DI] [BP+DI+8 bit] [BP+DI+16 bit]
Default and specified memory segments
OPERATION MEMORY POINTER DEFAULT SEGMENT SPECIFIED USAGE EXAMPLES FOR
REGISTER SEGMENT SPECIFIED SEGMENT
REGISTER REGISTERS USING SEGMENT
OVERRIDE PREFIX
OPCODE FETCH IP CS - -
STACK OPERATION

USING PUSH/POP SP SS - PUSH REG/MEM

USING MOV MOV CX, [BP],

BP SS CS, ES, DS
INSTRUCTION MOV CX, ES:[BP]
DATA TRANSFER OPERATION
[EA] MOV CX, [EA],
[BX] MOV CX, CS:[DI],
USING MOV DS CS, ES, SS
[SI] MOV CX, ES:[DI]
[DI] MOV CX, SS:[DI]
STRING OPERATION
MOVSB
SOURCE STRING SI DS CS, SS, ES
ES: MOVSB
DESTINATION
DI ES -
STRING
DATA TRANSFER INSTRUCTIONS
 MOV
 PUSH/POP
 XCHG
 XLAT
 LEA REG16, MEM
 LDS REG16, MEM32
 LES REG16, MEM32
 LAHF
 SAHF
 IN/OUT
DATA TRANSFER INSTRUCTIONS
Description/ Meaning Instruction Format Operation
Move content from Source (8/16) to Destination MOV reg16D, reg16S (reg16D) ← reg16S
Save Register content at the top of Stack PUSH reg16 (SP+1) ← (RegH), (SP+2) ← (RegL)
Load Register with data from top of Stack POP reg16 (RegL) ← (SP), (RegH) ← (SP-1)
Exchange byte or word from Reg8/16 or Mem XCHG AX, DX (AX)  (DX)
XCHG DX, [1234] (DX)  [1234]
Content of AL replaced by data at Lookup table XLAT AL ← [(DS)x16 +(BX)+ (AL)]
Load Effective Address of operand into Reg16 LEA reg16, EA (Reg16) ← (EA)
Load DS register and specified Reg16 from LDS reg16, Mem32 (Reg16) ← (Mem16)
Memory (DS) ← (Mem16+2)
Load ES register and other Reg16 from Mem LES reg16, mem16 (Reg16) ← (Mem16)
(ES) ← (Mem16+2)
Load Register AH with 8 LSBs of Flag Register LAHF (AH) ←(SF_LSB), flags not effected
Store Register AH to 8 LSBs of Flag Register Data SAHF (SF_LSB) ← (AH), flags changed
Input from port address[ DX/ DL] reg in Acc IN [DX] (Port addrs) ← (AX/ AL)
Output at Port address [DX/ DL] reg in Acc OUT [DX] (AX/ AL) ← (Port addrs)
MOV INSTRUCTION
 MOV D, S D (8/16) S(8/16)
R R
R MEM
MEM R
R/M IMMDATA
SEGREG (Except CS) R16/MEM16
R16/MEM16 SEGREG

XCHG
 XCHG reg/mem, reg
 XCHG AX, REG16
PUSH/POP instruction
 PUSH reg16/mem16, POP reg16/mem16
 PUSH segreg, POP segreg
STACK MEMORY SEGMENT
 PUSHF, POPF

LA MemLoc LA MemLoc LA MemLoc

7000:0000 7000:0000 7000:0000
7000:0001 7000:0001 7000:0001
7000:0002 7000:0002 7000:0002
************* ************* *************
7000:FFFC 7000:FFFC 7000:FFFC 34H SP=FFFD
7000:FFFD 7000:FFFD 7000:FFFD 12H
7000:FFFE 7000:FFFE 78H SP=FFFE 7000:FFFE 78H
7000:FFFF 7000:FFFF 56H 7000:FFFF 56H

MOV SP, 0000H MOV BX, 1234H

MOV DX, 5678H PUSH BX
PUSH DX
LEA: Load Effective address EFFECTIVE
ADDRESS of
16 BIT
Register 16
ADDRESS
 Load effective address of the given memory
memory operand in 16 bit register operand
 LEA R16, MEM
 example: LEA BX, [1234H]: BX<-1234H MOV BX, OP1 ; BX  1234H
 LEA SI, [BP+1234H]: SI<-BP+1234H LEA BX, OP1; BX  0000H
MOV BX, OFFSET OP1; BX  0000H
 Examples with assembler directives
LEA BX, OFFSET OP1
Data_Seg SEGMENT Let: BP=7000H & SI=1000H
OP1 DW 1234H LEA BP, 95H[BP+SI]; BP  7F95H
Data_Seg ENDS

LABEL [EA] MEM Data_Seg=Segment Base

VALUE VALUE address of the intended
OP1 [0000H] 34H memory segment
MOV BX, OP1 => MOV BX, [0000H]
OP1+1 [0001H] 12H LEA BX, OP1+1 => LEA BX, [0001H]: BX0001H
LDS and LES
MOV DI, 0000H
LDS SI, [DI]

 LDS R16, MEM32 EA MEMORY

SI
 Load specified 16 bit register 0000H 12H
and DS register with 32 bit data 16 BITS 3412H
0001H 34H
pointed by memory operand
MEM32, Example: LDS SI, [DI] 0003H 56H
 LES R16, MEM32 0004H 78H 16 BITS 7856H

 Load specified 16 bit register 0005H 9AH DS

and ES register with 32 bit data
pointed by memory operand
MEM32
LAHF & SAHF
 LAHF: Load Register AH with 8 LSBs of Flag Register Data. No flags are
Changed

Lower 8 bits of
16 bit flag AH
register

 SAHF: Store Register AH to 8 LSBs of Flag Register Data. All 8085 flags are
Changed

Lower 8 bits of
AH 16 bit flag
register
XLAT

 Translate or convert any 8 bit old code into any other 8 bit new code using
codes look up table
 This is a specialized data transfer instruction to read new code from lookup
table whose position is indexed by the value of old code
MOX AX, 7000H
LA Memory DS=7000H MOV DS, AX
XXXX:XXXX XX BX=0000H MOV BX, 0000H
7000:0000H FCH AL=04H MOV AL, 04H
XLAT
7000:0001H 60H HLT
7000:0002H DAH
7000:0003H F2H XLAT AL
7000:0004H 66H 66H
7000:0005H B6H
DS:[BX+AL] AL
XXXX:XXXX XX
Steps of initializations before using XLAT
 Transfer SBA of DMS in DS register
 Initialize LUT in DMS
 Load the EA of the starting location of LUT in register BX
 The 8 bit old code for which we have to obtain new code should be stored in
AL

A program to read an LUT that starts from PA 65007H and read new code for the old code
02h:

MOX AX, 6500H

MOV DS, AX
MOV BX, 0007H
MOV AL, 02H
XLAT
HLT
Using Assembler Directives
; multi-segment executable file template.
;;A program to convert a BCD number from 0-5 into excess-3 code using look up table approach
Data_segment SEGMENT
; add your data here!
LUT DB 30h, 31h, 32h, 33h, 34h, 35h
OC EQU 03h
NC DB ?
Data_segment ENDS

Code_segment SEGMENT
ASSUME CS: Code_segment, DS: Data_segment
start:
; set segment registers:
MOV AX, Data_segment
MOV DS, AX
; add your code here
LEA BX, LUT
MOV AL, OC
XLAT
MOV NC, AL

MOV AX, 4C00h ; exit to operating system.

INT 21h
Code_segment ENDS

END start ; set entry point and stop the assembler.

ASSEMBLER DIRECTIVES
 ORG address
 DB, DW, DD, DQ, DT
 Label DB expression
 OP1 DB 31H, 45H, 39H
 OP1 DB 31H+49H
 OP1 DB ?
 DUP
 OP1 DB 10DUP(05H)
 OP1 DW 10DUP(?)
 EQU (OP1 EQU 15)
 OFFSET
 MOV BX, OFFSET LUT
 PTR (INC WORD PTR [SI])
 SEGMENT
 ENDS
 END
 ASSUME
 PROC
 ENDP
 EXTERN
 GLOBAL
ARITHMATIC INSTRUCTIONS

 ADD, ADC, DAA, AAA

 SUB, SBB, DAS, AAS
 MUL, IMUL, AAM
 DIV, IDIV, AAD
 CMP, NEG
 INC, DEC
 CBW, CWD
Addition 8/16 bit

D(8/16) S(8/16)
 Addition (8/ 16 bit)
REG MEM
 ADD D, S
MEM REG
 ADC D, S
REG REG
 DAA
REG DATA
 AAA
MEM DATA
(i) ADD D, S
 Operation
 D←D+S
 All flags are affected
(ii) ADC D, S
 Operation
 D←D+S+CF (carry flag)
 All flags are affected
DAA (Decimal adjust after addition)
(iii) DAA
1. Decimal Adjust after Addition
2. Used to convert Binary addition results of Packed BCD numbers into
a valid BCD addition results in Packed BCD format.
3. Implicit addressing mode. Modifies the data of AL.
4. Used after ADD/ADC instructions

Binary Addition result of Valid BCD Addition result in

Packed BCD numbers Packed BCD format
DAA

Logic
1. If (Lower Nibble of AL) > 9 or AC=1
Then:
- Add 6H to lower nibble of AL
- Make AC=1
2. If (Higher nibble of AL) >9 or CF = 1
Then:
- Add 6H to higher nibble of AL
- Make CF = 1
Example

 39H+42H should give using ADD instruction a binary addition result of 7BH.
 However if 39H and 42H are indicated as their BCD equivalents; 39D and 42D
respectively, then the results of addition of these two BCD numbers should
have been 81H.
 However, addition of these two BCD numbers in microprocessor using ADD
instruction will be 7BH, which is an invalid BCD result.
 Invoking the DAA, will adjust the invalid BCD result, 7BH in AL; into a valid
BCD addition result in packed BCD format i.e. 81H.
Example Program for DAA
 Theoretical result of BCD result 39D+42D=81D
Data_Seg SEGMENT
OP1 DB 39H, 42H
RES DB 2DUP (?)
Data_Seg ENDS

Code_Seg SEGMENT
ASSUME CS: Code_Seg, DS: Data_Seg
Start:MOV AX, Data_Seg
MOV DS, AX
MOV AL, OP1
ADD AL, OP1+1
DAA
MOV AH, 00H
ADC AH, 00H
MOV RES, AL
MOV RES+1, AH
MOV AX, 4C00H
INT 21H
Code_Seg ENDS
END Start
Illustrative Programs
 Add two decimal numbers 89 and 42 present in extra memory segment
from EA 3000H. Store the result in extra memory segment

Extra_Seg SEGMENT
OP1 DB 89H, 42H
RES DB 2 DUP ?
Extra_Seg ENDS

Code_Seg SEGMENT
ASSUME CS: Code_Seg, ES: Extra_Seg
Start:MOV AX, Extra_Seg
MOV ES, AX
MOV AL, ES: OP1
ADD AL, ES: OP1+1
DAA
MOV AH, 00H
ADC AH, 00H
MOV ES: RES, AL
MOV ES: RES+1, AH
MOV AX, 4C00H
INT 21H
Code_Seg ENDS
END Start
 Code_Seg SEGMENT
Illustrative Programs ASSUME CS: Code_Seg, DS: Data_Seg, ES: Extra_Seg
Start: MOV AX, Data_Seg
 Store two 100 digit DECIMAL numbers in MOV DS, AX
data memory segment using assembler MOV AX, Extra_Seg
directives. Write a program to add these MOV ES, AX
two numbers and store the result of LEA SI, OP1
addition in extra memory segment. LEA BX, OP2
 100 digit decimal number in packed BCD LEA DI, Res
format means 50 bytes of data. As 2 MOV CL, 32H
decimal digits takes one Byte in packed CLC
BCD format(e.g 99D is represented in HORZADD:MOV AL, [SI]
packed BCD format as 99H) (remember in
ADC AL, [BX]
Unpacked BCD format 1 decimal digit is
represented as a 1 Byte BCD, e.g 99 D is
DAA
represented as 0909H). Therefore, As a MOV ES:[DI], AL
solution to the first part of the program, INC SI
Use assembler directive DB (Define Byte) INC BX
to store 50 bytes of data. INC DI
DEC CL
 Solution:
JNZ HORZADD
Data_Seg SEGMENT MOV AH, 00H
OP1 DB 50 DUP (89H) ADC ES:[DI], 00H
OP2 DB 50 DUP (42H) MOV AX, 4C00H
Data_Seg ENDS INT 21H
Extra_Seg SEGMENT Code_Seg ENDS
Res DB 51 DUP (?) END Start
Extra_Seg ENDS
AAA
 ASCII Adjust after Addition Logic
 Used to convert Binary addition results 1. If (Lower Nibble of AL) > 9 or AC=1
of ASCII numbers into a valid BCD Then:
addition results in unpacked BCD format. • Add 6H to lower nibble of AL
 Implicit addressing mode. Modifies the • Make AC=1 and CF = 1
data of AL. • AH = AH+1 (Increment AH)
 Used after ADD/ADC instructions 2. Mask the higher nibble of AL

Binary Addition result of Valid BCD Addition results

single digit ASCII in Unpacked BCD format
numbers (AL) (AH, AL)
Example Program: Add two single digit ASCII numbers 9 and 4 present in data memory segment and store
the result after the operands
LABEL INSTRUCTIONS COMMENTS
Data_Seg SEGMENT Start declaration of logical segment named Data_Seg
OP1 DB ‘9’ or OP1 DB 39H Declare 1 memory location for ASCII 9 EA [0000h], Thus
OP1=[0000H].
OP2 DB ‘4’ or OP1 DB 34H Declare 1 memory location for ASCII 4.
OP3 DB 2DUP (?) Reserve 2 bytes for result of ASCII sum
Data_Seg ENDS END declaration of logical segment named Data_Seg

Code_Seg SEGMENT Start declaration of logical segment Code_Seg

ASSUME CS: Code_Seg, DS: Data_Seg Tell the assembler to link logical segments named Code_Seg with
Code memory segment, Data_Seg with Data memory segment. Thus,
Data_Seg label is assigned the SBA of DMS, Code_Seg label is
assigned the SBA of CMS
Start: MOV AX, Data_Seg AX←SBA of DMS,
MOV DS, AX Populate the segment register DS
MOV AL, OP1 As OP1=[0000H], also eq. to MOV AL, [0000H]
ADD AL, OP2 AL← AL+[0001H], AL=6DH
MOV AH, 00H AH←00H, this step is important for carry collection in AH, this step
must be done before invoking AAA to collect final carry
AAA AL=03H, AC=1, CF=1, AH=01H(auto-incremented when ac=cf=1
occurs)
MOV Word Ptr OP3, AX OP3 is a byte pointer. Cast it as a word pointer and shift the
contents of OP3 and OP3+1 to AL and AH respectively at one go!!
Otherwise following instructions had to be used:
MOV OP3, AL
MOV OP3+1, AH
ADD AX, 3030H Convert UPBCD result into ASCII number
MOV AX, 4C00H
INT 21H
Code_Seg ENDS
END Start
Example program: Perform ASCII addition of 2 digit ASCII numbers
in DMS and store the result in EMS
Data_Seg SEGMENT MOV AL, OP1 MOV ES:OP3+2, AH; Store
OP1 DB '4', '1'; Note the Order of data ADD AL, OP2 final carry
entry: LSB first AAA ADD ES:OP3, 30H
OP2 DB '7', '3' MOV ES:OP3, AL; NOTE THE ADD WORD PTR ES:
Data_Seg ENDS SEGMENT OVERRIDE PREFIX AS OP3 IS OP3+1, 3030H
EQUIVALENT TO [EA] MOV AX, 4C00H
Extra_Seg SEGMENT MOV AL, OP1+1 INT 21H
OP3 DB 3 DUP(?) ADC AL, OP2+1; add with carry Code_Seg ENDS
Extra_Seg ENDS flag END Start
MOV AH, 00H; Note the use of this
Code_Seg SEGMENT statement to collect final carry, AH
ASSUME CS: Code_Seg, DS: Data_Seg, was also affected in earlier AAA
ES: Extra_Seg invocation but we do not bother to
START: MOV AX, Data_Seg collect last carry as CF was added in
MOV DS, AX the current addition
MOV AX, Extra_Seg AAA
MOV ES, AX MOV ES: OP3+1, AL
DAS: Decimal Adjust after subtraction
 Decimal Adjust after Subtraction Logic
 Used to convert Binary subtraction results of Packed 1. If (Lower Nibble of AL) > 9 or AC=1
BCD numbers into a valid BCD subtraction results in Then:
Packed BCD format.
Subtract 6H from lower nibble of AL
 Implicit addressing mode. Modifies the data of AL. Make AC=1
 Used after SUB/SBB instructions 2. If (Upper nibble of AL) >9 or CF = 1
 Negative result is expressed in 10’s complement Then:
format Subtract 6H from upper nibble of AL
Make CF=1

Binary Subtraction Valid BCD Subtraction

of Packed BCD result in Packed BCD
numbers format

Note:
(i) If after the execution of DAS instruction, CF=0 the result of subtraction is +ve
(ii) If after the execution of DAS instruction, CF=1, then the result of subtraction is –ve and the result is
obtained in 10’s complement form. (10’s complement method is decimal analogue of 2’s complement
method)
Example: Write a program to store 4 bytes of two multi-byte decimal
numbers in DMS. Write a program to subtract these two numbers and Store
the results in EMS
Data_seg segment iter: mov al, [si]
; add your data here! sbb al, [bx]
op1 db 4 dup (39h) das
op2 db 4 dup (42h) mov es:[di], al
Data_seg ends inc si
Extra_seg segment inc bx
op3 db 5 dup(?) inc di
Extra_seg ends loop iter
mov al, 0
code segment adc al, 0
start: mov es:[di], al; Store
; set segment registers: last borrow
mov ax, Data_seg
mov ds, ax mov ax, 4c00h ; exit to
mov ax, Extra_seg operating system.
mov es, ax int 21h
lea si, op1 code ends
lea bx, op2 end start
lea di, op3
clc
mov cx,04h
 AAS (Ascii adjust after addition)
 ASCII Adjust after Subtraction Logic
 Used to convert Binary subtraction results of ASCII 1. If (Lower Nibble of AL) > 9 or AC=1
numbers into a valid BCD subtraction result in Then:
unpacked BCD format. Subtract 6H from lower nibble of AL
 Implicit addressing mode. Modifies the data of AL. Make AC=1 and CF = 1
AH = AH-1 (Decrement AH)
 Used after SUB/SBB instructions
2. Mask the higher nibble of AL
 If the subtraction result is negative the
difference is obtained in 10’s complement
format.

Binary Subtraction Valid BCD Subtraction

results of single digit results in Unpacked BCD
ASCII numbers (AL) format (AH, AL)

Note (Let, AH is initially 00H):

(i) If after the execution of AAS instruction, AH=00h, then the result of subtraction is +ve
(ii) If after the execution of AAS instruction, AH=FFh, then the result of subtraction is –ve and the result is
obtained in 10’s complement form.
A Program to subtract two 10 byte ascii numbers
data segment
; add your data here! lea si, op1
op1 db 10 dup ('9') lea bx, op2 lea di, op3
op2 db 10 dup ('4') lea di, op3 mov cx, count+1
count equ $-op2 clc iter2: add es:[di], 30h ; Convert the
ends mov cx,count result in ASCII format
mov ah, 0 inc di
extra segment
iter: mov al, [si] loop iter2
op3 db count+1 dup(?)
ends
sbb al, [bx]
aas mov ax, 4c00h ; exit to operating
stack segment mov es:[di], al system.
dw 128 dup(0) inc si int 21h
ends inc bx ends
inc di end start ; set entry point and stop the
code segment loop iter assembler.
start:
; set segment registers:
mov ax, data
mov ah, 0
mov ds, ax adc ah, 0
mov ax, extra mov es:[di], ah
mov es, ax
AAM
 ASCII adjust after multiplication
 Implicit addressing mode
 Works only for single digit BCD operands in UPBCD format

Binary Multiplication Valid BCD Multiplication

result of single digit results in Unpacked BCD
UPBCD numbers in AL format (AH, AL)
QUOTIENT
Note: AL AH
When two BCD digits for e.g. 09h and 09h are
(0A)H REMAINDER
multiplied, the BCD multiplication result should be
AL
81h. However actually, the result of binary
multiplication will be 51h. The execution of AAM 08H
converts the binary number 51h into 0801H, i.e. in 51H AH
UPBCD format. The AAM uses following Logic for (0A)H 01H
conversion: AL
Example:
MOV AL, ‘9’; AL←39H
MOV AH, ‘9’; AH←39H
SUB AX, 3030H; Digits in UPBCD format
MUL AH; AH×AL= , AC=OF=0
AAM; AH←51H/0AH, AL←51-(51/0AH),

Note: AAM is also used to convert any binary number less than or equal to 63h in
AL into an UPBCD (0909h) number in AX.
Problems:
 The problems involving AAM instruction could take one of the following
forms:
1. Multiply two ASCII numbers and represent result in ASCII
 Steps: subtract 30h from operands, multiply two operands and get product in AL, AAM and then
ADD 3030H with the AX
2. Multiply two UPBCD numbers and represent result in UPBCD
 Steps: Multiply two UPBCD operands and get product in AL, AAM
3. Multiply two UPBCD numbers and represent result in packed BCD
 Steps: Multiply two UPBCD operands and get product in AL, AAM, and convert UPBCD result to
packed BCD
4. Convert Binary or Hexadecimal number (00H to 63H) to decimal/Packed BCD numbers
(00D-99D)
 Steps: Load the hex number in AL, AAM, Convert UPBCD number in AX to Packed BCD number in
AL
AAD
 ASCII adjust before division
 Implicit addressing mode
 Converts a UPBCD number in AX into a Binary number in AL
 This instruction is called before the division process.
 Result obtained will be correct if the quotient is of single
digit that is from 0-9.
 Logic
(i) AH × (0A)H + AL → AL & (ii) AH←00H

 Example:
0402h is the UPBCD representation of 42D. The binary
representation of 42D is 2AH. Invocation of AAD on 0402H (in AX)
data will change the value of AL to 2AH and AH will be reset.
Given following code:
MOV AX, 0402H
00H 04h × (0A)H+02H = 2AH
AAD
AH AL
Results in following operation on AH and AL
Problem variations:
 Conversion of a 2 digit ASCII number into binary:
E.g. Convert ASCII 94 into binary
MOV AH, ‘9’
MOV AL, ‘4’
SUB AX, 3030H
AAD
 Conversion of 2 digit UPBCD number into binary:
Convert UPBCD of 94d in binary
MOV AX, 0904h
AAD
 Conversion of 2 digit decimal number (Packed BCD) into binary:
MOV AL, 94H
MOV AH, AL
AND AL, 0FH; AL=04H
AND AH, F0H; AH= 90H
MOV CL, 04H; load shift count value
SHR AH, CL; AL=09H, Shift logical right AH data across by 4 bit positions
AAD; AL now contains binary of 94D.
Byte and word extension instructions

 Required for size extension of signed numbers

 Generally used for signed division and multiplication
 CBW (converts a byte in AL to a word in AX by copying the MSB of lower byte
into all the bits of higher byte)
 CWD (converts a word in AX to a word in DX-AX by copying the MSB of lower
word into all the bits of higher word)
 Example: To divide a
 MOV AL,-14
 MOV CL, 2
 CBW
 IDIV CL
MUL S
 S (reg8/16)/mem(8/16)
 Used for multiplication of Unsigned numbers. The range of results will be 0-
(216-1) (for 16 bit result) or 0-(232-1) (for 32 bit result)
 The content of accumulator(AL for 8 bit operand/or AX for 16 bit operand)
and register/memory (8/16) bit are multiplied and result is stored in AX (for
16 bit result) or DX-AX pair (for 32 bit result in case of multiplication of 16 bit
operands).
For byte operands
MUL reg8/mem8
(AX)←(AL)×(reg8/mem8)
For word operands
MUL reg16/mem16
(DX-AX)←(AX)×(reg16/mem16)
Note: How the Flags are affected during MUL instruction
(i) For 16 bit result (for 8 bit operands), the higher order byte of result is stored in AH and
lower byte in AL.
a) When AH ≠00h then CF=OF=1 and the full 16 bit data in AX is considered as the result.
b) If AH=00H and CF=OF=0 then the magnitude of the result spans less than or equal to 8 bits of
AL; In other words, the result is confined within AL.
c) Thus whenever the size of the magnitude crosses 8 bits of AL then CF & OF becomes 1.
(ii) For 32 bit result, the higher order word of result is stored in DX and lower word in AX.
a) When DX ≠0000h then CF=OF=1, which means that the result has crossed the size of AX. In
this case, whenever the size of the result crosses 16 bits of AX then CF & OF becomes 1. The
product is considered spanning full 32 bits of DX-AX pair.
b) However, when DX =0000h then CF=OF=0, which means that the magnitude of result has not
crossed the size of AX. Thus the data in AX may be considered as the product.
c) In summary, whenever the size of result crosses 16 bits of AX then CF & OF becomes 1 and
we have to consider the product as full 32 bits of DX-AX pair.
Program: Multiply the content of DL and SI.

 Soln:
8 bit register cannot be multiplied with 16 bit register.
 Thus the unsigned data of 8 bit register has to be extended to 16 bit.
 Data Extension rule: Zero Padding for unsigned data
 MUL instruction expects unsigned operands; hence the higher order byte of
16 bit equivalent of data in DL has to be composed of all zeroes.
 Codes
MOV AH, 00H
MOV AL, DL
MUL SI; Product in DX-AX pair
IMUL (reg8/16)/mem(8/16)
 Used for multiplication of Signed numbers. The range of signed results will be –(215)--0--+(215-1) (for
16 bit result, i.e. during multiplication of 8 bit operands) or -(231)--0--+(231-1) (for 32 bit result, i.e.
during multiplication of 16 bit operands).
 The operands/results should be stored in registers or memory in a sign extended binary in 2’s
complement format. The result obtained would be in twos complement format for negative numbers.
The MSB of result and operand indicates the sign; 1-negative, 0-positive.
 The content of accumulator(AL for 8 bit operand/or AX for 16 bit operand) and register/memory
(8/16) bit are multiplied and result is stored in AX (for 16 bit result) or DX-AX pair (for 32 bit result in
case of multiplication of 16 bit operands).
 For byte operands
MUL reg8/mem8
 (AX)←(AL)×(reg8/mem8)
 For word operands
MUL reg16/mem16
 (DX-AX)←(AX)×(reg16/mem16)
Note: How the Flags are affected during IMUL instruction
(i) For 16 bit result (for 8 bit operands), the higher order byte of result is stored in AH and
lower byte in AL.
a) When the data of AH is not the sign bit extension of AL then CF=OF=1, which means
that the magnitude of result is larger than 8 bits of AL. In this case the data of AX is
the result.
b) if AH is composed of sign bit extension of AL, then CF=OF=0, which means that the
magnitude of signed result is confined within AL. In this case the data of AL may be
considered as the product.
c) Thus whenever the size of the signed product crosses 8 bits of AL then CF & OF becomes 1.
(ii) For 32 bit result, the higher order word of result is stored in DX and lower word in AX.
a) When the data of DX is not the sign bit extension of AX then CF=OF=1, which means
that the magnitude of result is larger than 16 bits of AX. In this case the data of DX-
AX pair is the result
b) if DX is composed of sign bit extension of AX, then CF=OF=0, which means that the
magnitude of signed result is confined within AX.
c) In summary, whenever the size of the signed product crosses 16 bits of AX then CF & OF
becomes 1 and we have to consider the product as full 32 bits of DX-AX pair.
Prog: Perform multiplication of 8-bit signed number in with a 16
bit signed number present in DMS. Store 32 bit signed result in
DMS
Data SEGMENT
OP1 DB -12
OP2 DW 3456H
OP3 DD ?
Data ENDS

Code SEGMENT
ASSUME CS: Code, DS: Data
Start: MOV AX, Data
MOV DS, AX
MOV AL, OP1
CBW; CONVERT SIGNED BYTE TO WORD BY SIGN BIT EXTENSION
IMUL OP2
MOV WORD PTR OP3, AX
MOV WORD PTR OP3+2, DX
MOV AX, 4C00H
INT 21H
Code ENDS
END Start
DIV S NOTE:
1. If the quotient exceeds the size of
 S (reg8/16)/mem(8/16), Not Immediate Data destination register like AL and AX
 No flags are changed then INTO (8086 dedicated
interrupt 4; INT 4, for division
 Division of unsigned operands and the result is also unsigned overflow error) is executed. The
subprogram of INTO is used to
Case1: 16 bit number divided by 8 bit number display error message on output
screen regarding division overflow.
REMAINDER(8 bits) 2. If a valid quotient is obtained, the
AX (16 bit accumulator) AH 8/16 bit quotient is obtained in AL
Source register/memory QUOTIENT (8 bits) or AX respectively
(8 Bits) AL

Case 2: 32 bit number divided by 16 bit number

DX-AX (16 bit REMAINDER(16 bits)

accumulator) DX
Source register/memory QUOTIENT (16 bits)
(16 Bits) AX
IDIV S
 S (reg8/16)/mem(8/16), Not Immediate Data
 No flags are changed
 Division of signed operands and the result is also signed. Thus the
data and result is in 2’s complement format.
 Sign of the remainder will always be same as the sign of the
numerator (Dividend)

Case1: A 16 bit signed number divided by an 8 bit signed number

Signed Remainder (8 bits)

16 bit signed Dividend (AX) AH
8 Bit Signed Divisor (S8) Signed Quotient (8 bits)
AL

Case 2: A 32 bit signed number is divided by 16 bit signed number

Signed Remainder (16 bits)

32 bit signed Dividend (DX-AX) DX
16 Bit Divisor (S16) Signed Quotient (16 bits)
AX
Note: Division Overflow

 If 8 bit signed quotient is within +127D to -128D then microprocessor

stores quotient and remainder in AX (for 16 bit Dividend) and
microprocessor continues execution of subsequent instructions.
 If 16 bit signed number is within +32767D to -32768D then
microprocessor stores quotient and remainder in AX and DX respectively
(for 32 bit Dividend) and microprocessor continues execution of
subsequent instructions.
 If the range of signed quotient exceeds the designated range (+127D to
-128D for 8 bit dividend and +32767D to -32768D for 32 bit dividend)
then microprocessor will not store quotient, remainder instead it will
execute ISR for division overflow interrupt (INTO).
Program: Perform the division of two signed words stored
in DMS, Store the result in same memory space.
 Solution: Data SEGMENT
OP1 DW 3000H
As it is mentioned that, OP2 DW 0030H
Data ENDS
the operands are 16 bit
signed numbers: Code SEGMENT
ASSUME CS: Code, DS: Data
we have to perform the Start: MOV AX, Data
MOV DS, AX
sign bit extension of MOV AX, OP1
CWD
numerator to make it 32 IDIV OP2
MOV OP1, AX
bits using CWD (convert MOV OP2, DX
word to double word by MOV AX, 4C00H
INT 21H
sign bit extension). Code ENDS
END Start
Program: Write a program to perform the division of X/Y, where
X is a two digit ASCII number and Y is a single digit ASCII number
present in DMS. Store the ASCII result in DMS.
data segment mov ax,op1
op1 dw '14' xchg ah,al
op2 db '5' sub ax,3030h
op3 dw ? sub op2, 30h
ends aad
div op2
code segment add ax,3030h
start: mov op3, ax
; set segment registers:
mov ax, data mov ax, 4c00h ; exit to operating system.
mov ds, ax int 21h
mov es, ax ends
end start ; set entry point and stop the assembler.
Increment and Decrement operation
 INC S [S=R(8/16)/M(8/16)]
 S=S+1
 DEC S [S=R(8/16)/M(8/16)]
 S=S-1
 Note:
 DEC BX means BX=BX-1. The content of BX (which is of 16 bits is decreased by 1)
 But DEC Byte Ptr [BX] means 1 Byte data present in memory location with effective
address pointed by BX is decremented by 1.
 But DEC Wrods Ptr [BX] means 2 Byte data present in memory locations with effective
address pointed by BX and BX+1 will be decremented by 1.
 DEC [BX] is an INVALID instruction!! The size of data in memory must be indicated by
using PTR assembler directive
 DEC IP in a WRONG Instruction too!!
 All conditional flags are affected except Carry Flag
CMP X, Y
 Compares two operands
 During execution of CMP instruction, microprocessor internally invokes the
subtraction of Y from X (X-Y),
 Affects the status flags according to the result obtained in ALU.
 However, the subtraction result is not stored in any register or memory that user
has indicated along with the instruction.
 CMP instruction is used to compare the relative magnitudes of unsigned and signed
numbers.
 Examples of Usage
 CMP AL, BL
 CMP AX, [MEM]
 CMP Word Ptr [SI], Data 16
 CMP Byte Ptr [SI], Data 8
 CMP [SI], Data 16: NOT ALLOWED, THE SIZE OF MEMORY DATA IS NOT SPECIFIED
Instruction Example : CMP AL, BL
 If the data in AL and BL are known to be unsigned numbers:
 Then
 Data in AL > Data in BL is known by observing CF=0, ZF=0
 Data in AL < Data in BL is known by observing CF=1, ZF=0
 Data in AL = Data in BL is known by observing CF=0, ZF=1
 If the data in AL and BL are known to be signed numbers:
 Then
 Considering No Overflow condition: OF=0)
 Data in AL > Data in BL is known by observing SF=0, OF=0, ZF=0 (SF XOR OF) =0 [AL=127, BL=1]
 Data in AL < Data in BL is known by observing SF=1, OF=0, ZF=0 (SF XOR OF) =1 [AL=-128, BL=-1]
 Data in AL = Data in BL is known by observing SF=0, OF=0, ZF=1
 Considering the condition of OVERFLOW happened (OF=1):
 Data in AL > Data in BL is known by observing SF=1, OF=1, ZF=0 (SF XOR OF) =0 [AL=127, BL=-1]
 Data in AL < Data in BL is known by observing SF=0, OF=1, ZF=0 (SF XOR OF) =1 [AL=-128, BL=1]
 Data in AL = Data in BL is known by observing SF XOR OF=0, ZF=1
 Logical instructions
Instructio Comment D(8/16) S(8/16)
ns R M
AND D, S D←D.S; Bit by bit AND M R
OR D, S D←D+S; Bit by bit OR R R
R/M Data
XOR D, S D←D xor S; Bit by bit XOR

NOT S S←Not S; Invert each bit of S (8/16 bit

register or memory)

TEST D, S The result of D.S (Only affects flags and result

is not stored in D).

CF=0, OF=0,AC=Not Affected, Rest of the status flags are modified according to the result
 Rotate and shift instructions
SAL Reg/Mem(8/16), 1
 Shift Operation in 8086: SAL Reg(8/16), CL
 Shifts the byte or word in a register/Memory by one or
multiple places.
 Last outgoing bit is copied to CF and rest outgoing bits
are lost AH
 Incoming bits are predefined to either zero or sign bit 1 0 1 1 1 0 0 1 =-71
 SAL (Shift arithmetic left)
 SAR (Shift arithmetic right)
 SHL (Shift Logical left, Incoming bit is always zero, Same MSB 1 1 0 1 1 1 0 0 1
as SHL)
 SHR (Shift logical right, Incoming bit is always zero) CF
SAR AH, 01
0 0 1 1 1 0 0 1 =-36
=57 Note for SAR
1. The conservation of sign bit for shift arithmetic
right operation. Incoming bit is the sign bit
2. The division by 2 of the number
1 0 1 1 1 0 0 1 0 0 Note for SAL
1. Incoming bit is always 0
=114
2. The multiplication by 2 of the number
CF SAL AH, 01
Rotate Instructions
 ROR (Rotate right without carry)
 ROL (Rotate left without carry) ROR Reg/Mem(8/16), 1
ROR Reg(8/16), CL
 RCR (Rotate right with carry)
 RCL (Rotate left with carry)
AH
B7 B6 B5 B4 B3 B2 B1 B0 CF

ROR AH, 01

RCR AH, 01
B7 B6 B5 B4 B3 B2 B1 B0 AH

CF
Summary of shift instructions
Instructions Feature of instructions
Shift Arithmatic Left
SAL • Shift arithmetic left the 8/16 bit data in Register/Memory specified.
• Outgoing bit is MSB. Thus, MSB is copied into CF.
• New bits inserted at LSB position is 0.
• Has an effect of multiplication by 2Shift Count.
Shift Logical Left
SHL • Shift Logical left the 8/16 bit data in Register/Memory specified.
• Outgoing bit is MSB. Thus, MSB is copied into CF.
• New bits inserted at LSB position is 0.
• Has an effect of multiplication by 2Shift Count.
• SAME IN OPERATION AS SAL
Shift Arithmatic Right
SAR • Shift Arithmetic Right the 8/16 bit data in Register/memory specified.
• Outgoing bit is LSB. Thus, LSB is copied into CF.
• New bits inserted at MSB position is THE SIGN BIT i.e. previous bit of MSB is copied and inserted as new bit in MSB position.
• Has an effect of Division by 2Shift Count.
• Meaningful for Signed numbers.

Shift Logical Right

SHR • Shift Logical Right the 8/16 bit data in Register/Memory specified.
• Outgoing bit is LSB. Thus, LSB is copied into CF.
• New bit inserted at MSB position is 0.
• Has an effect of Division by 2Shift Count.
• Meaningful for Unsigned numbers
Review problems for Logical instructions

 Try the following problems related to logical and shift/rotate instructions.

 Convert a unpacked BCD number present in AX to a Packed BCD number to be
present AL.
 Multiply the content of HL by 4 with shift instructions
 Divide a signed number -7 by 4 with shift instructions
 Check the status of D0, D3 & D7 bit of register CL using TEST instructions
 Set the D0 and D5 bits of BX