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5 4 3 2 1

01
BOM
D Z8V Serials SKL ULT SYSTEM BLOCK DIAGRAM IV@ : iGPU D

EV@ : Optimus
KBL@ : Keyboard backlight
Dual Channel DDR IV VRAM TPM@ : TPM
DDR4-SODIMM CHA 1066/1333/1600 MHZ GPU GDDR5 GS@ :G-SENSOR
P12 SKY LAKE ULT 15W PCIE1-4
N16S-GT P19 TDI@ : TOUCH PAD I2C
MCP 1356pins PCI-E x4 TSU@ : TOUCH SCREEN USB
TX/RX TSI@ : TOUCH SCREEN I2C
DDR4-SODIMM CHB IMC
DC+GT3e X'TAL 27MHz
GT3@ : GT3 CPU
P13
42 mm X 24 mm
CLK NAC@ : Non IOAC
SATA0 P14~P18 IOAC@ : For IOAC
SATA - HDD EDP
P25 SATA eDP Conn. P21
eDP
SATA ODD SATA1
P25

DDI2 RTD2166-CG
VGA Conn. P21
Cardreader P20
USB2-3
CONN. 2in 1 RTS5170 DP
C
P28 (cardreader) P28 DDI1 PTN3366BS C

HDMI Conn. P22


USB2-3 Integrated PCH P22
POA USB3-1 & USB3-2
P25
USB3.0/2.0
USB2-7 USB2-1 & USB2-2 USB3 Port MB side
CCD(Camera) CN13 -> USB3 port 2 ( up )
P21 CN16 -> USB3 port 1 ( down )
USB2.0 P28
USB2-6 CLK
Touch Screen
P21
PCI-E x1 PCIE-6
USB2-5
Blue Tooth MINI CARD
P26 WLAN+BT
I/O board X'TAL P26
USB2-4 32.768KHz

USB2 IO*1 I/O Board Conn. PCIE-5


RTL8111H
P28
RJ45
X'TAL 24MHz P23
DMIC_CLK0
10/100/1G P23
DMIC_DATA0
CLK
P6 BATTERY RTC
P2~P10 I2C_0 X'TAL 25MHz
B Azalia IHDA
B

SPI
LPC
SPI ROM
8M P7

EC
Int. D-MIC ALC255 TPM(option)
D-MIC BQ24780RUYR G5316RZ1D Thermal Protection
AUDIO CODEC IT8987 P25 Batery Charger P30 +1.2VSUS P34 P38
P24 P24 P29
Discharger

RT6575AGQ MDV1528Q UP1658RQKF


+3V/+5V P31 +5V_S5/+3V_S5/+3V/+5V P31 +VGPU_CORE P39

RT8237CZQW ISL95859HRTZ-T RT8068AZQW


+1V_S5 P32 +VCORE/VCCSA/VCCGT P35 P40
+1.05V_GFX/+3V_GFX
+1.5V_GFX
K/B HALL
Universal HP Speaker*2 LED BL Touch PAD Fan Driver NB681GD-Z
P24 P24 P27
K/B Con. SENSOR (Fan signal)
P27 Con. P27 P27 P17 P27 +VCCOPC/+VCCEOPIOP33

A A

Quanta Computer Inc.


P7
PROJECT : ZRW
Size Document Number Rev
1A
Block Diagram
Date: Monday, February 22, 2016 Sheet 1 of 46
5 4 3 2 1
5 4 3 2 1

Skylake ULT (DISPLAY,eDP) 02


SKL_ULT
U34A
D D
(21) INT_HDMITX2N E55 C47 EDP_TXN0 EDP_TXN0 (20) Don't stuff if we use DP to VGA IC
F55 DDI1_TXN[0] EDP_TXN[0] C46 EDP_TXP0
(21) INT_HDMITX2P
E58 DDI1_TXP[0] EDP_TXP[0] D46 EDP_TXN1
EDP_TXP0 (20) eDP Panel +3V

HDMI
(21) INT_HDMITX1N DDI1_TXN[1] EDP_TXN[1] EDP_TXN1 (20)
(21) INT_HDMITX1P F58 C45 EDP_TXP1 EDP_TXP1 (20)
F53 DDI1_TXP[1] EDP_TXP[1] A45 EDP_TXN2
(21) INT_HDMITX0N DDI1_TXN[2] EDP_TXN[2] EDP_TXN2 (20)
(21) INT_HDMITX0P G53 B45 EDP_TXP2 EDP_TXP2 (20) CRT_AUXN R424 *100K_4
F56 DDI1_TXP[2] EDP_TXP[2] A47 EDP_TXN3
(21) INT_HDMICLK-
G56 DDI1_TXN[3] EDP_TXN[3] B47 EDP_TXP3
EDP_TXN3 (20) Reserve 2 Lane for 4K x 2K CRT_AUXP R423 *100K_4
(21) INT_HDMICLK+ DDI1_TXP[3] EDP_TXP[3] EDP_TXP3 (20)
C50 E45 EDP_AUXN
(19) CRT_TXN0 DDI2_TXN[0] DDI EDP EDP_AUXN EDP_AUXN (20)
D50 F45 EDP_AUXP

CRT
(19) CRT_TXP0 DDI2_TXP[0] EDP_AUXP EDP_AUXP (20)
(19) CRT_TXN1 C52
D52 DDI2_TXN[1] B52 DP_UTIL R432 *0_4 PCH_BRIGHT
(19) CRT_TXP1 DDI2_TXP[1] EDP_DISP_UTIL +3V_S5
A50 R444 *0_4
B50 DDI2_TXN[2] G50
ITE FAE suggest CAP DDI2_TXP[2] DDI1_AUXN
should be at PCH side. D51 F50 CRT_DATA R135 2.2K_4
C51 DDI2_TXN[3] DDI1_AUXP E48 CRT_AUX#_C C569 *short_4 CRT_CLK R134 *2.2K_4
DDI2_TXP[3] DDI2_AUXN CRT_AUXN (19)
F48 CRT_AUX_C C568 *short_4 CRT_AUXP (19)
DDI2_AUXP G46
DISPLAY SIDEBANDS DDI3_AUXN F46
HDMI_DDCCLK_SW L13 DDI3_AUXP 12/25 Change R134、R135 pull-up to +3V_S5
(21) HDMI_DDCCLK_SW GPP_E18/DDPB_CTRLCLK +3V_S5
(21) HDMI_DDCDATA_SW HDMI_DDCDATA_SW L12 +3V_S5 L9 INT_HDMI_HPD INT_HDMI_HPD (21)
GPP_E19/DDPB_CTRLDATA +3V_S5 GPP_E13/DDPB_HPD0 L7 CRT_HPD
N7
+3V_S5 GPP_E14/DDPC_HPD1 L6
CRT_HPD (19)
CRT_CLK SIO_EXT_SMI#
CRT_DATA N8 GPP_E20/DDPC_CTRLCLK +3V_S5 +3V_S5 GPP_E15/DDPD_HPD2 N9 SIO_EXT_SCI#
TP14 +3V
GPP_E21/DDPC_CTRLDATA +3V_S5 +3V_S5 GPP_E16/DDPE_HPD3 SIO_EXT_SCI# (28)
L10 EDP_HPD EDP_HPD (20)
N11 +3V_S5 GPP_E17/EDP_HPD
N12 GPP_E22/DDPD_CTRLCLK +3V_S5 R12 PCH_BLON
(24) PCH_ODD_EN PCH_BLON (20) SIO_EXT_SMI# R115 10K_4
GPP_E23/DDPD_CTRLDATA +3V_S5 EDP_BKLTEN R11 PCH_BRIGHT SIO_EXT_SCI# R123 10K_4
EDP_BKLTCTL PCH_BRIGHT (20)
24.9/F_4 R87 EDP_RCOMP E52 U13 EDP_VDD_EN
+VCCIO EDP_RCOMP EDP_VDDEN EDP_VDD_EN (20)
1 OF 20
eDP_RCOMP SKL_ULT/BGA
Trace length < 100 mils
Trace width = 20 mils
C C
Trace spacing = 25 mils CRT_HPD R82 100K_4
EDP_HPD R84 100K_4

+1V_VCCST

1K_4 R400 CPU_THRMTRIP# H_PECI (50ohm)


Route on microstrip only 100k pull-down on PCH side
49.9/F_4 R407 CATERR#
Spacing >18 mils U34D SKL_ULT
Trace Length: 0.4~6.125 iches
Stuff only for Debug
CATERR# D63
Ramp will not stuff (28) H_PECI TP53
H_PECI A54 CATERR#
H_PROCHOT# R442 499/F_4 H_PROCHOT#_R C65 PECI
(28,29,34) H_PROCHOT# PROCHOT# JTAG
THRMTRIP# R395 100/F_4 CPU_THRMTRIP# C63
Avoid 125Mhz A65 THERMTRIP# B61 XDP_TCK0
SKTOCC# PROC_TCK D60 XDP_TDI_CPU
CPU MISC PROC_TDI
XDP_BPM#0 C55 A61 XDP_TDO_CPU
+VCCIO TP54 BPM#[0] PROC_TDO
BPM#[0:7] XDP_BPM#1 D55 C60 XDP_TMS_CPU
TP52 BPM#[1] PROC_TMS
XDP_BPM#2 B54 B59 XDP_TRST#
Trace Length 1~6 inches TP59
XDP_BPM#3 C56 BPM#[2] PROC_TRST# MP remove(Intel)
R441 1K_4 H_PROCHOT#
Length match < 300 mils TP56 BPM#[3] B56 XDP_TCK1 PCH JTAG
A6 PCH_JTAG_TCK D59 XDP_TDI_CPU
GPP_E3/CPU_GP0 +3V_S5 PCH_JTAG_TDI JTAG_TCK,JTAG_TMS +1V_VCCST
A7 +3V_S5 A56 XDP_TDO_CPU
DGPU_PW_CTRL# BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 XDP_TMS_CPU
Trace Length < 9000mils
(4) DGPU_PW_CTRL# GPP_B3/CPU_GP2 +3V_S5 PCH_JTAG_TMS
AY5 +3V_S5 C61
GPP_B4/CPU_GP3 PCH_TRST# A59 XDP_TRST#
JTAGX TCK,TMS
SM_RCOMP[0:2] R590 49.9/F_4 AT16 Trace Length < 9000mils
R595 49.9/F_4 AU16 PROC_POPIRCOMP XDP_TCK0 XDP_TDO_CPU R448 51_4
Trace length < 500 mils PCH_OPIRCOMP
R100 49.9/F_4 H66 XDP_TMS_CPU R408 *51_4
Trace width = 12~15 mils R96 49.9/F_4 H65 OPCE_RCOMP XDP_TDI_CPU R409 *51_4
Trace spacing = 20 mils OPC_RCOMP
If use Intel DCI USB 3.0 fixture need to short
4 OF 20 1. XDP_TDO <--> XDP_TDO_CPU
SKL_ULT/BGA 2. XDP_TDI <--> XDP_TDI_CPU
B 3. XDP_TMS <--> XDP_TMS_CPU B

XDP_TCK0 R447 51_4


XDP_TCK1 R425 *51_4
H_PWRGOOD (50ohm) XDP_TRST# R446 *51_4
Trace Length: 1~11.25 inches
,XDP_TCK1,XDP_TMS
don't need pull up or pull down

XDP_TCK0 R558 Stuff

+1V_VCCST

CPU thermal trip


3

IMVP_PWRGD_3V 2 Q34

U27 +1V_VCCST +3V FDV301N_G

1 5
1

NC VCC
1

R402 +1V_VCCST
2 C537 10K_4 R454
(34) IMVP_PWRGD A *0.1u/16V_4 1K_4
A A
2

3 4 R414
GND Y IMVP_PWRGD_3V (8)
2

*1K_4
*74AUP1G07GW
THRMTRIP# 1 3
SYS_SHDN# (28,30,37)
Q33 MMBT3904-7-F
R401 *0_4

Quanta Computer Inc.


PROJECT : ZRW
Size Document Number Rev
1A
Skylake 1/4 (DDI/eDP)
Date: Monday, February 22, 2016 Sheet 2 of 46
5 4 3 2 1
5 4 3 2 1

Change Data and DQS to interleave.


03
SKL ULT (DDR4) SKL ULT (DDR4)
SKL_ULT
U34B SKL_ULT
U34C
D AU53 D
(11) M_A_DQ[63:0] DDR0_CKN[0] M_A_CLK0# (11) (12) M_B_DQ[63:0]
M_A_DQ0 AL71 AT53 M_A_CLK0 (11)
M_A_DQ1 AL68 DDR0_DQ[0] DDR0_CKP[0] AU55 M_B_DQ0 AF65 AN45
DDR0_DQ[1] DDR0_CKN[1] M_A_CLK1# (11) DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] M_B_CLK0# (12)
M_A_DQ2 AN68 AT55 M_A_CLK1 (11) M_B_DQ1 AF64 AN46 M_B_CLK1# (12)
M_A_DQ3 AN69 DDR0_DQ[2] DDR0_CKP[1] M_B_DQ2 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45
DDR0_DQ[3] DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] M_B_CLK0 (12)
M_A_DQ4 AL70 BA56 M_A_CKE0 (11) M_B_DQ3 AK64 AP46 M_B_CLK1 (12)
M_A_DQ5 AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 M_B_DQ4 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1]
DDR0_DQ[5] DDR0_CKE[1] M_A_CKE1 (11) DDR1_DQ[4]/DDR0_DQ[20]
M_A_DQ6 AN70 AW56 M_B_DQ5 AF67 AN56 M_B_CKE0 (12)
M_A_DQ7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56 M_B_DQ6 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55
DDR0_DQ[7] DDR0_CKE[3] DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] M_B_CKE1 (12)
M_A_DQ8 AR70 M_B_DQ7 AK66 AN55
M_A_DQ9 AR68 DDR0_DQ[8] AU45 M_B_DQ8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDR0_DQ[9] DDR0_CS#[0] M_A_CS#0 (11) DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
M_A_DQ10 AU71 AU43 M_A_CS#1 (11) M_B_DQ9 AF68
M_A_DQ11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 M_B_DQ10 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42
DDR0_DQ[11] DDR0_ODT[0] M_A_ODT0_DIMM (11) DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] M_B_CS#0 (12)
M_A_DQ12 AR71 AT43 M_A_ODT1_DIMM (11) M_B_DQ11 AH68 AY42 M_B_CS#1 (12)
M_A_DQ13 AR69 DDR0_DQ[12] DDR0_ODT[1] M_B_DQ12 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42
DDR0_DQ[13] DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] M_B_ODT0_DIMM (12)
M_A_DQ14 AU70 BA51 M_A_A5 M_B_DQ13 AF69 AW42 M_B_ODT1_DIMM (12)
M_A_DQ15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 M_A_A9 M_B_DQ14 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
M_A_DQ16 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 M_A_A6 M_B_DQ15 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48 M_B_A5
M_A_DQ17 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 M_A_A8 M_B_DQ16 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 M_B_A9
M_A_DQ18 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52M_A_A7 M_B_DQ17 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 M_B_A6
M_A_DQ19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 M_B_DQ18 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 M_B_A8
DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] M_A_BG#0 (11) DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
M_A_DQ20 BA65 AW54M_A_A12 M_B_DQ19 AN65 AP48 M_B_A7
M_A_DQ21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 M_A_A11 M_B_DQ20 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52
DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] M_B_BG#0 (12)
M_A_DQ22 BA63 BA55 M_A_ACT# M_A_ACT# (11) M_B_DQ21 AP66 AN50 M_B_A12
M_A_DQ23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 M_B_DQ22 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 M_B_A11
DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] M_A_BG#1 (11) DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
M_A_DQ24 BA61 M_B_DQ23 AU65 AN53 M_B_ACT# M_B_ACT# (12)
M_A_DQ25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 M_A_A13 M_B_DQ24 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52
DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] M_B_BG#1 (12)
M_A_DQ26 BB59 AU48 M_A_CAS# (11) M_B_DQ25 AU61
M_A_DQ27 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 M_B_DQ26 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43 M_B_A13
DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] M_A_WE# (11) DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
M_A_DQ28 BB61 AU50 M_A_RAS# (11) M_B_DQ27 AN60 AY43 M_B_CAS# (12)
M_A_DQ29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 M_B_DQ28 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44
DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] M_A_BA#0 (11) DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] M_B_WE# (12)
M_A_DQ30 BA59 AY51 M_A_A2 M_B_DQ29 AP61 AW44 M_B_RAS# (12)
C M_A_DQ31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 M_B_DQ30 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 C
DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] M_A_BA#1 (11) DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] M_B_BA#0 (12)
M_A_DQ32 AY39 AT50 M_A_A10 M_B_DQ31 AU60 AY47 M_B_A2
M_A_DQ33 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 M_A_A1 M_B_DQ32 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44
DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] M_B_BA#1 (12)
M_A_DQ34 AY37 AY50 M_A_A0 M_B_DQ33 AT40 AW46M_B_A10
M_A_DQ35 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 M_A_A3 M_B_DQ34 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 M_B_A1
M_A_DQ36 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 M_A_A4 M_B_DQ35 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 M_B_A0
M_A_DQ37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] M_B_DQ36 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 M_B_A3
M_A_DQ38 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 M_A_DQS#0 M_B_DQ37 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47 M_B_A4
M_A_DQ39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 M_A_DQS0 M_B_DQ38 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4]
M_A_DQ40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 M_A_DQS#1 M_B_DQ39 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 M_B_DQS#0
M_A_DQ41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 M_A_DQS1 M_B_DQ40 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 M_B_DQS0
M_A_DQ42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 M_A_DQS#2 M_B_DQ41 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 M_B_DQS#1
M_A_DQ43 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 M_A_DQS2 M_B_DQ42 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 M_B_DQS1
M_A_DQ44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 M_A_DQS#3 M_B_DQ43 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 M_B_DQS#2
M_A_DQ45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 M_A_DQS3 M_B_DQ44 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 M_B_DQS2
M_A_DQ46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 M_A_DQS#4 M_B_DQ45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 M_B_DQS#3
M_A_DQ47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 M_A_DQS4 M_B_DQ46 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 M_B_DQS3
M_A_DQ48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 M_A_DQS#5 M_B_DQ47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 M_B_DQS#4
M_A_DQ49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 M_A_DQS5 M_B_DQ48 AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 M_B_DQS4
M_A_DQ50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 M_A_DQS#6 M_B_DQ49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 M_B_DQS#5
M_A_DQ51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 M_A_DQS6 M_B_DQ50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 M_B_DQS5
M_A_DQ52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 M_A_DQS#7 M_B_DQ51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 M_B_DQS#6
M_A_DQ53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 M_A_DQS7 M_B_DQ52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 M_B_DQS6
M_A_DQ54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] M_B_DQ53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 M_B_DQS#7
M_A_DQ55 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50 M_A_ALERT# M_B_DQ54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 M_B_DQS7
DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# M_A_ALERT# (11) DDR1_DQ[54] DDR1_DQSP[7]
M_A_DQ56 AY27 AT52 M_A_PARITY M_A_PARITY (11) M_B_DQ55 AP25
M_A_DQ57 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR M_B_DQ56 AT22 DDR1_DQ[55] AN43 M_B_ALERT#
DDR0_DQ[57]/DDR1_DQ[41] DDR1_DQ[56] DDR1_ALERT# M_B_ALERT# (12)
M_A_DQ58 AY25 AY67 +VREF_CA_CPU M_B_DQ57 AU22 AP43 M_B_PARITY M_B_PARITY (12)
M_A_DQ59 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA AY68 +VREFDQ_SA_M3 M_B_DQ58 AU21 DDR1_DQ[57] DDR1_PAR AT13 CPU_DRAMRST#
DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ TP77 DDR1_DQ[58] DRAM_RESET#
M_A_DQ60 BB27 DDR CH - A BA67 +VREFDQ_SB_M3 M_B_DQ59 AT21 AR18 SM_RCOMP_0
M_A_DQ61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ M_B_DQ60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP_1
M_A_DQ62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_VTT_CTRL M_B_DQ61 AP22 DDR1_DQ[60] DDR_RCOMP[1] AU18 SM_RCOMP_2
B M_A_DQ63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL +3V_S5 M_B_DQ62 AP21 DDR1_DQ[61] DDR_RCOMP[2] B
DDR0_DQ[63]/DDR1_DQ[47] M_B_DQ63 AN21 DDR1_DQ[62] DDR CH - B
2 OF 20 +1.2VSUS DDR1_DQ[63]

SKL_ULT/BGA 3 OF 20 M_B_A[13:0]
SKL_ULT/BGA M_B_A[13:0] (12)
R544
2

*100K_4 M_B_DQS#[7:0]
M_B_DQS#[7:0] (12)
M_B_DQS[7:0]
M_B_DQS[7:0] (12)
R545 *10K_4 1 3 DDR_VTTT_PG_CTRL (33)
M_A_ALERT# R312 *0_4
Q36 M_B_ALERT# R291 *0_4
*DTC144EU

M_A_A[13:0]
M_A_A[13:0] (11)
REV:E connect to GND
M_A_DQS#[7:0] Stuff Q54 for both UMA and GPU in DDR_VTT_CNTL
M_A_DQS#[7:0] (11) DRAM COMP
M_A_DQS[7:0]
M_A_DQS[7:0] (11)

SM_RCOMP_0 120/F_4 R598


DRAMRST SM_RCOMP_1 80.6/F_4 R589

+1.2VSUS
1 SM_RCOMP_2 100/F_4 R596

A R577 A
470_4

CPU DRAM
2

CPU_DRAMRST# R593 *Short/0_4 DDR3_DRAMRST# (11,12)

1
C650
*0.1u/16V_4
Quanta Computer Inc.

2
PROJECT : ZRW
Size Document Number Rev
1A
Skylake 2/3 (DDR3 I/F)
Date: Monday, February 22, 2016 Sheet 3 of 46
5 4 3 2 1
5 4 3 2 1

H_PECI (50ohm)
SKL ULT (SIDEBAND ) GPIO 04
If route on microstrip, SKL_ULT
Spacing need >18 mils U34F
Trace Length: 2~15 iches Add GPU Power Control Siganls LPSS ISH

H_PWRGOOD (50ohm) AN8 +3V_S5


(38) VGPU_EN GPP_B15/GSPI0_CS# P2
Trace Length: 1~11.25 inches (13) DGPU_HOLD_RST# AP7 +3V_S5 +3V_S5 GPP_D9
GPP_B16/GSPI0_CLK P3
AP8 +3V_S5 +3V_S5 GPP_D10
(39) DGPU_PWR_EN GPP_B17/GSPI0_MISO P4
GSPI0_MOSI AR7 +3V_S5 +3V_S5 GPP_D11
D GPP_B18/GSPI0_MOSI P1 D
+3V_S5 GPP_D12
AM5 +3V_S5
(15) DGPU_PWROK GPP_B19/GSPI1_CS# M4
(13,16) GC6_FB_EN AN7 +3V_S5 +3V_S5 GPP_D5/ISH_I2C0_SDA
GPP_B20/GSPI1_CLK N3
AP5 +3V_S5 +3V_S5 GPP_D6/ISH_I2C0_SCL
+3V_S5 (16) DGPU_EVENT# GPP_B21/GSPI1_MISO
GSPI1_MOSI AN5 +3V_S5
GPP_B22/GSPI1_MOSI N1
+3V_S5 GPP_D7/ISH_I2C1_SDA N2
AB1 +3V_S5 +3V_S5 GPP_D8/ISH_I2C1_SCL
(26) ACCEL_INTA GPP_C8/UART0_RXD
2.2K_4 R137 I2C0_SDA Touch PAD (24) ODD_PRSNT# AB2 +3V_S5
GPP_C9/UART0_TXD AD11
2.2K_4 R125 I2C0_SCL TPD_INT# W4 +3V_S5 +1.8V_S5 GPP_F10/I2C5_SDA/ISH_I2C2_SDA
(26,28) TPD_INT# GPP_C10/UART0_RTS# AD12
*2.2K_4 R119 I2C1_SDA (20) TP_INT_PCH AB3 +3V_S5 +1.8V_S5 GPP_F11/I2C5_SCL/ISH_I2C2_SCL
*2.2K_4 R126 I2C1_SCL GPP_C11/UART0_CTS#
Touch Screen UART2_RXD AD1
GPP_C20/UART2_RXD +3V_S5 U1 Reserve UART FFC TP for Win 7 debug
UART2_TXD AD2 +3V_S5 +3V_S5 GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_C21/UART2_TXD U2 +3V_S5
PU 2.2K for touch pad I2C bus(400 KHz) UART2 for RMT UART2_RTS# AD3 +3V_S5 +3V_S5 GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
GPP_C22/UART2_RTS# U3
UART2_CTS# AD4 +3V_S5 +3V_S5 GPP_D15/ISH_UART0_RTS#
GPP_C23/UART2_CTS# U4
+3V_S5 GPP_D16/ISH_UART0_CTS#/SML0BALERT#
+3V GPU Control PU/PD I2C0_SDA U7
AC1
UART2_RXD R490 *49.9K/F_4
(26) I2C0_SDA GPP_C16/I2C0_SDA
+3V_S5 +3V_S5 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 TP68
Touch PAD I2C0_SCL U6 +3V_S5 +3V_S5 GPP_C13/UART1_TXD/ISH_UART1_TXD UART2_TXD R489 *49.9K/F_4
(26) I2C0_SCL GPP_C17/I2C0_SCL AC3 TP69
+3V_S5 GPP_C14/UART1_RTS#/ISH_UART1_RTS# UART2_RTS# R484 *49.9K/F_4
AB4 TP67
*EV@10K_4 R201 VGPU_EN *IV@10K_4 R198 I2C1_SDA U8 +3V_S5 +3V_S5 GPP_C15/UART1_CTS#/ISH_UART1_CTS# UART2_CTS# R488 *49.9K/F_4
(20) I2C1_SDA GPP_C18/I2C1_SDA TP66
Touch Screen I2C1_SCL U9 +3V_S5
(20) I2C1_SCL GPP_C19/I2C1_SCL AY8
*10K_4 R575 DGPU_PWR_EN *100K_4 R587 +3V_S5 GPP_A18/ISH_GP0 BA8
AH9 +1.8V_S5 +3V_S5 GPP_A19/ISH_GP1
GPP_F4/I2C2_SDA BB7
*10K_4 R192 GC6_FB_EN *10K_4 R188 AH10 +1.8V_S5 +3V_S5 GPP_A20/ISH_GP2
GPP_F5/I2C2_SCL BA7
+3V_S5 GPP_A21/ISH_GP3 AY7
1A-1 20131015 For GC6 NV DG GC6_FB_EN PD. AH11 +1.8V_S5 +3V_S5 GPP_A22/ISH_GP4
GPP_F6/I2C3_SDA AW7
AH12 +1.8V_S5 +3V_S5 GPP_A23/ISH_GP5
+3V GPP_F7/I2C3_SCL AP13
+3V_S5 GPP_A12/BM_BUSY#/ISH_GP6
AF11 +1.8V_S5
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL +1.8V_S5
R197 10K_4 DGPU_HOLD_RST#
6 OF 20
SKL_ULT/BGA
DGPU_PW_CTRL#
high UMA Only
C C
GPU power is control by PCH U34G SKL_ULT
low GPIO (Discrete, SG or Optimize)
HDA C644 *10p/50V_4 AUDIO

+3V R583 33_4 HDA_SYNC_R BA22


(23) PCH_AZ_CODEC_SYNC HDA_SYNC/I2S0_SFRM
R553 33_4 HDA_BCLK_R AY22
(2) DGPU_PW_CTRL# (23) PCH_AZ_CODEC_BITCLK HDA_BLK/I2S0_SCLK
(23) PCH_AZ_CODEC_SDOUT R569 33_4 HDA_SDO_R BB22 SDIO/SDXC
BA21 HDA_SDO/I2S0_TXD
(23) PCH_AZ_CODEC_SDIN0 HDA_SDI0/I2S0_RXD
R208 EV@100K_4 DGPU_PW_CTRL# R209 IV@1K_4 AY21 +3V_S5 AB11
DGPU_PWROK R104 *10K_4 R560 33_4 HDA_RST#_R AW22 HDA_SDI1/I2S1_RXD SD GPI GPP_G0/SD_CMD AB13
(23) PCH_AZ_CODEC_RST# HDA_RST#/I2S1_SCLK
+3V_S5 SD GPI GPP_G1/SD_DATA0
J5 +3V_S5 AB12
AY20 GPP_D23/I2S_MCLK +3V_S5 SD GPI GPP_G2/SD_DATA1 W12
DGPU_PWROK PD on GPU side I2S1_SFRM
+3V_S5 SD GPI GPP_G3/SD_DATA2
C636 AW20 +3V_S5 W11
*10p/50V_4 I2S1_TXD SD GPI GPP_G4/SD_DATA3 W10
+3V_S5 SD GPI GPP_G5/SD_CD#
AK7 +1.8V_S5 +3V_S5 W8
AK6 GPP_F1/I2S2_SFRM SD GPI GPP_G6/SD_CLK W7
GPP_F0/I2S2_SCLK +1.8V_S5 +3V_S5 SD GPI GPP_G7/SD_WP
DGPU_PW_CTRL# VGA H/W Setup AK9 +1.8V_S5
Signal Menu AK10 GPP_F2/I2S2_TXD BA9
GPP_F3/I2S2_RXD +1.8V_S5 +3V_S5 GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
UMA Only 1 UMA Hidden UMA boot +3V_S5 GPP_A16/SD_1P8_SEL
DMIC_CLK0_R H5 AB7 200/F_4 R148
TP70 GPP_D19/DMIC_CLK0 +3V_S5 SD_RCOMP
TP57 DMIC_DATA0_R D7
SG/Optimise 0 GPU Hidden GPU boot GPP_D20/DMIC_DATA0 +3V_S5
D8 AF13
Strapping C8 GPP_D17/DMIC_CLK1 +3V_S5 +1.8V_S5 GPP_F23
SPKR R549 *20K/F_4 GPP_D18/DMIC_DATA1 +3V_S5
(23) SPKR SPKR AW5
545659-103 GPP_B14/SPKR +3V_S5

Skylake-U Strapping Table SKL_ULT/BGA


7 OF 20
Touchpad INT +3V_S5

Pin Name Strap description Sampled Configuration note TPD_INT# TDI@10K_4 R117
0 = *Disable Top Swap (iPD 20K) R550 *1K_4 SPKR
B GPP_B14 (SPKR) Top-Block Swap override PCH_PWROK +3V B
1 = Enable Top Swap Mode
0 = *Disable No Reboot (iPD 20K) R543 *1K_4 GSPI0_MOSI
GPP_B18 No reboot PCH_PWROK +3V
(GSPI0_MOSI) 1 = Enable No Reboot Mode
0 = *Disable Intel ME Cryp to TLS(iPD 20K) R144 *10K_4
GPP_C2 TLS Confidentiality RSMRST# +3V_S5 SMBALERT# (7)
(SMBALERT#) 1 = Enable Intel ME Cryp to TLS
0 = *SPI (iPD 20K) R191 *1K_4 GSPI1_MOSI
GPP_B22 Boot BIOS Strap Bit (BBS) PCH_PWROK +3V
(GSPI1_MOSI) 1 = LPC
0 = *LPC is selected for EC (iPD 20K) R481 *1K_4
GPP_C5 eSPI or LPC RSMRST# +3V_S5 SML0ALERT# (7)
(SML0ALERT#) 1 = eSPI selected for EC

SPI0_MOSI Reserved RSMRST# (iPU 15 ~ 40K)

SPI0_MISO Reserved RSMRST# (iPU 15 ~ 40K)

GPP_B23
(SML1ALERT# Reserved RSMRST# (iPD 20K)
/PCHHOT#)

SPI0_IO2 Reserved RSMRST# (iPU 15 ~ 40K)

A SPI0_IO3 Reserved RSMRST# (iPU 15 ~ 40K) A

0 = *Enable security in the Flash


HDA_SDO / Flash Descriptor Security
Description (iPD 20K) change location to near CPU to prevent impact HDA_SDO signal
I2S_TXD0 Override / Intel ME Debug Mode PCH_PWROK HDA_SDO_R
1 = Disable Flash Descriptor Security (Override) R570 1K_4
ME_WR# (28)

GPP_E19 0 = *Port B is not detected (iPD 20K)


Display Port B Detected PCH_PWROK
(DDPB_CTRLDATA)
1 =Port B is detected Quanta Computer Inc.
0 = *Port C is not detected (iPD 20K) PROJECT : ZRW
GPP_E21 Size Document Number Rev
(DDPC_CTRLDATA) Display Port C Detected PCH_PWROK 1 =Port C is detected
1A
Skylake 6/7 (PEG/DMI/FDI)
Date: Monday, February 22, 2016 Sheet 4 of 46
5 4 3 2 1
5 4 3 2 1

+VCCCORE
U34L SKL_ULT +VCCCORE

Backside cap
05
CPU POWER 1 OF 4

A30
A34 VCC_A30 VCC_G32
G32
G33
Primary side cap
C203 A39 VCC_A34 S0 VCC VCC_G33 G35
C247 C227 C132 C301 C273 C209 C228 C248 C284 A44 VCC_A39 0.55V~1.5V VCC_G35 G37 C531 C66 C74 C538 C534 C56
1U/6.3V_2 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 AK33 VCC_A44 VCC_G37 G38
VCC_AK33 2+2 peak 24A VCC_G38
47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8
AK35 2+2 TPY 17A G40
AK37 VCC_AK35 VCC_G40 G42
Backside cap AK38
AK40
VCC_AK37
VCC_AK38 2+3e peak 24A
VCC_G42
VCC_J30
J30
J33
Primary side cap
VCC_AK40 2+3e TPY 17A VCC_J33
AL33 J37
C312 C235 AL37 VCC_AL33 VCC_J37 J40 C106 C83 C122 C573 C100 C574 C570 C138
C575 C300 C269 C545 C552 C558 C252 AL40 VCC_AL37 VCC_J40 K33 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4
1U/6.3V_2 1U/6.3V_2 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 AM32 VCC_AL40 VCC_K33 K35
AM33 VCC_AM32 VCC_K35 K37
AM35 VCC_AM33 VCC_K37 K38
D
Backside cap AM37
AM38
VCC_AM35
VCC_AM37
VCC_K38
VCC_K40
K40
K42 R29
+VCCCORE
100/F_4 100 ohm Near CPU D
G30 VCC_AM38 VCC_K42 K43
VCC_G30 VCC_K43 VCORE_SENSE (34)
C223 C580 C204 C217 VCORESS_SENSE (34)
C107 C275 C208 C327 TP13 K32 E32 +1V_VCCST
22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 RSVD_K32 VCC_SENSE
VSS_SENSE
E33 R32 100/F_4 SVID
TP27 AK32
RSVD_AK32 B63 H_CPU_SVIDART# Must close to CPU
Backside cap +VCCOPC
AB62
P62 VCCOPC_AB62S0 1.0V 3A
VIDALERT#
VIDSCK
A63
D64
H_CPU_SVIDCLK
H_CPU_SVIDDAT R418 C535
For 2+3e CPU V62 VCCOPC_P62 VIDSOUT 100/F_4 1000P/50V_4
C279 C230 C267 C581 C287 C243 VCCOPC_V62 G20
VCCSTG_G20 +VCCSTG
C315 +1.8V_PRIM +1.8V_PRIM H63
1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 VCC_OPC_1P8_H63 C119
1U/6.3V_2 R162 GT3@100/F_4 G61
Sx H_CPU_SVIDDAT
+VCCOPC VCC_OPC_1P8_G61 1.8V 50mA 1U/6.3V_4
H_CPU_SVIDDAT (34)

Backside cap (32) +VCCOPC_SRC R170


R175
GT3@0_4
GT3@0_4
AC63
AE63 VCCOPC_SENSE Place PU resistor
(32) 681_AGND VSSOPC_SENSE GT3 CPU close to CPU +1V_VCCST
C246 C221 C314 C214 C195 C307 R179 GT3@100/F_4 AE62
C256 AG62 VCCEOPIO
1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 VCCEOPIO S0 1.0V 3A
Place PU resistor
1U/6.3V_2 +VCCEOPIO
AL63 close to CPU R393
AJ62 VCCEOPIO_SENSE 54.9/F_4
For 2+3e CPU VSSEOPIO_SENSE
100 ohm near CPU H_CPU_SVIDART# R419 220/F_4 VR_SVID_ALERT#_VCORE (34)
12 OF 20

+VCCEOPIO Backside cap +VCCOPC_SRC


681_AGND
R164
R176
GT3@0_4
GT3@0_4
SKL_ULT/BGA

U34M SKL_ULT +VCCGT H_CPU_SVIDCLK


C310 C313 For 2+3e CPU H_CPU_SVIDCLK (34)
GT3@10u/6.3V_4 GT3@10u/6.3V_4 CPU POWER 2 OF 4

A48 VCCGT
N70
N71
Primary side cap
A53 VCCGT VCCGT R63
1.0V_CPU 3A
Backside cap +VCCOPC
A58
A62
VCCGT
VCCGT S0 VCCGT
VCCGT
VCCGT
R64
R65
C61 C244 C59 C302 C219 C60 C277

A66 VCCGT 0.55~1.5V VCCGT R66


47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8
+1.8V_PRIM
Backside cap C595
C593 C591 C589 C592 C590 C594 AA63
AA64
VCCGT
VCCGT 2+2 peak 31A
VCCGT
VCCGT
R67
R68 Primary side cap
VCCGT 2+2 TPY 15A VCCGT
C205 C220 GT3@1U/6.3V_2
GT3@10u/6.3V_4 GT3@1U/6.3V_2 GT3@1U/6.3V_2
GT3@1U/6.3V_2 GT3@1U/6.3V_2
GT3@1U/6.3V_2 AA66 R69
GT3@10u/6.3V_4 GT3@10u/6.3V_4 For 2+3e CPU AA67 VCCGT
2+3e peak 56A
VCCGT R70
AA69 VCCGT VCCGT R71 C599 C620 C134 C621 C114 C617 C96
VCCGT 2+3e TPY 17A VCCGT
AA70 T62 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6
For 2+3e CPU AA71 VCCGT VCCGT U65
47u/6.3V_8
C
R92 AC64 VCCGT VCCGT U68 C

+1.8V_S5 GT3@0_6 +1.8V_PRIM +VCCGT


AC65
AC66
VCCGT
VCCGT
VCCGT
VCCGT
U71
W63
Primary side cap C210 change back to 47u/6.3v_8 for cost
Backside cap AC67
AC68
VCCGT
VCCGT
VCCGT
VCCGT
W64
W65
AC69 VCCGT VCCGT W66 C598 C619 C93 C600 C597 C618
AC70 VCCGT VCCGT W67 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6
47u/6.3V_8
C316 C131 C116 C215 C241 C140 C250 C224 C92 C80 AC71 VCCGT VCCGT W68
10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 J43 VCCGT VCCGT W69
J45 VCCGT VCCGT W70
VCCGT VCCGT C202 change back to 47u/6.3v_8 for cost
J46 W71
J48 VCCGT VCCGT Y62
Backside cap J50
J52
VCCGT
VCCGT
VCCGT +VCCGT
Primary side cap
C210 C237 C239 C265 C263 C262 C261 C212 C213 C260 J53 VCCGT S0 VCCGTX AK42
J55 VCCGT 0.55~1.5V VCCGTX_AK42 AK43
1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 J56 VCCGT VCCGTX_AK43 AK45
VCCGT 2+2 X VCCGTX_AK45
J58 AK46 C294 C604 C292 C609 C596 C293 C291 C317
J60 VCCGT VCCGTX_AK46 AK48 22u/6.3V_6 GT3@22u/6.3V_6 22u/6.3V_6 GT3@22u/6.3V_6 GT3@22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6
VCCGT 2+3e peak 6A VCCGTX_AK48
K48 2+3e TPY 4A VCCGTX_AK50 AK50
K50 VCCGT AK52
C211 C238 K52 VCCGT VCCGTX_AK52 AK53
VCCGT VCCGTX_AK53 Stuff C277,C274,C275
K53 AK55
1U/6.3V_2 1U/6.3V_2 K55 VCCGT VCCGTX_AK55 AK56
K56 VCCGT VCCGTX_AK56 AK58 For 2+3e CPU
K58 VCCGT VCCGTX_AK58 AK60
K60 VCCGT VCCGTX_AK60 AK70
L62 VCCGT VCCGTX_AK70 AL43
L63 VCCGT VCCGTX_AL43 AL46
L64
L65
VCCGT
VCCGT
VCCGTX_AL46
VCCGTX_AL50
AL50
AL53
Backside cap
L66 VCCGT VCCGTX_AL53 AL56
L67 VCCGT VCCGTX_AL56 AL60
L68 VCCGT VCCGTX_AL60 AM48 C319 C271 C251 C216 C270 C242 C318 C225
L69 VCCGT VCCGTX_AM48 AM50 GT3@10u/6.3V_4 GT3@10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 GT3@10u/6.3V_4 10u/6.3V_4 GT3@10u/6.3V_4 10u/6.3V_4
L70 VCCGT VCCGTX_AM50 AM52
+VCCGT L71 VCCGT VCCGTX_AM52 AM53
M62 VCCGT VCCGTX_AM53 AM56
N63 VCCGT VCCGTX_AM56 AM58
N64 VCCGT VCCGTX_AM58 AU58
R83 N66 VCCGT VCCGTX_AU58 AU63
100/F_4 N67 VCCGT VCCGTX_AU63 BB57
100 ohm Near CPU VCCGT VCCGTX_BB57
N69 BB66
VCCGT VCCGTX_BB66
B B
(34) VCCGT_SENSE J70 AK62
J69 VCCGT_SENSE VCCGTX_SENSE AL61
(34) VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE

R78 13 OF 20
SKL_ULT/BGA
100/F_4

+1.2VSUS U34N SKL_ULT


+VCCIO
S0
Backside cap AU23
S3
CPU POWER 3 OF 4
0.85V/0.95V AK28 Backside cap Imax 3(A)
AU28 VDDQ_AU23 DDR4 VCCIO AK30
VDDQ_AU28 1.2V 3.0A VCCIO
AU35 AL30
C407 C329 C410 C355 AU42 VDDQ_AU35 VCCIO AL42 C296 C320 C297 C321
C375 C360 BB23 VDDQ_AU42 2A VCCIO AM28 C305 C304
10u/6.3V_4 10u/6.3V_4 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 BB32 VDDQ_BB23 VCCIO AM30 10u/6.3V_4 10u/6.3V_4 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2
BB41 VDDQ_BB32 VCCIO AM42
BB47 VDDQ_BB41 VCCIO

Primary side cap


BB51 VDDQ_BB47
VDDQ_BB51 S0 1.15V VCCSA
AK23
AK25
Primary side cap
2+2 peak 5A VCCSA
2+2 TPY 4A G23
AM40 VCCSA G25 C608 C627 C605 C628
VDDQC 2+3e peak 5.1A VCCSA
2+3e TPY 5A G27
A18 VCCSA G28 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
C466 C421 C435 C450 VCCST S3 1.0V 120mA VCCSA J22
10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 A22 VCCSA J23 +VCCSA
VCCSTG_A221.0V 40mA VCCSA J27

+VDDQC
AL23 S0
VCCPLL_OC
VCCSA
VCCSA
K23
K25
Backside cap
R181 *short/0_4 K20 S0 1.0V 260mA VCCSA K27
1 2 K21 VCCPLL_K20 VCCSA K28 C280 C249 C266 C236 C222 C288 C311
+1.2VSUS VCCPLL_K21 VCCSA K30 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4
Backside cap C322
C308
+1V_VCCST S3 1.0V 120mA VCCSA
AM23 TP28
1U/6.3V_2 10u/6.3V_4 VCCIO_SENSE AM22 TP26

C576
VSSIO_SENSE
H21
Backside cap
R430 *short/0_6 +VCCSTG VSSSA_SENSE H20 C194 C303 C207 C259 C285 C295 C276
+1V_SUS VCCSA_SENSE
1U/6.3V_4 R90 100/F_4
1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2 1U/6.3V_2
Primary side cap SKL_ULT/BGA
14 OF 20
VSASS_SENSE (34)
C136 VSA_SENSE (34)
A R81 *short/0_6 A
+VCCIO

Backside cap
1U/6.3V_4 +VCCSA Primary side cap
+VCCPLL R89 100/F_4
C245 C133 C231 C87 C115 C102
+1V_SUS R431 *short/0_6 100 ohm near CPU 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4

C577

Primary side cap 1U/6.3V_4

Quanta Computer Inc.


PROJECT : ZRW
Size Document Number Rev
1A
Skylake 12/13/14 (POWER)
Date: Monday, February 22, 2016 Sheet 5 of 46
5 4 3 2 1
5 4 3 2 1

Skylake ULT (GPU, SATA , ODD, CLK ,USB2&3)

U34H SKL_ULT
06
SSIC / USB3
PCIE/USB3/SATA
H8
USB3_1_RXN G8
USB3_RXN0
USB3_RXP0
(27)
(27)
PCH PU/PD +3V_S5
H13 USB3_1_RXP C13
(13) PEG_RX#0
G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13
USB3_TXN0 (27) MB USB3.0 CN16 ( Charger IC ) Down
(13) PEG_RX0 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_TXP0 (27)
(13) PEG_TX#0 C564 EV@0.22u/10V_4 C_PEG_TX#0 B17
D
C563 EV@0.22u/10V_4 C_PEG_TX0 A17 PCIE1_TXN/USB3_5_TXN J6 USB_OC0# R411 10K_4
D
(13) PEG_TX0 PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB3_RXN1 (27)
H6 USB_OC1# R405 10K_4
USB3_2_RXP/SSIC_1_RXP USB3_RXP1 (27)
(13) PEG_RX#1 G11 B13 USB3_TXN1 (27) MB USB3.0 CN13 -> Up USB_OC2# R404 10K_4
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13 USB_OC3# R422 10K_4
(13) PEG_RX1 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB3_TXP1 (27)
(13) PEG_TX#1 C550 EV@0.22u/10V_4 C_PEG_TX#1 D16
C549 EV@0.22u/10V_4 C_PEG_TX1 C16 PCIE2_TXN/USB3_6_TXN J10
dGPU PEG*4 (13) PEG_TX1 PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10
H16 USB3_3_RXP/SSIC_2_RXP B15
(13) PEG_RX#2 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN +3V
G16 A15
(13) PEG_RX2 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
(13) PEG_TX#2 C547 EV@0.22u/10V_4 C_PEG_TX#2 D17
C548 EV@0.22u/10V_4 C_PEG_TX2 C17 PCIE3_TXN E10
(13) PEG_TX2 PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15 DEVSLP0 R469 *10K_4
(13) PEG_RX#3 1A-1
F15 PCIE4_RXN USB3_4_TXN D15 DEVSLP1 R470 *10K_4
(13) PEG_RX3 PCIE4_RXP USB3_4_TXP
(13) PEG_TX#3 C542 EV@0.22u/10V_4 C_PEG_TX#3 B19 DEVSLP2 R471 *10K_4
C543 EV@0.22u/10V_4 C_PEG_TX3 A19 PCIE4_TXN AB9 PIRQA# R572 10K_4
(13) PEG_TX3 PCIE4_TXP USB2N_1 USBP0- (27)
AB10 MB USB3.0 CN16 ( Charger IC ) Down
USB2P_1 USBP0+ (27)
F16
E16 PCIE5_RXN AD6 SATAGP1 R439 *10K_4
PCIE5_RXP USB2N_2 USBP1- (27)
C19 AD7 USBP1+ (27) MB USB3.0 CN13 -> Up
D19 PCIE5_TXN USB2P_2
PCIE5_TXP AH3
USB2N_3 USBP2- (27)
G18 AJ3 USBP2+ (27) DB USB2.0
F18 PCIE6_RXN USB2P_3
D20 PCIE6_RXP AD9
PCIE6_TXN USB2N_4 USBP3- (24)
C20 AD10 POA (Reserved)
PCIE6_TXP USB2P_4 USBP3+ (24) +3V_S5
Add SSD ID 1/14
F20 AJ1 USBP4- (25)
(24) SATA_RXN0 E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2
(24) SATA_RXP0 PCIE7_RXP/SATA0_RXP USB2P_5 USBP4+ (25) BT Hight is SSD , Low is ODD
HDD B21 USB2
(24) SATA_TXN0 PCIE7_TXN/SATA0_TXN
A21 AF6
(24) SATA_TXP0 PCIE7_TXP/SATA0_TXP USB2N_6 AF7 USBP5- (20)
USBP5+ (20) Touch Screen (24) SSD_ID R438 10K_4 SATAGP0 R437 100K_4
G21 USB2P_6
(24) SATA_RXN1 F21 PCIE8_RXN/SATA1A_RXN AH1
(24) SATA_RXP1 PCIE8_RXP/SATA1A_RXP USB2N_7 USBP6- (20)
ODD D21 AH2 USBP6+ (20) CCD
(24) SATA_TXN1 PCIE8_TXN/SATA1A_TXN USB2P_7
C21
(24) SATA_TXP1 PCIE8_TXP/SATA1A_TXP AF8
USB2N_8 USBP7- (27)
C (22) PCIE_RX5-_LAN E22 AF9 USBP7+ (27) Card reader C
E23 PCIE9_RXN USB2P_8
(22) PCIE_RX5+_LAN PCIE9_RXP
LAN (22) PCIE_TX5-_LAN C560 0.1u/16V_4 PCIE_TX5- B23 AG1
C561 0.1u/16V_4 PCIE_TX5+ A23 PCIE9_TXN USB2N_9 AG2
(22) PCIE_TX5+_LAN PCIE9_TXP USB2P_9 Skylake-U userd 24 MHz (50 Ohm ESR) XTAL
(25) PCIE_RX6-_WLAN F25 AH7
E25 PCIE10_RXN USB2N_10 AH8
(25) PCIE_RX6+_WLAN PCIE10_RXP USB2P_10 USBCOMP
WIFI C541 0.1u/16V_4 PCIE_TX6- D23 C556 10P/50V_4
(25) PCIE_TX6-_WLAN
C540 0.1u/16V_4 PCIE_TX6+ C23 PCIE10_TXN AB6 USBCOMP R138 113/F_4
Impedance = 50 ohm
(25) PCIE_TX6+_WLAN PCIE10_TXP USB2_COMP Trace length < 500 mils
AG3 USB2_ID R492 1K_4
USB2_ID

3
4
R440 100/F_4 PCIE_RCOMPN F5 AG4 R185 1K_4 Trace spacing = 15 mils
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE Y3
PCIE_RCOMPP BG624000078 -> HHE(1st)
+3V_S5 A9 USB_OC0# USB_OC0# (27) MB U3 R426 24MHz
XDP_PRDY# D56 GPP_E9/USB2_OC0# C9 USB_OC1# 1M_4
TP55 PROC_PRDY# +3V_S5 GPP_E10/USB2_OC1# USB_OC1# (27) MB U3 BG624000044 -> TXC(2nd)
XDP_PREQ# D61 +3V_S5 D9 USB_OC2# DB U2
TP51 USB_OC2# (27)

1
2
PIRQA# BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3# XTAL24_IN
GPP_A7/PIRQA#
+3V_S5 +3V_S5 GPP_E12/USB2_OC3# XTAL24_OUT C544 10P/50V_4
SATA_RXN1/PEG_RXN10_L2 E28 +3V_S5 J1 DEVSLP0 DEVSLP0 (24)
(25) SATA_RXN1/PEG_RXN10_L2 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0
SATA_RXP1/PEG_RXP10_L2 E27 J2 DEVSLP1
(25) SATA_RXP1/PEG_RXP10_L2
SATA_TXN1/PEG_TXN10_L2 D24 PCIE11_RXP/SATA1B_RXP +3V_S5 GPP_E5/DEVSLP1 J3 DEVSLP2
(25) SATA_TXN1/PEG_TXN10_L2 PCIE11_TXN/SATA1B_TXN +3V_S5 GPP_E6/DEVSLP2 DEVSLP2 (25)
SATA_TXP1/PEG_TXP10_L2 C24
(25) SATA_TXP1/PEG_TXP10_L2 E30 PCIE11_TXP/SATA1B_TXP H2
SATA_RXN3/PEG_RXN9_L0 SATAGP0
(25) SATA_RXN3/PEG_RXN9_L0
SATA_RXP3/PEG_RXP9_L0 F30 PCIE12_RXN/SATA2_RXN +3V_S5 GPP_E0/SATAXPCIE0/SATAGP0 H3 SATAGP1 Note: Change Y4 to 38.4 MHz(ESR 30 ohm) for Cannonlake U
(25) SATA_RXP3/PEG_RXP9_L0 PCIE12_RXP/SATA2_RXP +3V_S5 GPP_E1/SATAXPCIE1/SATAGP1
SATA_TXN3/PEG_TXN9_L0 A25 G4 R436 *Short/0_4
(25) SATA_TXN3/PEG_TXN9_L0 B25 PCIE12_TXN/SATA2_TXN +3V_S5 GPP_E2/SATAXPCIE2/SATAGP2 NGFF3_DET (25)
SATA_TXP3/PEG_TXP9_L0
(25) SATA_TXP3/PEG_TXP9_L0 PCIE12_TXP/SATA2_TXP H1
+3V_S5 GPP_E8/SATALED#
CH01006JB08 -> 10p
8 OF 20 RTC Clock 32.768KHz (RTC) CH01506JB06 -> 15p
SKL_ULT/BGA CH-6806TB01 -> 6.8p
C349 6.8p/50V_4 RTC_X1

1
Trace length < 1000 mils
Y2 R225
32.768KHZ 10M_4 BG3327680C6 -> HHE(1st)
U34J SKL_ULT
B B
C350 6.8p/50V_4 RTC_X2

2
BG332768099 -> TXC(2nd)--EOD
SSD N16S VGA

CLOCK SIGNALS

D42
Change to BG332768104
(13) CLK_PCIE_VGA# CLKOUT_PCIE_N0
(13) CLK_PCIE_VGA C42
R259 CLK_PCIE_REQ0# AR10 CLKOUT_PCIE_P0
(13) CLK_PEGA_REQ# GPP_B5/SRCCLKREQ0# +3V_S5
*Short/0_4
(25) CLK_PCIE_NGFF1_N B42
A42 CLKOUT_PCIE_N1 F43 CLK_PCIE_XDPN
(25) CLK_PCIE_NGFF1_P CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N TP6
M.2

R211 CLK_PCIE_REQ1# AT7 E43 CLK_PCIE_XDPP


(25) PCIE_CLKREQ_NGFF1#
*Short/0_4 GPP_B6/SRCCLKREQ1# +3V_S5 CLKOUT_ITPXDP_P TP9 RTC Circuitry (RTC)
D41 BA17 SUSCLK
CLKOUT_PCIE_N2 +3V_S5 GPD8/SUSCLK SUSCLK (25) +3VPCU
C41 1B-1
CLK_PCIE_REQ2# AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN
TP31 GPP_B7/SRCCLKREQ2# XTAL24_IN
+3V_S5 E35 XTAL24_OUT On SKL voltage at VCCRTC does not exceed 3.2V
D40 XTAL24_OUT
C40 CLKOUT_PCIE_N3 E42 XCLK_BIASREF R452 2.7K/F_4
CLKOUT_PCIE_P3 XCLK_BIASREF +1V_S5
TP78 CLK_PCIE_REQ3# AT10 R329
GPP_B8/SRCCLKREQ3# +3V_S5 AM18 RTC_X1
RTCX1 1.5K/F_4
+3V_RTC
+3V_RTC
B40 AM20 RTC_X2
LAN

(22) CLK_PCIE_LANN
A40 CLKOUT_PCIE_N4 RTCX2 D9
Trace width = 30 mils
(22) CLK_PCIE_LANP CLKOUT_PCIE_P4
R230 CLK_PCIE_REQ4# AU8 AN18 SRTC_RST# +3V_RTC_2 R237
(22) CLK_PCIE_LAN_REQ# GPP_B9/SRCCLKREQ4# +3V_S5 SRTCRST#
*Short/0_4 AM16 RTC_RST# RTC_RST#
E40 RTCRST# R335 1K_4 +3V_RTC_1
WLAN

(25) CLK_PCIE_WLANN CLKOUT_PCIE_N5 VCCRTC_2

1
(25) CLK_PCIE_WLANP E38 20K/F_4
R213 CLK_PCIE_REQ5# AU7 CLKOUT_PCIE_P5 R330 BAT54CW_0.2A
(25) PCIE_CLKREQ_WLAN#
*Short/0_4 GPP_B10/SRCCLKREQ5# +3V_S5 1V power plane 45.3K/F_4 C357 J1
+3V_RTC_[0:2] 1u/6.3V_4 *JUMP
0.71 checklist p14

2
Trace width = 20 mils R233

1
10 OF 20 BT1 SRTC_RST#
SKL_ULT/BGA
20K/F_4
BAT_CONN

2
C363 C354
+3V add for EC reset RTC 1u/6.3V_4 1u/6.3V_4

A SRTC_RST# RTC_RST# A
1A-2 2013/10/16 Chage +3V_RTC_0 to VCCTC_2.
CLK_PCIE_REQ0# R258 10K_4
3

CLK_PCIE_REQ1# R205 10K_4


CLK_PCIE_REQ2# R223 *10K_4 1. AHL03003057 DBV CR2032
CLK_PCIE_REQ3# R574 *10K_4
CLK_PCIE_REQ4# R227 10K_4 2 CLR_CMOS 2 2. AHL03003003 VDE CR2032
(28) CLR_CMOS
CLK_PCIE_REQ5# R210 10K_4
Q41 Q39
*2N7002K 2N7002K
R594
Quanta Computer Inc.
1

100K_4

PROJECT : ZRW
Size Document Number Rev
1A
Skylake 9/10 (PEG/USB/CLK)
Date: Monday, February 22, 2016 Sheet 6 of 46
5 4 3 2 1
5 4 3 2 1

U34E
SPI - FLASH
SKL_ULT

SMBUS, SMLINK Strapping


07
PCH_SPI_CLK AV2 +3V_S5 R7 PCH_MBCLK0_R
PCH_SPI_SO AW3 SPI0_CLK GPP_C0/SMBCLK R8 PCH_MBDAT0_R
PCH_SPI_SI AV3 SPI0_MISO +3V_S5 GPP_C1/SMBDATA R10 SMBALERT#
SPI0_MOSI +3V_S5 GPP_C2/SMBALERT# SMBALERT# (4)
PCH_SPI_IO2 AW2
PCH_SPI_IO3 AU4 SPI0_IO2 +3V_S5 R9 VGA_MBCLK
D
PCH_SPI_CS0# AU3 SPI0_IO3 +3V_S5 GPP_C3/SML0CLK W2 VGA_MBDATA +3V_S5
D

AU2 SPI0_CS0# +3V_S5 GPP_C4/SML0DATA W1 SML0ALERT#


SPI0_CS1# GPP_C5/SML0ALERT# SML0ALERT# (4)
AU1 +3V_S5
SPI0_CS2# W3 SMB_ME1_CLK CLKRUN# R564 8.2K/F_4
+3V_S5 GPP_C6/SML1CLK V3 SMB_ME1_DAT IRQ_SERIRQ R566 10K_4
SPI - TOUCH +3V_S5 GPP_C7/SML1DATA AM7 SMB1ALERT# EC_RCIN# R546 10K_4
+3V_S5 GPP_B23/SML1ALERT#/PCHHOT# SMB1ALERT# (26)
M2 +3V_S5
M3 GPP_D1/SPI1_CLK +3V_S5
J4 GPP_D2/SPI1_MISO +3V_S5
V1 GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
+3V_S5 eSPI change to 15 ohm ckl v0.71 p.24
V2 +3V_S5
M1 GPP_D22/SPI1_IO3 AY13 R559 *short_4 +3V_S5
LPC
GPP_D0/SPI1_CS# +3V_S5 +3V_S5 GPP_A1/LAD0/ESPI_IO0 BA13 R547 *short_4
LPC_LAD0 (24,25,28)
+3V_S5 GPP_A2/LAD1/ESPI_IO1 BB13 R556 *short_4
LPC_LAD1 (24,25,28) SMBus
C LINK +3V_S5 GPP_A3/LAD2/ESPI_IO2 LPC_LAD2 (24,25,28)
AY12 R548 *short_4
G3 +3V_S5 GPP_A4/LAD3/ESPI_IO3 BA12 LPC_LAD3 (24,25,28)
LPC_LFRAME# (24,25,28) PCH_MBCLK0_R 2.2K_4 R473
G2 CL_CLK +3V_S5 GPP_A5/LFRAME#/ESPI_CS# BA11 R226 *0_4 PCH_MBDAT0_R 2.2K_4 R472
For M.2 wifi module must CL_DATA TP36
G1
CL_RST#
+3V_S5GPP_A14/SUS_STAT#/ESPI_RESET# C348 *0.1u/16V_4 VGA_MBDATA 2.2K_4 R479
eSPI change to 15 ohm VGA_MBCLK 2.2K_4 R145
AW9 R551 22/J_4 CLK_PCI_EC (28)
R573 *short_4 EC_RCIN# AW13 +3V_S5 GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9
(28) SIO_RCIN# GPP_A0/RCIN# +3V_S5 +3V_S5 GPP_A10/CLKOUT_LPC1 +3V_S5
AW11 R557 22/J_4 PCLK_TPM (24)
IRQ_SERIRQ AY11 +3V_S5 GPP_A8/CLKRUN# R558 22/J_4
(24,28) IRQ_SERIRQ GPP_A6/SERIRQ +3V_S5 CLKRUN#
CLK_PCI_LPC (25)
CLKRUN# (24,28)
SMB1ALERT# *150K_4 R187
5 OF 20
SKL_ULT/BGA
2/10 add C806 for EMI request ,
R748 no stuiff from EC site
move at CPU site Termination Resistor Requirement for PCH PCHHOT# Pin
Reserve PU 150K resister
PCH SPI ROM(8M)
15ohm CS01502JB12 R462 *0_6
C +3V_LDO_EC C
33ohm CS03302JB29 R475 0_6 +3V
+3V_S5 +3V_PCH_ME +3V_PCH_ME
Change to 2.2k
U29 C582 0.1u/16V_4
1A-13 PCH_SPI_CS0# 1 8
PCH_SPI_CLK_EC CS# VCC R456 R464
(28)
(28)
PCH_SPI_CLK_EC
PCH_SPI_SI_EC PCH_SPI_SI_EC
PCH_SPI_SO_EC
PCH_SPI_SO
PCH_SPI_SO_EC
R453
R457
15_4
15_4
SPI_SO_8M 2
IO1/DO IO3/HOLD#
7 SPI_HOLD_IO3_ME R466 1K_4 SMBus(PCH) Q35
2.2K_4 2.2K_4
(28) PCH_SPI_SO_EC
3 6 SPI_CLK_8M R461 15_4 PCH_SPI_CLK S5 5 S0
IO2/WP# CLK
5 SPI_SI_8M R465 15_4 PCH_SPI_SI PCH_MBDAT0_R 3 4 CLK_SDATA (11,12,19,26)
4 IO0/DI
GND
C587 2
W25Q64FV -- 8MB *22p/50V_4
PCH_SPI_CLK_EC R463 15_4 PCH_MBCLK0_R 6 1 CLK_SCLK (11,12,19,26)
PCH_SPI_SI_EC R468 15_4

SP@ socket P/N: DFHS08FS023 only for A-TEST +3V_PCH_ME R433 1K_4 SPI_WP_IO2_ME PCH_XDP_WLAN/S5 DMN601DWK-7 DDR_TP/S0
SPI ROM Vender Size Quanta P/N Vender P/N PCH_SPI_IO2 R415 15_4 SPI_WP_IO2_ME
3.3K is original and for no
WND 8M AKE3EFP0N07 W25Q64FVSSIQ support fast read function SMBus(EC)
Skylake PCH_SPI_IO3 R477 15_4 SPI_HOLD_IO3_ME
reserve for SPI fast read
3.3V GGD 8M AKE2EZN0Q00 GD25B64CSIGR

(28) SPI_CS0#_UR_ME R428 *Short/0_4 PCH_SPI_CS0# (16,28) 2ND_MBCLK 2ND_MBCLK R480 *Short/0_4 SMB_ME1_CLK
B (16,28) 2ND_MBDATA 2ND_MBDATA R476 *Short/0_4 SMB_ME1_DAT B

only 0ohm option


+3V_PCH_ME
EC/S5
R445 10K_4 SPI_CS0#_UR_ME

A A

Quanta Computer Inc.


PROJECT : ZRW
Size Document Number Rev
1A
Skylake 5 (SATA/HDA/SPI)
Date: Monday, February 22, 2016 Sheet 7 of 46
5 4 3 2 1
5 4 3 2 1

(28) RSMRST# R580


PCI_PLTRST#

SYS_RESET#

*short_4 PCH_RSMRST#
U34K SKL_ULT

SYSTEM POWER MANAGEMENT


AT11 SUS0#
SUS0#

SUSB#
(31)

(28,31)
08
R451 10K_4 +3V_S5 GPP_B12/SLP_S0# AP15 SUSB#
GPD4/SLP_S3# SUSC# (28)
+VCCIO AN10 +3V_S5 BA16 SUSC# +3V
B5 GPP_B13/PLTRST# +3V_S5 GPD5/SLP_S4# TP79
Reserve PU 10K SYS_RESET#
+3V_S5 GPD10/SLP_S5#
AY16 PCH_SLP_S5#
VCCST_PWRGD AY17 +3V_S5 SYS_RESET# R429 10K_4
RSMRST# AN15 PCH_SLP_SUS# TP23
R450 *10K_4 PROC_PWRGD PROC_PWRGD A68
I SLP_SUS# AW15 PCH_SLP_LAN#
B65 PROCPWRGD I SLP_LAN# BB17 TP33
EC_PWROK R420 *short_4 PCH_SLP_WLAN#
R568 *0_4 VCCST_PWRGD +3V_S5 GPD9/SLP_WLAN# AN16 PCH_SLP_A#
TP72
D
SYS_PWROK_R B6 +3V_S5 GPD6/SLP_A# *short_4 R585 TP75 D
SYS_PWROK DNBSWON# (28) +3V_S5
EC_PWROK_R BA20 BA15 PCH_PWRBTN#
DPWROK_R BB20 PCH_PWROK +3V_S5 GPD3/PWRBTN# AY15 PCH_ACPRESENT *short_4 R584
DSW_PWROK +3V_S5 GPD1/ACPRESENT SB_ACDC (28)
AU13 PCH_BATLOW# PCH_ACPRESENT R565 8.2K/F_4
+3V_S5 GPD0/BATLOW# TP35
(28) PCH_SUSPWRDNACK R597 *0_4 PCH_SUSPWRDNACK_C AR13 PCH_BATLOW# R229 8.2K/F_4
GPP_A13/SUSWARN#/SUSPWRDNACK +3V_S5 TP32
EC only PD, so PD 10K SUSACK#_R AP11
TP29 GPP_A15/SUSACK# +3V_S5 AU11 R222 1M_4 PCIE_LAN_WAKE# R236 10K_4
+3V_S5 GPP_A11/PME# +3V_RTC
(22,25) PCIE_LAN_WAKE# PCIE_LAN_WAKE# BB15 AP16 INTRUDER#
PCH_SUSPWRDNACK_C AM15 WAKE# INTRUDER# MPHY_EXT_PWR R184 *1K_4
TP25 AW17 GPD2/LAN_WAKE# +3V_S5 AM10 MPHY_EXT_PWR
AT15 GPD11/LANPHYPC +3V_S5 +3V_S5 GPP_B11/EXT_PWR_GATE# AM11 PCH_VRALERT# PCH_VRALERT# R206 10K_4
GPD7/RSVD +3V_S5 GPP_B2/VRALERT# TP30
+3V_S5
R579
11 OF 20 12/25 Change R206 pull-up to +3V_S5
SKL_ULT/BGA
10K_4

PCH_RSMRST# R567 10K_4


PCH_PWROK R555 10K_4
SKL_ULT
U34I SYS_PWROK_R R435 10K_4

CSI-2
+3V_S5
REV:E tPLT15(max 200us)
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
->SLP_S4# assertion to
C38 CSI2_DP0 CSI2_CLKP0 C32 VDDQ(+1.35VSUS) ramp
CSI2_DN1 CSI2_CLKN1 down start(SUSON)
12/28 Delete U12/C361 & Add R695
D38 D32 C361 *0.1u/16V_4
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29

5
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26 2 SUSC#
CSI2_DP3 CSI2_CLKP3 SUSON_R 4
C31 E13 R86 100/F_4 (31,33) SUSON_R 1 SUSON
CSI2_DN4 CSI2_COMP SUSON (28)
D31 B7
C33 CSI2_DP4 +3V_S5 GPP_D4/FLASHTRIG TP58 U12
Board ID

3
+1.8V_S5 D33 CSI2_DN5 *TC7SH08FU
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2 RAM_ID1
C R526 10K_4 RAM_ID1 R527 *10K_4 A33 CSI2_DP6 +1.8V_S5 GPP_F13/EMMC_DATA0 AP1 RAM_ID2 C
R524 10K_4 RAM_ID2 R525 *10K_4 B33 CSI2_DN7 +1.8V_S5 GPP_F14/EMMC_DATA1 AP3 RAM_ID3
R538 10K_4 RAM_ID3 R540 *10K_4 CSI2_DP7 +1.8V_S5 GPP_F15/EMMC_DATA2 AN3 Board_ID0 R235 0_4
R506 10K_4 Board_ID0 R507 *10K_4 A29 +1.8V_S5 GPP_F16/EMMC_DATA3 AN1 Board_ID1
R504 NAC@10K_4 Board_ID1 R505 IOAC@10K_4 B29 CSI2_DN8 +1.8V_S5 GPP_F17/EMMC_DATA4 AN2 Board_ID2
R521 10K_4 Board_ID2 R522 *GS@10K_4 C28 CSI2_DP8 +1.8V_S5 GPP_F18/EMMC_DATA5 AM4 Board_ID3
R498 *10K_4 Board_ID3 R499 TPM@10K_4 D28 CSI2_DN9 +1.8V_S5 GPP_F19/EMMC_DATA6 AM1 Board_ID4
CSI2_DP9 +1.8V_S5 GPP_F20/EMMC_DATA7 Board_ID4 (20)
Board_ID4 R500 TSU@10K_4 A27
B27 CSI2_DN10 AM2 Board_ID5
R495 10K_4 Board_ID5 R501 *10K_4 C27 CSI2_DP10 +1.8V_S5 GPP_F21/EMMC_RCLK AM3 Board_ID6
R493 10K_4 Board_ID6 R494 *10K_4 D27 CSI2_DN11 +1.8V_S5 GPP_F22/EMMC_CLK AP4 Board_ID7
CSI2_DP11 +1.8V_S5 GPP_F12/EMMC_CMD 12/28 Delete U14/R245/C372 & Change "MAINON_R" to "MAINON"
R519 10K_4 Board_ID7 R520 *10K_4
AT1 200/F_4 R542
EMMC_RCOMP
9 OF 20
SKL_ULT/BGA +3V_S5
REV:E tPLT17(max
200us) ->SLP_S3# C368 *0.1u/16V_4
Low High Low High assertion to IMVP
VR_ON(VRON) deassertion 12/28 Change from "SUSB#" to "MAINON"

5
BOARD_ID0 VRAM X32 VRAM X16 BOARD_ID5 For 14" For 15" / 17" 2 SUSB#
(R506) (R507) (R495) (R501) 4
(32,34) VRON_R 1 VRON VRON (28)
BOARD_ID1 Non IOAC IOAC BOARD_ID6 Reserved Reserve U13
(R504) (R505) (Default)

3
*MC74VHC1G08DFT2G

BOARD_ID2 Non G-sensor G-sensor BOARD_ID7 Reserved Reserve


(R521) (R522) (Default)
R244 0_4
BOARD_ID3 No TPM TPM
(R498) (R499)

B BOARD_ID4 No-Touch panel Touch panel Power Sequence B


(R500) Non Deep Sx

(28) PCH_PWROK R552 0_4 EC_PWROK_R

For platforms not supporting Deep B2A


S0->S5 & S0->S3
Sx, connect directly to RSMRST# No Deep Sx Power of sequence 1us
DPWROK_R R582 0_4 PCH_RSMRST# SUSB# -> VCCST_PWRGD
VCCST PWRGD CRB is via +1.05V PG +3V_S5

Remove
+3V_S5 U25 C529 0.1u/16V_4
+1V_VCCST
5 1
VCC NC

5
C528 2 SUSB#
Close to CPU R416
1K_4
0.1u/16V_4
A
2 VCCST_PWRGD_EN_L 4
1VCCST_PWRGD_EN

VCCST_PWRGD VCCST_PWRGD_R 4 3 U24

3
Y GND C527 C530 MC74VHC1G08DFT2G
R427 60.4/F_4 *1000P/50V_4 *1000P/50V_4
C557 74AUP1G07GW
1000P/50V_4
+3V
SYSPWOK Shortpad change
R388 *0_4
PLTRST# Buffer to 60.4 ohm. 11/6
C341 0.1u/16V_4 Stuff 1000P/50V
R390 *0_4 PCH_PWROK
5

R403 *0_4 IMVP_PWRGD_3V (2) VCCST_PWRGD_EN R391 0_4 HWPG HWPG (28) Reserve 1000P/50V
2
4
Rev:D change netmane for HWPG
PLTRST# (13,22,24,25,28) 1A-6 2013/10/21 Del APWORK.
A PCI_PLTRST# 1 A
EC_PWROK EC_PWROK (28)
U8
3

MC74VHC1G08 R212
100K_4

R410
*10K_4

Quanta Computer Inc.


PROJECT : ZRW
Size Document Number Rev
1A
Skylake 9/11 (PWROK/Board_ID)
Date: Monday, February 22, 2016 Sheet 8 of 46
5 4 3 2 1
5 4 3 2 1

U34S SKL_ULT
VCCPRIM_1P0 & VCCPRIM_CORE Short GPIO Group Power Plane 09
SKL_ULT
U34O C325 *1U/6.3V_4
RESERVED SIGNALS-1 C309 1U/6.3V_4
CPU POWER 4 OF 4
C255 1U/6.3V_4
E68 BB68 AB19 C274 *1U/6.3V_4
CFG[0] RSVD_TP_BB68 +1V_S5 VCCPRIM_1P0
D B67 BB69 AB20 AK15 +VCCPGPPA *short_6 R186 D
D65 CFG[1] RSVD_TP_BB69 C199 1U/6.3V_4 P18 VCCPRIM_1P0 1.0V 696mA VCCPGPPA AG15 +VCCPGPPB *short_6 R180
+3V_S5
D67 CFG[2] AK13 VCCPRIM_1P0 S5 VCCPGPPB Y16 +VCCPGPPC *short_6 R154
+3V_S5
CFG[3] RSVD_TP_AK13 TP24 44mA VCCPGPPC +3V_S5
CFG4 E70 AK12 AF18 S5 Y15 +VCCPGPPD *short_6 R153
CFG[4] RSVD_TP_AK12 +1V_S5 VCCPRIM_CORE VCCPGPPD +3V_S5
C68 Rev:F reserve TP C603 1U/6.3V_4 AF19 T16 +VCCPGPPE *short_6 R161
D68 CFG[5] BB2 V20 VCCPRIM_CORE 1.0V 2.574A VCCPGPPE AF16 +VCCPGPPF *short_6 R166
+3V_S5
CFG[6] RSVD_BB2 VCCPRIM_CORE S5 33mA VCCPGPPF +1.8V_S5
C67 BA3 Rev:F Stuff C699 C554 47u/6.3V_8 V21 41mA AD15 +VCCPGPPG *short_6 R171
CFG[7] RSVD_BA3 VCCPRIM_CORE VCCPGPPG +3V_S5
F71 C283 1U/6.3V_4
G69 CFG[8] 1U/6.3V_4 C623 +VCCDSW_1P0 AL1 75mA with AJ21 pin V19 +VCCPRIM_3P3 C299 *1U/6.3V_4
F70 CFG[9] AU5 DCPDSW _1P0 1.0V VCCPRIM_3P3_V19
G68 CFG[10] TP5 AT5 K17 T1 +VCCPRIM_1P0
H70 CFG[11] TP6 +1V_S5
C233 1U/6.3V_4 C602 1U/6.3V_4 L1 VCCMPHYAON_1P0 1.0V 1.0V VCCPRIM_1P0_T1 C286 1U/6.3V_4
+1V_S5
CFG[12] VCCMPHYAON_1P0 22mA
G71 6mA 1.8V AA1 +VCCATS_1P8 *short_6 R165
H69 CFG[13] D5 N15
S5 VCCATS_1P8 *short_6 R248
+1.8V_S5
CFG[14] RSVD_D5 +1V_S5 VCCMPHYGT_1P0_N15 +3V_S5
G70 D4 C121 1U/6.3V_4 N16 <1mA AK17 +VCCPRTCPRIM_3P3 C362 0.1U/16V_4
CFG[15] RSVD_D4 B2 N17 VCCMPHYGT_1P0_N16 1.0V VCCRTCPRIM_3P3 C358 1U/6.3V_4
E63 RSVD_B2 C2 C117 47u/6.3V_8 P15 VCCMPHYGT_1P0_N17 AK19 +VCCPRTC *short_6 R231
CFG[16] RSVD_C2 VCCMPHYGT_1P0_P15 1.258A VCCRTC_AK19 +3V_RTC
F63 P16 3.0V+ BB14 C352 1U/6.3V_4
CFG[17] B3 VCCMPHYGT_1P0_P16 VCCRTC_BB14 C353 0.1U/16V_4
E66 RSVD_B3 A3 K15
RTC BB10 DCPRTC C641 0.1U/16V_4
F66 CFG[18] RSVD_A3 C111 1U/6.3V_4 L15 VCCAMPHYPLL_1P0 DCPRTC
CFG[19] AW 1 VCCAMPHYPLL_1P0 1.0V A14
RSVD_AW 1 VCCCLK1 +1V_S5
R79 49.9/F_4 CFG_RCOMP E60 V15
CFG_RCOMP E1
+1V_S5 VCCAPLL_1P0 1.0V 26mA 1.0V K19
R88 1.5K/F_4 E8 RSVD_E1 E2 AB17
S5 VCCCLK2 C198 *1U/6.3V_4
+1V_S5 ITP_PMODE RSVD_E2 +1V_S5
Y18 VCCPRIM_1P0_AB17 135mA L21
C282 *1U/6.3V_4 1.0V 696mA
AY2 BA4 VCCPRIM_1P0_Y18 VCCCLK3
AY1 RSVD_AY2 RSVD_BA4 BB4 R200 *0_6 +VCCPDSW_3P3 AD17
S5 S5 N20
RSVD_AY1 RSVD_BB4 +3VPCU VCCDSW _3P3_AD17 VCCCLK4
R194 *short_6 AD18 3.3V S5
+3V_S5 VCCDSW _3P3_AD18
D1 A4 *0.1U/16V_4 C336 AJ17 118mA L19
C D3 RSVD_D1 RSVD_A4 C4 R588 0_6 VCCDSW _3P3_AJ17 VCCCLK5 C
RSVD_D3 RSVD_C4 +3V
R600 *0_6 +VCCHDA AJ19 1.5V 30mA A10
+1.5V VCCHDA VCCCLK6
K46 BB5 C652 1U/6.3V_4 C578 1U/6.3V_4
K45 RSVD_K46 TP4 R174 *short_6 +VCCPSPI AJ16 AN11 V0P85A_VID0
RSVD_K45 A69
+3V_S5 VCCSPI 3.3V 11mA S5 GPP_B0/CORE_VID0 AN13 TP37
AL25 RSVD_A69 B69 AF20
+3V GPP_B1/CORE_VID1
AL27 RSVD_AL25 RSVD_B69 AF21 VCCSRAM_1P0
RSVD_AL27 AY3
+1V_S5
T19 VCCSRAM_1P0 1.0V
RSVD_AY3 VCCSRAM_1P0 642mA
C71 C108 1U/6.3V_4 T20
B70 RSVD_C71 D71 VCCSRAM_1P0
RSVD_B70 RSVD_D71 C70 R155 *short_6 +VCCPRIM_3P3 AJ21
F60 RSVD_C70 +3V_S5
C278 1U/6.3V_4 VCCPRIM_3P3_AJ21 3.3V 75mA S5
RSVD_F60 C54 AK20
A52 RSVD_C54 D54
+1V_S5 VCCPRIM_1P0_AK20 1.0V 696mA S5
RSVD_A52 RSVD_D54 N18
BA70 AY4 +1V_S5 VCCAPLLEBB
C110 1U/6.3V_4 1.0V 33mA
BA68 RSVD_TP_BA70 TP1 BB3
RSVD_TP_BA68 TP2 15 OF 20
J71 AY71 SKL_ULT/BGA
J68 RSVD_J71 VSS_AY71 AR56 R172 GT3@0_4
RSVD_J68 ZVM# LPM_ZVM_N (32)
F65 AW 71
G65 VSS_F65 RSVD_TP_AW 71 AW 70
VSS_G65 RSVD_TP_AW 70 For 2+3e CPU No Stuff
F61 AP56
E61 RSVD_F61 MSM# C64 R417 100K_4 TP21
RSVD_E61 PROC_SELECT#

19 OF 20
+1V_VCCST
B SKL_ULT/BGA B

Pin Name Strap description Configuration Note


1 = *Normal Operation; No stall (iPU 3K)
CFG[0] Stall reset sequence after PCU PLL lock until de-asserted
0 = Stall

CFG[1] Reserved Configuration lane

1 = *Normal Operation(iPU 3K)


CFG[2] PCI Express* Static x16 Lane Numbering Reversal H & S processor used only
0 = Lan number reversed

CFG[3] Reserved Configuration lane

1 = Disabled (iPU 3K) CFG4


CFG[4] eDP enable R455 1K_4
0 = *Enabled

00 = 1x8, 2x4 PCI Express*


01 = reserved
CFG[6:5] PCI Express* Bifunction H & S processor used only
A 10 = 2x8 PCI Express* A

11 = 1x16 PCI Express*


1 = *PEG Train immediatedly follow
CFG[7] PEG Training RESET# de-assertion (iPU 3K)
H & S processor used only
0 = PEG wait for BIOS for training
Quanta Computer Inc.
CFG[19:8] Reserved Configuration lane PROJECT : ZRW
Size Document Number Rev
1A
Skylake PCH-LP 15/19 (POWER)
Date: Monday, February 22, 2016 Sheet 9 of 46
5 4 3 2 1
5 4 3 2 1

Skylake ULT (GND) 10


SKL_ULT U34P SKL_ULT U34Q
SKL_ULT
U34R U34T SKL_ULT ?
D D
GND 1 OF 3 GND 2 OF 3 GND 3 OF 3 SPARE

A5 AL65 AT63 BA49 F8 L18 AW69 F6


A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2 AW68 RSVD_AW69 RSVD_F6 E3
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20 +1.8V_S5 AU56 RSVD_AW68 RSVD_E3 C11
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4 AW48 RSVD_AU56 RSVD_C11 B11
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8 C7 RSVD_AW48 RSVD_B11 A11
AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10 R491 *0_4 U12 RSVD_C7 RSVD_A11 D12
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13 U11 RSVD_U12 RSVD_D12 C12
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19 H11 RSVD_U11 RSVD_C12 F52
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21 RSVD_H11 RSVD_F52
AB18 VSS VSS AM55 AV68 VSS VSS BB30 G58 VSS VSS N6 C614
AB21 VSS VSS AM60 AV69 VSS VSS BB34 G6 VSS VSS N65
VSS VSS VSS VSS VSS VSS 20 OF 20
AB8 AM61 AV70 BB38 G60 N68 *1U/6.3V_4
VSS VSS VSS VSS VSS VSS SKL_ULT/BGA
AD13 AM68 AV71 BB43 G63 P17 REV = 1 ?
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE65 VSS VSS AN33 AW26 VSS VSS C25 J28 VSS VSS T18
C
AE66 VSS VSS AN35 AW28 VSS VSS C5 J32 VSS VSS T2
Reserve 1uF no stuff in CPU U11,U12 ball C

AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21 support Cannonlake-U PCH
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF2 VSS VSS AP18 AW45 VSS VSS D30 K61 VSS VSS U69
AF4 VSS VSS AP20 AW47 VSS VSS D34 K63 VSS VSS U70
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
AG19 VSS VSS AP38 AW57 VSS VSS D48 K68 VSS VSS W6
AG20 VSS VSS AP42 AW6 VSS VSS D53 K70 VSS VSS W9
AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15
AJ15 VSS VSS AR20 B14 VSS VSS E18 18 OF 20
B SKL_ULT/BGA B
AJ18 VSS VSS AR23 B18 VSS VSS E21
AJ20 VSS VSS AR28 B22 VSS VSS E46
AJ4 VSS VSS AR35 B30 VSS VSS E50
AK11 VSS VSS AR42 B34 VSS VSS E53
AK16 VSS VSS AR43 B39 VSS VSS E56
AK18 VSS VSS AR45 B44 VSS VSS E6
AK21 VSS VSS AR46 B48 VSS VSS E65
AK22 VSS VSS AR48 B53 VSS VSS E71
AK27 VSS VSS AR5 B58 VSS VSS F1
AK63 VSS VSS AR50 B62 VSS VSS F13
AK68 VSS VSS AR52 B66 VSS VSS F2
AK69 VSS VSS AR53 B71 VSS VSS F22
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL28 VSS VSS AR63 BA14 VSS VSS F28
AL32 VSS VSS AR8 BA18 VSS VSS F32
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL38 VSS VSS AT20 BA23 VSS VSS F35
AL4 VSS VSS AT23 BA28 VSS VSS F37
AL45 VSS VSS AT28 BA32 VSS VSS F38
AL48 VSS VSS AT35 BA36 VSS VSS F4
AL52 VSS VSS AT4 F68 VSS VSS F40
AL55 VSS VSS AT42 BA45 VSS VSS F42
A AL58 VSS VSS AT56 VSS VSS BA41 A
AL64 VSS VSS AT58 VSS
VSS VSS

16 OF 20
17 OF 20
Quanta Computer Inc.
SKL_ULT/BGA SKL_ULT/BGA
PROJECT : ZRW
Size Document Number Rev
1A
Skylake 10/17/18 (GND)
Date: Monday, February 22, 2016 Sheet 10 of 46
5 4 3 2 1
5 4 3 2 1

(3) M_A_A[13:0]
144
P/N and F/P
JDIM2A
8
M_A_DQ[63:0] (3)
111
112
JDIM2B

VDD1
C379 2.2U/6.3V/X7R_6
11
M_A_A0 M_A_DQ0 C377 0.1U/25V_4
M_A_A1 133 A0 DQ0 7 M_A_DQ1 117 VDD2
M_A_A2 132 A1 DQ1 20 M_A_DQ3 118 VDD3 255 R271 *0_4
A2 DQ2 VDD4 VDDSPD +2.5V
M_A_A3 131 21 M_A_DQ6 +1.2VSUS 123
A3 DQ3 0-7 VDD5 R282 *short/0_4
M_A_A4 128 4 M_A_DQ5 124 +3V
M_A_A5 126 A4 DQ4 3 M_A_DQ4 129 VDD6 257
A5 DQ5 VDD7 VPP1 +2.5V_SUS
M_A_A6 127 16 M_A_DQ7 130 259
A6 DQ6 VDD8 VPP2 12/4 Change for +3.3V to +3V
M_A_A7 122
A7 DQ7
17 M_A_DQ2 135
VDD9
0.5A
M_A_A8 125 28 M_A_DQ9 136
M_A_A9 121 A8 DQ8 29 M_A_DQ8 2250mA 141 VDD10 258
A9 DQ9 VDD11 VTT +VDDQ_VTT
M_A_A10 146 41 M_A_DQ11 142
D M_A_A11 120 A10/AP DQ10 42 M_A_DQ10 8-15 147 VDD12 600mA D
M_A_A12 119 A11 DQ11 24 M_A_DQ13 148 VDD13
M_A_A13 158 A12 DQ12 25 M_A_DQ12 153 VDD14 164 VREF_CA_DIMM0
151 A13 DQ13 38 M_A_DQ14 154 VDD15 VREF_CA
(3) M_A_WE# A14/WE# DQ14 VDD16
156 37 M_A_DQ15 159
(3) M_A_CAS# A15/CAS# DQ15 VDD17
152 50 M_A_DQ21 160
(3) M_A_RAS# A16/RAS# DQ16 VDD18
49 M_A_DQ16 163
TP41 162 DQ17 62 M_A_DQ19 VDD19
TP40 165 S2#/C0 DQ18 63 M_A_DQ22 16-23
S3#/C1 DQ19 46 1 2

DDR4 SODIMM 260 PIN


M_A_DQ17
DQ20 45 M_A_DQ20 5 VSS1 VSS48 6
+1.2VSUS 114 DQ21 58 M_A_DQ23 9 VSS2 VSS49 10
(3) M_A_ACT# ACT# DQ22 VSS3 VSS50
143 59 M_A_DQ18 15 14
(3) M_A_PARITY PARITY DQ23 VSS4 VSS51
116 70 M_A_DQ25 19 18
(3) M_A_ALERT# ALERT# DQ24 VSS5 VSS52
M_A_EVENT# 134 71 M_A_DQ28 23 22
108 EVENT# DQ25 83 M_A_DQ27 27 VSS6 VSS53 26
(3,12) DDR3_DRAMRST# RESET# DQ26 24-31 VSS7 VSS54
R315 84 M_A_DQ30 31 30
DQ27 VSS8 VSS55

DDR4 SODIMM 260 PIN


240/F_4 C460 *0.1U/16V_4 66 M_A_DQ24 35 36
DQ28 67 M_A_DQ29 39 VSS9 VSS56 40
M_A_EVENT# DQ29 79 M_A_DQ26 43 VSS10 VSS57 44
DQ30 80 M_A_DQ31 47 VSS11 VSS58 48
DQ31 174 M_A_DQ33 51 VSS12 VSS59 52
DQ32 173 M_A_DQ37 57 VSS13 VSS60 56
DQ33 187 M_A_DQ35 61 VSS14 VSS61 60
DQ34 186 M_A_DQ34 65 VSS15 VSS62 64
32-39

(260P)
DQ35 170 M_A_DQ36 69 VSS16 VSS63 68
DQ36 169 M_A_DQ32 73 VSS17 VSS64 72
DQ37 183 M_A_DQ38 77 VSS18 VSS65 78
DQ38 182 M_A_DQ39 81 VSS19 VSS66 82
DQ39 195 M_A_DQ45 85 VSS20 VSS67 86
150 DQ40 194 M_A_DQ41 89 VSS21 VSS68 90
(3) M_A_BA#0 BA0 DQ41 VSS22 VSS69
+3V 145 207 M_A_DQ46 93 94
(3) M_A_BA#1 BA1 DQ42 VSS23 VSS70
115 208 M_A_DQ42 99 98

(260P)
(3) M_A_BG#0 BG0 DQ43 40-47 VSS24 VSS71
113 191 M_A_DQ44 103 102
(3) M_A_BG#1 BG1 DQ44 VSS25 VSS72
190 M_A_DQ40 107 106
149 DQ45 203 M_A_DQ47 167 VSS26 VSS73 168
(3) M_A_CS#0 S0# DQ46 VSS27 VSS74
157 204 M_A_DQ43 171 172
(3) M_A_CS#1 S1# DQ47 VSS28 VSS75
C 109 216 M_A_DQ52 175 176 C
(3) M_A_CKE0 CKE0 DQ48 VSS29 VSS76
R313 R311 R332 110 215 M_A_DQ53 181 180
(3) M_A_CKE1 CKE1 DQ49 VSS30 VSS77
*10K_4 *10K_4 *10K_4 228 M_A_DQ50 185 184
137 DQ50 229 M_A_DQ51 48-55 189 VSS31 VSS78 188
(3) M_A_CLK0 CK0 DQ51 VSS32 VSS79
CHA_SA0 CHA_SA1 CHA_SA2 139 211 M_A_DQ48 193 192
(3) M_A_CLK0# CK0# DQ52 VSS33 VSS80
138 212 M_A_DQ49 +1.2VSUS 197 196
(3) M_A_CLK1 CK1 DQ53 VSS34 VSS81
R322 R320 R333 140 224 M_A_DQ55 201 202
(3) M_A_CLK1# CK1# DQ54 VSS35 VSS82
10K_4 10K_4 10K_4 225 M_A_DQ54 205 206
155 DQ55 237 M_A_DQ63 209 VSS36 VSS83 210
(3) M_A_ODT0_DIMM ODT0 DQ56 VSS37 VSS84
161 236 M_A_DQ58 213 214
(3) M_A_ODT1_DIMM ODT1 DQ57 VSS38 VSS85
249 M_A_DQ56 R306 217 218
253 DQ58 250 M_A_DQ61 223 VSS39 VSS86 222
(7,12,19,26) CLK_SCLK SCL DQ59 56-63 240/F_4 VSS40 VSS87
254 232 M_A_DQ59 227 226
(7,12,19,26) CLK_SDATA SDA DQ60 VSS41 VSS88
233 M_A_DQ62 M_A_DQS8 231 230
CHA_SA0 256 DQ61 245 M_A_DQ60 235 VSS42 VSS89 234
CHA_SA1 260 SA0 DQ62 246 M_A_DQ57 239 VSS43 VSS90 238
+1.2VSUS
+1.2VSUS CHA_SA2 166 SA1 DQ63 243 VSS44 VSS91 244
SA2 M_A_DQS[7:0] (3) VSS45 VSS92
13 M_A_DQS0 247 248
M_A_CB0 92 DQS0 34 M_A_DQS1 251 VSS46 VSS93 252
R319 240/F_4 CB0 DQS1 VSS47 VSS94
R305 240/F_4 M_A_CB1 91 55 M_A_DQS2
M_A_CB2 101 CB1 DQS2 76 M_A_DQS3
R308 240/F_4 CB2 DQS3 R307
R309 240/F_4 M_A_CB3 105 179 M_A_DQS4
CB3 DQS4 240/F_4
R318 240/F_4 M_A_CB4 88 200 M_A_DQS5 261
M_A_CB5 87 CB4 DQS5 221 M_A_DQS6 GND 262
R304 240/F_4 CB5 DQS6 M_A_DQS#8 GND
R317 240/F_4 M_A_CB6 100 242 M_A_DQS7
M_A_CB7 104 CB6 DQS7 97 M_A_DQS8
R316 240/F_4 CB7 DQS8
M_A_DQS#[7:0] (3)
12 11 M_A_DQS#0
33 DM0 DQS#0 32 M_A_DQS#1
+1.2VSUS DM1 DQS#1
54 53 M_A_DQS#2
75 DM2 DQS#2 74 M_A_DQS#3
178 DM3 DQS#3 177 M_A_DQS#4 12/21 Change JDIM2 footprint to "ddr4-d4as0-26001-1p52-std-smt " for SMT requset
199 DM4 DQS#4 198 M_A_DQS#5
220 DM5 DQS#5 219 M_A_DQS#6
241 DM6 DQS#6 240 M_A_DQS#7
DM7 DQS#7 +1.2VSUS
96
DM8 DQS#8
95 M_A_DQS#8 VREF DQ0 M1 Solution
B B

R321
1K/F_4

+VREF_CA_CPU R327 2/F_6 VREF_CA_DIMM0 *0_4 R325 +VDDQ

1
C473
0.022U/25V_4 R328
1K/F_4

2
R334 24.9/F_4

Place these Caps near So-Dimm1.


1uF/10uF 4pcs on each side of connector
+1.2VSUS +VDDQ_VTT VREF_CA_DIMM0

C399 1U/6.3V_4 C465 0.1U/16V_4


C425 1U/6.3V_4
C391 1U/6.3V_4 C464 2.2U/6.3V_6
C412 1U/6.3V_4
C408 1U/6.3V_4
C423 1U/6.3V_4
C381 1U/6.3V_4 +2.5V_SUS
C415 1U/6.3V_4
C449 1U/6.3V_4 C374 0.1U/16V_4
C409 10U/6.3V_6
C414 1U/6.3V_4 C378 2.2U/6.3V_6
+3V
A C427 1U/6.3V_4 A
C444 0.1U/16V_4
C438 1U/6.3V_4
C441 2.2U/6.3V_6
C392 10U/6.3V_6
C385 10U/6.3V_6

C383 10U/6.3V_6
(3,5,12,33) +1.2VSUS C382 10U/6.3V_6
(12,33) +VDDQ_VTT
C393 10U/6.3V_6
(2,4,6,7,8,9,12,13,15,19,20,21,22,23,24,25,26,27,28,30,31,32,33,34,37,38,39) +3V C426 10U/6.3V_6 Quanta Computer Inc.
C416 10U/6.3V_6
C386 10U/6.3V_6 PROJECT : ZRW
Size Document Number Rev
1A
DDR4 DIMM-RVS(5.2H) CHA
Date: Monday, February 22, 2016 Sheet 11 of 46
5 4 3 2 1
5 4 3 2 1

(3) M_B_A[13:0]
M_B_DQ[63:0] (3)
12
JDIM1A
M_B_A0 144 8 M_B_DQ9 JDIM1B
A0 DQ0 C395 2.2U/6.3V/X7R_6
M_B_A1 133 7 M_B_DQ8
A1 DQ1 111
M_B_A2 132 20 M_B_DQ10 VDD1
A2 DQ2 112 C401 0.1U/25V_4
M_B_A3 131 21 M_B_DQ15 VDD2
A3 DQ3 8-15 117
M_B_A4 128 4 M_B_DQ13 VDD3
A4 DQ4 118 255 R276 *0_4
M_B_A5 126 3 M_B_DQ12 VDD4 VDDSPD +2.5V
A5 DQ5 +1.2VSUS 123
M_B_A6 127 16 M_B_DQ11 VDD5
A6 DQ6 124 R281 *short/0_4
M_B_A7 122 17 M_B_DQ14 VDD6 +3V
A7 DQ7 129 257
M_B_A8 125 28 M_B_DQ5 VDD7 VPP1 +2.5V_SUS
D A8 DQ8 130 259
M_B_A9 121 29 M_B_DQ1 VDD8 VPP2 D
A9 DQ9 135 12/4 Change for +3.3V to +3V
M_B_A10 146
A10/AP DQ10
41 M_B_DQ6
136 VDD9 0.5A
M_B_A11 120 42 M_B_DQ7 VDD10
A11 DQ11 0-7 141 258
M_B_A12 119
A12 DQ12
24 M_B_DQ4 2250mA 142 VDD11 VTT +VDDQ_VTT
M_B_A13 158 25 M_B_DQ0 VDD12
A13 DQ13 147
(3) M_B_WE#
151
A14/WE# DQ14
38 M_B_DQ2
148 VDD13 600mA
156 37 M_B_DQ3 VDD14
(3) M_B_CAS# A15/CAS# DQ15 153 164 VREF_CA_DIMM1
152 50 M_B_DQ17 VDD15 VREF_CA
(3) M_B_RAS# A16/RAS# DQ16 154
49 M_B_DQ21 VDD16
DQ17 159
TP39 162 62 M_B_DQ23 VDD17
S2#/C0 DQ18 16-23 160
TP38 165 63 M_B_DQ19 VDD18
S3#/C1 DQ19 163
46 M_B_DQ16 VDD19
DQ20 45 M_B_DQ20
114 DQ21 58 M_B_DQ22
1 2

DDR4 SODIMM 260 PIN


(3) M_B_ACT# ACT# DQ22
143 59 M_B_DQ18 VSS1 VSS48
(3) M_B_PARITY PARITY DQ23 5 6
116 70 M_B_DQ28 VSS2 VSS49
+1.2VSUS (3) M_B_ALERT# ALERT# DQ24 9 10
M_B_EVENT# 134 71 M_B_DQ25 VSS3 VSS50
EVENT# DQ25 15 14
108 83 M_B_DQ26 VSS4 VSS51
(3,11) DDR3_DRAMRST# RESET# DQ26 24-31 19 18
84 M_B_DQ27 VSS5 VSS52
DQ27 23 22

DDR4 SODIMM 260 PIN


C461 *0.1U/16V_4 66 M_B_DQ29 VSS6 VSS53
DQ28 27 26
67 M_B_DQ24 VSS7 VSS54
DQ29 31 30
R301 79 M_B_DQ30 VSS8 VSS55
DQ30 35 36
240/F_4 80 M_B_DQ31 VSS9 VSS56
DQ31 39 40
174 M_B_DQ37 VSS10 VSS57
DQ32 43 44
M_B_EVENT# 173 M_B_DQ32 VSS11 VSS58
DQ33 47 48
187 M_B_DQ39 VSS12 VSS59
DQ34 51 52
186 M_B_DQ34 VSS13 VSS60
DQ35 32-39 57 56
170 M_B_DQ36 VSS14 VSS61
DQ36 61 60
169 M_B_DQ33 VSS15 VSS62
DQ37 65 64
183 M_B_DQ38

(260P)
69 VSS16 VSS63 68
DQ38 182 M_B_DQ35
73 VSS17 VSS64 72
DQ39 195 M_B_DQ44
77 VSS18 VSS65 78
150 DQ40 194 M_B_DQ45
(3) M_B_BA#0 81 VSS19 VSS66 82
145 BA0 DQ41 207 M_B_DQ42
+3V (3) M_B_BA#1 85 VSS20 VSS67 86
115 BA1 DQ42 208 M_B_DQ47
89 VSS21 VSS68 90

(260P)
(3) M_B_BG#0 BG0 DQ43 40-47
113 191 M_B_DQ41 VSS22 VSS69
(3) M_B_BG#1 BG1 DQ44 93 94
190 M_B_DQ40 VSS23 VSS70
DQ45 99 98
C 149 203 M_B_DQ43 VSS24 VSS71 C
(3) M_B_CS#0 S0# DQ46 103 102
157 204 M_B_DQ46 VSS25 VSS72
(3) M_B_CS#1 S1# DQ47 107 106
109 216 M_B_DQ49 VSS26 VSS73
(3) M_B_CKE0 CKE0 DQ48 167 168
R300 R302 R290 110 215 M_B_DQ53 VSS27 VSS74
(3) M_B_CKE1 CKE1 DQ49 171 172
*10K_4 10K_4 *10K_4 228 M_B_DQ54 VSS28 VSS75
DQ50 48-55 175 176
137 229 M_B_DQ50 VSS29 VSS76
(3) M_B_CLK0 CK0 DQ51 181 180
CHB_SA0 CHB_SA1 CHB_SA2 139 211 M_B_DQ52 VSS30 VSS77
(3) M_B_CLK0# CK0# DQ52 185 184
138 212 M_B_DQ48 VSS31 VSS78
(3) M_B_CLK1 CK1 DQ53 189 188
R294 R295 R287 140 224 M_B_DQ51 VSS32 VSS79
(3) M_B_CLK1# CK1# DQ54 193 192
10K_4 *10K_4 10K_4 225 M_B_DQ55 VSS33 VSS80
DQ55 197 196
155 237 M_B_DQ56 VSS34 VSS81
(3) M_B_ODT0_DIMM ODT0 DQ56 201 202
161 236 M_B_DQ60 VSS35 VSS82
(3) M_B_ODT1_DIMM ODT1 DQ57 205 206
249 M_B_DQ58 VSS36 VSS83
DQ58 209 210
253 250 M_B_DQ62 VSS37 VSS84
(7,11,19,26) CLK_SCLK SCL DQ59 56-63 213 214
254 232 M_B_DQ61 VSS38 VSS85
(7,11,19,26) CLK_SDATA SDA DQ60 217 218
233 M_B_DQ57 VSS39 VSS86
DQ61 223 222
CHB_SA0 256 245 M_B_DQ59 VSS40 VSS87
SA0 DQ62 227 226
CHB_SA1 260 246 M_B_DQ63 VSS41 VSS88
+1.2VSUS SA1 DQ63 231 230
CHB_SA2 166 +1.2VSUS VSS42 VSS89
SA2 M_B_DQS[7:0] (3) 235 234
13 M_B_DQS1 VSS43 VSS90
DQS0 239 238
R292 240/F_4 M_B_CB0 92 34 M_B_DQS0 VSS44 VSS91
CB0 DQS1 243 244
R272 240/F_4 M_B_CB1 91 55 M_B_DQS2 VSS45 VSS92
CB1 DQS2 247 248
R280 240/F_4 M_B_CB2 101 76 M_B_DQS3 VSS46 VSS93
CB2 DQS3 251 252
R275 240/F_4 M_B_CB3 105 179 M_B_DQS4 VSS47 VSS94
CB3 DQS4 R277
R293 240/F_4 M_B_CB4 88 200 M_B_DQS5
M_B_CB5 87 CB4 DQS5 221 M_B_DQS6 240/F_4
R273 240/F_4 CB5 DQS6
R288 240/F_4 M_B_CB6 100 242 M_B_DQS7
CB6 DQS7 M_B_DQS8 261
R303 240/F_4 M_B_CB7 104 97 M_B_DQS8 GND
CB7 DQS8 262
M_B_DQS#[7:0] (3) +1.2VSUS GND
12 11 M_B_DQS#1
33 DM0 DQS#0 32 M_B_DQS#0
+1.2VSUS DM1 DQS#1
54 53 M_B_DQS#2
75 DM2 DQS#2 74 M_B_DQS#3
178 DM3 DQS#3 177 M_B_DQS#4
DM4 DQS#4 R278
199 198 M_B_DQS#5
220 DM5 DQS#5 219 M_B_DQS#6 240/F_4
241 DM6 DQS#6 240 M_B_DQS#7
DM7 DQS#7 M_B_DQS#8
B 96 95 M_B_DQS#8 B
DM8 DQS#8

12/21 Change JDIM1 footprint to "ddr4-d4ar0-26001-1p52-rvs-smt " for SMT requset


(2,4,6,7,8,9,11,13,15,19,20,21,22,23,24,25,26,27,28,30,31,32,33,34,37,38,39) +3V

(3,5,11,33) +1.2VSUS
(11,33) +VDDQ_VTT

Place these Caps near So-Dimm0.


For EMI RESERVE 1uF/10uF 4pcs on each side of connector
+1.2VSUS +VDDQ_VTT VREF DQ1 M1 Solution
+1.2VSUS
+1.2VSUS C380 1U/6.3V_4 C471 1U/6.3V_4

EC1 *120P/50V_4 EC16 *120P/50V_4 C448 1U/6.3V_4 C453 1U/6.3V_4 +1.2VSUS

EC8 *120P/50V_4 EC10 *120P/50V_4 C458 1U/6.3V_4 C459 1U/6.3V_4

EC2 *120P/50V_4 EC12 *120P/50V_4 C454 1U/6.3V_4 C467 1U/6.3V_4


R286
EC3 120P/50V_4 EC9 *0.1U/16V_4 C457 1U/6.3V_4 C424 1U/6.3V_4 1K/F_4

EC4 *120P/50V_4 EC11 *0.1U/16V_4 C456 1U/6.3V_4 +VREFDQ_SB_M3 +VREFDQ_SB_M3 R298 2/F_6 VREF_CA_DIMM1 *0_4 R296 +VDDQ

1
EC5 *120P/50V_4 EC15 *0.1U/16V_4 C436 1U/6.3V_4
VREF_CA_DIMM1 C419
EC6 *120P/50V_4 EC13 *0.1U/16V_4 C432 1U/6.3V_4 0.022U/25V_4 R297

2
C411 0.1U/16V_4 1K/F_4

C469 10U/6.3V_6 C413 2.2U/6.3V_6 R299


A +VDDQ_VTT 24.9/F_4 A
C437 10U/6.3V_6
EC7 *120P/50V_4 +2.5V_SUS
C470 10U/6.3V_6
EC14 *120P/50V_4 C434 0.1U/16V_4
C468 10U/6.3V_6
C430 2.2U/6.3V_6
C439 10U/6.3V_6

C463 10U/6.3V_6 +3V

C462 10U/6.3V_6 C428 0.1U/16V_4 Quanta Computer Inc.


C440 10U/6.3V_6 C431 2.2U/6.3V_6
PROJECT : ZRW
Size Document Number Rev
1A
DDR4 DIMM-STD(5.2H) CHB
Date: Monday, February 22, 2016 Sheet 12 of 46
5 4 3 2 1
1 2 3 4 5 6 7 8

PEX_IOVDD/Q : 3300mA
+1.05V_GFX
To be placed no further from the GPU
than bewteen the PS and GPU
AG19
AG21
AG22
AG24
U1030A
N15P-GT
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
[PEG Interface]
PEX_RX0
PEX_RX0_N
PEX_RX1
AN12
AM12
AN14
AM14
PEG_TX0
PEG_TX#0
PEG_TX1
PEG_TX#1
(6)
(6)
(6)
(6)
13
AH21 PEX_IOVDD_4 PEX_RX1_N AP14
PEX_IOVDD_5 PEX_RX2 PEG_TX2 (6)
C1175 EV@22U/6.3V_6X AH25 AP15 PEG_TX#2 (6)
C1139 EV@22U/6.3V_6X PEX_IOVDD_6 PEX_RX2_N AN15
PEX_RX3 PEG_TX3 (6)
C1143 EV@22U/6.3V_6X AG13 AM15 PEG_TX#3 (6)
C1140 EV@22U/6.3V_6X AG15 PEX_IOVDDQ_1 PEX_RX3_N AN17
A A
C1138 EV@10U/6.3V_6X AG16 PEX_IOVDDQ_2 PEX_RX4 AM17
C1104 EV@10U/6.3V_6X AG18 PEX_IOVDDQ_3 PEX_RX4_N AP17
C1102 EV@10U/6.3V_6X AG25 PEX_IOVDDQ_4 PEX_RX5 AP18
C1103 EV@10U/6.3V_6X AH15 PEX_IOVDDQ_5 PEX_RX5_N AN18
AH18 PEX_IOVDDQ_6 PEX_RX6 AM18
AH26 PEX_IOVDDQ_7 PEX_RX6_N AN20
PLACE NEAR BALLS AH27 PEX_IOVDDQ_8 PEX_RX7 AM20
AJ27 PEX_IOVDDQ_9 PEX_RX7_N AP20
C1159 EV@1U/6.3V_4X AK27 PEX_IOVDDQ_10 PEX_RX8 AP21
C1182 EV@1U/6.3V_4X AL27 PEX_IOVDDQ_11 PEX_RX8_N AN21
C1165 EV@1U/6.3V_4X AM28 PEX_IOVDDQ_12 PEX_RX9 AM21
3V MAIN POWER
C1077 EV@1U/6.3V_4X AN28 PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_RX9_N
PEX_RX10
AN23 GC6:+3V_MAIN +3V_GFX +3V_GFX
AM23
PEX_RX10_N AP23 3/11 GC6 timing issue from
PLACE UNDER BGA PEX_RX11 AP24
GC6 Power control 200K change to 100K
PEX_RX11_N AN24
C1097 EV@4.7U/10V_6X PEX_RX12 AM24
C1126 EV@4.7U/10V_6X PEX_RX12_N AN26 +3V_GFX R1140 C1294
PEX_RX13 AM26 EV@10K_4

1
PEX_RX13_N AP26 EV@0.022U/25V_4
PEX_RX14 AP27
PEX_RX14_N already PU@P.17
AN27
PEX_RX15 AM27 R1145 R1148 EV@100K_4 2 Q1023
PEX_RX15_N EV@AO3413
*EV@10K_4

3
AK14 PEG_RXP0_C C1186 EV@0.22U/10V_4
PEX_TX0 PEG_RX0 (6) +3V_MAIN
AJ14 PEG_RXN0_C C1179 EV@0.22U/10V_4
PEG_RX#0 (6)

3
PEX_TX0_N AH14 PEG_RXP1_C C1176 EV@0.22U/10V_4 C1311
PEX_TX1 PEG_RX1 (6)
B AG14 PEG_RXN1_C C1167 EV@0.22U/10V_4 (16) +3V_MAIN_EN 2 B
PEX_TX1_N PEG_RX#1 (6)
AK15 PEG_RXP2_C C1136 EV@0.22U/10V_4 EV@0.022U/25V_4
PEX_TX2 PEG_RX2 (6)
AJ15 PEG_RXN2_C C1118 EV@0.22U/10V_4 Q1017
PEX_TX2_N PEG_RX#2 (6)
AL16 PEG_RXP3_C C1162 EV@0.22U/10V_4 EV@2N7002K 1A-7
PEX_TX3 PEG_RX3 (6)
AK16 PEG_RXN3_C C1152 EV@0.22U/10V_4
PEG_RX#3 (6)

1
PEX_TX3_N AK17
PEX_TX4 AJ17
PEX_TX4_N AH17
AC6 PEX_TX5 AG17
AJ28 NC_1 PEX_TX5_N AK18
AJ4 NC_2 PEX_TX6 AJ18
AJ5 NC_3 PEX_TX6_N AL19
AL11 NC_4 PEX_TX7 AK19
C15 NC_5 PEX_TX7_N AK20
D19 NC_6 PEX_TX8 AJ20
D20 NC_7 PEX_TX8_N AH20
D23 NC_8 PEX_TX9 AG20 +3V +3V
D26 NC_9
NC_10
PEX_TX9_N
PEX_TX10
AK21 GC6 PEGX_RST# +3V_GFX
H31 AJ21
NC_11 PEX_TX10_N (16) SYS_PEX_RST_MON#
T8 AL22
V32 NC_12 PEX_TX11 AK22
Y1 NC_13 PEX_TX11_N AK23 C1621
Y2 NC_14 PEX_TX12 AJ23 EV@0.1U/16V_4X C1613 R1471
Y3 NC_15 PEX_TX12_N AH23 EV@0.1U/16V_4X *EV@10K_4

5
AA1 NC_16 PEX_TX13 AG23

5
PLACE CLOSE TO BGA AA2 NC_17 PEX_TX13_N AK24 2
NC_18 PEX_TX14 (8,22,24,25,28) PLTRST#
C1343 EV@4.7U/6.3V_4X AA3 AJ24 4 RST_MON# 2
C1210 EV@1U/6.3V_4X AA4 NC_19 PEX_TX14_N AL25 1 4 PEGX_RST#
NC_20 PEX_TX15 (4) DGPU_HOLD_RST#
AA5 AK25 1
C AA6 NC_21 PEX_TX15_N C1630 U1032 C

3
C1209 EV@0.1u/16V_4 AA7 NC_22 EV@74AHC1G09GW

3
C1183 *EV@0.1U/16V_4X AA8 NC_23 AL13 U1031 R1469
NC_24 PEX_REFCLK CLK_PCIE_VGA (6)
C1188 *EV@0.1U/16V_4X AK13 CLK_PCIE_VGA# (6) EV@1000p/50V_4 EV@MC74VHC1G08 EV@100K_4
PEX_REFCLK_N (16) GPU_PEX_RST_HOLD#
PLACE CLOSE TO GPU BALLS
AJ26 PEX_TSTCLK R1063 *EV@200/F_4 *EV@0_4
J8 PEX_TSTCLK_OUT AK26 PEX_TSTCLK# RST_MON# R1470 PEGX_RST#
K8 3V3_AON_1 PEX_TSTCLK_OUT_N
+3V_GFX 3V3_AON_2
+3V_MAIN L8 AJ11
M8 3V3_MAIN_1 NC AJ12 PEGX_RST#
VDD33 : 85mA 3V3_MAIN_2 PEX_RST_N PEGX_RST# (16)

PLACE CLOSE TO BGA


PEX_CLKREQ_N
AK12 PEX_CLKREQ# R1092 EV@10K_4 +3V_GFX
GC6 FBVDDQ_EN
C1344 EV@4.7U/6.3V_4X +1.05V_GFX
C1200 EV@1U/6.3V_4X AP29 PEX_TERMP R1056 EV@2.49K/F_4 (4,16) GC6_FB_EN GC6_FB_EN 1
PEX_TERMP
R1397 EV@0_6
B2A 3
FBVDDQ_EN (39)
PLACE CLOSE TO GPU BALLS AK11 TESTMODE R1462 EV@10K_4
C1201 EV@0.1u/16V_4 TESTMODE 2
(38) GPU_PWR_GD C3A

1
C1302 EV@0.1u/16V_4 AG26 PEX_PLLVDD PEX_PLLVDD : 150mA C1575 EV@4.7U/6.3V_4X PLACE NEAR GPU D1015
PEX_PLLVDD GC6@BAT54CW_200MA R1444
AH12 PEX_SVDD_3V3 : 210mA +3V_GFX C1574 EV@1U/6.3V_4X PLACE NEAR GPU EV@100K_4
PEX_PLL_HVDD AG12 EV@0.1u/16V_4 C1339

2
PEX_SVDD_3V3 EV@4.7U/6.3V_4X C1203 C1076 EV@0.1u/16V_4 PLACE UNDER GPU BALLS
EV@4.7U/6.3V_4X C1303
D
P8 3.3V_AUX D
3.3V_AUX_NC PLACE NEAR BGA
TP1016
L4 +3V_MAIN
VDD_SENSE VGA_VCCSENSE (38)
2

L5
GND_SENSE VGA_VSSSENSE (38)
PEX_CLKREQ# 1 3
Quanta Computer Inc.
CLK_PEGA_REQ# (6)
PROJECT : Z8V
Q1011 Size Document Number Rev
EV@2N7002KW_115MA 1A
N16S-GT - 1/5 (PCIE)
Date: Monday, February 22, 2016 Sheet 13 of 46
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

14
U1030B U1030C
N15P-GT N15P-GT
D13 G9
E14 FBB_CMD0 FBC_D00 E9
FBA_CMD0 U30 L28 VMA_DQ0 F14 FBB_CMD1 FBC_D01 G8
(18) FBA_CMD0
FBA_CMD1 T31 FBA_CMD0
[MEMORY I/F A]
FBA_D00 M29 VMA_DQ1 VMA_DQ0 (18) A12 FBC_CMD2 MEMORY I/F C FBC_D02 F9
(18) FBA_CMD1 U29 FBA_CMD1 FBA_D01 L29 VMA_DQ1 (18) B12 FBB_CMD3 FBC_D03 F11
FBA_CMD2 VMA_DQ2
(18) FBA_CMD2 R34 FBA_CMD2 FBA_D02 M28 VMA_DQ2 (18) C14 FBB_CMD4 FBC_D04 G11
FBA_CMD3 VMA_DQ3
(18) FBA_CMD3 R33 FBA_CMD3 FBA_D03 N31 VMA_DQ3 (18) B14 FBB_CMD5 FBC_D05 F12
FBA_CMD4 VMA_DQ4
(18) FBA_CMD4 U32 FBA_CMD4 FBA_D04 P29 VMA_DQ4 (18) G15 FBB_CMD6 FBC_D06 G12
FBA_CMD5 VMA_DQ5
(18) FBA_CMD5 U33 FBA_CMD5 FBA_D05 R29 VMA_DQ5 (18) F15 FBC_CMD7 FBC_D07 G6
FBA_CMD6 VMA_DQ6
(18) FBA_CMD6 U28 FBA_CMD6 FBA_D06 P28 VMA_DQ6 (18) E15 FBB_CMD8 FBC_D08 F5
FBA_CMD7 VMA_DQ7
(18) FBA_CMD7 V28 FBA_CMD7 FBA_D07 J28 VMA_DQ7 (18) D15 FBB_CMD9 FBC_D09 E6
FBA_CMD8 VMA_DQ8
(18) FBA_CMD8 V29 FBA_CMD8 FBA_D08 H29 VMA_DQ8 (18) A14 FBB_CMD10 FBC_D10 F6
FBA_CMD9 VMA_DQ9
A (18) FBA_CMD9 V30 FBA_CMD9 FBA_D09 J29 VMA_DQ9 (18) D14 FBB_CMD11 FBC_D11 F4
A
FBA_CMD10 VMA_DQ10
(18) FBA_CMD10 U34 FBA_CMD10 FBA_D10 H28 VMA_DQ10 (18) A15 FBB_CMD12 FBC_D12 G4
FBA_CMD11 VMA_DQ11
(18) FBA_CMD11 U31 FBA_CMD11 FBA_D11 G29 VMA_DQ11 (18) B15 FBB_CMD13 FBC_D13 E2
FBA_CMD12 VMA_DQ12
(18) FBA_CMD12 V34 FBA_CMD12 FBA_D12 E31 VMA_DQ12 (18) C17 FBB_CMD14 FBC_D14 F3
FBA_CMD13 VMA_DQ13
(18) FBA_CMD13 V33 FBA_CMD13 FBA_D13 E32 VMA_DQ13 (18) D18 FBB_CMD15 FBC_D15 C2
FBA_CMD14 VMA_DQ14
(18) FBA_CMD14 Y32 FBA_CMD14 FBA_D14 F30 VMA_DQ14 (18) E18 FBB_CMD16 FBC_D16 D4
FBA_CMD15 VMA_DQ15
(18) FBA_CMD15 AA31 FBA_CMD15 FBA_D15 C34 VMA_DQ15 (18) F18 FBB_CMD17 FBC_D17 D3
FBA_CMD16 VMA_DQ16
(18) FBA_CMD16 AA29 FBA_CMD16 FBA_D16 D32 VMA_DQ16 (18) A20 FBB_CMD18 FBC_D18 C1
FBA_CMD17 VMA_DQ17
(18) FBA_CMD17 AA28 FBA_CMD17 FBA_D17 B33 VMA_DQ17 (18) B20 FBB_CMD19 FBC_D19 B3
FBA_CMD18 VMA_DQ18
(18) FBA_CMD18 AC34 FBA_CMD18 FBA_D18 C33 VMA_DQ18 (18) C18 FBB_CMD20 FBC_D20 C4
FBA_CMD19 VMA_DQ19
(18) FBA_CMD19 AC33 FBA_CMD19 FBA_D19 F33 VMA_DQ19 (18) B18 FBB_CMD21 FBC_D21 B5
FBA_CMD20 VMA_DQ20
(18) FBA_CMD20 AA32 FBA_CMD20 FBA_D20 F32 VMA_DQ20 (18) G18 FBB_CMD22 FBC_D22 C5
FBA_CMD21 VMA_DQ21
(18) FBA_CMD21 AA33 FBA_CMD21 FBA_D21 H33 VMA_DQ21 (18) G17 FBB_CMD23 FBC_D23 A11
FBA_CMD22 VMA_DQ22
(18) FBA_CMD22 Y28 FBA_CMD22 FBA_D22 H32 VMA_DQ22 (18) F17 FBB_CMD24 FBC_D24 C11
FBA_CMD23 VMA_DQ23
(18) FBA_CMD23 Y29 FBA_CMD23 FBA_D23 P34 VMA_DQ23 (18) D16 FBB_CMD25 FBC_D25 D11
FBA_CMD24 VMA_DQ24
(18) FBA_CMD24 W 31 FBA_CMD24 FBA_D24 P32 VMA_DQ24 (18) A18 FBB_CMD26 FBC_D26 B11
FBA_CMD25 VMA_DQ25
(18) FBA_CMD25 Y30 FBA_CMD25 FBA_D25 P31 VMA_DQ25 (18) D17 FBB_CMD27 FBC_D27 D8
FBA_CMD26 VMA_DQ26
(18) FBA_CMD26 AA34 FBA_CMD26 FBA_D26 P33 VMA_DQ26 (18) A17 FBB_CMD28 FBC_D28 A8
FBA_CMD27 VMA_DQ27
(18) FBA_CMD27 Y31 FBA_CMD27 FBA_D27 L31 VMA_DQ27 (18) B17 FBB_CMD29 FBC_D29 C8
FBA_CMD28 VMA_DQ28
(18) FBA_CMD28 Y34 FBA_CMD28 FBA_D28 L34 VMA_DQ28 (18) E17 FBC_CMD30 FBC_D30 B8
FBA_CMD29 VMA_DQ29
(18) FBA_CMD29 Y33 FBA_CMD29 FBA_D29 L32 VMA_DQ29 (18) FBC_CMD31 FBC_D31 F24
FBA_CMD30 VMA_DQ30
(18) FBA_CMD30 V31 FBA_CMD30 FBA_D30 L33 VMA_DQ30 (18) FBC_D32 G23
FBA_CMD31 VMA_DQ31
(18) FBA_CMD31 FBA_CMD31 FBA_D31 AG28 VMA_DQ31 (18) E11 FBC_D33 E24
VMA_DQ32
FBA_D32 AF29 VMA_DQ33 VMA_DQ32 (18) E3 FBC_DQM0 FBC_D34 G24
FBA_DBI0 P30 FBA_D33 AG29 VMA_DQ34 VMA_DQ33 (18) A3 FBC_DQM1 FBC_D35 D21
(18) FBA_DBI[7:0] F31 FBA_DQM0 FBA_D34 AF28 VMA_DQ34 (18) C9 FBC_DQM2 FBC_D36 E21
FBA_DBI1 VMA_DQ35
FBA_DBI2 F34 FBA_DQM1 FBA_D35 AD30 VMA_DQ36 VMA_DQ35 (18) F23 FBC_DQM3 FBC_D37 G21
FBA_DBI3 M32 FBA_DQM2 FBA_D36 AD29 VMA_DQ37 VMA_DQ36 (18) F27 FBC_DQM4 FBC_D38 F21
FBA_DBI4 AD31 FBA_DQM3 FBA_D37 AC29 VMA_DQ38 VMA_DQ37 (18) C30 FBC_DQM5 FBC_D39 G27
FBA_DBI5 AL29 FBA_DQM4 FBA_D38 AD28 VMA_DQ39 VMA_DQ38 (18) A24 FBC_DQM6 FBC_D40 D27
FBA_DBI6 AM32 FBA_DQM5 FBA_D39 AJ29 VMA_DQ40 VMA_DQ39 (18) FBC_DQM7 FBC_D41 G26
B FBA_DBI7 AF34 FBA_DQM6 FBA_D40 AK29 VMA_DQ41 VMA_DQ40 (18) FBC_D42 E27 B
FBA_DQM7 FBA_D41 AJ30 VMA_DQ42 VMA_DQ41 (18) D10 FBC_D43 E29
FBA_D42 AK28 VMA_DQ43 VMA_DQ42 (18) D5 FBC_DQS_W P0 FBC_D44 F29
FBA_EDC0 M31 FBA_D43 AM29 VMA_DQ44 VMA_DQ43 (18) C3 FBC_DQS_W P1 FBC_D45 E30
(18) FBA_EDC[7:0] G31 FBA_DQS_W P0 FBA_D44 AM31 VMA_DQ44 (18) B9 FBC_DQS_W P2 FBC_D46 D30
FBA_EDC1 VMA_DQ45
FBA_EDC2 E33 FBA_DQS_W P1 FBA_D45 AN29 VMA_DQ46 VMA_DQ45 (18) E23 FBC_DQS_W P3 FBC_D47 A32
FBA_EDC3 M33 FBA_DQS_W P2 FBA_D46 AM30 VMA_DQ47 VMA_DQ46 (18) E28 FBC_DQS_W P4 FBC_D48 C31
FBA_EDC4 AE31 FBA_DQS_W P3 FBA_D47 AN31 VMA_DQ48 VMA_DQ47 (18) B30 FBC_DQS_W P5 FBC_D49 C32
FBA_EDC5 AK30 FBA_DQS_W P4 FBA_D48 AN32 VMA_DQ49 VMA_DQ48 (18) A23 FBC_DQS_W P6 FBC_D50 B32
FBA_EDC6 AN33 FBA_DQS_W P5 FBA_D49 AP30 VMA_DQ50 VMA_DQ49 (18) FBC_DQS_W P7 FBC_D51 D29
FBA_EDC7 AF33 FBA_DQS_W P6 FBA_D50 AP32 VMA_DQ51 VMA_DQ50 (18) FBC_D52 A29
FBA_DQS_W P7 FBA_D51 AM33 VMA_DQ52 VMA_DQ51 (18) D9 FBC_D53 C29
FBA_D52 AL31 VMA_DQ53 VMA_DQ52 (18) E4 FBC_DQS_RN0 FBC_D54 B29
M30 FBA_D53 AK33 VMA_DQ54 VMA_DQ53 (18) B2 FBC_DQS_RN1 FBC_D55 B21
H30 FBA_DQS_RN0 FBA_D54 AK32 VMA_DQ55 VMA_DQ54 (18) A9 FBC_DQS_RN2 FBC_D56 C23
E34 FBA_DQS_RN1 FBA_D55 AD34 VMA_DQ56 VMA_DQ55 (18) D22 FBC_DQS_RN3 FBC_D57 A21
M34 FBA_DQS_RN2 FBA_D56 AD32 VMA_DQ57 VMA_DQ56 (18) D28 FBC_DQS_RN4 FBC_D58 C21
GDDR5 NO USE AF30 FBA_DQS_RN3
FBA_DQS_RN4
FBA_D57
FBA_D58
AC30 VMA_DQ58 VMA_DQ57
VMA_DQ58
(18)
(18)
A30 FBC_DQS_RN5
FBC_DQS_RN6
FBC_D59
FBC_D60
B24
AK31 AD33 VMA_DQ59 B23 C24
AM34 FBA_DQS_RN5 FBA_D59 AF31 VMA_DQ60 VMA_DQ59 (18) FBC_DQS_RN7 FBC_D61 B26
AF32 FBA_DQS_RN6 FBA_D60 AG34 VMA_DQ61 VMA_DQ60 (18) FBC_D62 C26
FBA_DQS_RN7 FBA_D61 AG32 VMA_DQ62 VMA_DQ61 (18) FBC_D63
FBA_D62 AG33 VMA_DQ63 VMA_DQ62 (18)
AA27 FBA_D63 VMA_DQ63 (18) D12
+1.35V_GFX FBVDDQ_1 FBC_CLK0
AA30 E12
AB27 FBVDDQ_2 R30 FBC_CLK0_N E20
AB33 FBVDDQ_3 FBA_CLK0 R31 VMA_CLK0 (18) FBC_CLK1 F20
AC27 FBVDDQ_4 FBA_CLK0_N AB31 VMA_CLK0# (18) FBC_CLK1_N
AD27 FBVDDQ_5 FBA_CLK1 AC31 VMA_CLK1 (18)
PLACE CLOSE TO GPU BALLS
AE27 FBVDDQ_6 FBA_CLK1_N VMA_CLK1# (18) G14 FBB_DEBUG0_K
AF27 FBVDDQ_7 FBB_CMD32 G20 TP1009
C1065 EV@1U/10V_4X FBB_DEBUG1_K TP1008
C C1061 EV@1U/10V_4X AG27 FBVDDQ_8 R28 FBA_DEBUG0_K FBB_CMD33 C12 FBB_DEBUG0 R1087 *EV@60.4/F_4 C
FBVDDQ_9 FBA_CMD32 TP1003 FBB_CMD34 +1.35V_GFX
C1116 EV@1U/10V_4X B13 AC28 FBA_DEBUG1_K C20 FBB_DEBUG1 R1069 *EV@60.4/F_4
FBVDDQ_10 FBA_CMD33 TP1004 FBB_CMD35
C1107 EV@1U/10V_4X B19 R32 FBA_DEBUG0 *EV@60.4/F_4 R1059
FBVDDQ_12 FBA_CMD34 +1.35V_GFX
E13 AC32 FBA_DEBUG1 *EV@60.4/F_4 R1055
E19 FBVDDQ_13 FBA_CMD35 F8
B2A H10 FBVDDQ_15 H26 FBB_W CK01 E8
C1088 EV@0.1U/16V_4X H11 FBVDDQ_16 FB_VREF FBB_W CK01_N A5
C1193 EV@0.1U/16V_4X H12 FBVDDQ_17 K31 FBB_W CK23 A6
H13 FBVDDQ_18 FBA_W CK01 L30 VMA_WCK01 (18) FBB_W CK23_N D24
C1199 EV@0.1U/16V_4X
H14 FBVDDQ_19 FBA_W CK01_N H34 VMA_WCK01# (18) FBB_W CK45 D25
C1174 EV@0.1U/16V_4X WCK only for GDDR5
H18 FBVDDQ_20 FBA_W CK23 J34 VMA_WCK23 (18) FBB_W CK45_N B27
H19 FBVDDQ_23 FBA_W CK23_N AG30 VMA_WCK23# (18) FBB_W CK67 C27
H20 FBVDDQ_24 FBA_W CK45 AG31 VMA_WCK45 (18) FBB_W CK67_N
H21 FBVDDQ_25 FBA_W CK45_N AJ34 VMA_WCK45# (18)
H22 FBVDDQ_26 FBA_W CK67 AK34 VMA_WCK67 (18) D6
H23 FBVDDQ_27 FBA_W CK67_N VMA_WCK67# (18) NC D7
H24 FBVDDQ_28 J30 NC C6
H8 FBVDDQ_29 NC J31 NC B6
H9 FBVDDQ_30 NC J32 NC F26
L27 FBVDDQ_31 NC J33 R1512 EV@10K_4 NC E26
M27 FBVDDQ_32 NC AH31 NC A26
N27 FBVDDQ_33 NC AJ31 NC A27
PLACE CLOSE TO BGA P27 FBVDDQ_34 NC AJ32 +1.05V_GFX NC
R27 FBVDDQ_35 NC AJ33
FBVDDQ_36 NC C262 close to H27 (under GPU)
C1164 EV@4.7U/6.3V_4X T27 FB_PLLAVDD EV@HCB1005KF-330T30 L1001 H17 FB_PLLAVDD
C1137 EV@4.7U/6.3V_4X T30 FBVDDQ_37 E1 PS_FB_CLAMP FBB_PLL_AVDD
FBVDDQ_38 FB_CLAMP +FB_PLLAVDD : 62mA
C1178 EV@4.7U/6.3V_4X T33 B2A
Y27 FBVDDQ_39 K27
C1215 EV@4.7U/6.3V_4X
FBVDDQ_44 FB_DLL_AVDD
C1078 EV@0.1U/16V_4X C574 close to K27 (under GPU) B2A
C1028 EV@10U/6.3V_6X C1157
C1084 EV@10U/6.3V_6X U27 +1.35V_GFX C1085 EV@0.1U/16V_4X C575 close to U27 (under GPU) EV@0.1U/16V_4X
FBA_PLL_AVDD
B16 F1 FBVDDQ_SENSE
C576 near to GPU
D R1502 *EV@0_4 D
C1051 EV@22U/6.3V_6X E16 FBVDDQ_AON_1 FB_VDDQ_SENSE C1086 EV@22U/6.3V_6X
H15 FBVDDQ_AON_2 F2 FB_GND_SENSE R1501 *EV@0_4
B2A H16 FBVDDQ_AON_3 FB_GND_SENSE
C1075 EV@22U/6.3V_6X V27 FBVDDQ_AON_4 J27 FB_CAL_PD_VDDQ R1058 EV@40.2/F_4
FBVDDQ_AON_5 FB_CAL_PD_VDDQ +1.35V_GFX
W 27
W 30 FBVDDQ_AON_6 H27 FB_CAL_PU_GND R1057 EV@40.2/F_4
W 33 FBVDDQ_AON_7 FB_CAL_PU_GND
FBVDDQ_AON_8
FB_CALTERM_GND
H25 FB_CAL_TERM_GND R1064 EV@60.4/F_4 Quanta Computer Inc.
PLACE CLOSE TO GPU BALLS
PROJECT : Z8V
Size Document Number Rev
1A
N16S-GT - 2/5 (Memory)
Date: Monday, February 22, 2016 Sheet 14 of 45
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

AH8
U1030D
N15P-GT
IFPAB_PLLVDD
[IFPA/B_LVDS]
IFPA_TXC
IFPA_TXC_N
AM6
AN6
AP3
15
AG8 IFPA_TXD0 AN3
IFPA_IOVDD IFPA_TXD0_N AN5
AG9 IFPA_TXD1 AM5
IFPB_IOVDD IFPA_TXD1_N
IFPA_TXD2
AL6
AK6
3V_MAIN_PWGD +3V_GFX
IFPA_TXD2_N AJ6
A A
AJ8 IFPA_TXD3 AH6
IFPAB_RSET IFPA_TXD3_N
AJ9 +3V
IFPB_TXC AH9 R1184
IFPB_TXC_N AP6 EV@1.5K/F_4
IFPB_TXD4 AP5
IFPB_TXD4_N AM7 R1192 3V_MAIN_PW GD
IFPB_TXD5 3V_MAIN_PW GD (38,39)
AL7 EV@4.7K_4
IFPB_TXD5_N

3
AN8
IFPB_TXD6 AM8 R1182
IFPB_TXD6_N AK8 2
IFPB_TXD7 *100K/F_4

3
AL8
IFPB_TXD7_N R1121 EV@4.7K_4 2
+3V_MAIN
C1347 Q1026

1
AF7 AG3 Q1019 EV@1000p/50V_4 EV@DTC144EU

1
IFPC_PLLVDD IFPC_AUX_I2CW_SCL AG2 C1245 EV@MMBT3904-7-F
AG7
[IFPC/D_TMDS]IFPC_AUX_I2CW_SDA_N AK1 *1000p/50V_4
IFPD_PLLVDD IFPC_L0 +1.05V_GFX and GPU core power EN
AJ1
IFPC_L0_N AJ3
IFPC_L1 AJ2
IFPC_L1_N AH3
IFPC_L2 AH4
IFPC_L2_N AG5
AF6 IFPC_L3 AG4
IFPC_IOVDD IFPC_L3_N
AG6 AK3
IFPD_IOVDD IFPD_AUX_I2CX_SCL AK2
IFPD_AUX_I2CX_SDA_N 2/16 Reserve R1539 for DGPU_PWROK doesn't have any sequence requirement
AM1
B IFPD_L0 AM2 R1539 *0_4 B
IFPD_L0_N AM3
AF8 IFPD_L1 AM4
IFPC_RSET IFPD_L1_N AL3
AN2 IFPD_L2 AL4
NC IFPD_L2_N AK4 +3V_GFX
IFPD_L3 AK5
IFPD_L3_N
DGPU_PGOK-1
AB8 AB3 +3V R1105
IFPEF_PLLVDD IFPE_AUX_I2CY_SCL AB4 EV@4.7K_4
[IFPE/F_DP] IFPE_AUX_I2CY_SDA_N AD2
AC7 IFPE_L0 AD3
AC8 IFPE_IOVDD IFPE_L0_N AD1 R1088
IFPF_IOVDD IFPE_L1 DGPU_PW ROK (4)
AC1 EV@4.7K_4
IFPE_L1_N AC2
IFPE_L2

3
AD6 AC3
IFPEF_RSET IFPE_L2_N AC4
IFPE_L3 AC5 2 Q1012 R1098
IFPE_L3_N

3
EV@100K/F_4
AF3 R1082 DGPU_POK2 2
EV@4.7K_4 Q1010 EV@DTC144EUA
IFPF_AUX_I2CZ_SCL (39) HW PG_1.35VGFX
AF2 EV@METR3904-G

1
IFPF_AUX_I2CZ_SDA_N AE3 C1181

1
IFPF_L0 AE4 C1187 EV@1000P/50V_4
IFPF_L0_N AF4 *1000P/50V_4
IFPF_L1 AF5
IFPF_L1_N AD4
IFPF_L2 AD5
IFPF_L2_N AG1
C IFPF_L3 AF1 C
IFPF_L3_N

AG10 AK9
DACA_VDD DACA_RED AL10
[DACA/B_CRT] DACA_GREEN AL9
AP9 DACA_BLUE
DACA_VREF
AM9 BG627000039 -> HHE(1st)
AP8 DACA_HSYNC AN9
DACA_RSET DACA_VSYNC XTAL27_IN BG627000035 -> TXC(2nd)
XTAL27_OUT
Y1004
R4 I2CA_SCL EV@1.8K/F_4 R1499
I2CA_SCL R5 I2CA_SDA EV@1.8K/F_4 R1129 3 2
I2CA_SDA 4 1
PLACE CLOSE TO GPU PLACE CLOSE TO BALLS
PLLVDD : 200mA EV@27MHZ_10
+1.05V_GFX L1006 EV@HCB1005KF-330T30 NV_PLLVDD AD8
PLLVDD
B2A Reserve C1637 C1638
C1253 C1213 EV@10P/50V_4C EV@10P/50V_4C
EV@22U/6.3V_6X EV@0.1U/16V_4X +3V_GFX
B2A
XTAL_OUTBUFF R1146 *EV@10K_4
PLLVDD AE8
SP_PLLVDD
C5092 Close to AE8
D D
C5090 Close to AD7AD7 H3 XTAL27_IN
L1005 EV@HCB1005KF_1.5A XTAL_IN H2 XTAL27_OUT
+1.05V_GFX VID_PLLVDD XTAL_OUT
[XTAL IN] J4 XTAL_OUTBUFF R1147 EV@10K_4
XTAL_OUTBUFF H1
B2A XTAL_SSIN
XTAL_SSIN R1523 EV@10K_4
C1242 C1204 C1214 C1231
EV@22U/6.3V_6XEV@4.7U/6.3V_4X EV@0.1U/16V_4X EV@0.1U/16V_4X
Quanta Computer Inc.
PROJECT : Z8V
Size Document Number Rev
1A
N16S-GT - 3/5 (Display)
Date: Monday, February 22, 2016 Sheet 15 of 45
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

Resistor P/N

16
+3V_GFX +3V_MAIN
4.99K---> CS24992FB26
STRAP0
10K ---> CS31002FB26 DG : STUFF 50KΩ PU TO 3.3V_AON
15K ---> CS31502FB24

2
20K ---> CS32002FB29 R1515 R1103 R1111 R1132 R1525
24.9K --->CS32492FB16 EV@49.9K/F_4 *EV@45.3K/F_4 *EV@15K/F_4 *EV@34.8K/F_4 *EV@20K/F_4 R1497
*EV@4.99K
R1096
GT1@4.99K/F_4
R1139
*10K/F_4
Package DevID
30.1K --->CS33012FB18 U1030E

1
34.8K---> CS33482FB22 N15P-GT STRAP0
STRAP1 ROM_SI
N16S-GT1-KB GB4b-128 0x179C
45.3K ---> CS34532FB18 GM [MIOA] STRAP2 ROM_SO
STRAP3 ROM_SCLK
49.9K ---> CS34992FB10 GT STRAP4
N16S-GTR GB4b-128 0x134D
A A

R1513 R1095 R1138


R1496 R1102 R1109 R1131 R1519 EV@45.3k GTR@4.99K/F_4 4.99K/F_4
+3V_GFX *EV@4.99K/F_4 *EV@4.99K/F_4 *EV@24.9K/F_4 *EV@4.99K/F_4 *EV@45.3K/F_4

R1494 EV@10K_4 GPU_OVT#


R1500 EV@10K_4 GPU_ALERT

R1188 EV@10K_4 GPU_EVENT#_D

R1518 EV@10K_4 GPIO12_ACIN PU +3V_MAIN


Mutil-level mode strapping:
PD For N16S-GT1-KB-A2 :
R1152 EV@10K_4 +3V_MAIN_EN
R490=40.2k PD
R1492 EV@10K_4 SYS_PEX_RST_MON# 4.99K 1000 0000 1.ROM_SCLK =4.99K PD
10K 1001 0001 2.ROM_SO = 4.99K PU (N16S-GTR = 4.99KPD)
R1171 EV@10K_4 GPU_PEX_RST_HOLD#
3.ROM_SI= Memory strap setting
R1521 *EV@10K_4 GPIO10_VREF 15K 1010 0010 4.STRAP0 = 49.9k PU
5.Strap4~1 = Reserve Pull up and Pull down
R1149 EV@10K_4 DGPU_PSI 20K 1011 0011
24.9K 1100 0100 N16S-GT1-KB-A2 N16S-GTR

R1507 EV@10K_4 GPIO10_VREF


[MIOB] 30.1K 1101 0101
+3V_GFX ROM_SO R93 PU 4.99K R92 PD 4.99K
R1196 EV@10K_4 GC6_FB_EN_R 34.8K 1110 0110
Q1025A
45.3K 1111 0111 ROM_SI As below configuration table

2
*EV@ME2N7002DKW-G_115MA
N16S-GT1-KB-A2 VRAM Configuration Table:
GC6_FB_EN_R 1 6
GC6_FB_EN (4,13)

Reserve PU/PD for Debug ROM_SI DESCRIPTION Vendor Vendor P/N STN P/N ROM_SI
B R1191 EV@0_4 B
4GbX2 0011 (0x3) GDDR5 128MBx32,2500MHz SAMSUNG K4G41325FC-HC03 --C die AKG5PGDT505 20K Pull down
+3V_MAIN (1GB) 0110 (0x6) GDDR5 128MBx32,2500MHz HYNIX 34.8K Pull down
H5GC4H24AJR-T2C --A die AKG5PWUTW21
+3V_GFX
R1451 *EV@10K_4 JTAG_TMS 4GbX4 0011 (0x3) GDDR5 256MBx16,2500MHz SAMSUNG K4G41325FC-HC03 --C die AKG5PGDT505 20K Pull down
R1443 *EV@10K_4 JTAG_TDI Q1025B (2GB) 0110 (0x6) GDDR5 256MBx16,2500MHz HYNIX H5GC4H24AJR-T2C --A die AKG5PWUTW21 34.8K Pull down

5
R1466 *EV@10K_4 JTAG_TCK *EV@ME2N7002DKW-G_115MA 8GbX2 0000 (0x8) GDDR5 256MBx32,2500MHz SAMSUNG K4G80325FB-HC03 --B die AKG5QGDT502 4.99K Pull up
R1458 EV@10K_4 JTAG_TRST# (2GB) 0001 (0x9) GDDR5 256MBx32,2500MHz MICRON MT51J256M32HF-60:A--A die AKG5LGUTL04 10K Pull up
GPU_EVENT#_D 4 3
DGPU_EVENT# (4)

8GbX4 0000 (0x8) GDDR5 512MBx16,2500MHz SAMSUNG K4G80325FB-HC03 --B die AKG5QGDT502 4.99K Pull up
R1193 EV@0_4 (4GB) 0001 (0x9) GDDR5 512MBx16,2500MHz MICRON MT51J256M32HF-60:A--A die AKG5LGUTL04 10K Pull up
B2A
TP1087 JTAG_TCK AM10 P6 GC6_FB_EN_R
TP1085 JTAG_TMS AP11 JTAG_TCK GPIO0 M3 TP1093
TP1084 JTAG_TDI AM11 JTAG_TMS [MISC_GPIO/I2C/JTAG/THER] GPIO1 L6 TP1022
TP1082 JTAG_TDO AP12 JTAG_TDI GPIO2 P5 TP1020
TP1086 JTAG_TRST# AN11 JTAG_TDO GPIO3 P7 TP1013
JTAG_TRST_N GPIO4 L7 +3V_MAIN_EN
GPIO5 +3V_MAIN_EN (13) N16S-GTR VRAM Configuration Table:
M7 GPU_EVENT#_D
R1517 EV@1.8K/F_4 I2CB_SCL R7 GPIO6 N8 TP1018
R1116 EV@1.8K/F_4 I2CB_SDA R6 I2CB_SCL GPIO7
I2CB_SDA ROM_SI DESCRIPTION Vendor Vendor P/N STN P/N ROM_SI
L3 SYS_PEX_RST_MON#
GPIO8 SYS_PEX_RST_MON# (13)
4GbX2 0011 (0x3) GDDR5 128MBx32,2500MHz SAMSUNG K4G41325FC-HC03 --C die AKG5PGDT505 20K Pull down
R1516 EV@1.8K/F_4 I2CC_SCL R2 (1GB) 0110 (0x6) GDDR5 128MBx32,2500MHz HYNIX H5GC4H24AJR-T2C --A die AKG5PWUTW21 34.8K Pull down
R1498 EV@1.8K/F_4 I2CC_SDA R3 I2CC_SCL M2 GPU_ALERT
I2CC_SDA GPIO9 L1 GPIO10_VREF
GPIO10 GPIO10_VREF (18)
M5 4GbX4 0011 (0x3) GDDR5 256MBx16,2500MHz SAMSUNG K4G41325FC-HC03 --C die AKG5PGDT505 20K Pull down
T4 GPIO11 N3 PWM-VID (38)
GFX_SCL GPIO12_ACIN (2GB) 0110 (0x6) GDDR5 256MBx16,2500MHz HYNIX H5GC4H24AJR-T2C --A die AKG5PWUTW21 34.8K Pull down
GFX_SDA T3 I2CS_SCL GPIO12 M4 DGPU_PSI
I2CS_SDA GPIO13 N4 DGPU_PSI (38)
GPIO14 8GbX2 0000 (0x0) GDDR5 256MBx32,2500MHz SAMSUNG K4G80325FB-HC03 --B die AKG5QGDT502 4.99K Pull down
P2 (2GB) 0001 (0x1) GDDR5 256MBx32,2500MHz MICRON MT51J256M32HF-60:A--A die AKG5LGUTL04 10K Pull down
K4 GPIO15 R8
K3 THERMDN GPIO16 M6
THERMDP GPIO17 R1
C GPIO18 8GbX4 0000 (0x0) GDDR5 512MBx16,2500MHz SAMSUNG K4G80325FB-HC03 --B die AKG5QGDT502 4.99K Pull down C
P3 (4GB) 0001 (0x1) GDDR5 512MBx16,2500MHz MICRON MT51J256M32HF-60:A--A die AKG5LGUTL04 10K Pull down
GPIO19 P4
GPIO20 P1 GPU_PEX_RST_HOLD#
GPIO21 GPU_PEX_RST_HOLD# (13)

H4 ROM_SCLK
STRAP0 J2 ROM_SCLK H6
STRAP1 J7 STRAP0 [MISC2_ROM] ROM_CS_N H5 ROM_SI
STRAP2 J6 STRAP1 ROM_SI H7 ROM_SO
STRAP3 J5 STRAP2 ROM_SO
STRAP4 J3 STRAP3
+3V_GFX STRAP4 N16S-GT1-KB-A2 (GB4b-128)
L2 GPU_BUFRST R1495 *EV@10K_4 Logical Logical Logical Logical
R1514 *EV@10K_4 MULTISTRAP_REF_GND J1 BUFRST_N
MULTISTRAP_REF_GND Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED 0000
R1493 M1 GPU_OVT#
EV@40.2K/F_4 OVERT
ROM_SI RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0] XXXX
ROM_SO DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE 0000
STRAP0 Keep footprint to PU to 3V3_AON and PD to GND [Stuff 49.9K PU] 0001
STRAP1
STRAP2
PEGX_RST# (13) Keep footprint to PU to 3V3_AON and PD to GND [Do Not Stuff
+3V_GFX
STRAP3
2

+3V_MAIN
STRAP4
GPU_OVT# 1 6 dGPU_OTP#
dGPU_OTP# (28)
Q1022A R1162 R1179
EV@ME2N7002DKW-G_115MA EV@2.2K_4 EV@2.2K_4 GFx SMBus Isolation
D
5 D

+3V_GFX GFX_SCL 4 3
2ND_MBCLK (7,28)

2
5

GFX_SDA 1 6
R1158 GPIO12_ACIN4 3 2ND_MBDATA (7,28)
(29) GPU_THROTTING# dGPU_OPP# (28)
*EV@0_4 Q1022B Q1021
EV@ME2N7002DKW-G_115MA EV@ME2N7002DKW-G_115MA Quanta Computer Inc.
GPIO12 AC detect
AC high PROJECT : Z8V
DC low B2A Size Document Number Rev
1A
N16S-GT - 4/5 (MISC)
Date: Monday, February 22, 2016 Sheet 16 of 45
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

VDD/XVDD : 43A
+VGPU_CORE
U1030F
N15P-GT
+VGPU_CORE
A2
AA17
AA18
AA20
U1030G
N15P-GT
GND_1
GND_2
GND_3
[GPU GND]
GND_101
GND_102
GND_103
D2
D31
D33
E10
+VGPU_CORE
17
AA12 U1 AA22 GND_4 GND_104 E22 C1158 EV@1U/6.3V_4X
AA14 VDD_001 XVDD_001 U2 AB12 GND_5 GND_105 E25 C1206 EV@1U/6.3V_4X
AA16 VDD_002 [GPU VDD] XVDD_002 U3 AB14 GND_6 GND_106 E5 C1114 EV@1U/6.3V_4X
AA19 VDD_003 XVDD_003 U4 AB16 GND_7 GND_107 E7 C1094 EV@1U/6.3V_4X
PLACE UNDER GPU
AA21 VDD_004 XVDD_004 U5 AB19 GND_8 GND_108 F28 C1091 EV@1U/6.3V_4X
AA23 VDD_005 XVDD_005 U6 AB2 GND_9 GND_109 F7 C1089 EV@1U/6.3V_4X
A A
AB13 VDD_006 XVDD_006 U7 AB21 GND_10 GND_110 G10 C1092 EV@1U/6.3V_4X
AB15 VDD_007 XVDD_007 U8 A33 GND_11 GND_111 G13 C1160 EV@1U/6.3V_4X
AB17 VDD_008 XVDD_008 V1 AB23 GND_12 GND_112 G16
AB18 VDD_009 XVDD_009 V2 AB28 GND_13 GND_113 G19 C1168 EV@4.7U/6.3V_6X
AB20 VDD_010 XVDD_010 V3 AB30 GND_14 GND_114 G2 C1197 EV@4.7U/6.3V_6X
AB22 VDD_011 XVDD_011 V4 AB32 GND_15 GND_115 G22 C1172 EV@4.7U/6.3V_6X
AC12 VDD_012 XVDD_012 V5 AB5 GND_16 GND_116 G25 C1098 EV@4.7U/6.3V_6X
AC14 VDD_013 XVDD_013 V6 AB7 GND_17 GND_117 G28 C1166 EV@4.7U/6.3V_6X
AC16 VDD_014 XVDD_014 V7 AC13 GND_18 GND_118 G3
AC19 VDD_015 XVDD_015 V8 AC15 GND_19 GND_119 G30
AC21 VDD_016 XVDD_016 W2 AC17 GND_20 GND_120 G32 C1196 *EV@4.7U/6.3V_6X
AC23 VDD_017 XVDD_017 W3 AC18 GND_21 GND_121 G33
B2A
M12 VDD_018 XVDD_018 W4 AA13 GND_22 GND_122 G5
M14 VDD_019 XVDD_019 W5 AC20 GND_23 GND_123 G7 C1112 EV@4.7U/6.3V_6X
M16 VDD_020 XVDD_020 W7 AC22 GND_24 GND_124 K2 C1267 EV@4.7U/6.3V_6X
M19 VDD_021 XVDD_021 W8 AE2 GND_25 GND_125 K28 C1099 EV@4.7U/6.3V_6X
M21 VDD_022 XVDD_022 Y4 AE28 GND_26 GND_126 K30
M23 VDD_023 XVDD_026 Y5 AE30 GND_27 GND_127 K32
N13 VDD_024 XVDD_027 Y6 AE32 GND_28 GND_128 K33 C1180 *EV@4.7U/6.3V_6X
N15 VDD_025 XVDD_028 Y7 AE33 GND_29 GND_129 K5
B2A
N17 VDD_026 XVDD_029 Y8 AE5 GND_30 GND_130 K7
N18 VDD_027 XVDD_030 AE7 GND_31 GND_131 M13 C1142 EV@4.7U/6.3V_6X
N20 VDD_028 AH10 GND_32 GND_132 M15
N22 VDD_029 AA15 GND_33 GND_133 M17
P12 VDD_030 AH13 GND_34 GND_134 M18 C1170 *EV@4.7U/6.3V_6X
P14 VDD_031 AH16 GND_35 GND_135 M20 C1205 *EV@4.7U/6.3V_6X
B2A
P16 VDD_032 AH19 GND_36 GND_136 M22
P19 VDD_033 AH2 GND_37 GND_137 N12
B P21 VDD_034 AH22 GND_38 GND_138 N14 C1133 EV@4.7U/6.3V_6X B
P23 VDD_035 AH24 GND_39 GND_139 N16 C1122 EV@4.7U/6.3V_6X
R13 VDD_036 AH28 GND_40 GND_140 N19
R15 VDD_037 AH29 GND_41 GND_141 N2
R17 VDD_038 AH30 GND_42 GND_142 N21
R18 VDD_039 AH32 GND_43 GND_143 N23
R20 VDD_040 AH33 GND_44 GND_144 N28
PLACE NEAR GPU
R22 VDD_041 AH5 GND_45 GND_145 N30
T12 VDD_042 AH7 GND_46 GND_146 N32 C11312 1 EV@22U/6.3V_6X
T14 VDD_043 AJ7 GND_47 GND_147 N33 C11112 1 EV@22U/6.3V_6X
T16 VDD_044 AK10 GND_48 GND_148 N5 C11902 1 EV@22U/6.3V_6X
T19 VDD_045 AK7 GND_49 GND_149 N7 C11712 1 EV@22U/6.3V_6X
T21 VDD_046 AL12 GND_50 GND_150 P13 C11552 1 EV@22U/6.3V_6X
T23 VDD_047 AL14 GND_51 GND_151 P15 C11732 1 EV@22U/6.3V_6X
U13 VDD_048 AL15 GND_52 GND_152 P17
B2A
U15 VDD_049 AL17 GND_53 GND_153 P18
U17 VDD_050 AL18 GND_54 GND_154 P20 C1177 2 1 EV@22U/6.3V_6X
U18 VDD_051 AL2 GND_55 GND_155 P22 C1189 EV@4.7U/10V_6X
U20 VDD_052 AL20 GND_56 GND_156 R12 C1184 EV@4.7U/10V_6X
U22 VDD_053 AL21 GND_57 GND_157 R14
V13 VDD_054 AL23 GND_58 GND_158 R16
V15 VDD_055 AL24 GND_59 GND_159 R19 C1639 *EV@4.7U/10V_6X
V17 VDD_056 AL26 GND_60 GND_160 R21
B2A
V18 VDD_057 AL28 GND_61 GND_161 R23
V20 VDD_058 AL30 GND_62 GND_162 T13
V22 VDD_059 AL32 GND_63 GND_163 T15 C1277 EV@4.7U/10V_6X
W12 VDD_060 AL33 GND_64 GND_164 T17
W14 VDD_061 AL5 GND_65 GND_165 T18 C1185 EV@4.7U/10V_6X
W16 VDD_062 AM13 GND_66 GND_166 T2
C W19 VDD_063 AM16 GND_67 GND_167 T20 C1641 330u/2V_7343 C
W21 VDD_064 AM19 GND_68 GND_168 T22

+
W23 VDD_065 AM22 GND_69 GND_169 AG11
Y13 VDD_066 AM25 GND_70 GND_170 T28
Y15 VDD_067 AN1 GND_71 GND_171 T32
Y18 VDD_068 AN10 GND_72 GND_172 T5
Y17 VDD_069 AN13 GND_73 GND_173 T7
Y20 VDD_070 AN16 GND_74 GND_174 U12
Y22 VDD_071 AN19 GND_75 GND_175 U14
VDD_072 AN22 GND_76 GND_176 U16
AN25 GND_77 GND_177 U19
AN30 GND_78 GND_178 U21
AN34 GND_79 GND_179 U23
AN4 GND_80 GND_180 V12
AN7 GND_81 GND_181 V14
AP2 GND_82 GND_182 V16
AP33 GND_83 GND_183 V19
B1 GND_84 GND_184 V21
B10 GND_85 GND_185 V23
B22 GND_86 GND_186 W13
B25 GND_87 GND_187 W15
B28 GND_88 GND_188 W17
B31 GND_89 GND_189 W18
B34 GND_90 GND_190 W20
B4 GND_91 GND_191 W22
B7 GND_92 GND_192 W28
C10 GND_93 GND_193 Y12
C13 GND_94 GND_194 Y14
C19 GND_95 GND_195 Y16
D GND_96 GND_196 D
C22 Y19
C25 GND_97 GND_197 Y21
C28 GND_98 GND_198 Y23
C7 GND_99 GND_199 AH11
GND_100 GND_200
C16
GND_OPT_1
W32
Quanta Computer Inc.
GND_OPT_2
PROJECT : Z8V
Size Document Number Rev
1A
N16S-GT - 5/5 (Power)
Date: Monday, February 22, 2016 Sheet 17 of 45
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

VMA_DQ[63..0]
(14) VMA_DQ[63..0]

CHANNEL A: 1G/2G GDDR5x32


18
FBA_DBI[7..0]
(14) FBA_DBI[7..0]
FBA_EDC[7..0]
(14) FBA_EDC[7..0]

Channel 0 Channel 0
<0-31> LOWER HALF <32-63>
MF=0 Non-mirrored +1.35V_GFX MF=1 mirrored +1.35V_GFX

U1022 U1021
VMA_DQ31 M2 B1 VMA_DQ39 M2 B1
VMA_DQ30 M4 DQ31 | DQ7 VDDQ-B1 B3 VMA_DQ38 M4 DQ31 | DQ7 VDDQ-B1 B3
VMA_DQ29 N2 DQ30 | DQ6 VDDQ-B3 B12 VMA_DQ37 N2 DQ30 | DQ6 VDDQ-B3 B12
VMA_DQ28 N4 DQ29 | DQ5 VDDQ-B12 B14 VMA_DQ36 N4 DQ29 | DQ5 VDDQ-B12 B14
A
QD24~31 VMA_DQ27
VMA_DQ26
VMA_DQ25
T2
T4
U2
DQ28 | DQ4
DQ27 | DQ3
DQ26 | DQ2
DQ25 | DQ1
VDDQ-B14
VDDQ-D1
VDDQ-D3
VDDQ-D12
D1
D3
D12
QD32~39 VMA_DQ35
VMA_DQ34
VMA_DQ33
T2
T4
U2
DQ28 | DQ4
DQ27 | DQ3
DQ26 | DQ2
DQ25 | DQ1
VDDQ-B14
VDDQ-D1
VDDQ-D3
VDDQ-D12
D1
D3
D12
A

VMA_DQ24 U4 D14 VMA_DQ32 U4 D14


VMA_DQ23 M13 DQ24 | DQ0 VDDQ-D14 E5 VMA_DQ47 M13 DQ24 | DQ0 VDDQ-D14 E5
VMA_DQ22 M11 DQ23 | DQ15 VDDQ-E5 E10 VMA_DQ46 M11 DQ23 | DQ15 VDDQ-E5 E10
VMA_DQ21 N13 DQ22 | DQ14 VDDQ-E10 F1 VMA_DQ45 N13 DQ22 | DQ14 VDDQ-E10 F1

QD16~23 VMA_DQ20
VMA_DQ19
VMA_DQ18
N11
T13
T11
DQ21 | DQ13
DQ20 | DQ12
DQ19 | DQ11
DQ18 | DQ10
VDDQ-F1
VDDQ-F3
VDDQ-F12
VDDQ-F14
F3
F12
F14
QD40~47 VMA_DQ44
VMA_DQ43
VMA_DQ42
N11
T13
T11
DQ21 | DQ13
DQ20 | DQ12
DQ19 | DQ11
DQ18 | DQ10
VDDQ-F1
VDDQ-F3
VDDQ-F12
VDDQ-F14
F3
F12
F14
VMA_DQ17 U13 G2 VMA_DQ41 U13 G2
VMA_DQ16 U11 DQ17 | DQ9 VDDQ-G2 G13 VMA_DQ40 U11 DQ17 | DQ9 VDDQ-G2 G13
VMA_DQ15 F13 DQ16 | DQ8 VDDQ-G13 H3 VMA_DQ55 F13 DQ16 | DQ8 VDDQ-G13 H3
VMA_DQ14 F11 DQ15 | DQ23 VDDQ-H3 H12 VMA_DQ54 F11 DQ15 | DQ23 VDDQ-H3 H12
VMA_DQ13 E13 DQ14 | DQ22 VDDQ-H12 K3 VMA_DQ53 E13 DQ14 | DQ22 VDDQ-H12 K3
VMA_DQ12 E11 DQ13 | DQ21 VDDQ-K3 K12 VMA_DQ52 E11 DQ13 | DQ21 VDDQ-K3 K12

QD8~15 VMA_DQ11
VMA_DQ10
VMA_DQ9
B13
B11
A13
DQ12 | DQ20
DQ11 | DQ19
DQ10 | DQ18
DQ9 | DQ17
VDDQ-K12
VDDQ-L2
VDDQ-L13
VDDQ-M1
L2
L13
M1
QD48~55 VMA_DQ51
VMA_DQ50
VMA_DQ49
B13
B11
A13
DQ12 | DQ20
DQ11 | DQ19
DQ10 | DQ18
DQ9 | DQ17
VDDQ-K12
VDDQ-L2
VDDQ-L13
VDDQ-M1
L2
L13
M1
VMA_DQ8 A11 M3 VMA_DQ48 A11 M3
VMA_DQ7 F2 DQ8 | DQ16 VDDQ-M3 M12 VMA_DQ63 F2 DQ8 | DQ16 VDDQ-M3 M12
VMA_DQ6 F4 DQ7 | DQ31 VDDQ-M12 M14 VMA_DQ62 F4 DQ7 | DQ31 VDDQ-M12 M14
VMA_DQ5 E2 DQ6 | DQ30 VDDQ-M14 N5 VMA_DQ61 E2 DQ6 | DQ30 VDDQ-M14 N5

QD0~7 VMA_DQ4
VMA_DQ3
E4
B2
DQ5 | DQ29
DQ4 | DQ28
VDDQ-N5
VDDQ-N10
N10
P1
VMA_DQ60
VMA_DQ59
E4
B2
DQ5 | DQ29
DQ4 | DQ28
VDDQ-N5
VDDQ-N10
N10
P1
VMA_DQ2
VMA_DQ1
VMA_DQ0
B4
A2
A4
DQ3 | DQ27
DQ2 | DQ26
DQ1 | DQ25
DQ0 | DQ24
VDDQ-P1
VDDQ-P3
VDDQ-P12
VDDQ-P14
P3
P12
P14
QD56~63 VMA_DQ58
VMA_DQ57
VMA_DQ56
B4
A2
A4
DQ3 | DQ27
DQ2 | DQ26
DQ1 | DQ25
DQ0 | DQ24
VDDQ-P1
VDDQ-P3
VDDQ-P12
VDDQ-P14
P3
P12
P14
T1 T1
VDDQ-T1 T3 VDDQ-T1 T3
VDDQ-T3 T12 VDDQ-T3 T12
VDDQ-T12 T14 VDDQ-T12 T14
VDDQ-T14 VDDQ-T14
J5 J5
(14) FBA_CMD9 RFU/A12/NC (14) FBA_CMD25 RFU/A12/NC
K4 C5 K4 C5
(14) FBA_CMD6 A7/A8 | A0/A10 VDD-C5 (14) FBA_CMD26 A7/A8 | A0/A10 VDD-C5
K5 C10 K5 C10
(14) FBA_CMD7 A6/A11 | A1/A9 VDD-C10 (14) FBA_CMD27 A6/A11 | A1/A9 VDD-C10
K10 D11 K10 D11
(14) FBA_CMD4 A5/BA1 | A3/BA3 VDD-D11 (14) FBA_CMD17 A5/BA1 | A3/BA3 VDD-D11
K11 G1 K11 G1
(14) FBA_CMD3 A4/BA2 | A2/BA0 VDD-G1 (14) FBA_CMD18 A4/BA2 | A2/BA0 VDD-G1
H10 G4 H10 G4
(14) FBA_CMD1 A3/BA3 | A5/BA1 VDD-G4 (14) FBA_CMD20 A3/BA3 | A5/BA1 VDD-G4
H11 G11 H11 G11
(14) FBA_CMD2 A2 /BA0 | A4/BA2 VDD-G11 (14) FBA_CMD19 A2 /BA0 | A4/BA2 VDD-G11
H5 G14 H5 G14
(14) FBA_CMD11 A1/A9 | A6/A11 VDD-G14 (14) FBA_CMD23 A1/A9 | A6/A11 VDD-G14
H4 L1 H4 L1
(14) FBA_CMD10 A0/A10 | A7/A8 VDD-L1 (14) FBA_CMD22 A0/A10 | A7/A8 VDD-L1
L4 L4
VDD-L4 L11 VDD-L4 L11
VDD-L11 L14 VDD-L11 L14
B
D4 VDD-L14 P11 D4 VDD-L14 P11 B
(14) VMA_WCK01 WCK01 | WCK23 VDD-P11 (14) VMA_WCK67 WCK01 | WCK23 VDD-P11
D5 R5 D5 R5
(14) VMA_WCK01# WCK01# | WCK23# VDD-R5 (14) VMA_WCK67# WCK01# | WCK23# VDD-R5
R10 R10
P4 VDD-R10 P4 VDD-R10
(14) VMA_WCK23 WCK23 | WCK01 (14) VMA_WCK45 WCK23 | WCK01
P5 P5
(14) VMA_WCK23# WCK23# | WCK01# (14) VMA_WCK45# WCK23# | WCK01#
A1 A1
FBA_EDC3 R2 VSSQ-A1 A3 FBA_EDC4 R2 VSSQ-A1 A3
FBA_EDC2 R13 EDC3 | EDC0 VSSQ-A3 A12 FBA_EDC5 R13 EDC3 | EDC0 VSSQ-A3 A12
FBA_EDC1 C13 EDC2 | EDC1 VSSQ-A12 A14 FBA_EDC6 C13 EDC2 | EDC1 VSSQ-A12 A14
FBA_EDC0 C2 EDC1 | EDC2 VSSQ-A14 C1 FBA_EDC7 C2 EDC1 | EDC2 VSSQ-A14 C1
EDC0 | EDC3 VSSQ-C1 C3 EDC0 | EDC3 VSSQ-C1 C3
FBA_DBI3 P2 VSSQ-C3 C4 FBA_DBI4 P2 VSSQ-C3 C4
FBA_DBI2 P13 DBI3# | DBI0# VSSQ-C4 C11 FBA_DBI5 P13 DBI3# | DBI0# VSSQ-C4 C11
FBA_DBI1 D13 DBI2 #| DBI1# VSSQ-C11 C12 FBA_DBI6 D13 DBI2 #| DBI1# VSSQ-C11 C12
FBA_DBI0 D2 DBI1# | DBI2# VSSQ-C12 C14 FBA_DBI7 D2 DBI1# | DBI2# VSSQ-C12 C14
DBI0# | DBI3# VSSQ-C14 E1 DBI0# | DBI3# VSSQ-C14 E1
VSSQ-E1 E3 VSSQ-E1 E3
VSSQ-E3 E12 VSSQ-E3 E12
G3 VSSQ-E12 E14 G3 VSSQ-E12 E14
(14) FBA_CMD12 RAS# | CAS# VSSQ-E14 (14) FBA_CMD31 RAS# | CAS# VSSQ-E14
L3 F5 L3 F5
(14) FBA_CMD15 CAS# | RAS# VSSQ-F5 (14) FBA_CMD28 CAS# | RAS# VSSQ-F5
F10 F10
VSSQ-F10 H2 VSSQ-F10 H2
J3 VSSQ-H2 H13 J3 VSSQ-H2 H13
(14) FBA_CMD14 CKE# VSSQ-H13 (14) FBA_CMD30 CKE# VSSQ-H13
J11 K2 J11 K2
(14) VMA_CLK0# CK# VSSQ-K2 (14) VMA_CLK1# CK# VSSQ-K2
J12 K13 J12 K13
(14) VMA_CLK0 CK VSSQ-K13 (14) VMA_CLK1 CK VSSQ-K13
M5 M5
VSSQ-M5 M10 VSSQ-M5 M10
G12 VSSQ-M10 N1 G12 VSSQ-M10 N1
(14) FBA_CMD0 CS# | WE# VSSQ-N1 (14) FBA_CMD21 CS# | WE# VSSQ-N1
L12 N3 L12 N3
(14) FBA_CMD5 WE# | CS# VSSQ-N3 (14) FBA_CMD16 WE# | CS# VSSQ-N3
N12 N12
VSSQ-N12 N14 VSSQ-N12 N14
R1044 EV@120/F_4 J13 VSSQ-N14 R1 R1051 EV@120/F_4 J13 VSSQ-N14 R1
R1045 EV@1K_4 SEN_A J10 ZQ VSSQ-R1 R3 SEN_A J10 ZQ VSSQ-R1 R3
SEN VSSQ-R3 R4 SEN VSSQ-R3 R4
VSSQ-R4 R11 VSSQ-R4 R11
J2 VSSQ-R11 R12 J2 VSSQ-R11 R12
(14) FBA_CMD13 RESET# VSSQ-R12 (14) FBA_CMD29 RESET# VSSQ-R12
J1 R14 +1.35V_GFX J1 R14
R1050 EV@1K_4 MF VSSQ-R14 U1 R1049 EV@1K_4 MF VSSQ-R14 U1
VSSQ-V1 U3 VSSQ-V1 U3
VSSQ-V3 U12 VSSQ-V3 U12
VSSQ-V12 U14 VSSQ-V12 U14
A5 VSSQ-V14 A5 VSSQ-V14
U5 Vpp,NC U5 Vpp,NC
Vpp,NC1 B5 Vpp,NC1 B5
VREFD_VMA1 A10 VSS-B5 B10 VREFD_VMA2 A10 VSS-B5 B10
C C
U10 VREFD1 VSS-B10 D10 U10 VREFD1 VSS-B10 D10
2 1 VREFD2 VSS-D10 G5 2 1 VREFD2 VSS-D10 G5
C1060 EV@820P/50V_4 VSS-G5 G10 C1533 EV@820P/50V_4 VSS-G5 G10
2 1 VSS-G10 H1 2 1 VSS-G10 H1
C1534 EV@820P/50V_4 VSS-H1 H14 C1067 EV@820P/50V_4 VSS-H1 H14
VSS-H14 K1 VSS-H14 K1
VREFC_VMA1 J14 VSS-K1 K14 VREFC_VMA2 J14 VSS-K1 K14
2 1 VREFC VSS-K14 L5 2 1 VREFC VSS-K14 L5
C1046 EV@820P/50V_4 VSS-L5 L10 C1048 EV@820P/50V_4 VSS-L5 L10
VSS-L10 P10 VSS-L10 P10
J4 VSS-P10 T5 J4 VSS-P10 T5
(14) FBA_CMD8 ABI# VSS-T5 (14) FBA_CMD24 ABI# VSS-T5
T10 T10
VSS-T10 VSS-T10

EV@GDDR5 U1022 EV@GDDR5 U1021

VREF_VMA1_MOS VREF_VMA1_MOS
VREF_VMA1_MOS

+1.35V_GFX +1.35V_GFX +1.35V_GFX +1.35V_GFX

VMA_CLK0 VMA_CLK1
2

2
2

R1038 R1373 R1040 R1369


R1037 EV@931/F_4 R1372 *EV@931/F_4 R1039 EV@931/F_4 R1368 *EV@931/F_4
3

EV@549/F_4 *EV@549/F_4 EV@549/F_4 *EV@549/F_4


R1046 R1047
1

1
1

EV@80.6/F_4 EV@80.6/F_4 VREFC_VMA1 VREFD_VMA1 VREFC_VMA2 VREFD_VMA2 Q1031


2
GPIO10_VREF (16)
VMA_CLK0# VMA_CLK1# R1042 R1371 R1048 R1370
EV@1.33K/F_4 *EV@1.33K/F_4 EV@1.33K/F_4 *EV@1.33K/F_4 EV@2N7002K
1

+1.35V_GFX
D D

+1.35V_GFX +1.35V_GFX +1.35V_GFX +1.35V_GFX


GDDR5 Mode H Mapping
< 0-31 > < 32-63 > Memory
+1.35V_GFX C1038 EV@1u/6.3V_4 C1066 EV@1u/6.3V_4 C1050 EV@0.1u/16V_4 FBA_CMD14 R1053 EV@10K_4 CMD0 CMD16 CS*
C1535 EV@1u/6.3V_4 C1054 EV@1u/6.3V_4 C1531 EV@1u/6.3V_4 C1044 EV@1u/6.3V_4 FBA_CMD30 R1054 EV@10K_4 CMD1 CMD17 A3_BA3
C1536 EV@1u/6.3V_4 C1039 EV@1u/6.3V_4 C1068 EV@1u/6.3V_4 C1034 EV@1u/6.3V_4 CMD2 CMD18 A2_BA0
C1529 EV@330u/2V_7343 C1041 EV@1u/6.3V_4 C1062 EV@1u/6.3V_4 C1026 EV@1u/6.3V_4 C1057 EV@1u/6.3V_4
+

CKE* is strap pin to set ODT value of memory chip CMD3 CMD19 A4_BA2
C1059 EV@0.047u/10V_4 C1058 EV@0.047u/10V_4 C1074 EV@0.1u/16V_4 C1047 EV@0.047u/10V_4 CMD4 CMD20 A5_BA1
C1029 EV@0.1u/16V_4 C1049 EV@0.047u/10V_4 C1064 EV@0.047u/10V_4 C1052 EV@0.1u/16V_4 C1530 EV@0.047u/10V_4 CMD5 CMD21 WE*
C1025 EV@10U/6.3V_6 C1032 EV@0.1u/16V_4 C1033 EV@0.1u/16V_4 C1040 EV@0.1u/16V_4 C1030 EV@0.1u/16V_4 FBA_CMD13 R1041 EV@10K_4 CMD6 CMD22 A7_A8
C1053 EV@10U/6.3V_6 C1056 EV@0.1u/16V_4 C1043 EV@0.1u/16V_4 C1063 *EV@0.1u/16V_4 C1036 EV@0.1u/16V_4 FBA_CMD29 R1043 EV@10K_4 CMD7 CMD23 A6_A11
C1070 EV@10U/6.3V_6 C1027 EV@0.1u/16V_4 C1532 EV@0.1u/16V_4 C1042 *EV@0.1u/16V_4 C1045 EV@0.1u/16V_4 CMD8 CMD24 ABI*
C1037 EV@0.1u/16V_4 C1055 EV@0.1u/16V_4 C1035 *EV@0.1u/16V_4 C1031 EV@0.1u/16V_4 CMD9 CMD25 A12_RFU
201201117 Add C764 for EMI suggestion. CMD10 CMD26 A0_A10 Quanta Computer Inc.
CMD11 CMD27 A1_A9
CMD12 CMD28 RAS* PROJECT : Z8V
RST PD place @ the end of daisy-chain. CMD13 CMD29 RST*
CMD14 CMD30 CKE* Size Document Number Rev
CMD15 CMD31 CAS* 1A
N13PGV GDDR5x32-VRAM
Date: Monday, February 22, 2016 Sheet 18 of 45
1 2 3 4 5 6 7 8
5 4 3 2 1

DP TO VGA
19
D D

Power
R95 *0_4
+3V +3V (7,11,12,26) CLK_SDATA
(7,11,12,26) CLK_SCLK
R94 *0_4
VGA
L8 AVCC33 L7 VDD_DAC_33
60ohm@100MHz_6 60ohm@100MHz_6 C150

0.1U/16V_4

CRT_HPD

CIIC_SDA
CIIC_SCL

+3V
VCCK_V12
DDCDAT DDCDAT (20)
C559

33

32

31

30

29

28

27

26

25
CPU U5
0.1U/16V_4
C156
2.2U/6.3V_6
DDCCLK DDCCLK (20)

XI
EXT1.2V_CTRL

SMB_SCL

PVCC_33

VCCK_12
SMB_SDA

LDO_RSTB
EPAD

HPD
HSYNC HSYNC (20)
(2) CRT_HPD CRT_HPD
C C
VSYNC VSYNC (20)

AVCC33 1 24
AVCC_33 GND
AUX_CH_P 2 23 CRT_RED
AUX_P RED_P
AUX_CH_N 3 22 CRT_GRE
AUX_N GREEN_P
VCCK_V12

LANE0_P
4

5
AVCC_12

LANE0_P
RTD2166 VDD_DAC_33
BLUE_P
21

20
CRT_BLU

VDD_DAC_33
C141 CRT_RED CRT_RED (20)
(2) CRT_AUXN C137 0.1U/16V_4 AUX_CH_N 0.1U/16V_4 LANE0_N 6 19 HSYNC C565
LANE0_N HSYNC
C135 0.1U/16V_4 AUX_CH_P LANE1_P 7 18 VSYNC +5V 0.1U/16V_4 CRT_GRE
(2) CRT_AUXP LANE1_P VSYNC CRT_GRE (20)

POL1/SPI_CEB
LANE1_N 8 17
LANE1_N HVSYNC_PWR CRT_BLU CRT_BLU (20)

VGA_SDA
VGA_SCL
SPI_CLK

VCC_33
SPI_SO
C555 C546

SPI_SI
C104 0.1U/16V_4 LANE0_P POL2 4.7U/6.3V_6
(2) CRT_TXP0 0.1U/16V_4

(2) CRT_TXN0 C97 0.1U/16V_4 LANE0_N


9

10

11

12

13

14

15

16
C82 0.1U/16V_4 LANE1_P R74

DDCDAT
DDCCLK
(2) CRT_TXP1 +3V R73

(2) CRT_TXN1 C77 0.1U/16V_4 LANE1_N 4.7K_4 4.7K_4 +3V

B B

+3V
TP7

R693 4.7K_4

R694 *4.7K_4

Note:

1- C1,C3,C4,C5,C11,C16, C21 should be placed close to chip


2- C5 shold be X5R material
3- R6, R7, R8 should be 75 ohm with +/-1%
4- Suggest to connect Pin 29 and Pin 30 to PCH SMBUS for debug purpose.
5- This configuration is for internal ROM mode and using embedded LDO mode.

A A

(2,4,6,7,8,9,11,12,13,15,20,21,22,23,24,25,26,27,28,30,31,32,33,34,37,38,39) +3V
(20,21,23,24,26,30,37) +5V

Quanta Computer Inc.


PROJECT : ZRW
Size Document Number Rev
1A
DP to VGA iT6165
Date: Monday, February 22, 2016 Sheet 19 of 46
5 4 3 2 1
5 4 3 2 1

CRT CRTVDD5

RTD2166 integrate 5V HSYNC/VSYNC buffer inside IC


12/24 Delete R449
+5V

12/18 Change R412 to 47ohm for vendor requset


+5V 3
IN
Q8
OUT
GND
1
2
C70

CRTVDD5
*0.1u/16V_4

CN5
20

16
AP2331SA-7
R412 47/F_4 12/18 Change to BLM15BB220SN1D (CX5BB220005) 12/21 Change CN5 footprint to "dsub-95-0005-01-15p" for layout requset
C562 for vendor request 6
L4 BLM15BB220SN1D_4 CRT_R1 1 11 CRT_11 TP61
(19) CRT_RED 7
U30 0.1u/16V_4
L3 BLM15BB220SN1D_4 CRT_G1 2 12 DDCDAT DDCDAT (19)
(19) CRT_GRE
1 5 8
OE# VCC L2 BLM15BB220SN1D_4 CRT_B1 3 13 CRTHSYNC
(19) CRT_BLU
9
HSYNC R458 *0_4 2 4 R421 *33_4 CRTHSYNC 4 14 CRTVSYNC
(19) HSYNC A Y C143 C112 C88 C95 C128 C148 10
D D
R91 R85 R77 5 15 DDCCLK DDCCLK (19)
3 Close to RTD2166 IC 75/F_4 75/F_4 75/F_4 5.6p/16V_4 5.6p/16V_4 5.6p/16V_4 *5.6p/16V_4 *5.6p/16V_4 *5.6p/16V_4
GND
CRT CONN

17
*M74VHC1GT125DF2G DDCDAT 2.2K_4 R443 CRTVDD5
12/24 Delete R396 +5V 12/18 Un-Stuff C95/C128/C148 for vendor requset DDCCLK 2.2K_4 R398
Co-Layout 12/18 Change R399 to 47ohm for vendor requset U28
R399 47/F_4 CRTHSYNC 1 10 CRTHSYNC C67 *0.22u/6.3V_4
C533 CRTVDD5 2 1 10 9 CRTVDD5
3 2 9 C68 *220p/50V_4
U26 0.1u/16V_4 CRTVSYNC 4 GND_3/8 7 CRTVSYNC
DDCCLK 5 4 7 6 DDCCLK C69 0.1u/16V_4 CRTVDD5
Power trace tracking
1 5 5 6
OE# VCC (2,4,6,7,8,9,11,12,13,15,19,21,22,23,24,25,26,27,28,30,31,32,33,34,37,38,39) +3V
*RClamp0524P C539 *33P/50V_4 CRTVSYNC (19,21,23,24,26,30,37) +5V
(6,9,22,23,24,25,26,28,29,30,37,38,39) +3VPCU
VSYNC R392 *0_4 2 4 R406 *33_4 CRTVSYNC U6 C551 *33P/50V_4 CRTHSYNC
(19) VSYNC A Y (23,24,29,30,31,32,33,34,35,36,37,38,39) VIN
CRT_R1 1 10 CRT_R1
CRT_G1 2 1 10 9 CRT_G1 C532 *10p/50V_4 DDCCLK
3 3 2 9
GND Realtek FAE suggest close to connector GND_3/8
DDCDAT 4 7 DDCDAT C571 *10p/50V_4 DDCDAT
CRT_B1 5 4 7 6 CRT_B1
*M74VHC1GT125DF2G 5 6
Realtek FAE suggest close to connector
*RClamp0524P 12/18 Un-Stuff C539/C551 for vendor requset

LCD CONNECTOR LCD Power


VIN TP_PWR +3V
+3V

C21 C19 C8 C507 C10 C11


C20 U2 LCDVCC
4.7u/25V_8 1000p/50V_4 0.1u/16V_4 0.1u/16V_4_X7R
C 1000p/50V_4 1000p/50V_4 1u/6.3V_4 6 1 LCDVCC C
IN OUT
4 2 C7 C12 C6 C9 C18
IN GND
R30 *Short/0_4 EDP_VDD_EN_R 3 5 *0.1u/16V_4 *2.2u/50V_8 0.1u/16V_4 0.01u/50V_4 22u/6.3V_8
(2) EDP_VDD_EN ON/OFF GND

+3V 1A-5 VIN G5245AT11U

CN2 R31
MAX 1.5A R26 *short/0_8

G_5
R373 *100K_4 EDP_AUX_C R371 *100K_4 R27 *short/0_8 V_BLIGHT 1st : AL005245000---GMT
R374 *100K_4 EDP_AUX#_C R372 *100K_4 40 100K_4
TP_RST# R23 *TSI@10K_4 39
38 2nd : AL007553000---UPI
LCDVCC C17 C16 37
*1u/6.3V_4 *1u/6.3V_4 36
R24 *short/0_8 LCDVCC_R 35
34
2013/12/12 change eDP pin define +3V
C1642 *22U/6.3V_6 33
32
colayout FHD Panel for A2 stage R22 *short/0_6 TP_PWR 31 G_4 Touch screen level shift I2C(reserve) +3V
+5V 30
+3V R21 *0_4 TP_RST#
29
PCH_BRIGHT 28
Prevent ESD/EOS Layout near device (2) PCH_BRIGHT 27
BL_ON
R18 33_4 EDP_HPD_R 26
(2) EDP_HPD 25 R13 *TSI@0_4 R6 R16
EDP_AUXP C508 .1U/16V_4 EDP_AUX_C 24 *TSI@10K_4 *TSI@10K_4 S0
(2) EDP_AUXP 23
C4 EDP_AUXN C509 .1U/16V_4 EDP_AUX#_C
(2) EDP_AUXN 22 Q2
180P/50V_4 TPD->100kHz,TS=400Khz
EDP_TXP1 C504 .1U/16V_4 EDP_TXP1_C 21
(2) EDP_TXP1 20 S5 Intel design guide suggestion
EDP_TXN1 C503 .1U/16V_4 EDP_TXN1_C +3V 6 1 I2C1_SDA_C
eDP FHD (2) EDP_TXN1 19 MCP PIN 10u.
18 Per inch 3u TS=3x5inch
EDP_TXP0 C500 .1U/16V_4 EDP_TXP0_C 2 400kHz10~100u =2.4~0.4k.
(2) EDP_TXP0 17
EDP_TXN0 C499 .1U/16V_4 EDP_TXN0_C (4) I2C1_SDA
(2) EDP_TXN0 16 100Khz 10~100u=9k~1k.
15 (4) I2C1_SCL
Touch Panel-I2C I2C1_SCL_C R10 *TSI@0_4 (6) USBP6+ R362 *short_4 USBP6+_R 3 4 I2C1_SCL_C
B
I2C1_SDA_C R9 *TSI@0_4 R359 *short_4 USBP6-_R 14 B
CCD-USB (6) USBP6- 13 5
USBP5+ R8 TSU@0_4 12
(6) USBP5+ 11
Touch Panel-USB (6) USBP5- USBP5- R7 TSU@0_4
10 G_1 *TSI@DMN601DWK-7
EDP_TXP2 C497 .1U/16V_4 EDP_TXP2_C 9 R12 *TSI@0_4
(2) EDP_TXP2 8
EDP_TXN2 C496 .1U/16V_4 EDP_TXN2_C
(2) EDP_TXN2 7
eDP 4k*2k TS_EN R356 *Short/0_4 TS_EN_R
(28) TS_EN 6
EDP_TXP3 C495 .1U/16V_4 EDP_TXP3_C
(2) EDP_TXP3 5
EDP_TXN3 C494 .1U/16V_4 EDP_TXN3_C
(2) EDP_TXN3 4
R353 33_4 BOARD_ID4_TOUCH_S 3 +3VPCU
(8) Board_ID4 2
TP_INT
1
G_0

S5 C492 50398-04071-001
180P/50V_4
R11
Prevent ESD/EOS Layout near device *100K_4

+3V LID# LID# (28)

LID591#,EC intrnal PU
TS_EN R1 *0_4 TP_INT
D1
R28 R20 1N4148WS
1C1-2 2014/03/11 Add R698 for TS_EN short TP_INT,
for issue debug. 10K_4 10K_4
BL_ON
BL#
+3V
Hall Sensor (HSR) (2) PCH_BLON
R43 0_4 PCH_BLON_C

3
(28) PCH_BLON_R R42 0_4 R44
+3VPCU 2
EC_FPBACK# (28)
100K_4
Touch Panel interrupt R3 Q4
*TSI@10K_4 R678 *100K_4 Q6 DTC144EUA

1
2

DMN601DWK-7
A A

1
3 1 TP_INT
(4) TP_INT_PCH
D4
Q1 *VPORT_6
S5 *TSI@2N7002K S0 1 2
1 2 LID#
2

R2 *TSI@0_4 1B-3 2013/12/10 change Q3.3 from +3V to +3VPCU.


D31
C396 *VPORT_6
4.7U/6.3V_6
3

MR1
Quanta Computer Inc.
1

AH9249NTR-G1

1st:AL009249000 -- BCD
PROJECT : ZRW
Size Document Number Rev
2nd:AL009132001 -- ANC 1A
CRT/LVDS/CAMERA/LID
Date: Monday, February 22, 2016 Sheet 20 of 46
5 4 3 2 1
5 4 3 2 1

HDMI
<HDM>
+3V +3V

21

0.1U/16V_4_X7R
HDMI_EQ0 R250 *10K_4 HDMI_EQ1 R255 10K_4

R249 0_4 R254 *0_4


+3V

C402
HDMI_DDCDATA_MB
HDMI_DDCCLK_MB
D D
C404

HDMI_MB_HPD
0.1U/16V_4_X7R
+3V

U15

24
23
22
21
20
19
18
17
PTN3366BS

HPD_SNK
SDA_SNK
SCL_SNK
GND
TERM_EN
DDC_EN

VDD
OE_N
HDMI_DDCDATA_SW
(2) HDMI_DDCDATA_SW
HDMI_DDCCLK_SW
(2) HDMI_DDCCLK_SW

INT_HDMITX0P C397 0.1u/16V_4 INT_HDMITX0P_C_R 25 16 INT_HDMITX0P_C


(2) INT_HDMITX0P IN_D1- OUT_D1-
INT_HDMITX0N C394 0.1u/16V_4 INT_HDMITX0N_C_R 26 15 INT_HDMITX0N_C
(2) INT_HDMITX0N IN_D1+ OUT_D1+
INT_HDMITX1P C390 0.1u/16V_4 INT_HDMITX1P_C_R 27 14 INT_HDMITX1P_C
From PCH (2)
(2)
INT_HDMITX1P
INT_HDMITX1N
INT_HDMITX1N C384 0.1u/16V_4 INT_HDMITX1N_C_R 28 IN_D2-
IN_D2+
OUT_D2-
OUT_D2+
13 INT_HDMITX1N_C
INT_HDMITX2P C376 0.1u/16V_4 INT_HDMITX2P_C_R 29 12 INT_HDMITX2P_C
(2) INT_HDMITX2P IN_D3- OUT_D3-
INT_HDMITX2N C373 0.1u/16V_4 INT_HDMITX2N_C_R 30 11 INT_HDMITX2N_C
(2) INT_HDMITX2N IN_D3+ OUT_D3+
INT_HDMICLK+ C371 0.1u/16V_4 INT_HDMICLK+_C_R 31 10 INT_HDMICLK+_C
(2) INT_HDMICLK+ IN_D4- OUT_D4-
INT_HDMICLK- C370 0.1u/16V_4 INT_HDMICLK-_C_R 32 9 INT_HDMICLK-_C
(2) INT_HDMICLK- IN_D4+ OUT_D4+
33 37

HPD_SRC
SDA_SRC
SCL_SRC
CEN_PAD GND 36
GND

REXT
35

GND
VDD
EQ1

EQ0
GND 34
GND

1
2
3
4
5
6
7
8
+3V
+3V

HDMI_DDCDATA_SW
HDMI_DDCCLK_SW
HDMI_MB_HPD_R
HDMI-detect

HDMI_EQ1
C C

HDMI_EQ0
C403 C365 C364 C405 C367 C366 C406
+3V +3V 0.1U/16V_4_X7R 0.1U/16V_4_X7R 0.1U/16V_4_X7R 0.1U/16V_4_X7R 0.1U/16V_4_X7R 0.1U/16V_4_X7R 0.1U/16V_4_X7R

12.4K/F_4
C369
0.1U/16V_4

R274
S5 input high S0
2

*1M_4

(2) INT_HDMI_HPD 1 3 HDMI_MB_HPD_R

Q27

R253
*2N7002K HDMI connector
R285 *short/0_4
CN10
20
INT_HDMITX2P_C 1 SHELL1
2 D2+
INT_HDMITX2N_C 3 D2 Shield
INT_HDMITX1P_C 4 D2-
5 D1+
INT_HDMITX1N_C 6 D1 Shield
INT_HDMITX0P_C 7 D1-
R251 2.2K_4 HDMI_DDCCLK_SW 8 D0+
+3V D0 Shield
INT_HDMITX0N_C 9 23
R252 2.2K_4 HDMI_DDCDATA_SW INT_HDMICLK+_C 10 D0- GND
11 CK+ 22
D8 RB500V-40 R283 2.2K_4 INT_HDMICLK-_C 12 CK Shield GND
HDMI_5V 2 1 HDMI_DDCCLK_MB 13 CK-
14 CE Remote
D7 RB500V-40 R284 2.2K_4 +5V HDMI_DDCCLK_MB 15 NC
2 1 HDMI_DDCDATA_MB HDMI_DDCDATA_MB 16 DDC CLK
Q26 17 DDC DATA
B GND B
3 1 HDMI_5V 18
IN OUT 2 19 +5V
GND HDMI_MB_HPD HP DET 21
AP2331SA-7 C351 D3 SHELL2

1
*220p/50V_4 *EGA10402V05AH HDMI connector
DDS AL002331000 R246
*20K_4

2
EMI
INT_HDMITX2P_C

R261 *120/F_4

INT_HDMITX2N_C

INT_HDMITX1P_C

R264 *120/F_4

INT_HDMITX1N_C

INT_HDMITX0P_C
A A
R268 *120/F_4

INT_HDMITX0N_C

INT_HDMICLK+_C

R257 *120/F_4
Power trace tracking INT_HDMICLK-_C
Quanta Computer Inc.
(2,4,6,7,8,9,11,12,13,15,19,20,22,23,24,25,26,27,28,30,31,32,33,34,37,38,39)
(19,20,23,24,26,30,37)
+3V
+5V
PROJECT : ZRW
Size Document Number Rev
1A
HDMI (PS8407 4k*2k)
Date: Monday, February 22, 2016 Sheet 21 of 46
5 4 3 2 1
5 4 3 2 1

Giga LAN (LAN)

XTAL2 C324 12p/50V_4


LANVCC
40 mils (Iout=1A)
22

1
2
C328 C337 C339 C332
Y1 BG625000081 -> TXC(1st)
0.1u/16V_4 0.1u/16V_4 4.7U/6.3V_6 4.7U/6.3V_6
25MHZ +-30PPM BG625000085 -> HHE(2nd)

3
4
D D
XTAL1
VDD10 C306 12p/50V_4 For RTL8111H
R196 2.49K/F_4 RSET TP22 Place 0.1uF,4.7uF CAP close to each VDD33 pin-- 11, 32
10 mils TP19
LANVCC TP20

32
31
30
29
28
27
26
25
U7 RTL8111H (LDO mode) close to each VDD10 pin-- 3, 8, 22, 30 close to each VDD10 pin-- 22

AVDD33
RSET
AVDD10
CKXTAL2
CKXTAL1
LED0
LED1
LED2
REGOUT (reserve)
33 +3V VDD10
GND
40 mils (Iout=1A) 40 mils (Iout=1A)
R136 *short/0_8
R146
1K_4
MDI_0+ 1 24 REGOUT C268 C335 C338 C611 C333 C612 C613
MDI_0- 2 MDIP0 REGOUT 23 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 *1U/6.3V_4 *0.1u/16V_4
MDIN0 VDDREG LANVCC
VDD10
3 22 VDD10
MDI_1+ 4 AVDD10 DVDD10 21 PCIE_LAN_WAKE#_R
MDI_1- 5 MDIP1 LANW AKEB 20 ISOLATEB R128 NAC@0_4
MDIN1 ISOLATEB PLTRST# (8,13,24,25,28)
MDI_2+ 6 RTL8111H-CG 19 PERSTB R131 IOAC@0_4 IOAC_RST# (25,28) R147
MDI_2- 7 MDIP2(NC) PERSTB 18 C226 180P/50V_4 *15K_4
8 MDIN2(NC) HSON 17
VDD10 AVDD10 HSOP PCIE_RX5-_LAN_C C257 0.1u/16V_4
PCIE_RX5-_LAN (6)
PCIE_RX5+_LAN_C C258 0.1u/16V_4
PCIE_RX5+_LAN (6)
REFCLK_N
MDIN3(NC)

REFCLK_P
MDIP3(NC)

CLKREQB
AVDD33

C C
Consider VCC33 may be connected to Main
HSIN
HSIP

Power or chipset/bios's GPO, the pull-low


resistor R14 can be NC only when Main Power
or chipset/bios's GPO can ensure to drive the
9
10
11
12
13
14
15
16

ISOLATEB pin to a voltage level < 0.8V at the


system state S3~S5.
CLK_PCIE_LANN (6) If the ISOLATEB pin can not be well-controlled to
MDI_3+ CLK_PCIE_LANP (6) a voltage level < 0.8V at S3~S5, the pull-low
MDI_3- PCIE_TX5-_LAN (6) resistor R14 is needed to make sure the LAN
PCIE_TX5+_LAN (6)
LANVCC chip is well isolated.
PCIE_REQ_LAN#_R

Layout:All termination
Leakage circuit (MPC) Tramsformer signal should have 30 RJ45 Connector
+3V +3V mil trace

U11
+3V 1 24 LAN_MCT0
R168 R178 MDI_3+ 2 TCT1 MCT1 23 LAN_MX3+
CLK_PCIE_REQ4# have PU 10k. MDI_3- 3 TD1+ MX1+ 22 LAN_MX3- CN9
*10K/F_4 10K/F_4 TD1- MX1-
2

MAIN POWER(3V_S0)
4 21 LAN_MCT1 9
B
3 1 PCIE_REQ_LAN#_R MDI_2+ 5 TCT2 MCT2 20 LAN_MX2+ 9 B
S0 (6) CLK_PCIE_LAN_REQ#
MDI_2- 6 TD2+ MX2+ 19 LAN_MX2- 10
Q19 TD2- MX2- LAN_MX0+ 1 10
2N7002K 7 18 LAN_MCT2 LAN_MX0- 2 0+
R177 *0/J_4 MDI_1+ 8 TCT3 MCT3 17 LAN_MX1+ LAN_MX1+ 3 0-
MDI_1- 9 TD3+ MX3+ 16 LAN_MX1- LAN_MX2+ 4 1+
LANVCC TD3- MX3- LAN_MX2- 5 2+
10 15 LAN_MCT3 LAN_MX1- 6 2-
FAE suggest to TCT4 MCT4 1-
MDI_0+ 11 14 LAN_MX0+ LAN_MX3+ 7
change to 1K

GND
MDI_0- 12 TD4+ MX4+ 13 LAN_MX0- LAN_MX3- 8 3+
TD4- MX4- 3-
11

75/F_8
75/F_8

75/F_8

75/F_8
R129 TRANSFORMER

25
IOAC@1K_4 11
C346 12
12
2

EC_PCU LANVCC 0.01U/50V/X7R_4


12/16 Change P/N to CS07504FA11 RJ45
RES CHIP 75 1/8W +-1%(0805)

R224
R215

R217

R221
R112 NAC@0_4 3 1 PCIE_LAN_WAKE#_R
(8,25) PCIE_LAN_WAKE#
R111 IOAC@0_4 Q12
(28) IOAC_LAN_WAKE#
IOAC@2N7002K

TERM9
R130 NAC@0/J_4
Reserve IOAC No Stuff
Q13 IOAC@AO3413 LANVCC +3V_S5
4/20 REV:D add TP85 ~TP100 for AZ chip ICT/ATE Capacitor test

+3VPCU 1 3+3V_LANR118 R105 NAC@0_8 C342


1000P/3KV_1808
C206 IOAC@0_8
A R124 C234 C272 C253 C323 A
2

*IOAC@0.1U/16V_4 *IOAC@100K/J_4 10u/6.3V_6 0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4

(28) LANPWR# R108


IOAC@10K_4 C185

*IOAC@1000p/50V_4
Quanta Computer Inc.
PROJECT : ZRW
Size Document Number Rev
1A
LAN(RTL8111H)
Date: Monday, February 22, 2016 Sheet 22 of 46
5 4 3 2 1
5 4 3 2 1

Codec(ADO) DC-DET circuit(ADO) Rev:D change to shortpad

23
R626 *short_6
+5V
HP-R2 VIN
3 1 PVDD
HP-L2
+5V C671 Q43
LINE1-VREFO-L R624 *10u/6.3V_4 *AO3404

2
*1M_6
LINE1-VREFO-R

MIC2-VREFO
Close to codec R634

3
*100K_4
CODEC_VREF C719 2.2U/6.3V_4 ADOGND
DC-DET R629 *0_4 2 Q42
INT_AMIC-VREFO C715 10u/6.3V_4 *DTC144EU
D ADOGND +5VA D

C712

C716

C720
Change to 1U from Realtek's suggestion
R657 100K_4

1
10u/6.3V_4

1U/6.3V_4

1U/6.3V_4
C709
C710
0.1u/16V_4 10u/6.3V_4

+AZA_VDD
Place next to pin 26 Single DMIC and Dual DIMC same PN: AL403010A00
D-Mic (MIC)

36

35

34

33

32

31

30

29

28

27

26

25
+1.5VA
U37
ADOGND

CPVEE

HP-OUT-L

LINE1-VREFO-L

MIC2-VREFO

LDO1-CAP

AVDD1

AVSS1
CPVDD

CBN

HP-OUT-R

LINE1-VREFO-R

VREF
C704 +3V Far away rubber +3V
C706
10u/6.3V_4 0.1u/16V_4 C344 10u/6.3V_4 C340 *10u/6.3V_4
ADOGND 37 24 C345 0.1u/16V_4 C179 *0.1u/16V_4
CBP LINE2-L C343 10p/50V_4 C181 *10p/50V_4
38 23
ADOGND AVSS2 LINE2-R U10 U9
Place next to pin 40 C707 10u/6.3V_4 39 22 LINE1-L Close to codec 1 3DMIC_CLK_L1 R218 DMIC_CLK_L
*short/0_4 1 3DMIC_CLK_L3 R578 *0_4 DMIC_CLK_L2
LDO2-CAP LINE1-L VDD CLK VDD CLK
Analog 40 21 LINE1-R 2 4DMIC_DAT_L1 R586 DMIC_DAT_L
*short/0_4 2 4DMIC_DAT_L3 R554 *0_4 DMIC_DAT_L2
AVDD2 LINE1-R LR DATA LR DATA

D2
C347

C648
Digital L12 +5V_PVDD 41 20 R324 *short_6 5 7 5 7
PVDD PVDD1 NC +3VPCU GND GND GND GND

D26
PBY160808T-600Y-N(60,3A) analog digital 6 8 6 8
GND GND GND GND

1
L_SPK+ 42 19 C472 10u/6.3V_4
SPK-L+ MIC-CAP ADOGND
C697 C698 KMM40301026-18DS *KMM40301026-18DS
ALC255

TVS/6pF_4
43 18

*10p/50V_4

*10p/50V_4
L_SPK- SLEEVE trace width of SLEEVE & RING2 DUAL SECOND DMIC_CLK_L2

2
SPK-L- MIC2-R/SLEEVE

TVS/6pF_4
10u/6.3V_4 0.1u/16V_4
are required at least 40mil and

2
R_SPK- 44 17 RING2 Single DMIC DMIC_DAT_L2
SPK-R- MIC2-L/RING2 its length should be asshort as possible Place very closed

D16

D15
C640
C645
R_SPK+ 45 16 DUAL MAIN
SPK-R+ MONO-OUT

1
Low is power down
amplifier output 46 15
PVDD2 SPDIFO/FRONT JD
Close to codec
GPIO0/DMIC-DATA

47 14

*TVS/6pF_4

*TVS/6pF_4
PD#

*10p/50V_4
*10p/50V_4
GPIO1/DMIC-CLK
Placement near Audio Codec
Left Right

2
C C691 C692 PDB MIC2/LIN2 JD C
48 13 SENSEA R643 200K_4 HP_JD#
TP83 SPDIF-OUT SDATA-OUT HP/LINE1 JD

LDO3-CAP
10u/6.3V_4 0.1u/16V_4 R220 *0_4 DMIC_CLK_L2

SDATA-IN

DVDD-IO

PCBEEP
RESETB
BIT-CLK
R644 100K_4 +3V
DVDD

SYNC
49
DVSS

DGND R219 *0_4 DMIC_DAT_L2


Analog
Digital
1

10

11

12
DMIC_DAT

DMIC_CLK

C455
DC-DET

Change 47K to 22K for PCBEEP


1.6Vrms
+3V R630 *short/0_6 +AZA_VDD
10u/6.3V_4

PCBEEP C688 0.1u/16V_4 BEEP_1 R627 22K_4 D21 1N4148WS


SPKR (4)
R323

C678 D20 1N4148WS


PCBEEP_EC (28)
C676 C685 100p/50V_4 R632
0.1u/16V_4 10u/6.3V_4 Change to 10K from Realtek's suggestion
10K_4
*Short/0_4

+3V +1.5V

CPU 3.3V

DMIC_DAT_L R639 *short_4


PCH_AZ_CODEC_RST#

PCH_AZ_CODEC_SYNC
(4)

(4)
R631 *short/0_4
Universal Audio Jack HEADPHONE/MIC/LINE combo (ADO)
Tied at one point only DMIC_CLK_L R638 22_4 DVDD_IO R628 *0_4
under SLEEVE/RING2 trace > 40mils
the codec or near the codec
R660 *0_4 C674 ACZ_SDIN R314 33_4
PCH_AZ_CODEC_SDIN0 (4)
C686 C677 HP/LINE trace > 10mils
R661
R665
*0_4
*0_4
Close to codec 10p/50V_4
PCH_AZ_CODEC_BITCLK (4) 0.1u/16V_4 10u/6.3V_4
L/R spacing > 10mils
R655 *0_4 MIC2-VREFO R646 2.2K/J_4
R326 *0_4 C679 *22p/50V_4 R420& R422 change to 62 ohm -> 3/11
R331 *SHORT_4 R645 2.2K/J_4
C728 *1000p/50V_4 PCH_AZ_CODEC_SDOUT (4) Place next to pin 9
SLEEVE
SLEEVE (27)
C727 *0.1u/16V_4
RING2
B RING2 (27) B

ADOGND HP-L2 R663 62/F_4 HP-L3


HP-L3 (27)
Cap need near AVDD1 HP-R2 R664 62/F_4 HP-R3
HP-R3 (27)
and AVDD2
power source input HP_JD#
HP_JD# (27)
R653 R649
LINE1-L C711 4.7U/6.3V_6 *10K/J_4 *10K/J_4 C723 C729 C733 C734

LINE1-VREFO-L R654 4.7K_4 100p/50V_4 100p/50V_4 100p/50V_4 100p/50V_4

LINE1-VREFO-R R656 4.7K_4

LINE1-R C705 4.7U/6.3V_6 ADOGND

Codec PWR 5V(ADO) Mute(ADO)


+AZA_VDD +1.5V

R635
1K_4
2

DIGITAL ANALOG
PD# D28 *RB500V-40 3 1 PCH_AZ_CODEC_RST#

+5V +5VA R640

L14 HCB2012KF220T60/6A/22ohm_8
*10K/J_4 C690
*1u/10V_4
Q44
*PJA138K Codec PWR 1.5V(ADO)
D29 RB500V-40
AMP_MUTE# (28)
C718 C722

*10u/6.3V_6 *0.1u/16V_4 +1.5VA

C732 C672 DIGITAL ANALOG


A A
*0.1u/16V_4 *10u/6.3V_6 ADOGND
Internal Speaker +1.5V L13 HCB1608KF-121T30_3A

40mil for each signal 4 ohm : 40mil for each signal C708

SPK_CONN_4P 1U/6.3V_4
1003 change 0603type
R_SPK+ R688 *short_6 R_SPK+_1
R_SPK- R687 *short_6 R_SPK-_1 1
L_SPK- R686 *short_6 L_SPK-_1 2
L_SPK+ R685 *short_6 L_SPK+_1 3 5
4 6
CN18 Quanta Computer Inc.
C743 C744 C742 C741
Rev:D change to shortpad
*68p/50V_4 *68p/50V_4 *68p/50V_4 *68p/50V_4 PROJECT : ZRW
1B-2 2013/12/04 Change PN and footprint. Size Document Number Rev
1A
1B-5 2013/12/17 Change CN14 pin define ALC255/HP/SPK
Date: Monday, February 22, 2016 Sheet 23 of 46
5 4 3 2 1
5 4 3 2 1

SATA HDD
CN11
20120921 change Cn10 Pin define following Z09.
SATA ODD Connector
24
26 24 CN7
25 23 14
22 GND14
21 1
20 DEVSLP0_R R637 *0_4 GND1 2 SATA_TXP1_C C622 0.01u/50V_4
DEVSLP0 (6) RXP SATA_TXP1 (6)
19 3 SATA_TXN1_C C616 0.01u/50V_4
18 120mil +5V_HDD R625 *short0/J_8 +5V RXN 4
SATA_TXN1 (6)
17 GND2 5 SATA_RXN1_C C610 0.01u/50V_4
D TXN SATA_RXN1 (6) D
16 C669 C670 C680 C689 C675 6 SATA_RXP1_C C606 0.01u/50V_4
15 TXP 7 SATA_RXP1 (6)
+ C182 180P/50V_4
GND3 SSD_ID (6)
14 10u/6.3V_6 *0.1u/16V_4 *0.1u/16V_4 0.01u/50V_4 R102 33_4
13 ODD_PRSNT# (4)
*100u/6.3V_3528 R101 10K_4 +3V Prevent ESD/EOS Layout near device
12 8 ODD_PRSNT#_C C178 *15p/50V_4
11 DP 9 +5VODD R483 *short/0_8 +5V_ODD
10 +5V 10
9 +5V 11 C584 C586 C583 C585 C601 C588

+
8 R310 *0_4 MD 12
ACCEL_INT2 (26) Connect to G-sensor INT2 GND
7 13 0.01u/50V_4 0.01u/50V_4 *0.1u/16V_4 *0.1u/16V_4 10u/6.3V_6 *100u/6.3V_3528
6 SATA_RXP0_C C681 0.01u/50V_4 GND
5 SATA_RXP0 (6) 15
SATA_RXN0_C C682 0.01u/50V_4
SATA_RXN0 (6) GND15
4
3 SATA_TXN0_C C683 0.01u/50V_4 SATA_TXN0 (6) 6030D-13G20
EC_ODD_EJ# (28)
2 SATA_TXP0_C C684 0.01u/50V_4 SATA_TXP0 (6)
1
1A-8
R97 10K_4 +3V
MAIN_SATA_CONN

ODD Power (SATA) +3VPCU Q14 POA(FPD) +POA_PWR D49


1
*FPD@D5V0X1B2LP-7B
2 USBP3+_R
VIN +5V IOAC@AO6402A +5V_ODD +POA_PWR
+5V
1

6 +3V_LDO_EC R859 FPD@0_4 C726 *FPD@2.2u/16V_6


D50 *FPD@D5V0X1B2LP-7B
R167 5 4 R121 NAC@0_8 1 2 USBP3-_R
IOAC@100K 2 R860 *FPD@0_4
+3VPCU
C 1 R139 C

1
R865 *FPD@0_4 Q45
Reserve IOAC Power No Stuff IOAC@22_8 +3V
2

R110 FPD@AO3413
3

ODD_EN_Q 2 1
MOD_EN_5V

R1530
IOAC@100K R652 FPD@10K/J_4 2 +3V_POA_R
(28) POA_FP_PWREN# *FPD@0_4

3
(28) ODD_POWER R141 IOAC@0_4 ODD_EN C927
ODD_EN_Q 2

3
5

6
1

R152 *IOAC@0_4 *FPD@1000p/50V_4


(2) PCH_ODD_EN
C189 Q17 20mil +3V_POA R666 FPD@0_4 20mil
R133 IOAC@0.1u/25V_6 IOAC@2N7002K
C731 C724
2

*IOAC@100K
1

Can not change to shortpad in ramp stage FPD@4.7u/6.3V_6 FPD@0.01u/50V_4


2

IOAC@DMN601DWK-7
Q15 CN17
1 10
Co-Layout
4

USBP3+_R 2 9
USBP3+ R1526 FPD@0_4 USBP3+_R3 R1528 FPD@0_4 USBP3+_R USBP3-_R 3
USBP3- R1527 FPD@0_4 USBP3-_R3 R1529 FPD@0_4 USBP3-_R 4
FPD@0_4 R1535 5
(28) POA_EN# 6
FPD@0_4 R1536
(28) POA_PWR_INT#
FPD@0_4 R1537 7
(28) POA_AUTH_ERR
FPD@0_4 R1538 8
U39 (28) POA_POWERREQ
+3VPCU FPD@CONN_AOP
Can not change to shortpad
*FPD@0_4 R1531 USBP3+_U 1 4
(6) USBP3+ Y+ M- TP88
*FPD@0_4 R1532 USBP3-_U 2 5
(6) USBP3- Y- M+ TP89
3 6 USBP3-_R2 *FPD@0_4 R1534 USBP3-_R SEL OE# Y+ Y-
R650 *FPD@0_4 R651 *FPD@10_4 9 GND D- 7 USBP3+_R2 *FPD@0_4 R1533 USBP3+_R
10 VCC D+ 8 R659 *FPD@0_4
(28,30,33,37) MAINON SEL OE# X H Hi-Z Hi-Z
SP@ BOM周周不NPCT650 C702 C703
A,B,C P/N:AL009655K01(SLB9655TT1.2- FW4.31) L L M+ M-
*FPD@PI3USB102
RAMP P/N: AL000650K01 (NPCT650AAAWX) *FPD@0.01u/50V_4 *FPD@0.1U/16V/X7R_4 H L D+ D-
TPM NPCT650 (TPM)
B
+3V3_TPM_VSB
Spec define: High Active B

+3V_S5 +3V3_TPM
+3V_S5
AL000650K01 :NPCT650AAAWX R647 TPM@0_6
C699 TPM@10u/6.3V_6 R662 TPM@0_6
C696 TPM@0.1u/16V_4 HOLE2 HOLE13 HOLE12 HOLE9 HOLE5
C695 TPM@0.1u/16V_4 C721 TPM@10u/6.3V_6 HOLE23 *HG-C354D118P2 *HG-Z8V-1 *HG-C315D118P2 HOLE4 EV@MBZRQ001010 EV@MBZRQ001010
C687 TPM@0.1u/16V_4 C700 TPM@0.1u/16V_4 MBZAA002010 7 6 7 6 7 6 *H-C315D118P2
TPMM 1.2 AL009655K01 8 5 8 5 8 5
9 4 9 4 9 4
TPMM 2.0 AL000650K01
22
14

U36
8

1
2
3

1
2
3

1
1
2
3

1
VDD3
VDD2
VDD1

VSB

1
12/30 Delete Hole3 & Hole22 for DXF
(7,25,28) LPC_LAD3 LPC_LAD3 15 4 TPM_PP WLAN NUT For GPU sku
18 LAD3 PP 3 TP84
(7,25,28) LPC_LAD2 LPC_LAD2 GPX HOLE18
LAD2/SPI_IRQ GPX/GPIO2 TP85
(7,25,28) LPC_LAD1 LPC_LAD1 21 30 HOLE7 HOLE11 HOLE6 HOLE10 *HG-TC315BC236D118P2
LAD1/MOSI GPIO1 TP87
LPC_LAD0 24 *H-TC315IC186BC146D146PT *H-TC315IC186BC146D146PT *H-TC315IC186BC146D146PT *H-TC315IC186BC146D146PT 7 6 SPAD1 SPAD2 SPAD4
(7,25,28) LPC_LAD0 LAD0/MISO
LPC_LFRAME# 20 29 8 5 *SPAD-C315 *SPAD-C315 *pad-z8v-2-np
(7,25,28) LPC_LFRAME# LFRAME/SCS GPIO0/XOR_OUT TP86
(7,28) IRQ_SERIRQ IRQ_SERIRQ 27 6 TPM_BADD R642 *TPM@10K_4 9 4
PCLK_TPM 19 SERIRQ GPIO3/BADD 5
(7) PCLK_TPM LCLK/SCLK TEST

1
2
3

1
1
CLKRUN# R633 TPM@0_4 TPM_CLKRUN# 13 2
(7,28) CLKRUN#
1

1
1
PLTRST# R636 TPM@0_4 TPM_LRESET# 17 CLKRUN/GPIO04 NC1 7
(8,13,22,25,28) PLTRST# LRESET/SPI_RST NC2
LPCPD 28 10 1/4 Add for DXF
LPCPD NC3 11
NC4 SSD NUT
26 12
31 NC7 NC5 25 BADD SELECTION
NC8 NC6
GND1
GND2
GND3
GND4

0 EEh - EFh HOLE15 HOLE16 HOLE20 HOLE21 HOLE8 HOLE19


B.M.

3/4 EMI request add 33p near TPM IC 1 7Eh - 7Fh MBZAA001010 MBZAA001010 MBZAA001010 *HG-Z8V-3 *HG-TC354BC315D118P2 *HG-TC354BC315D118P2 HOLE24
7 6 7 6 7 6 *o-z8v-1
C673
TPM@NPCT620/650_QFN32 8 5 8 5 8 5
33

9
16
23
32

CLKRUN# '1' - pin is left open. 9 4 9 4 9 4


'0' - pin is pulled down.
A +3V3_TPM A
1

1
2
3
1

1
2
3
1

1
2
3
TPM@33P/50V_4

1
LPCPD R648 *TPM@4.7K_4

12/31 Add for D-Shape Hole


HOLE1 HOLE14 HOLE17
*h-c197d197n *H-C118D118N *H-O118X157D118X157N

Quanta Computer Inc.


1
1
1

PROJECT : ZRW
12/30 Modify Hole1、Hole14、Hole17 to NC Size Document Number Rev
1A
HDD/ODD/TPM NPCT650
Date: Monday, February 22, 2016 Sheet 24 of 46
5 4 3 2 1
5 4 3 2 1

NGFF_M.2 WiFi & BT (NGF)


25
+3VPCU (6,9,20,22,23,24,26,28,29,30,37,38,39)
+1.5V (9,23,37)
+3V (2,4,6,7,8,9,11,12,13,15,19,20,21,22,23,24,26,27,28,30,31,32,33,34,37,38,39)

CN3
Leakage circuit (MPC)
+WL_VDD +WL_VDD

1 NGFF 2 +3V +WL_VDD +WL_VDD


USBP4+ 3 GND 3.3Vaux 4 C493 10u/6.3V_6 +3V
(6) USBP4+ USB_D+ 3.3Vaux
USBP4- 5 6 C2 0.1u/16V_4
(6) USBP4- USB_D- LED#1
7 8 C14 0.1u/16V_4
9 GND PCM_CLK 10 C15 0.1u/16V_4
SDIO CLK(O) PCM_SYNC R15 R14
11 12 C1 0.1u/16V_4 APU Internal PU 2N7002KDW R364
13 SDIO CMDIO) PCM_IN 14 APU External nu-PU 4.7K/J_4 4.7K/J_4
*10K_4
15 SDIO DAT0(IO) PCM_OUT 16 5
SDIO DAT1(IO) LED#2 IOAC S0
17 18
19 SDIO DAT2(IO) GND 20 WLAN_CLKREQ# 4 3
21 SDIO DAT3(IO) UART Wake 22 S0 PCIE_CLKREQ_WLAN# (6)
23 SDIO Wake(I) UART Rx 24
25 SDIO Reset Key 5 26 2
KEY1 Key 6 IOAC
27 28 EC_PCU
29 KEY2 Key 7 30 WLAN_WAKE_R# 1 6
31 KEY3 Key 8 32 S0 IOAC_WLAN_WAKE# (28)
33 KEY4 UART Tx 34 Q3
D D
PCIE_TX6+_WLAN 35 GND UART CTS 36
(6) PCIE_TX6+_WLAN PETp0 UART RTS
PCIE_TX6-_WLAN 37 38 R363 *0/J_4 R365
(6) PCIE_TX6-_WLAN PETn0 Clink RESET
39 40 R368 *0/J_4
GND CLink DATA PCIE_LAN_WAKE# (8,22)
PCIE_RX6+_WLAN 41 42 WIFI_SUSCLK
(6) PCIE_RX6+_WLAN PERp0 CLink CLK
PCIE_RX6-_WLAN 43 44 IOAC No Stuff *0_4
(6) PCIE_RX6-_WLAN
45 PERn0 COEX3 46 C498 180P/50V_4 S0
CLK_PCIE_WLANP 47 GND COEX2 48 WIFI card reset (non-IOAC)
(6) CLK_PCIE_WLANP REFCLKP0 COEX1
CLK_PCIE_WLANN 49 50 R360 IOAC@0_4 WIFI card reset (IOAC)
(6) CLK_PCIE_WLANN REFCLKN0 SUSCLK(32KHz) IOAC_RST# (22,28)Debug card reset
51 52 WLAN_RST# R361 NAC@0_4 PLTRST#
GND PERST0# PLTRST# (8,13,22,24,28)
WLAN_CLKREQ# 53 54 BT_EN BT_EN (28)
WLAN_WAKE_R# 55 CLKREQ0# W_DISABLE#2 56 RF_EN
PEWake0# W_DISABLE#1 RF_EN (28)
57 58
59 GND NFC I2C SM DATA 60
61 PETp1 NFC I2C SM CLK 62
63 PETn1 NFC I2C IRQ 64 LPC_LAD0_C R358 *short_4 LPC_LAD0
GND NFC Reset# LPC_LAD0 (7,24,28)
65 66 LPC_LAD1_C R357 *short_4 LPC_LAD1
PERp1 RESERVED3 LPC_LAD1 (7,24,28)
67 68 LPC_LAD2_C R355 *short_4 LPC_LAD2
PERn1 RESERVED4 LPC_LAD2 (7,24,28)
69 70 LPC_LAD3_C R354 *short_4 LPC_LAD3
GND RESERVED5 LPC_LAD3 (7,24,28)
CLK_PCI_LPC R5 *0_4 CLK_PCI_LPC_C 71 72
(7) CLK_PCI_LPC Reserved1 3.3Vaux +WL_VDD
(7,24,28) LPC_LFRAME# LPC_LFRAME# R4 *0_4 LPC_LFRAME#_C 73 74 Rev:D change to shortpad
75 Reserved2 3.3Vaux
GND

For Debud Card use WLAN_NGFF CONN(Type 2230)


12/21 Change CN3 footprint to "ngff-nase0-s6701-ts48-ke-smt " for SMT requset

Stuff
Q29 IOAC@AO3413 +WL_VDD +3V

1 3+3V_WLAN R375 R352 NAC@0_8


+3VPCU
Low Mini card +3V power enable C505 IOAC@0_8
R369 C510 C3 C13 C511

2
*IOAC@0.1U/16V_4 *10u/6.3V_6 *0.1u/16V_4 **0.1u/16V_4 **0.1u/16V_4
High Mini card +3V power disable *IOAC@100K/J_4

(28) WLANPWR# WLANPWR#


R370
IOAC@10K_4 C506

*IOAC@1000p/50V_4
Reserve only for Intel module no need to stuff by default 11/24 Reserve IOAC No Stuff

Reserver +1.5v for WIFI module


U1 +3V_S5 +WL_VDD Q28 *IOAC@AO3413

R17 **10K_4 1 5 1 3+3V_WLAN


C +3V_S5 NC VCC +1.5V C
1

R19 C502
SUSCLK 2 C5 *10K_4 R367
(6) SUSCLK A
2
*0.1u/16V_4 **IOAC@0.1U/16V_4
2

**IOAC@100K/J_4
3 4 WIFI_SUSCLK
GND Y WLANPWR#
R366
*74AUP1G07GW *IOAC@10K_4 C501

**IOAC@1000p/50V_4
No Stuff

+3V3_SATA_N1 +3V
NGFF_M.2 SSD (NGF) R576 *short/0_8 C649 10u/6.3V_6
C647 0.1u/16V_4
C638 10u/6.3V_6
C639 0.1u/16V_4
C642 0.1u/16V_4
C643 0.1u/16V_4
C637 0.1u/16V_4

CN8 +3V3_SATA_N1

1 NGFF 2
3 GND 3.3V 4
5 GND 3.3V 6 +3V3_SATA_N1
7 PERn3 NC 8
9 PERp3 NC 10 TP73
11 GND DAS 12
13 PETn3 NOTCH/3.3V 14 12/17 Delete R571 & Net "+3V3_SATA_N1_N"
15 PETp3/NOTCH NOTCH/3.3V 16
17 GND/NOTCH NOTCH/3.3V 18
19 PERn2/NOTCH NOTCH/3.3V 20
21 PERp2/NOTCH NC 22
23 GND/CONFIG_0 NC 24
25 PETn2 NC 26
27 PETp2 NC 28
SATA_RXN1/PEG_RXN10_L2 R503 *Short/0_4 SATA_RXN1/PEG_RXN10_L2_N 29 GND NC 30
(6) SATA_RXN1/PEG_RXN10_L2 PERn1 NC
SATA_RXP1/PEG_RXP10_L2 R502 *Short/0_4 SATA_RXP1/PEG_RXP10_L2_N 31 32
(6) SATA_RXP1/PEG_RXP10_L2 PERp1 NC
33 34
SATA_TXN1/PEG_TXN10_L2 C630 0.1u/16V_4 SATA_TXN1/PEG_TXN10_L2_N 35 GND NC 36 R563 *Short/0_4 DEVSLP2
(6) SATA_TXN1/PEG_TXN10_L2 PETn1 NC DEVSLP2 (6)
SATA_TXP1/PEG_TXP10_L2 C629 0.1u/16V_4 SATA_TXP1/PEG_TXP10_L2_N 37 38 DEVSLP_N1 R561 *10K_4
(6) SATA_TXP1/PEG_TXP10_L2 PETp1 DEVSLP
39 40
SATA_RXP3/PEG_RXP9_L0 R497 *Short/0_4 SATA_RXP3/PEG_RXP9_L0_N 41 GND NC 42
B (6) SATA_RXP3/PEG_RXP9_L0 B
SATA_RXN3/PEG_RXN9_L0 R496 *Short/0_4 SATA_RXN3/PEG_RXN9_L0_N 43 PERn0/SATA-B+ NC 44
(6) SATA_RXN3/PEG_RXN9_L0 PERp0/SATA-B- NC
45 46
SATA_TXN3/PEG_TXN9_L0 C626 0.1u/16V_4 SATA_TXN3/PEG_TXN9_L0_N 47 GND NC 48
(6) SATA_TXN3/PEG_TXN9_L0 PETn0/SATA-A- NC
SATA_TXP3/PEG_TXP9_L0 C625 0.1u/16V_4 SATA_TXP3/PEG_TXP9_L0_N 49 50 NGFF1_RST# R562 *Short/0_4 PLTRST#
(6) SATA_TXP3/PEG_TXP9_L0 51 PETp0/SATA-A+ PERST# 52 PCIE_CLKREQ_NGFF1#
GND CLKREQ# PCIE_CLKREQ_NGFF1# (6)
(6) CLK_PCIE_NGFF1_N CLK_PCIE_NGFF1_N 53 54
CLK_PCIE_NGFF1_P 55 REFCLKn PEWake# 56 TP74
(6) CLK_PCIE_NGFF1_P +3V3_SATA_N1 REFCLKp N/C
57 58 TP76
12/17 Add R692 for Sata SSD 59 GND N/C 60
R692 *10K_4 61 NOTCH NOTCH 62
63 NOTCH NOTCH 64 +3V3_SATA_N1
NGFF3_DET R189 1M_4 65 NOTCH NOTCH 66
(6) NGFF3_DET NOTCH NOTCH
67 68
3

NGFF3_PEDET 69 NC SUSCLK(32KHz) 70
Q23 R183 71 PEDET 3.3V 72
73 GND 3.3V 74
2 75 GND 3.3V
*0_4
GND
GND

GND

2N7002K NGFF_SSD
76
77
1

12/21 Change CN8 footprint to "ngff-nasm0-s6701-ts50-km-smt " for SMT requset

A A

Quanta Computer Inc.


PROJECT : ZRW
Size Document Number Rev
1A
Mini-Card/WL/3G/SIM
Date: Monday, February 22, 2016 Sheet 25 of 46
5 4 3 2 1
5 4 3 2 1

TOUCHPAD BOARD CONN (TPD I2C/PS2 co-lay) 1C-2 2014/01/13 Change TP power rail from +3V_S51C-4 2014/01/15 reserve TP power rail +3V_S5.
KEYBOARD (KBC)
26
to +3V_SUS.
R671 0_6 1C1-1 2014/02/17 Add Q47 for PTP
CN15 power EN and soft up R694\C713.
1 MX0 TPD->100kHz,TS=400Khz R667 *short_4 *AO3413 and C712\C686.
MX0 (28) <EMI> +3V_S5
2 MX1 Intel design guide suggestion +3V_S5 1 3
MX1 (28)
3 MX2 MX4 1 2 MCP PIN 10u.
MX2 (28)
4 MX3 MX5 3 4 CP4 Per inch 3u TS=3x5inch C730 Q47 C736 + C739
MX3 (28)
5 MX4 MX6 5 6 *220P_8P4R
400kHz10~100u =2.4~0.4k. R670 R669
MX4 (28)

2
6 MX5 MX7 7 8 0.1u/16V_4 0.22u/25V_6 0.1u/16V_4
7 MX6
MX5 (28)
MY3 1 2
100Khz 10~100u=9k~1k. 10K_4 10K_4
MX6 (28) TP CN
8 MX7 MY2 3 4 CP1 R658 *0_4 C725 *1000p/50V_4 50mil
MX7 (28) (28) PTP_PWR_EN#
9 MY17 MY1 5 6 *220P_8P4R +TPVDD 8 10
D MY17 (28) D
10 MY16 MY0 7 8 R672 *short_4 TPCLK_R 7 9
MY16 (28) (28) TPCLK
11 MY15 MY7 1 2 R673 *short_4 TPDATA_R 6
MY15 (28) (28) TPDATA
12 MY14 MY6 3 4 CP2 5
MY14 (28)
13 MY13 MY5 5 6 *220P_8P4R +TPVDD I2C_TP_SDA_R 4
MY13 (28)
14 MY12 MY4 7 8 R668 TDI@0_4 I2C_TP_SCL_R 3
MY12 (28)
15 MY11 MY11 1 2 TPD_INT# 2
MY11 (28) *TDI@DMN601DWK-7
16 MY10 MY10 3 4 CP3 *2.2K_4 R675 C738 C737 TPD_EN 1
MY10 (28)
17 MY9 MY9 5 6 *220P_8P4R *0.1u/16V_4 *0.1u/16V_4
18
19
MY8
MY7
MY9
MY8
(28)
(28)
MY8
MX0
7
1
8
2
S5 1 6 S5 *2.2K_4 R676 CN16
MY7 (28)
20 MY6 MX1 3 4 CP5 (4) I2C0_SDA 2 I2C_TP_SDA_R I2C PU at CPU side
MY6 (28)
21 MY5 MX2 5 6 *220P_8P4R (4) I2C0_SCL I2C_TP_SCL_R
MY5 (28) (28) TPD_EN
22 MY4 MX3 7 8
MY4 (28)
23 MY3 MY15 1 2 4 3
MY3 (28)
24 MY2 MY14 3 4 CP6 1A-5 2013/10/18 Change CN21 Pin8 for
MY2 (28) (4,28) TPD_INT#
25 MY1 MY13 5 6 *220P_8P4R 5 I2C/PS2 TPD idendify.
MY1 (28)
26 MY0 MY12 7 8
MY0 (28) Q48
27 2013/10/29 Change CN21 power rail to S5
28 R677 TDI@0_4 change Q42 direction and net name,
R674 33_4 +3V_S5 1A-12 reseve PS2 PU to +3V.
NBSWON# (28)
29
30 +3VPCU
1

KB CONN C735
D30
*VPORT_6
180P/50V_4 RP1
10
*10K_10P8R
1 MX3
CPU FAN (THM) +3V
Prevent ESD/EOS MX4 9 2
12/16 Change FAN design from PWM-type to DAC-type
2

Layout near MX6 8 3 MX2


MX5 7 4 MX0 +3V
device 6 5 MX1 R690
C MX7 C

R691 +5V 10K_4

*10K_4
AL000991000 EOD, change to AL005606002
+3V
KB_BL LED (KBC)

2
C747
(28) FAN1_RPM
2.2U/6.3V_6
Q49 U40 30mils CN19

1
2
2N7002K 2 3 TH_FAN_POWER
+5V +5V VIN VO 5 1
1 3 1 GND 6 2 4
(7) SMB1ALERT#

2
C36 KBL@2.2u/6.3V_6 /FON GND 7 C746 C748 C745 3 5
R33 4 GND 8 FAN_3P
1

(28) FAN1_DAC VSET GND 2.2U/6.3V_6 .01U/50V_4 *.01U/50V_4

1
KBL@10K_4 Q5 EC DAC SIGNAL G991P11U
KBL@AO3413
2
FANPWR = 1.6*VSET
1A-1 2013/10/15 change pin define and add pwm IC U17.
3

20mil 20mil 1A-4 2013/10/17 Change U17 to G991P11U and PU U17 pin1.
3

2 +5V_KB
(28) KB_BL_LED
1A-9 2013/10/24 Add alert on U17.1 for CPU themal tempture.
Q7 C23 C22
KBL@DTC144EU CN4 1A-13 2013/10/31CN15 Pin2/3 swap.
1

KBL@4.7u/6.3V_6 KBL@0.01u/50V_4
4
3 6
2 5
B 1 B

KBL@KB_backlight

1A-7 2013/10/22 change CN25 pin define for spec.


R684 *1M_4
1A-8 2013/10/23 change CN25 footprint.
+3VPCU Blue71B5 ohm CS07152FB15 -B 5/18 ReB E
POWER LED(UIF) R679 *1M_4 +3V Amber 130 ohm CS11302FB15 -B 5/18 ReB E
R683 *1M_4 +3VPCU

G-sensor(ACS) Power LED


D10 1 2 *5.5V/25V/410P_4

*GS@0_6 R265 +G_SEN_PW Blue


LED1
+3V
R348 71.5/F_4 2 3 R681 0_4 +3VPCU
(28) PWRLED#
U16
C388 C429 1 2 R350 130/F_4 1
Vdd_IO NC (28) SUSLED# +3VPCU
*GS@0.1U/16V_4 14 3 R682 *0_4 +3V_S5
*GS@10u/6.3V_6 VDD NC LED_AMBER/BLUE
Rev:E change Amber
1 2
D11 *5.5V/25V/410P_4 C740
10 39P/50V_4
*GS@RB500V-40 D6 ACCEL_INTA_R 11 RESERVED 15
to CPU (4) ACCEL_INTA INT1 RESERVED
to SATA HDD *GS@RB500V-40 D5 ACCEL_INT2_R 9 R343 *1M_4 +3VPCU
(24) ACCEL_INT2 INT2
R266 *shortGS@0_4 7 R680 *1M_4 for ESD
CLK_SDATA R269 *shortGS@0_4 G_MBDATA_R 6 SA0 5
(7,11,12,19)
(7,11,12,19)
CLK_SDATA
CLK_SCLK CLK_SCLK R279 *shortGS@0_4 G_MBCLK_R 4 SDA
SCL
GND
GND
12 Battery D13 1 2 *5.5V/25V/410P_4
13
A
ACCEL_INTA +G_SEN_PW 8 GND 16 Blue
LED2
A
+G_SEN_PW CS GND R345 71.5/F_4 2 3 R347 0_4 +3VPCU
(28) BATLED0#
G_MBDATA_R C389 *33P/50V_4
*GS@LIS3DHTR R344 130/F_4 1
(28) BATLED1#
C420 G_MBCLK_R C400 *33P/50V_4 R349 *0_4 +3V_S5
*22P/50V_4 LED_AMBER/BLUE

R267 *4.7K_4 G_MBDATA_R


Rev:E change Amber
1 2
Quanta Computer Inc.
+G_SEN_PW D12 *5.5V/25V/410P_4
R289 *4.7K_4 G_MBCLK_R
PROJECT : ZRW
Size Document Number Rev
KB/TP/FAN 1A

Date: Monday, February 22, 2016 Sheet 26 of 46


5 4 3 2 1
5 4 3 2 1

USB Charger to 3.0 (UBC) USBPWR0

+5VPCU
80 mils (Iout=2A)

C482
1
U19

IN OUT

ILIM_LO
12

15
16
ILIM_LO
ILIM_HI
(RILIM_LO 1.2A)
80 mils (Iout=2A)
SDP
CTL1
1
CTL2
1
CTL3
1
ILIM_SEL
0
27

+
1U/10V_4 ILIM_HI C476 C474
(RILIM_HI 2.3A) R338 C477
9 R340 470P/50V_4 0.1u/16V_4 CDP 1 1 1 1
STATUS 17 100u/6.3V_1206
20K/F_4 39K/F_4
13 GND_PAD
(6) USB_OC0# 4 FAULT 14
(28) USB_BC_ON ILIM_SEL GND DCP 0 1 1 X
5 11 USBP0-_C iPAD charging current is about 2.1A so set on 2.3A
(28) USB_CHARGE_ON EN DM_IN 10 1.2A current limit of USB 3.0 SDP mode
R339 100K_4 USBP0+_C
D
6 DP_IN D
(28) USB_CLT1 7 CTL1 2
R337 10K_4 CTL2
+5VPCU CTL2 DM_OUT USBP0- (6)
R336 10K_4 CTL3 8 3
CTL3 DP_OUT USBP0+ (6)
18 21 RILIM_LO is optional and the ILIM_LO pin may be left unconnected if the following conditions are met:
19 GND GND 22
GND GND
1. ILIM_SEL is always set high
20 2. Load Detection - Port Power Management is not used
GND
GMT:AL003703000(G3703) TPS2544RTER
3. Mouse / Keyboard wake function is not used
If conditions 1 and 2 are met but the mouse / keyboard wake function is also desired, it is recommended to use
TI:AL002544001(TPS2544) RILIM_LO < 80.6 kΩ.
Silergy: AL055544000 (SLGC55544VTR) The following equation programs the typical current limit:
(1) IOS_typ(mA) = 50,250/{RILIM_XX(KΩ)+0.1}
RILIM_XX corresponds to either RILIM_HI or RILIM_LO as appropriate.

USB 3.0 Connector (UB3)


USBP0-_C
USBP0+_C
TP95 USBP0-_C TP99 USBPWR0
USBP0+_C CN14 USBPWR0
TP94 TP101
USB3.0 CONN
USB3_RXN0 1 U20
TP97 TP90 1 VBUS
2 USB3_TXP0_C 1
USB3_RXP0 3 2 D- I/O 1 10 USB3_TXN0_C
TP96 TP91 C484 *1.6P/50V_4
4 3 D+ 2 I/O 6
USB3_TXN0_C 5 4 GND VDD 9
TP98 TP93 (6) USB3_RXN0 5 SSRX- GND_2
6 C475 3
(6) USB3_RXP0 7 6 SSRX+ NC_1 8
TP100 USB3_TXP0_C TP92 0.1u/16V_4
12/18 Add for ESD C483 *1.6P/50V_4 8 7 GND USBP0-_C 4 NC_2
9 8 SSTX- I/O 2 7 USBP0+_C
9 SSTX+ USB3_RXP0 5 I/O 5

13
12
11
10

GND_1
I/O 3 6 USB3_RXN0
+5V_S5 I/O 4

13
12
11
10
C C

11
C481 0.1u/16V_4 USB3_TXN0_C
(6) USB3_TXN0
C479 0.1u/16V_4 USB3_TXP0_C
C422 USBPWR1 (6) USB3_TXP0
U17 USB30_ESD_AZ1065-06F.R7G
1u/6.3V_4 Close USB3.0
5
IN OUT
1 C480 C478 USB protection diodes for ESD.
*1.6P/50V_4 *1.6P/50V_4
2 as close as possible to USB connector pins.
GND
USBON# 4 3 C418 C417 C433
(28) USBON# /EN /OC 470P/50V_4 0.1u/16V_4 100U/6.3V_1206

G524B2T11U
(6) USB_OC1#

Enable: Low Active /2.5A (6) USBP1-


BCD:AL002822000 (6) USBP1+ USBPWR1
GMT:AL000524007 USBPWR1
CN12 U18
USB3.0 CONN USB3_TXN1_C 1
USBP1- 1 I/O 1 10 USB3_TXP1_C
TP107 TP111 1 VBUS I/O 6
2 2
3 2 D- VDD 9
TP106 USBP1+ TP113 C452 *1.6P/50V_4
4 3 D+ C447 3 GND_2
USB3_RXN1 5 4 GND 0.1u/16V_4 NC_1 8
TP109 TP102 (6) USB3_RXN1 5 SSRX- NC_2
6 USBP1- 4
(6) USB3_RXP1 7 6 SSRX+ I/O 2 7
USB3_RXP1 USBP1+
TP108 TP103 7 GND I/O 5
C451 *1.6P/50V_4 8 USB3_RXP1 5

GND_1
USB3_TXN1_C 9 8 SSTX- I/O 3 6 USB3_RXN1
TP110 TP105 9 SSTX+ I/O 4

13
12
11
10
TP112 USB3_TXP1_C TP104
12/18 Add for ESD

13
12
11
10

11
USB30_ESD_AZ1065-06F.R7G
C445 0.1u/16V_4 USB3_TXN1_C
(6) USB3_TXN1
(6) USB3_TXP1
C442 0.1u/16V_4 USB3_TXP1_C USB protection diodes for ESD.
as close as possible to USB connector pins.
B B
C446 C443
*1.6P/50V_4 *1.6P/50V_4

CN1
+5V_S5
USB2.0 DB (UB2) Card Reader (CRD) SD_WP/MS_D1
SD_CDZ
11
10 WP
CD NC
16
USBPWR2 SD_D2/MS_D5 9 17
1u/6.3V_4 U38 SD_D1/MS_D7 8 DATA2 NC
C694 TP44
TP46 TP48 SD_D0/MS_D6 7 DATA1
5 1 6 DATA0
IN OUT SD_CLK R351 0_4 SD_CLK_R 5 VSS2

SD_D2/MS_D5
SD_D3/MS_D4
2 C701 VCC_XD reserve for EMI 4 CLK
GND C714 C713 C717 C491 1u/10V_4 3 VDD
USBON# 4 3 470P/50V_4 0.1u/16V_4 10U/6.3V_6 100U/6.3V_1206 SD_CMD 2 VSS1

GND
GND
GND
GND
/EN /OC CMD

XD_D7
SD_D3/MS_D4 1

SP14

SP11
CD/DATA3

V18
G524B2T11U Enable: Low Active /2.5A SD-CARD

12
13
14
15
USB_OC2#
(6) USB_OC2# BCD:AL002822000 24 R696 C486
23
22
21
20
19
GMT:AL000524007 U21 *2K/F_4 C485
USBPWR2 4.7u/6.3V_6 0.1u/16V_4
V18
XD_D7
SP14
SP13
SP12
SP11
+3V
CN13 R346 6.2K/F_4 RREF 1 18 SD_CMD
2 RREF SP10 17 GPIO0 TP49
1 (6) USBP7- 3 DM GPIO0 16 SP9
RTS5170 SP9 TP50
2 (6) USBP7+ 4 DP 15
R341 *short/0_6 +3V_CR SD_CLK 12/31 Add R696 for discharge
3 VCC_XD 5 3V3_IN SP8 14 SP7 TP47
4 SDREG 6 CARD_3V3 SP7 13 SD_CDZ
5 SDREG SP6
XD_CD#

6
7
C487 C490 C488 EMI 0218 reserve for EMI
SP1
SP2
SP3
SP4
SP5

USBP2- Pin Numbers: 4.7U/6.3V_6 0.1u/16V_4 1u/10V_4 SD_CLK_R


(6) USBP2- 8 GND
USBP2+ 25 SD_CMD
(6) USBP2+ 9 USBPWR: 5 SD_D2/MS_D5
7
SD_WP/MS_D1 8
9
SD_D1/MS_D710
SD_D0/MS_D611
12

10 GND: 7 SD_D1/MS_D7
A
11 Audio Signal: 5 R342 C489 SD_D0/MS_D6 A
12 *0_4 0.1u/16V_4 SD_D3/MS_D4
13 ADOGND: 4
HP_JD#
XD_CD#

(23) HP_JD# 14 NC: 1 C1648 C1647 C1643 C1644 C1645 C1646


15 USBP2+/-: 2
SP2

SP5

SLEEVE 16 *10p/50V_4 *10p/50V_4 *10p/50V_4 *10p/50V_4 *10p/50V_4 *10p/50V_4


(23) SLEEVE 17
RING2 18
(23) RING2 19
HP-L3 20
(23) HP-L3 21 TP42TP43 TP45
HP-R3 22
(23) HP-R3 23
24
Quanta Computer Inc.
CONN SMD FFC 24P 1R FR(P0.5,H2.0)
PROJECT : ZRW
Size Document Number Rev
ADOGND 1A
USB3/Charger/CR/USB2 DB
Date: Monday, February 22, 2016 Sheet 27 of 46
5 4 3 2 1
5 4 3 2 1

EC(KBC) R612 *0_4

28
+3V_LDO_EC
L11 +A3VPCU
BLM15AG121SN1D(120,500MA)_4 +3VPCU_ECPLL L9 +3VPCU_EC +3V_S5 R613 0_4 VSTBY_FSPI
C667 11/11 FAE BLM15AG121SN1D(120,500MA)_4
0.1u/16V_4 suggestion C657 +3V_LDO_EC
(For PLL Power)
pin106 +3V_RTC
ECAGND change to 0.1u/16V_4
+3VPCU_EC S5_ON R615 10K_4
R616 2.2_6 12 mils Prevent ESD/EOS Layout near device NBSWON# R260 10K_4
1 2 SB_ACDC (8)
+3V_LDO_EC +3VPCU_EC
POA_EN# (24)
R623 33_4
BT_EN (25)
C662 C658 C661 C660 C356 C665
+3VPCU_EC and +3V_RTC POA_PWR_INT# (24)
+3V_GFX
0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 C668
minimum trace width 12mils. POA_POWERREQ (24)
180P/50V_4
TP80 Prevent ESD/EOS Layout near device
DGPU_OTP# R232 EV@10K_4
VSTBY_FSPI USBON# (27)
R601 *2.2_6 R617 33_4 DGPU_OPP# R620 EV@10K_4
1 2 TPD_EN (26)
D +3V +3V_EC D
1 2 USB_BC_ON (27)
+3V_S5 USB_CHARGE_ON (27)
R605 2.2_6 C654 C663
CLKRUN# (7,24)
180P/50V_4
(7,24,25) LPC_LAD0
0.1u/16V_4 MAINON R256 100K_4
(7,24,25) LPC_LAD1

114
121

106

127
U35

11
26
50
92

74

84
83
82

19
20

99
98
97
96
93
(7,24,25) LPC_LAD2

3
12/16 Add D32 for production-line requset SUSON R239 100K_4
(7,24,25) LPC_LAD3 10 110 MBCLK

VSTBY
VSTBY
VSTBY
VSTBY
VSTBY

VSTBY(PLL)

EGCLK/GPE3
EGCS#/GPE2
EGAD/GPE1

L80HLAT/BAO/GPE0
L80LLAT/GPE7

GPH7
ID6/GPH6
ID5/GPH5
ID4/GPH4
ID3/GPH3
CLKRUN#/ID0/GPH0
VCC

VSTBY_FSPI
AVCC
9 LAD0/GPM0(3) SMCLK0/GPB3 111 MBCLK (29)
C359 180P/50V_4 MBDATA LID#_C VRON R619 100K_4
8 LAD1/GPM1(3) SMDAT0/GPB4 115 MBDATA (29)
SM BUS 2ND_MBCLK 2ND_MBCLK (7,16)
LAD2/GPM2(3) SMCLK1/GPC1

2
+3V_LDO_EC 7 116 2ND_MBDATA PCH_SPI_SI_EC R614 *10K_4
LAD3/GPM3(3) SMDAT1/GPC2 2ND_MBDATA (7,16)
22 117 EC_PECR_R R608 43_4 D32
(8,13,22,24,25) PLTRST# LPCRST#/GPD2 PECI/SMCLK2/GPF6(3) H_PECI (2)
13 118 LID#_C R607 33_4 TVM0G5R5M220R PCH_SPI_SO_EC R263 *10K_4
(7) CLK_PCI_EC 6 LPCCLK/GPM4(3) SMDAT2/PECIRQT#/GPF7(3) LID# (20)

1
(7,24,25) LPC_LFRAME# LFRAME#/GPM5(3) C659 180P/50V_4
PROCHOT_EC 17 Prevent ESD/EOS Layout near EC
LPCPD#/GPE6
2

D17 126 PS/2


R603 SDMK0340L-7-F
(7,24) IRQ_SERIRQ
TP81 5
15
GA20/GPB5(3)
SERIRQ/GPM6(3) PS2CLK0/CEC/TMB0/GPF0
85
86 IOAC_RST# (22,25) TVS PN: SM BUS PU(KBC)
100K_4 LPC
(8) PCH_SUSPWRDNACK
23 ECSMI#/GPD4(3) PS2DAT0/TMB1/GPF1 89 EC_FPBACK# (20) Priority1: CY000220Z00
(2) SIO_EXT_SCI# TPCLK (26) Priority2: CY402220B00
1

WRST# 14 ECSCI#/GPD3 PS2CLK2/GPF4 90


WRST# GPIO PS2DAT2/GPF5 TPDATA (26)
4 +3V_LDO_EC
(7) SIO_RCIN# 16 KBRST#/GPB6(3)
C653
1u/6.3V_4
(25) IOAC_WLAN_WAKE# PWUREQ#/BBO/SMCLK2ALT/GPC7(3)
IT8987E/CX PWM0/GPA0
PWM1/GPA1
24
25 PWRLED#
BATLED1#
(26)
(26) Battery module
MBCLK
MBDATA
R611
R610
4.7K_4
4.7K_4

R270 33_4
(26)
(8)
KB_BL_LED
DNBSWON#
113
123 CRX0/GPC0
CTX0/TMA0/GPB2(3) CIR
LQFP PWM2/GPA2
PWM3/GPA3
PWM4/GPA4
28
29
30
31
SUSLED#
SUSLED#
BATLED0#
MAINON
(26)
(26)
(24,30,33,37)
+3V_S5
(20) TS_EN PWM5/GPA5 USB_CLT1 (27)
TS_EN_C
Pin 80 EC_APWROK reserve TP 2ND_MBCLK R247 2.2K_4
PWM
C387 180P/50V_4 TP82 80 UMA& VGA SKU 2ND_MBDATA R243 2.2K_4
119 DAC4/DCD0#/GPJ4(3) 47
Prevent ESD/EOS Layout near device (8,31) SUSB# DSR0#/GPG6 TACH0A/GPD6(3) FAN1_RPM (26) Need Stuff
33 48
(8) EC_PWROK 88 GINT/CTS0#/GPD5 TACH1A/TMA1/GPD7(3) POA_AUTH_ERR (24)
(20) PCH_BLON_R 81 PS2DAT1/RTS0#/GPF3 120
(26) FAN1_DAC 87 DAC5/RIG0#/GPJ5(3) TMRI0/GPC4(3) 124 SUSON (8)
C
(22) IOAC_LAN_WAKE# 109 PS2CLK1/DTR0#/GPF2 TMRI1/GPC6(3) DGPU_OTP# (16) C
12/16 SWAP with "TS_EN_C" to pin81 (4) ME_WR# 108 TXD/SOUT0/GPB1
(23) AMP_MUTE# RXD/SIN0/GPB0
71 107 NBSWON#
(24) ODD_POWER 72 ADC5/DCD1#/GPI5(3) PWRSW/GPE4 18 NBSWON# (26)
(29) ACIN ADC6/DSR1#/GPI6(3) UART port RI1#/GPD0(3) SUSC# (8)
73 WAKE UP 21 HWPG
(29) TEMP_MBAT# 35 ADC7/CTS1#/GPI7(3) RI2#/GPD1 HWPG (8) H_PROCHOT# (2,29,34)
(25) WLANPWR# RTS1#/GPE5

3
34
(23) PCBEEP_EC 122 PWM7/RIG1#/GPA7 112 Q40
(33) DDR4_SUSON_2V5 95 DTR1#/SBUSY/GPG1/ID7 RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 RSMRST# (8)
Prevent ESD/EOS Layout near device +1V_S5_ON
(31) +1V_S5_ON 94 CTX1/SOUT1/GPH2/SMDAT3/ID2 2
R621 33_4 EC_ODD_EJ_R# Prevent ESD/EOS Layout near device PROCHOT_EC
(24) EC_ODD_EJ# CRX1/SIN1/SMCLK3/GPH1/ID1
105 R618 33_4
(7) PCH_SPI_CLK_EC 101 FSCK/GPG7 RF_EN (25)
C666 180P/50V_4 R599 2N7002K
(7) SPI_CS0#_UR_ME 102 FSCE#/GPG3
EXTERNAL SERIAL FLASH ICMNT

1
(7) PCH_SPI_SI_EC 103 FMOSI/GPG4 66 ICMNT (29)
C664 100K_4
(7) PCH_SPI_SO_EC FMISO/GPG5 ADC0/GPI0(3) 67 C398 10u/6.3V_6 ECAGND 180P/50V_4
56 ADC1/GPI1(3) 68
12/16 SWAP with "FAN1_DAC" to pin32 (26) MY16 57 KSO16/SMOSI/GPC3(3) ADC2/GPI2(3) 69 DGPU_OPP# (16)
(26) MY17 32 KSO17/SMISO/GPC5(3) ADC3/GPI3(3) 70 VRON (8)
TS_EN_C
PWM6/SSCK/GPA6 ADC4/GPI4(3) LANPWR# (22)
S5_ON 100 A/D D/A
(30,37) S5_ON 125 SSCE0#/GPG2
(26) PTP_PWR_EN# SSCE1#/GPG0 SPI ENABLE
76
36 TACH2/GPJ0(3) 77 POA_FP_PWREN# (24)
CLK_PCI_EC SYS_HWPG
(26) MY0 37 KSO0/PD0 GPJ1(3) 78
(26) MY1 38 KSO1/PD1 DAC2/TACH0B/GPJ2(3) 79 PCH_PWROK (8)
(26) MY2 39 KSO2/PD2 DAC3/TACH1B/GPJ3(3) CLR_CMOS (6)
(26) MY3 40 KSO3/PD3
R602 +3V
(26)
(26)
MY4
MY5
41
42
KSO4/PD4
KSO5/PD5
HWPG(KBC)
*22_4 KBMX DDR=1.5V, D1 DNP and D2 POP
(26) MY6 43 KSO6/PD6
(26) MY7 44 KSO7/PD7 DDR=1.35V, D1 POP and D2 DNP R604
(26) MY8 45 KSO8/ACK# 10K_4
(26) MY9 46 KSO9/BUSY
C651
(26) MY10 51 KSO10/PE 2
*10p/50V_4 D23 RB500V-40 HWPG
(26) MY11 KSO11/ERR# GPJ7 SYS_SHDN# (2,30,37) (37) HWPG_1.5V
KSI3/SLIN#
KSI1/AFD#

52 128
KSI0/STB#

KSI2/INIT#

CLOCK R606 33_4


(26) MY12 53 KSO12/SLCT GPJ6 TPD_INT# (4,26)
D22 *RB500V-40
VCORE

(26) MY13 54 KSO13 (37) HWPG_1.8VS5


AVSS

Prevent ESD/EOS Layout near device


KSI4
KSI5
KSI6
KSI7

(26) MY14
VSS

VSS
VSS
VSS

KSO14
VSS

B 55 C656 D27 *RB500V-40 B


(26) MY15 KSO15 (33) HWPG_VDDR
180P/50V_4
IT8987/CX SM BUS ARRANGEMENT TABLE D24 *RB500V-40
(31) HWPG_1VS5
1

27
49
91

ECAGND 75

12
58
59
60
61
62
63
64
65

104

SM Bus 1 Battery D18 *RB500V-40


(30) SYS_HWPG
(26) MX0
C655 D19 *RB500V-40
(26) MX1 AJ089870F02 IT8987E/CX SM Bus 2 PCH/VGA
(32) HWPG_+VCCOPC
(26) MX2
0.1u/16V_4 D25 *RB500V-40
(26) MX3 (33) HWPG_2.5V
R609
R622
R262

R234

EC_GND

(26) MX4
(26) MX5 SM Bus 3
L10
(26) MX6
*0_4
*0_4
*0_4
*Short/0_4

(26) MX7
BLM15AG121SN1D(120,500MA)_4 SM Bus 4

+3V_LDO_EC
Reserve switch for test Reset SW (FSW) R592 *0_4 +3V_RTC
(MP remove)
R641 R591 *0_4
10K_4
Battery Detect Switch +3VPCU Reserve no stuff
12/14 Add R689 for Acer requset
SW2 R689 *0_4 +3V_RTC R581
POWER_SW SW3 *10K_4
NBSWON# 1 3
2 4 WRST#
1

3 2
(29) BI
C693 4 1 R536
5

C646
0.1u/16V_4 100K_4
*0.1u/16V_4
3

Vgs = 1.5V
2

2 BI_GATE

Vgs = 1.5V
1

SW1
5

A
PJA138K C634 A
3
4

POWER_SW
1

Q37 *0.1u/25V_6 6
2

Q38
5 *PJ4N3KDW
4

1
1
2

Quanta Computer Inc.


(6,9,20,22,23,24,25,26,29,30,37,38,39) +3VPCU PROJECT : ZRW
(13,15,16,39) +3V_GFX
Size Document Number Rev
(2,4,6,7,8,9,11,12,13,15,19,20,21,22,23,24,25,26,27,30,31,32,33,34,37,38,39) +3V
1A
(2,3,4,6,7,8,9,22,24,25,26,30,32,33,38) +3V_S5 KBC IT8587
Date: Monday, February 22, 2016 Sheet 28 of 46
5 4 3 2 1
5 4 3 2 1

Double Check ADP-In Type

12/22 Change PJ2 footprint to "50320-0040n-001-4p-l-smt"


& reverse Pin1~4 for SMT request

PJ2
VA

1
PD1
SV1040
VA1 PQ1
AON6414AL

3
VA2 PR3
0.01/F_0612 VIN
PQ2
AON6414AL

3
29
3 5 2 1 2 5 2
4 2 1 1
3
2

P4SMAFJ20A

47n/50V_6

*0.01u/50V_4
1

PC2
PR2 0_4 24780_ACN

0.1u/50V_6

4
PD2

PC5

PC17
Power conn PC12 PC7
D 0.1u/50V_6 2200p/50V_4 D
PR1 0_4 24780_ACP

2
PC14 PC13 PC1
0.1u/50V_6 2200p/50V_4 1n/50V_4

PR29 PR28
4.02K/F_4 4.02K/F_4
PR4
*short_6

24780_ACP

24780_ACN PR7 10/F_6

PC36 PC25 PC35


0.1u/50V_6 0.1u/50V_6 0.1u/50V_6

24780_CMSRC

1
PR16 3 18 24780_BATDRV

ACN
ACP
20_1206 CMSRC BATDRV
17 24780_BATSRC VIN
BATSRC
C 24780_ACDRV 4 REGN6V C
PR31 ACDRV
REGN6V 866K/F_4 24780_VCC 28
VCC 24 24780_REGN
PC16 REGN PC9
0.47u/25V_6 2.2u/10V_6 PC172 PC170
2200p/50V_4 10u/25V_8
PR39 PR211 PR11
100K/F_4 137K/F_4 0_6

5
24780_ACDET 6 25 24780_BST
ACDET BTST PC15
PR30 *short_4 5 47n/50V_6
(28) ACIN ACOK
MBDATA PR19 *short_4 11 26 24780_DH 4
SDA HIDRV PQ30 PR209
PR40 MBCLK PR17 *short_4 12 AON7410 0.01/F_0612 BAT-V
100K/F_4 SCL PU1 PL5

3
2
1
ICMNT PR32 *short_4 7 BQ24780SRUYR 6.8uH_7X7X3
(28) ICMNT IADP 27 24780_LX 1 2 BAT-V
D/C# PR26 *short_4 8 PHASE
TP1 IDCHG

5
PMON PR25 *short_4 9
(34) PMON PMON
100P/50V_4

100P/50V_4
*100P/50V_4
PC18

PC20

PC37
PR33
UMA-> PR342 CS31542FB14 15.4K 1/16W +-1% (0402) For 78W PR23 no stuff *4.7_6
12.7K/F_4 23 24780_DL 4 PR210 PR208
LDODRV PQ29 *short_4 *short_4
Dis -> PR342 CS31272FB17 12.7K 1/16W +-1% (0402) For 95W AON7410
24780_BM# 16
+3VPCU

3
2
1
PR9 10K_4 TB_STAT PR5 PC6 24780_SRP PC165 PC164 PC166
PC167 24780_CMPOUT 14 0_6 0.1u/25V_4 PC19 2200p/50V_4 10U/25V_8 10U/25V_8
0.1u/50V_6 PR15 *10K_4 CMPOUT 20 24780_SRP *680p/50V_6 24780_SRN
B 24780_ILIM 21 SRP B
ILIM PC3

PROCHOT
PC168 PR204 24780_CMPIN 13 PR6 0.1u/25V_4

BATPRES
*100p/50V_4 316K/F_4 CMPIN 0_6
19 24780_SRN

GND
GND
GND
GND

GND

GND
GND
GND
GND
GND
PAD
SRN

BAT-V PC4

35
36
37
38
10

15

22
29
30
31
32
33
34
0.1u/25V_4
PR206 PR207
BI (28)
100K/F_4 100K_4
PR10 *0_4
9 8
7
50458-00801-V01

6 PR14 100_4 TEMP_MBAT#


5 TEMP_MBAT# (28) Power charger circuit reserBe 2N7002 for GPU throtting

*0_4
PR8 *short_4
4 PC8
3 0.01u/50V_4
2 +3VPCU GPU_THROTTING# (16)
PR18 1M_4
10 1

PR205

3
PJ1
TEMP_MBAT#

24780_CMPOUT 2
PR13 PR12 PQ28
100_4 100_4 *EV@2N7002K
REGN MAX voltage 6.5V
Double Check BATT-In Type
V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr

1
H_PROCHOT#
MBCLK (28)
H_PROCHOT# (2,28,34) =0.793V for 3.965A current limit
A A
MBDATA (28) PR22
ILIM=0.793V
*100K_4 Rsr = 0.01ohm
1
1

PC10 PC11
*47p/50V_4 *47p/50V_4

+VCCIO
Quanta Computer Inc.
2
2

PD3 PD4
PDZ5.6B PDZ5.6B Check PU high with HW side PROJECT : ZRW
Size Document Number Rev
1A
Charger (BQ24780S)
Date: Monday, February 22, 2016 Sheet 29 of 46
5 4 3 2 1
5 4 3 2 1

SYS_SHDN#
(2,28,37) SYS_SHDN#
PR171

30
*short_6

+3VPCU VL 3V_LDO
PR186
(28) SYS_HWPG
10K/F_4
VIN VIN
SYS_SHDN#

10u/6.3V_6

0.1u/25V_4

4.7u/6.3V_6
1
+
PC128 PC140 PC135 PC136 PC139
33u/25V_6x4.5 10u/25V_8 2200p/50V_4 PR179 PR181 PR180 PR183 2200p/50V_4 10u/25V_8

2
*short_4 100K/F_4 *short_4 10K/F_4

PC141

PC142
51225_VIN

PC151
D D

+5VPCU

5
PQ22 +3VPCU
+3VPCU

5
PQ21 AON7410
+5VPCU AON7410 3.3 Volt +/- 5%
5 Volt +/- 5%

13

12
TDC : 5.53A

3
4
TDC : 7A 4
PEAK : 7.4A

VREG5

VREG3
VIN
PEAK : 9.3A 7 6 SYS_SHDN# OCP : 10A

3
2
1
PGOOD EN2
OCP : 12A Width : 240mil

1
2
3
51225_EN1 20 10 51225_DH2
Width : 2800mil EN1 DRVH2 PR178 PC149
PL2 51225_DH1 16 9 51225_VBST2 PL3
2.2uH_7X7X3 PC148 PR177 DRVH1 VBST2 2.2uH_7X7X3
51225_VBST1 17 8 51225_SW2 1/F_6 0.1u/50V_6
VBST1 PU9 SW2
0.1u/50V_6 1/F_6 51225_SW1 18 TPS51225RUKR 11 51225_DL2
SW1 DRVL2

5
PR184 51225_DL1 15 4 51225_FB2 PR188
15.8K/F_4 DRVL1 VFB2 6.49K/F_4
51225_FB1 2 21 PR168
+ PR167 4 VFB1 GND 4 *4.7_6 +
PC127 PC125 *4.7_6 14 22 PC126 PC124
VO1 GND

VCLK
220u/6.3V_6X4.2 0.1u/50V_6 0.1u/50V_6 220u/6.3V_6X4.2

GND

GND

GND

GND
CS1

CS2
PQ23 PQ24

1
2
3

3
2
1
AON7752 AON7752 PC131
PR185 *680p/50V_6 PR189

19

26

25

24

23
10K/F_4 PC130 9.31K/F_4
*680p/50V_6

51225_CS1

51225_CS2
PR192 PR189 change to 9.31K for IR camera

120K/F_4

102K/F_4
*short_6
C
Rds(on)=14.5m ohm C

OCP:10A
Rds(on)=14.5m ohm L(ripple current)
=(9-3.3)*3.3/(2.2u*0.355M*9)
OCP:12A ~2.676A
L(ripple current) Iocp=10-(2.676/2)=8.662A

PR182

PR190
=(9-5)*5/(2.2u*0.3M*9) Vth=(8.662A*14.5mOhm)+1mV=126.599mV
=3.367A R(Ilim)=(126.599mV*8)/10uA
Iocp=12-(3.367/2)=10.316A
Power auto recovery =101.279K
Vth=(10.316A*14.5mOhm)+1mV=150.589mV
R(Ilim)=(150.589mV*8)/10uA 3V_LDO
+3V_LDO_EC
~120.47K +3VPCU PR312 0_6

PR287 *0_6

B B

+5VPCU +5VPCU +3VPCU +3VPCU

PR130 PR129 PR172 PR173


*short_8 *short_8 *short_8 *short_8
TDC : 3.38A TDC : 3.6A TDC : 1.05A TDC : 3.15A
PEAK : 4.5A PEAK : 4.8A PEAK : 1.4A PEAK : 4.2A
Width : 140mil Width : 160mil Width : 60mil Width : 140mil
PC103 PC104 PC143 PC144
1u/25V_4 1u/25V_4 1u/25V_4 1u/25V_4
1

7
+5V_S5 +5V +3V_S5 +3V
VIN1

VIN1

VIN2

VIN2

VIN1

VIN1

VIN2

VIN2
PR128 13 8 PR127 PR169 13 8
*short_8 14 VOUT1 OUT2 9 *short_8 *short_8 14 VOUT1 OUT2 9
VOUT1 OUT2 VOUT1 OUT2
PC97 PC99 PC102 PC98 PC133 PC137 PC138 PC134
10U/6.3V_6 0.1U/16V_4 11 0.1U/16V_4 10U/6.3V_6 10U/6.3V_6 0.1U/16V_4 11 0.1U/16V_4 10U/6.3V_6
PU5 GND PU8 GND
APL3523A 15 APL3523A 15
4 GND 4 GND
+5VPCU VBIAS +5VPCU VBIAS
PR136 *short_4 PC108 PR175 *short_4 PC145

A 0.1U/16V_4 0.1U/16V_4 A
S5_ON 3 5 MAINON S5_ON 3 5 MAINON
(28,37) S5_ON ON1 ON2 ON1 ON2
CT1

CT2

CT1

CT2
PR131 *short_4 PR132 *short_4 MAINON (24,28,33,37) PR174 *short_4 PR176 *short_4

PC106 PC107 PC147 PC146


12

10

12

10

*0.1U/16V_4 *0.1U/16V_4 *0.1U/16V_4 *0.1U/16V_4

PC100 PC101 PC129 PC132


1000P/50V_4 1000P/50V_4 1000P/50V_4 1000P/50V_4

Quanta Computer Inc.


Soft-Start Soft-Start PROJECT : ZRW
Size Document Number Rev
1A
SYSTEM 5V/3V (TPS51225R)
Date: Monday, February 22, 2016 Sheet 30 of 46
5 4 3 2 1
5 4 3 2 1

VIN
31
PU16
8
IN
9

10u/25V_8
2200p/50V_4
*0.1U/25V_4
D IN D

PC81

PC218

PC217
7 22
+5VPCU PR104 NC IN
10_6 24 Fsw=550KHz
+1V_S5
IN
G5335-VCC-1 21
VCC 1.0 Volt +/- 5%
G5335QT2U PR268 PC221 TDC : 6.82A
PC234 73.2K/F_4 *0.01U/50V_4
+3V 10U/6.3V_6 6 G5335-TON-1 PEAK : 9.1A
TON
Width : 280mil
PR275 20 G5335-BST-1 +1V_S5
100K/F_4 BST
PR277 PC235
2.2_6 0.1U/25V_4 PL12
PR276 *short_4G5335-PWRGD-1 1 0.68uH_7X7X3
(28) HWPG_1VS5 PGOOD 10 G5335-LX-1 1 2
+5VPCU LX 11
LX 16
PR98 *0_4 LX 17

22U/6.3V_6

22U/6.3V_6

22U/6.3V_6

22U/6.3V_6

22U/6.3V_6

0.1U/16V_4
*22U/6.3V_6

*22U/6.3V_6
LX 18

PC230

PC222

PC227

PC220

PC224

PC219

PC231

PC233
PR272 *short_4 G5335-PFM-1 3 LX 25
G5335-AGND-1 PFM LX PR99
R1
Pulse-Skipping mode *4.7_6

PR269 PC225
4.99K/F_4 *1000P/50V_4
PC82
C PR274 *short_4 G5335-EN-1 2 *680p/50V_6 C
(28) +1V_S5_ON EN 12
PGND
PC228 13
*0.047U/10V_4 PGND
14
R2
PGND
G5335-AGND-1 15 PR270 Vo=0.8*(R1+R2)/R2
PGND
19
20K/F_4 =1V
G5335-SS-1 23 PGND
SS

4 G5335-AGND-1 G5335-AGND-1
PC232 AGND
0.047U/10V_4

5 G5335-FB-1 VFB=0.8V
G5335-AGND-1 FB

PR273 *short_4

G5335-AGND-1
PR2060 0_4
(33,37) MAIND +1V_S5

B B
VIN TDC : 2.36A
PEAK : 3.14A

5
VIN Width : 100mil
PR2058
VIN +1V_SUS VIN +1V_S5 +VCCIO *1M_6
4
PR2056 PQ35
*1M_6 MDV1528Q
PR79 PR105 PR191 PR2057 PR2059 *0_4

3
2
1
1M_6 22_8 1M_6 *22_8

3
3

+3V

+VCCIO
SUSD 2 2 PC2064
*2200p/50V_4
3
3

3
PQ11 2 PQ2007 PC236
(8) SUS0#
2 AO3404 4 2 *AO3404 *22u/6.3V_6
(8,33) SUSON_R

1
1

2 2 1 PR2055 2
(8,28) SUSB#
*1M_6
+1V_SUS
PR80 PQ10 PQ25 PU20 PQ2009
1

1
PQ7 1M_6 2N7002K 2N7002K *74AHC1G09GW PQ2010 *2N7002K
DTC144EU PC152 *DTC144EU
1

1
*2.2n/50V_4 PC83
22u/6.3V_6 TDC : 0.18A
PEAK : 0.24A
A Width : 20mil 12/28 Change VCCIO design A

ZRW Rev F Add


Quanta Computer Inc.
PROJECT : ZRW
Size Document Number Rev
1A
+1V_S5 (G5335QT2U)
Date: Monday, February 22, 2016 Sheet 31 of 46
5 4 3 2 1
5 4 3 2 1

+3V_S5

PR138
*short_4
+VCCOPC Power only for 2+3e CPU 32
D D

+VCCOPC_3V3
PC109 +VCCOPC
GT3@1u/10V_4 TDC : 4.5A
PEAK : 6A

10
1 Width : 200mil

3V3
VIN VIN

GT3@10u/25V_8

GT3@10u/25V_8

GT3@2200P/50V_4

GT3@0.1U/25V_4
PC122

PC119

PC115

PC117
PR135 PC105 GT3@0.1u/50V_6
9 +VCCOPC_VBST
BST
*short_6 PL1
GT3@0.68uH_7X7X3
8 +VCCOPC_SW R216 GT3@0_8
SW +VCCOPC
PR141 *short_4 +VCCOPC_EN 5
(8,34) VRON_R EN R214 GT3@0_8
+3V_S5 +VCCEOPIO
+VCCOPC_MODE 7 PU6 12 PR146 GT3@10/F_4

GT3@0.1u/16V_4
*100K/F_4

GT3@22uF/6.3V_6

GT3@22uF/6.3V_6

GT3@22uF/6.3V_6
VOUT
MODE GT3@NB681GD-Z

PC96

PC95

PC94

PC93
PR144

GT3@100K/F_4
C C

PR134
R228 2 +VCCOPC_SRC (5)
*GT3@10K_4 PGND

PR133 *short_4 PR137 *short_4 +VCCOPC_LP# 6 3 VCCOPC_VID1_C PR150 *short_4 VCCOPC_VID1


(9) LPM_ZVM_N LP# C1
4 VCCOPC_VID0_C PR147 *short_4 VCCOPC_VID0
C0

AGND
PR149 *short_4 13
(28) HWPG_+VCCOPC PG

PR140 +3V_S5
GT3@100K/F_4

11
PR148

*short_6

R241 R238
GT3@10K_4 *10K_4
+3V 681_AGND (5)
B B
VCCOPC_VID0
VCCOPC_VID1

Mode VR Rail LP# C1 C0 Vo


R240 R242
*10K_4 GT3@10K_4
0 ohm VCCIO 0 X X 0V

Floating PRIMCORE 1 0 0 0.8V(MSM)

100K EDRAM/EOPIO 1 0 1 0.95V


VCCEDRAM
150K Other 1 1 0 1.0V

1 1 1 1.05V
A A

(5) +VCCOPC
Quanta Computer Inc.
(20,23,24,29,30,31,33,34,35,36,37,38,39) VIN
(2,4,6,7,8,9,11,12,13,15,19,20,21,22,23,24,25,26,27,28,30,31,33,34,37,38,39) +3V PROJECT : ZRW
(2,3,4,6,7,8,9,22,24,25,26,28,30,33,38) +3V_S5
Size Document Number Rev
1A
+VCCOPC (NB681GD-Z)
Date: Monday, February 22, 2016 Sheet 32 of 46
5 4 3 2 1
5 4 3 2 1

+3V
33
PR2016
100K/F_4

PR2017 *short_4 (20,23,24,29,30,31,32,34,35,36,37,38,39) VIN


(28) HWPG_VDDR
(27,30,34,35,36,38) +5V_S5
(11,12) +VDDQ_VTT
PR2018 *short_4 (11,12) +VDDQ
D (8,31) SUSON_R D
(3,5,11,12) +1.2VSUS
PC2021
*0.1U/16V_4 Ilimit=9A
+1.2VSUS
PR2019 VIN 1.2 Volt +/- 5%

1P35V_PGOOD
232K/F_4 Fsw=500KHz
(24,28,30,37) MAINON
PR2020 *short_4 TDC : 5A

1P35V_CS
1P35V_S3

1P35V_S5
PC2022 PR2021
PEAK : 6.67A
*0.1U/16V_4 1P35V_TON OCP : 9A

10u/25V_8

10u/25V_8
0.1U/25V_4

2200P/50V_4

0.1U/25V_4
499K/F_4 Width : 200mil

PC2023

PC2027

PC2024

PC2028

PC2025
10

13
7

9
TDC : 0.45A

5
PQ2005 +1.2VSUS

S3

S5

PGOOD

TON
CS
PEAK : 0.6A +VDDQ_VTT AON7410

Width : 20mil 20
VTT 17 1P35V_UGATE 4
2 UGATE
PC2026 VTTSNS PC2029
10U/6.3V_6 18 1P35V_BOOT PR2022
TDC : 0.38A

3
2
1
1 BOOT1 PL2001
VTTGND 2.2_6
PEAK : 0.5A +VDDQ
PU2001 16 1P35V_PHASE
0.1u/50V_6 1uH_7X7X3

Width : 20mil RT8231BGQW PHASE

*330u/2.5V_6X4.2
5
PR2023 4 15 1P35V_LGATE

0.1U/16V_4

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8
VTTREF LGATE +

PC2031

PC2035

PC2032

PC2036

PC2037

PC2033
100/F_4
19 12 1P35V_VDD PR2025
VLDOIN VDD +5V_S5
PC2034 PC2030 PR2024 *short_4 *4.7_6 PR2026
*10U/6.3V_6

0.1U/16V_4 0.033U/10V_4 4 *short_4


PC2038

PC2040
PGND

VDDQ
1U/6.3V_4 PQ2006 PC2039
GND

PAD

3
2
1
VID

AON7752 *680p/50V_6
C
+1.2VSUS FB C
3

11

14

1P35V_S3 PR2027 *0_4 1P35V_S5 21


1P35V_VID

1P35V_FB

PR2028 *short_4
Rds(on)=14.5mohm
PR2029 *0_4 1P35V_S3
(3) DDR_VTTT_PG_CTRL
+5V_S5 1P35V_VDDQ
PR2030 *short_4
PR2032
PR2031 *0_4
7.87K/F_4

VID Ref. Voltage PR2033


10K/F_4
High 0.675V

Low 0.75V
S3 S5 VDDQ VTTREF VTT
OCP=9A
L ripple current S0 1 1 ON ON ON
=(19-1.2)*1.2/(1u*500k*19)
=2.248A S3 (mainon off) 0 1 ON ON OFF
Vtrip=9-(2.248/2)*14.5mohm DDR=1.2V
=114.202mV PR2032=7.87K/F_4
PR2033=10K/F_4 S4/S5 0 0 OFF OFF OFF
Rlimit=114.202mV/5uA*10=228.4Kohm

B B

+2.5VSUS Power Rail For DDR4


10/26 Reserve +2.5V for DDR4 VDDSPD
+2.5V_SUS +2.5V_SUS
+2.5V_SUS (11,12)
2.5Volt +/- 5%
+3V_S5 PR310 0_6 TDC : 0.91A
+3V
PC264
PEAK : 1.21A

3
Width : 40mil
4.7U/6.3V_6
Check PU high with HW PR311
100K/F_4 JP18 +2.5V_SUS MAIND 2
(31,37) MAIND
0.001/F_3720
4

PU19 PQ40
*AO3404
VIN

(28) HWPG_2.5V PL15


PR309 0_4 5 3 G5719LX2.5V +2.5V_SUS_SRC 1 2

1
PG LX 2.2uH/1.85A_2.5X2X1.2

+2.5V
SUSON_R PR304 *0_4 PR306 10K_4 1 2 PR303 0_4
EN GND
+2.5V (11,12,37)
PC260 PC261 PC262
FB

PC263
10U/6.3V_6

0.1U/16V_4
*10U/6.3V_6

PR305 0_4 G5719BTB1U


TDC : 0.16A
0.47uF/6.3V_4

(28) DDR4_SUSON_2V5
6

R1
PR307 PEAK : 0.21A
47.5K/F_4 Width : 20mil
PR308
R2 15K/F_4

A
Vo=(0.6(R1+R2)/R2) A

Quanta Computer Inc.


PROJECT : ZRW
Size Document Number Rev
1A
DDR4_+1.2VSUS (G5316RZ1D)
Date: Monday, February 22, 2016 Sheet 33 of 46
5 4 3 2 1
5 4 3 2 1

Check PU high with HW


GT2 : PR217 Unstuff
GT2 : PR34 CS00002JB38 0 ohm
GT2 : PC26 Unstuff
GT3 : PR217 CS41003F932 100K
GT3 : PR34 Unstuff
GT3 : PC26 CH3224K1B01 0.022U/25V
34
GT2 : PC27 Unstuff GT3 : PC27 CH3224K1B01 0.022U/25V
GT2 : PR224 CS38872FB18 88.7K +1V_VCCST
GT3 : PR224 CS39312FB15 93.1K SVID near PU1 +5V_S5 GT2 : PR220 CS12672FB02 267 ohm GT3 : PR220 CS13242FB07 324 ohm

1000P/50V_4
GT2 : PC29 CH31004KB17 0.01uF/25V GT3 : PC29 CH3473K1B00 47nF/25V

PC43
PR224 88.7K/F_4
ZRW REV:F add 1000p PR53 PR57 VIN
45.3/F_4
GT2 : PC30 CH41002KB93 0.1uF/10V GT3 : PC30 CH4152K9B02 0.15uF/10V
100/F_4
GT2 : PR224 CS38872FB18 88.7K GT3 : PR224 CS39312FB15 93.1K
IMVP8 Vcore Controller

1/F_6
D D
PC34 330P/50V_4 Close to PR56 10_4 ISL95857_SDA

PR236 *short_8
(5) H_CPU_SVIDDAT GT2 : PR232 CS37872FB15 78.7k GT3 : PR232 CS38872FB18 88.7k
VCCGT MOS
PR262
(5) VR_SVID_ALERT#_VCORE GT2 : PR239 CS41622FB11 162k GT3 : PR239 CS41402FB14 140k CQ1A

PR234
12/11 Change to 13.7K PR249 13.7K/F_4 PR52 49.9/F_4 ISL95857_SCLK
GT2 : PR230 CS38872FB18 88.7K
470K_4_4700NTC
(5) H_CPU_SVIDCLK

GT2 : PR225 CS21912FB13 1.91K


GT3 : PR230 CS39312FB15 93.1K
GT3 : PR225 CS22552FB01 2.55K
Rail A(1 phase):VCORE
PR260 27.4K/F_4 GT2 : PR243 CS12492FB12 249
PC33 33P/50V_4
+3V +VCCIO

GT2 : PR233 CS21372FB19 1.37K


GT3 : PR243 CS12742FB02 274
GT3 : PR230 CS21542FB00 1.54K
Rail B(2 phase):VCCGT
GT2 : PR225 CS21912FB13 1.91K
PR223
Rail C(1 phase):VCCSA

PR47
PC169

PR49
10K/F_4
GT3 : PR225 CS22552FB01 2.55K

*10K/F_4
3300P/50V_4 3K/F_4 PC55 PR77
PR48 *short_4
ISL95857_VR_HOT
(2,28,29) H_PROCHOT#

2K/F_4

0.1u/25V_4

0.1u/25V_4
63.4K/F_4

78.7K/F_4
PR35

PR36
PR46 *short_4

PR235

PR232

PC48

PC45
2200p/50V_4 1K/F_4

1K/F_4
ISL95857_VR_READY

ISL95857_PROG1

ISL95857_PROG2
(2) IMVP_PWRGD

ISL95857_VCC
+VCCGT

ISL95857_VIN
Close to

1.91K/F_4
PR225
PR238 VCCSA Choke
PR43 *short_4
ISL95857_VR_EN ISUMN_C (36)
(8,32) VRON_R
PC22

220p/50V_4

470P/50V_4
PC23

PC24
PR95 475/F_4

PR44
*10_4

*10K/F_4
no stuff *0.01U/50V_4 PR264
(29) PMON

40

39

38

37

36

35

34

33

32

31
10K/F_4_3435NTC
GT2 : PR232 CS37872FB15 78.7k

1
0.1u/25V_4

0.015UF/16V_4
VCC

VIN
VR_HOT#

ALERT#

PROG1

PROG2
VR_ENABLE

VR_READY

SCLK

SDA

2
PC64

PC52
+3V GT3 : PR232 CS38872FB18 88.7k
(5) VCCGT_SENSE PR94 *short_4 PR37 PC60 PR75
PC31 *short_4 Rail C 0.047U/10V_4 11K/F_4

1
(5) VSSGT_SENSE PR90 *short_4 *0.01U/50V_4

2
ISL95857_PSYS 1 30 ISL95857_PWM_C PR65 *short_4 PR78
PSYS PWM_C PWM_C (36)
C 2.61K/F_4 C
ISL95857_IMON_B 2 29 ISL95857_FCCM_C PR68 *short_4
IMON_B FCCM_C FCCM_C (36)

2
ISL95857_NTC_B 3 28 ISL95857_ISUMN_C
NTC_B ISUMN_C
PR91 PC32 ISL95857_COMP_B 4 27
no stuff *10_4 COMP_B ISUMP_C ISUMP_C (36)
PU2
ISL95857_FB_B 5 26 ISL95857_RTN_C
0.01U/50V_4 FB_B RTN_C
GT2 : PC30 CH41002KB93 0.1uF/10V ISL95859HRTZ-T
ISL95857_RTN_B 6 25 ISL95857_FB_C
RTN_B FB_C
GT3 : PC30 CH4152K9B02 0.15uF/10V 7 24 ISL95857_COMP_C
(35) ISUMP_B ISUMP_B COMP_C
8 23

PR73

301/F_4
ISL95857_ISUMN_B ISL95857_IMON_C
ISUMN_B IMON_C

PR240

2.49K/F_4

2.05K/F_4
9 22 ISL95857_PWM_A

330P/50V_4

33P/50V_4

*2K/F_4
ISEN1_B PWM_A
2

2.61K/F_4

10 21 +VCCSA
PR222

PR241
ISL95857_FCCM_A
ISEN2_B FCCM_A
PC65
2

PR27 PC28

1000P/50V_4
0.01u/50V_4

ISUMN_A
0.1U/25V_4

ISUMP_A
PWM1_B

PWM2_B

COMP_A
FCCM_B
1

IMON_A

162K_4
41
PR221

PC30

PC29

PR239

PC63
11K/F_4

NTC_A

RTN_A
1

EP

FB_A
PR92

2200P/50V_4
1K/F_4 2200P/50V_4 Rail A *0.01U/50V_4

*680P/50V_4
*10_4 no stuff
2

PC56

PC57

PR76
1

PC184

PC185
PR265

11

12

13

14

15

16

17

18

19

20
10K/F_4_3435NTC PR72 *short_4
Close to PWM_A (35)
VCCGT Choke PR71 *short_4

ISL95857_ISUMN_A
ISL95857_PWM1_B

ISL95857_PWM2_B

ISL95857_COMP_A
FCCM_A (35)

ISL95857_FCCM_B
PR220

ISL95857_IMON_A

ISL95857_NTC_A

ISL95857_RTN_A
PR93 *short_4

ISL95857_FB_A
(35) ISUMN_B VSA_SENSE (5)
PC58
267/F_4 GT2 : PR239 CS41622FB11 162k *0.01U/50V_4 PR89 *short_4 VSASS_SENSE (5)
PC62 PR74
GT3 : PR239 CS41402FB14 140k
PC21 PC27 *0.022U/25V_4 2200p/50V_4 1K/F_4
0.1U/25V_4 ISEN1_B (35)
GT2 : PR243 CS12492FB12 249 PC59
PR88
B
GT3 : PR243 CS12742FB02 274 Close to B
PC26 *0.022U/25V_4 ISEN2_B (35) PR243 Vcore Choke *10_4 no stuff
ISUMN_A (35)
GT2 : PC29 CH31004KB17 0.01uF/25V PR34 0_4 +5V_S5 0.01U/50V_4
249/F_4
GT3 : PC29 CH3473K1B00 47nF/25V
PR266

0.1u/25V_4
PC61
(35) FCCM_B PR38 *short_4 10K/F_4_3435NTC

1
PR42 *short_4

0.1u/25V_4
GT2 : PR220 CS12672FB02 267 ohm (35) PWM1_B

2
PC54
PR70
GT3 : PR220 CS13572FB10 357 ohm (35) PWM2_B PR45 *short_4 PC53 11K/F_4

1
0.022U/25V_4

1
PR69

2
2.61K/F_4

Rail B

470K_4_4700NTC

2
PR55
2K/F_4

499/F_4
Skylake-U U23e 15W/28W
ISUMP_A (35)

PR58
27.4K/F_4

1.37K/F_4
4.87K/F_4
PR231
(1+2+1+1 Phase)
330P/50V_4

VCCGTU merge to VCCGT


+VCCCORE
PC47

1000P/50V_4
PR261

PR263

PR233

PC44
88.7K/F_4

33P/50V_4
PR230

2200p/50V_4

470P/50V_4
VCORE VCCGT VCCSA VCCGTU *0.01u/50V_4 PR60
*10_4 no stuff
PC40

13.7K/F_4

Close to
Icc TDC PL2:23A Icc TDC PL2:40A Icc TDC PL2:6A VCORE MOS
PR63 *short_4
Icc Max:32A Icc Max:64A Icc Max:7A VCORE_SENSE (5)
PR250

PC41

PC177

PC42

PC49 PR66 *short_4


*0.01u/50V_4 VCORESS_SENSE (5)
A
OCP:35A OCP:A OCP:8A A

12/11 Change to 13.7K


Fsw:800KHz Fsw:800KHz Fsw:800KHz GT2 : PR233 CS21372FB19 1.37K PC50
PR67
GT3 : PR230 CS21542FB00 1.54K *10_4 no stuff
VCORE L/L: VCCGT L/L: VCCSA L/L: GT2 : PR230 CS38872FB18 88.7K 0.01u/50V_4
GT3 : PR230 CS38662FB16 86.6K
R_DC_LL:2.1mV/A R_DC_LL:2mV/A R_DC_LL:10.3mV/A Quanta Computer Inc.
PROJECT : ZRW
R_AC_LL:2.1mV/A R_AC_LL:2mV/A R_AC_LL:10.3mV/A Size Document Number Rev
1A
CPU_CORE (ISL95859HRTZ-T)
Date: Monday, February 22, 2016 Sheet 34 of 46
5 4 3 2 1
5 4 3 2 1

35
GT2 : PR19 Unstuff GT3 : PR19 CS41003F932 100K

VCORE
D
PR82
VIN VCORE D

*short_6

33U/25V_6x4.5
1
Icc TDC PL2:23A

10u/25V_8

10u/25V_8

0.1U/50V_6

2200P/50V_4
+5V_S5
+

PC71

PC74
PC195

PC199

PC182
4.7U/6.3V_6 PU15 AOZ5049QI
PC191

Icc Max:29A

2
6
VCORE_VCC 23 VIN 22
24 PVCC VIN
VCC OCP:35A
Rail A GH
4
3 VCORE_VBST +VCCCORE Fsw:800KHz
PR258 *short_4 1 BOOT PR253 *short_6
(34) PWM_A PWM
PR259 *short_4 2 PC190
(34) FCCM_A FCCM 0.1u/50V_6 PL10 VCORE L/L:
5 0.15uH_7X7X4
VSWH 13 VCORE_PHASE 1 2 DCR=0.66mOhm
VSWH R_DC_LL:2.1mV/A

PGND

PGND
19

4
GL 20
GL PR87 + +
2.2/F_6 R_AC_LL:2.1mV/A

330u/2V_7343

330u/2V_7343
21

0.1u/16V_4

22u/6.3V_8

22u/6.3V_8

PC78
PC205

PC208

PC210

PC203
PC77
1000P/50V_4

(34) ISUMP_A PR245 3.65K/F_6

(34) ISUMN_A
PR244 1/F_6

C
VCCGT C

PR84
*short_6
+5V_S5 VIN
4.7U/6.3V_6

33U/25V_6x4.5
1
PC196

10u/25V_8

10u/25V_8

0.1U/50V_6

2200P/50V_4
PU14 AOZ5049QI +
PC73

PC198

PC193

PC197

PC181
6
VCCGT_VCC1 23 VIN 22
VCCGT

2
24 PVCC VIN
VCC
Rail B
GH
4
+VCCGT
Icc TDC PL2:40A
3 VCCGT_VBST1
PR256 *short_4 1 BOOT PR252 *short_6
(34) PWM1_B PWM Icc Max:64A
PR257 *short_4 2 PC189
(34) FCCM_B FCCM 0.1u/50V_6 PL9
5 0.15uH_7X7X4 OCP:A
VSWH
VSWH
13 VCCGT_PHASE1 1 2 DCR=0.66mOhm
Fsw:800KHz
PGND

PGND

19

0.1u/16V_4

22u/6.3V_8

22u/6.3V_8

330u/2V_7343
3

4
GL 20 +

PC211

PC212

PC213

PC209
GL
PR86
VCCGT L/L:
21

2.2/F_6

PC76 R_DC_LL:2mV/A
1000P/50V_4

R_AC_LL:2mV/A
(34) ISUMP_B PR216 3.65K/F_6

ISEN1_B PR217 GT3@100K/F_6

PR218 *100K/F_4
VCCGT = 1 phase for U22 , 不不不 (34) ISUMN_B
PR212 10/F_6 ISEN2_B (34)

B
VCCGT = 2 phase for U23e , 不不 2015/10/2 FAE Suggestion
B

PR83 VIN
*short_6
+5V_S5
GT3@4.7U/6.3V_6

PU13 GT3@AOZ5049QI
PC192

GT3@10u/25V_8

GT3@10u/25V_8

GT3@2200P/50V_4
GT3@0.1U/50V_6

6
PC70

PC69

PC72
PC194

VCCGT_VCC2 23 VIN 22
24 PVCC VIN
VCC

Rail B GH
4
3 VCCGT_VBST2 +VCCGT
PR254 *short_4 1 BOOT PR251 *short_6
(34) PWM2_B PWM
FCCM_B PR255 *short_4 2 PC188
FCCM GT3@0.1u/50V_6 PL8
5 GT3@0.15uH_7X7X4
VSWH
VSWH
13 VCCGT_PHASE2 1 2 DCR=0.66mOhm
PGND

PGND

19
GT3@0.1u/16V_4

GT3@22u/6.3V_8

GT3@22u/6.3V_8
3

GT3@330u/2V_7343

GL 20 PR85 +
PC214

PC216

PC215

PC207

GL GT3@2.2/F_6
21

PC75
GT3@1000P/50V_4

ISUMP_B PR215 GT3@3.65K/F_6

ISEN2_B PR214 GT3@100K/F_6

A ISUMN_B PR219 *100K/F_4 A


PR213 GT3@10/F_6 ISEN1_B (34)

2015/10/2 FAE Suggestion

(5,34) +VCCCORE

(20,23,24,29,30,31,32,33,34,36,37,38,39) VIN

(5,34) +VCCGT

(27,30,33,34,36,38) +5V_S5
Quanta Computer Inc.
PROJECT : ZRW
Size Document Number Rev
1A
VCORE/VCCGT (ISL95808HRZ-T)
Date: Monday, February 22, 2016 Sheet 35 of 46
5 4 3 2 1
5 4 3 2 1

36
D

VCCSA D

PR64
*short_6
+5V_S5
VIN
4.7U/6.3V_6

VCCSA
PC180

10u/25V_8

10u/25V_8

2200P/50V_4
PQ32

0.1U/50V_6
PC186

PC66

PC187

PC67
AON7410

5
ISL95808
PU12
Icc TDC PL2:5A
UGATE 1 VCCSA_DRVH
Rail C VCCSA_VCC 6 VCC
4 Icc Max:5A
PR242 *short_4 7
C (34) FCCM_C FCCM
BOOT 2 VCCSA_VBST OCP:6A C

3
2
1
PR237 *short_4 3 PWM PR246 *short_6 +VCCSA
(34) PWM_C
Fsw:800KHz
PC183 PL7
0.1u/50V_6 0.47uH_7X7x3
PHASE 8 VCCSA_SW 1 2 DCR=4.2mOhm
VCCSA L/L:

0.1u/16V_4

22u/6.3V_8

22u/6.3V_8
3

4
5

PC202

PC204

PC206
R_DC_LL:10.3mV/A
PR81
9 E_PAD LGATE 5 VCCSA_DRVL 2.2/F_6
4 4
GND
R_AC_LL:10.3mV/A
PC68

3
2
1
PQ31 1000P/50V_4
AON7752

B B
(34) ISUMP_C PR248 3.65K/F_6

(34) ISUMN_C
PR247 1/F_6

(5,34) +VCCSA
(20,23,24,29,30,31,32,33,34,35,37,38,39) VIN
(27,30,33,34,35,38) +5V_S5

A A

Quanta Computer Inc.


PROJECT : ZRW
Size Document Number Rev
1A
VCCSA (ISL95808HRZ-T)
Date: Monday, February 22, 2016 Sheet 36 of 46
5 4 3 2 1
5 4 3 2 1

37
+5VPCU +5VPCU

Check PU high with HW Check PU high with HW


PR113 PR143
*short_4 *short_4
PR107 100K_4 +3V PR155 100K_4 +3V
D PC150 1u/6.3V_4 PU3 PC153 1u/6.3V_4 PU7 D
YB1282PSP8 YB1282PSP8
PC89 *1u/10V_4 4 1 PC110 *1u/10V_4 4 1
VPP PGOOD HWPG_1.8VS5 (28) VPP PGOOD HWPG_1.5V (28)
S5_ON 2 6 +1.8V_S5 MAINON 2 6 +1.5V
(28,30) S5_ON VEN VO (24,28,30,33) MAINON VEN VO
PR282 *short_4 PR110 *short_8 PR156 *short_4 PR145 *short_8
3 3
+3VPCU VIN +3VPCU VIN
PR112 *short_8 8 PR109 PR151 *short_8 8 PR152
GND R1 GND R1

ADJ

ADJ
9 5 43.2K/F_4 9 5 30K/F_4
GND NC GND NC
PR281 PC87 +1.8V_S5 PR154 PC111 +1.5V

7
100K_4 10u/6.3V_6 1.8Volt +/- 5% 100K_4 10u/6.3V_6 1.5Volt +/- 5%
VFB=0.8V TDC : 0.08A VFB=0.8V TDC : 0.49A
PR108 PR153
PC88 PC86 PC85 34K/F_4 PEAK : 0.06A PC112 PC113 PC123 34K/F_4 PEAK : 0.66A
10u/6.3V_6 0.1u/50V_6 *0.1u/50V_6 R2 Width : 20mil 10u/6.3V_6 0.1u/50V_6 *0.1u/50V_6 R2 Width : 20mil

Vo =0.8(1+R1/R2) Vo =0.8(1+R1/R2)
=1.8V =1.5V

PR153 Change to
C 220 ohm for bo bo C
sound issue.
VIN
VIN +3V +5V +VCCIO +2.5V VIN
Thermal protection
PD5 PR116 PR106 PR126 PR111 PR298 PR59
DA2J10100L 1M_6 *22_8 *220_8 22_8 *22_8 1M_6
Need fine tune
for thermal protect point MAINON_ON_G MAIND
MAIND (31,33)
Note placement position

3
3
TEMP=85C
PR119 PR118
1M_6 1 MAINON 2 PQ16 1M_6 2 2 2 2 2
DTC144EU PC51
PQ17 PQ12 PQ19 PQ14 PQ41 PQ6 2200p/50V_4
AO3409 *2N7002K *2N7002K 2N7002K *2N7002K 2N7002K

1
2 PR120

1
*100K/F_6
ZRW Rev:D Stuff
3

S5_ON 2

PQ18 PR283
1

DTC144EU *short_6

B VL VL B

SYS_SHDN# (2,28,30)

PR114 PC91 PR284


PR117 200K/F_4 0.1u/50V_6 200K_6
3

1.47K/F_4
8

PR267
10K/F_4_3435NTC 2.469V 3
+ 1 2
LM393_PIN2 2
- PQ15
3

PU4A 2N7002K
4

AS393MTR-E1 PC92
1

0.1u/50V_6
S5_ON 2
PR115
PQ20 200K/F_4
2N7002K
1

5
+ 7
6
-
PU4B
A AS393MTR-E1 A

For EC control thermal protection (output 3.3V)

Quanta Computer Inc.


PROJECT : ZRW
Size Document Number Rev
1A
+1.8V/+1.5V/Thermal Protect
Date: Monday, February 22, 2016 Sheet 37 of 46
5 4 3 2 1
5 4 3 2 1

+5V_S5
38
PR157
*short_6

D
Double Check OCP SETTING VIN
D

EV@10u/25V_8

EV@10u/25V_8
EV@2200p/50V_4

EV@0.1u/50V_6

*EV@33U/25V_6x4.5
PR285

18 1658R-PVCC
EV@2.2/F_6 +

PC121

PC118

PC248

PC246

PC243
1
1658R-EN 1658R-VREF PR293 EV@6.81K/F_4 PR160 EV@12.4K/F_4 1658R-BOOT1
PC249

2
EV@1U/10V_4

2
PC258 *EV@0.01U/50V_4 PC250

5
PR162 1 2 EV@0.22u/25V_6
EV@100K/F_4 PU18
PR299 1 1658R-BOOT1

PVCC
VIN PR302 *EV@1/F_4 1658R-OCS/CB 9 BOOT1 1658R-UGATE1 4 PQ39
OCS/CB 2 1658R-UGATE1 EV@AON6414AL
PR161 *EV@0_4 *EV@499K/F_4 UGATE1
(4) VGPU_EN

1
2
3
20 1658R-PHASE1 PL14
PR289 *short_4 1658R-EN 3 PHASE1 EV@0.24uH_7X7X3
(15,39) 3V_MAIN_PWGD EN 19
DCR=1.1m ohm
1658R-LGATE1 1658R-PHASE1 +VGPU_CORE
LGATE1
DGPU_PSI PR290 *short_4 1658R-PSI 4
(16) DGPU_PSI PSI

5
EV@UP1658RQKF PR139
EV@2.2/F_6
PWM-VID PR291 *short_4 1658R-VID 5 15 1658R-BOOT2 +

EV@330u/2V_7343
(16) PWM-VID VID BOOT2 1658R-LGATE1 4

EV@0.1u/16V_4

EV@10u/6.3V_8
14 1658R-UGATE2

PC90

PC238

PC240
1 2 1658R-VREF 8 UGATE2

1
2
3
PC256 EV@1U/10V_4 VREF 16 1658R-PHASE2 PQ37 PC114
PHASE2 EV@AON6752 EV@1000p/50V_4
1658R-REFADJ 6 17 1658R-LGATE2
Check PU high with HW REFADJ LGATE2 1 2
+3V
PR158 EV@10K_4
7
C
+3V_S5 +3VPCU R1 PR166 REFIN 13 1658R-PG
C

PR297 EV@20K/F_4
R2 PGOOD PR288 *short_4 GPU_PWR_GD (13)

1658R-REFIN

*EV@0.01U/50V_4
EV@20K/F_4 12 1658R-COMP

PC255
COMP

GND

EV@4700P/25V_4
PR165 PR163 10

FB
FBRTN

1
*EV@10K_4 *EV@10K_4 VIN

PC253
1

PR286

11

21
DGPU_PSI PR164 EV@2.2/F_6
C R3

EV@22P/50V_4
2
PC257 EV@2K/F_4 1658R-BOOT2

1658R-FBRTN
2

1
EV@2700P/50V_4

PC252
EV@16K/F_6

EV@10u/25V_8

EV@10u/25V_8
EV@2200p/50V_4

EV@0.1u/50V_6
1658R-FB
PR159 PC251

PR294

PC120

PC244

PC245

PC247
2

5
*EV@0_4 EV@0.22u/25V_6

1658R-UGATE2 4
PR296
EV@18.2K/F_4
R4

1
2
3
Phase Number of Operation PQ38 PL13
*EV@22P/50V_4
1

EV@AON6414AL EV@0.24uH_7X7X3 DCR=1.1m ohm

PR292

PR295
*short_4

*short_4
PR301 1658R-PHASE2
PC254

+VGPU_CORE
*EV@5.1K/F_4
2

PR300

5
*short_4 PR142
PWM-SVID : Config B R5 EV@2.2/F_6 + +

EV@330u/2.5V_6X4.2
Check PWM-SVID by SKU

EV@330u/2V_7343
3

1658R-LGATE2 4

EV@10u/6.3V_8
EV@0.1u/16V_4

PC242

PC239
PC241

PC237
1
2
3
B B
2 PQ36 PC116
PQ42 EV@AON6752 EV@1000p/50V_4
*EV@2N7002K
1

Standby PC259
1

Function *EV@1U/10V_4
2

+VGPU_CORE

PR125
*EV@100_4
N16S-GT (23W/GDDR5)
OpenVR Config:B
PR123 *short_4
(13) VGA_VCCSENSE

(13) VGA_VSSSENSE PR122 *short_4 +VGPU_CORE


Countinue current:26.5A
PR124
*EV@100_4
Peak current:53A
Parallel OCP:72A
A
FSW:300KHz A

L/L=0mV/A

Quanta Computer Inc.


PROJECT : ZRW
Size Document Number Rev
1A
+VGPU_CORE(UP1658RQKF)
Date: Monday, February 22, 2016 Sheet 38 of 46
5 4 3 2 1
5 4 3 2 1

(13,14,15)
(13,15,16,28)
+1.05V_GFX
+3V_GFX
39
(14,18) +1.35V_GFX

+1.05V_GFX
+3V
TDC : 1.58A
D PEAK : 2.1A D

Width : 80mil
PR62
*EV@100K/F_4 PC39 PR51
PR54 +1.05V_GFX
TP2 *EV@0_4 *EV@2200P/50V_4 *EV@2.2_6
HWPG_1.05VGFX 554PG_0.95V PU11
PL6
4 1 554LX_0.95V
PG NC EV@1uH_7X7X3 554FB_0.95V_S

EV@0.1U/16V_4

EV@22U/6.3V_6
+3VPCU 9 2 PR229 *short_4
PVIN LX PC171

PC175

PC174
10 3 *EV@22P/50V_4
PVIN LX PR226
7 554NC_0.95V PC176
R1 EV@7.5K/F_4
NC *EV@68P/50V_4
PR61
554SVIN_0.95V 8 6 554FB_0.95V
EV@10_6 SVIN FB
EV@10U/6.3V_6
EV@0.01U/50V_4

11 5 554EN_0.95V
EV@1U/6.3V_4 GND EN PR228
PC178

PC179

PR227
R2 EV@10K/F_4 Vo=0.6*(R1+R2)/R2
PC46

EV@RT8068AZQW *short_4

PC173
*EV@0.1u/16V_4 3V_MAIN_PWGD
3V_MAIN_PWGD (15,38)

C VIN +3V_GFX VIN +3VPCU C

PR21 PR121 PR24

3
EV@1M_6 EV@22_8 EV@1M_6

DGPU_D 2

3
3

PR50 PQ13
*short_4 PR20 EV@AO3404
+3V_GFX

1
2 EV@1M_6 2 2 +3V_GFX
(4) DGPU_PWR_EN PC84 TDC : 0.05A
1

PQ3 PQ5 *EV@2.2n/50V_4


PQ4 EV@2N7002K EV@2N7002K PEAK : 0.06A
1

PC38 PR41 EV@PDTC143TT


Width : 20mil
1

1
*EV@1u/10V_4 EV@100K_4
2

+1.35V_GFX for GDDR5

VIN

PU2003
8
IN
9

EV@10u/25V_8
EV@2200p/50V_4
*EV@0.1U/25V_4
IN

PC2046

PC2047

PC2048
7 22
+5VPCU PR2043 NC IN
EV@10_6 24 Fsw=550KHz
+1.35V_GFX
B IN B
G5335-VCC 21
VCC 1.35 Volt +/- 5%
EV@G5335QT2U PR2044 PC2050 TDC : 4.67A
PC2049 EV@73.2K/F_4 *EV@0.01U/50V_4
+3V EV@10U/6.3V_6 6 G5335-TON
PEAK : 6.22A
TON
Width : 200mil
PR2045 20 G5335-BST +1.35V_GFX
EV@100K/F_4 BST
PR2046 PC2051
EV@2.2_6 EV@0.1U/25V_4 PL2003
(15) HWPG_1.35VGFX PR2047 *short_4 G5335-PWRGD 1 EV@0.68uH_7X7X3
PGOOD 10 G5335-LX 1 2
+5VPCU LX 11
LX 16
PR2048 *EV@0_4 LX 17
EV@22U/6.3V_6

EV@22U/6.3V_6
EV@22U/6.3V_6

EV@22U/6.3V_6

EV@22U/6.3V_6

EV@0.1U/16V_4
*EV@22U/6.3V_6

*EV@22U/6.3V_6
LX 18
PC2052

PC2055
PC2053

PC2054

PC2056

PC2057

PC2058

PC2059
PR2049 *short_4 G5335-PFM 3 LX 25
G5335-AGND PFM LX PR2050
R1
Pulse-Skipping mode *EV@4.7_6

PR2051 PC2060
EV@14K/F_4 *EV@1000P/50V_4
PC2061
PR2052 *short_4 G5335-EN 2 *EV@680p/50V_6
(13) FBVDDQ_EN EN 12
PGND
PC2062 13
*EV@0.047U/10V_4 PGND
14
R2
PGND
G5335-AGND 15 PR2053 Vo=0.8*(R1+R2)/R2
PGND
19
EV@20K/F_4 =1.35V
G5335-SS 23 PGND
SS
A A
4 G5335-AGND
AGND G5335-AGND
PC2063
EV@0.047U/10V_4

5 G5335-FB VFB=0.8V
G5335-AGND FB

PR2054 *short_4
Quanta Computer Inc.
G5335-AGND PROJECT : ZRW
Size Document Number Rev
1A
+1.35V_GFX/+1.05V_GFX/+3V_GFX
Date: Monday, February 22, 2016 Sheet 39 of 46
5 4 3 2 1
1 2 3 4 5 6 7 8

VGA power up sequence


40
+3VPCU
SKYLAKE
PCH +3V_MAIN
MOSFET +3V_GFX
DGPU_PWR_EN
GPP_B17 MOSFET
A A
3V_MAIN_EN (GPU GPIO5)
3V_MAIN_PWGD
PG All 3.3V

t>0
NVVDD

PXE_VDD
+1.05V
+1.05V_S5 t>0
FBVDDQ

MOSFET +1.05V_GFX N15x Power on sequance


3V_MAIN_PWGD Notes: -All 3.3V includes all rails powered at 3.3V
-PEX_VDD 1.05V inculdes all rails that are shared

PWM-VID (GPU GPIO11)

VIN
B
+VGPU_CORE B

3V_MAIN_PWGD VIN +1.35V_GFX


PWM
PWM
VGPU_PWRGD
OR FBVDDQ_EN HWPG_1.5VGFX
Gate DGPU_PWROK
VGPU_PWRGD

EC_FB_CLAMP(EC)

GC6_FB_EN (GPU GPIO0 )

C C

GPP_B19

VGA Reset

PLTRST#
PEGX_RST#
PCH DGPU_HOLD_RST#

PEX_RST timing
D D

I/O 3.3V

PEX_RST

Trise >= 1uS Tfail <=500nS Quanta Computer Inc.


PROJECT : ZRW
Size Document Number Rev
1A
GPU PWR CRL
Date: Monday, February 22, 2016 Sheet 40 of 46
1 2 3 4 5 6 7 8
5 4 3 2 1

Battery Mode
Non Deep Sx
3
+3VPCU
VIN 1
+5VPCU

VL
3
1
VIN BAT-V
41
5V_LDO 3V/5V 2
11 2 VR
3 +5VPCU +5V_S5
+15V
CHARGER Battery

EN2

EN1
D
+3VPCU S5 PWR +3V_S5 10 4 D

3
3
S5_ON 8 NBSWON# +3VPCU or +3V_S5

1 VIN Delay DSW power well 10ms DSW PWR


+1V_S5
PWR 6 DPWROK DPWROK
VCCPRIM PWR
DDR VDDQ +1.2VSUS 18 BTN 13 RSMRST# +1V_S5
RSMRST#
VR 7 14 ACPRESENT VCCMPHY PWR
+VDDQ 19 EC ACPRESENT +1.8V_S5
30 DNBSWON#
15 PWRBTN#
HWPG SUSC# 16 SPI PWR
+VDDQ_VTT 23 SLP_S4# V1_MPHY
SUSB# 20 SLP_S3#
HSIO PWR
PCH_SUSACK# SUSACK V1_MPHY
HWPG_VDDR 24
PG PCH_SUSPWARN# SUSWRAN
PLL PWR
S5

S3

PCH_SLP_SUS# SLP_SUS# +1V_S5

31a
VCCST_PWRGD PCH
DDR_VTTT_PG_CTRL VCCST_PWRGD CORE PWR
C
21 31b PCH_PWROK
+1V_S5 C

MAINON
22 31C EC_PWROK PCH_PWROK VCCSRAM PWR
PCH_CLK +1.5V
35
SUSON PLTRST# HDA PWR

VRON

SUSON

S5_ON
MAINON
EC_PWROK

+1V_S5_ON
PLTRST#
17 38 VCCPGPPA PWR +3V_S5
+3VPCU 24 HWPG_VDDR IMVP_PWRGD VCCPGPPB PWR
3 36 SYS_PWROK VCCPGPPC PWR
SYS_PWROK VCCPGPPD PWR
26 HWPG_1V_S5 EC_PWROK VCCPGPPE PWR
+1.5V 12 31C
VCCPGPPG PWR
VCCPGPPF PWR
1.5V +1.8V_S5
HWPG_1.5V 31C 32b 21 17 9 8
VR

PLTRST#
29 29 38
HWPG_1.5V
PG
EN

+VCCIN

MAINON CORE PWR


21 +1.2VSUS

RESET#
CPU
VDDQ PWR
+1V_VCCST
RUN PWR +1VSUS
+1V_VCCST PROCPWRGD
B
3 +5VPCU +5V 28 VCCST PWR B

MOS1

SM_PG_CNTL1

VCCST_PWRGD
0 ohm
3 +3VPCU +3V 27

VR_READY
MOS2

VR_EN
EC_PWROK 10K ohm

SVID
9 +1V_S5 +VCCIO 31C
MOS3 29
G

HWPG_1VS5
1 VIN 12
MAINON 33

VRON
DDR_PG_CTRL
21 +VCC_CORE

IMVP_PWRGD
VCCST_PWRGD_EN
SVID
PCH_PWROK VCCST_PWRGD_EN
IMVP +VCCSA 33 31b
VIN
1 9 VR +VCCGT
33 SYS_PWROK
+1V_S5 36
+1V_S5
VR 34 HWPG+1ms
12 IMVP_PWRGD 37 22 34 32a
HWPG_1VS5 PG
EN

PG
EN

A A

8 SVID VRON 32a


+1V_S5
37

CPU Quanta Computer Inc.


PROJECT : ZRW
Size Document Number Rev
1A
Power Sequence
Date: Monday, February 22, 2016 Sheet 41 of 46
5 4 3 2 1
5 4 3 2 1

Skylake U Non-Deep Sx Platform


42
Power on sequence
D D

C C

B B

A A

Quanta Computer Inc.


PROJECT : ZRW
Size Document Number Rev
1A
Power on Sequence
Date: Monday, February 22, 2016 Sheet 42 of 46
5 4 3 2 1
5 4 3 2 1

實實實defult
虛實實reserve

SYS_HWPG S5D
MDV1528Q +5V_S5

PWRGD
VGPU_PWRGD
43
VIN Vin
VGPU Core Vout
+VGPU_CORE
up1658
5V_LDO PWRGD
+5VPCU MDV1528Q +5V EN
D
PWR EN1 5V S5_Vout
D
3V_MAIN_PWGD
TPS51225
MAIND

3V_LDO 3V
EN1
HWPG_1.5VGFX
Vin S3_Vout +3VPCU AO3404 +3V_S5
VIN PWRGD
S5D
VIN Vin
+1.5V_GFX Vout
NB671GQ-Z
+1.5V_GFX
EN
MDV1528Q +3V FBVDDQ_EN

MAIND

IMVP_PWRGD
RT8068AZQW +1.05V_GFX
PWRGD
VIN Vin
C C
3V_MAIN_PWGD
VIN Vin
+VCC_CORE Vout
ISL95857HRTZ-T AOZ5029QI
+VCCCORE
AO3404 +3V_GFX EN
VRON
dGPU_PWR_EN
SVID PWM_A
PCH FCCM_A

HWPG_1VS5
IMVP_PWRGD
MDV1528Q +VCCIO
PWRGD VIN
PWRGD Vin
VIN +1.0V_S5 MAIND
Vin Vout +1V_S5 VIN +VCCSA
RT8237CZQW Vin Vout +VCCSA
ISL95857HRTZ-T AOZ5029QI
EN
EN
+1V_S5_ON AO3404 +1V_SUS VRON
EC
SUSON SVID PWM_C
B B
FCCM_C
0 ohm
EC IMVP_PWRGD
TPS22965DSGR V1_MPHY
PWRGD
VIN Vin
MPHY_EXT_PWR
PCH VIN Vin
+VCCGT Vout
ISL95857HRTZ-T AOZ5029QI
+VCCGT
EN
HWPG_VDDR VRON

SVID PWM1_B
FCCM_B
SUSON PWRGD
EC S5 EN
+1.2VSUS
S5_Vout HWPG_1.5V
+1.2VSUS +VDDQ_VTT
G5316RZ1D HWPG_1.8VS5
MAINON PWRGD
EC
S3 EN +3V_S5 +1.5V
A A
Vin S3_Vout +VDDQ Vin Vout +1.5V
DDR_VTTT_PG_CTRL PWRGD APW8824

+3V_S5 +1.8V_S5 EN
PCH Vin Vout +1.8V_S5
APW8824 MAINON
EN
Quanta Computer Inc.
VIN S5_ON
PROJECT : ZRW
Size Document Number Rev
1A
SKL PCH PWR CONTROL
Date: Monday, February 22, 2016 Sheet 43 of 46
5 4 3 2 1
1 2 3 4 5 6 7 8

+3V_S5 +3V 44
SDRAM
2.2K 2.2K 2.2K 2.2K
+3V
R7 SMB_PCH_CLK CLK_SCLK
A 2N7002DW A

R8 SMB_PCH_DAT Level shift CLK_SDATA G-Sensor

XDP

Skylake U
+3V_S5

2.2K 2.2K
B B

R9 VGA_MBCLK

W2 VGA_MBDATA

+3V_S5

*2.2K *2.2K
+3V_S5
W3 SMB_ME1_CLK
*2N7002DW
V3 SMB_ME1_DAT Level shift

+3V_S5 +3V_GFX

C 0 0 C

2.2K 2.2K 2.2K 2.2K

+3V_MAIN
115 2ND_MBCLK
2N7002DW GFX_SCL
Level shift VGA
116 2ND_MBDATA GFX_SDA

EC
+3VPCU
IT8987CX
D D
4.7K 4.7K
110 MBCLK

111 MBDATA CHARGER


Quanta Computer Inc.
PROJECT : ZRW
Size Document Number Rev
1A
SMBUS Block Diagram
Date: Monday, February 22, 2016 Sheet 44 of 46
1 2 3 4 5 6 7 8

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