CS8351- DPSD

UNIT 2 – COMBINATIONAL LOGIC

ANNA UNIVERSITY QUESTIONS – (TOPICWISE)

I. Combinational Circuits – Analysis and Design Procedures

2 Marks:
1. Distinguish between the combinational and sequential logic circuits. (2010 May)
2. Define combinational circuit. (2009 May)
3. What is the difference between sequential and combinational circuits? Give examples. (2008 Dec)

16 Marks:
1. Analyse the combinational circuit shown in figure to determine the truth table and the Boolean expression governing
the outputs of the circuit. (2012 Dec, 10 Marks)

2. Explain the analysis procedure. Analysze the following logic diagram.

3. Design a combinational circuit that comprises of only NOR gates for the following expression giving the
input output relation. Y=ABC’ + AC + B’C (2011 May,10 Marks)
4. Design a combinational circuit with three inputs and one output. The output is 1, when the binary value of
the inputs is less than 3. The output is 0 otherwise. (2008 Dec,8 Marks)
5. Implement the function F(A,B,C,D)=∑(0,1,3,4,8,9,15) using combinational circuit.
6. What are the design procedures of combinational circuit? (2008 May, 4 Marks)

II. Circuits for Arithmetic Operations

2 Marks:
1. Write down the truth table of a full subtractor. (2013 May)
2. Implement a full adder with two half adders .(2012 Dec)
3. Implement a 4-bit even parity checker. (2012 Dec)
4. Draw the truth table for Half-subtractor (2011 Dec)
5. Draw the schematic (logic diagram) of Half-adder logic. (2011 May,2009 Dec)
6. Compare Serial and Parallel adder. (2010 Dec)
7. Define look ahead carry addition. (2010 Dec) .
8. Write short notes on Propagation Delay (2015 Dec)
9. Draw the truth table of Half adder (2015 Dec)

16 Marks:
1. Explain BCD adder with a neat block diagram. (Or) Design a combinational circuit to perform BCD
addition (2013 Nov, 2012 Dec , 2011 Dec,2009 May, 16 Marks)
2. Design a 2-bit magnitude comparator. (2014 May, 6 marks)
3. Design a 2-bit magnitude comparator and write a verilog HDL code (2014 Nov, 16 marks)
4. Design a 4-bit magnitude comparator with three outputs A>B, A = B, A<b.
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(2013 Nov (12marks), 2008 Dec,8Marks)
5. Draw the schematic of a magnitude comparator and give its truth table. (2011 May, 6 Marks)

6. Draw the schematic of a full adder circuit and give its truth table.
(2011 May(6 marks), 2010 May(10marks))
7. Design a full adder using 2 half adders (2013 May,16 Marks)
8. Design a full adder and subtractor using NAND and NOR gates. (2010 Dec,16 Marks)
9. Design and implement a full adder with two half adders and an OR gate. (2008 Dec,8 Marks)
10. Design a half subtractor circuit (2009 Dec,6 Marks)
11. Design a 3-bit Adder. (2008 May, 4 Marks)
12. Draw the diagram of a 4-bit adder subtractor using full adders. (2012 Dec, 4 Marks)
13. Construct a 4-bit odd parity generator circuit using gates. (2013 Nov,4 Marks)
14. Design a full adder and realize it using only NOR gates (2014 May, 8 Marks)
15. Design a four bit parallel binary adder/subtractor (2014 May, 8 Marks)
16. Design a full subtractor and derive the expression for difference and borrow. Relaize using gates.
17. With neat diagram explain the 4-bit adder with carry lookahead (2015 Dec, 8 Marks)

III. Code Conversion

2 Marks:
1. Obtain the truth table for BCD to Excess-3 code converter. (2013 Nov)
2. What is the need for code conversion? Give two commonly used codes. (2009 May)
3. Realize 4-bit binary to gray code converter using EX-OR gates. (2014 May)
4. Define Code converter logic circuit.

16 Marks:
1. Design and Implement a 8421 to gray code converter. Realize the ocnverter using only NAND gates.
(2014 Nov, 16marks)
2. Design a Combinational Logic Diagram for BCD to Excess-3 Code Converter (or) Design a circuit that
converts 8421 BCD to Excess-3 code.(2014 May(R13), 2012 Dec,2011 May2010 May, 2010 Dec, 2008 May)
3. Design a combinational circuit to convert binary to gray code (2013 May, 16 Marks)
4. Derive the logic circuitry for Excess-3 to BCD code conversion. (2011 Dec, 16 Marks)
5. Explain the gray code to binary converter with the necessary diagram (2009 Dec,10 Marks)
6. Design a combinational circuit to convert gray code to BCD (2008 May, 12 Marks)

IV. Decoders and Encoders

2 Marks:
1.Construct a 4×16 decoder using 3×8 decoders. (2012 Dec)
2. Define Priority encoder (2010 Dec, 2008 May)
3. Define Encoder. (2010 May)
4. What is a decoder? Draw the block diagram and truth table for 2 to 4 decoder. (2009 May)
5. Implement the function S(x,y,z) = ∑(1,2,4,7) using a decoder. (2008 Dec)
6. Implement the function G=∑m(0,3) using a 2×4 decoder.

16 Marks:
1. Realize 4×16 decoder using two 3×8 decoders with enable inputs (2013 Nov)
2. Design a 4-input priority encoder. (2012 Dec, 6 Marks)
3. Design a 3 to 8 line decoder with necessary diagram (2010 May,8 Marks)
4. Explain with necessary diagram a BCD to 7 segment display decoder.
(2009 May, 2009 Dec,16 Marks)
5. Define Decoder. Design a 3 to 8 decoder with suitable block diagram. Explain how a 4 to 16 decoder can be
formed by using the same. (2009 May,16 Marks)
6. Design 8 to 3 priority encoder (2014 May, 8 marks)
7. Construct a 5 ×32 line decoder using 3 to 8 line decoders and 2 to 4 line decoder (2015 Nov, 8 marks)

V. Multiplexers and Demultiplexers

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2 Marks:
1. Distinguish between a decoder and a demulitiplexer? (2014 May (R13),2013 May, 2011 Dec, 2009 Dec)
2. Determine the size and number of multiplexers required to implement a full adder. (2011 May)
3. What is a multiplexer? (2010 May, 2010 Dec)
4. Give some applications of multiplexer. (2009 May)
5. What is a demultiplexer? (2008 May)
6. Draw the circuit for 2-to-1 multiplexer (2014 May-R13)
7. Implement the following Boolean function using 8:1 Multiplexer F(A,B,C)=∑M(1,3,5,6)

16 Marks:
1. Implement the following Boolean function using 8 to 1 Multiplexer. F(A,B,C,D) = A’BD’ + ACD + B’CD + A’C’D.
Also implement the function using 16 to 1 multiplexer. (2014 May(R13), 16 Marks)
2. Implement the switching function F=∑m(0,1,3,4,12,14,15) using an 8 input MUX. (2013 May, 16 Marks)
3. Implement F(A,B,C,D)=∑(1,3,4,11,12,13,14,15) using 8×1 multiplexer. (2012 Dec,8 Marks)
4. Implement the following Boolean function using 4:1 mux f(A,B,C,D) = ∑m(0,1,2,4,6,9,12,14)
(2011 Dec, 8 Marks)
5. Design a combinational logic using a suitable multiplexer to realize the following Boolean expression.
Y=AD’+B’C+BC’D’ (2011 May, 10 marks)
6. Implement the following Boolean function using 8:1 MUX.
F(A,B,C,D) = ABD + ACD + BCD + ACD (2010 Dec, 14 Marks)
7. Implement the given Boolean function using 4×1 multiplexer F(x,y,z)=∑(1,2,6,7) (2010 May,8 Marks)
8. Implement the function F(A,B,C,D) = ∑0,1,3,4,8,9,15) using a multiplexer (2008 Dec, 8 Marks)
9. Implement the Boolean function using 4:1 multiplexer F(W,X,Y,Z) = ∑ (1,2,3,6,7,8,11,12,14)
(2008 May,8 Marks)
10. Compare and contrast encoders and multiplexers. (2011 May, 6 marks)
11. Implement the function using 8 to 1 multiplexer F(a,b,c,d)=∑(0,1,3,5,9,12,14,15) (2014 May, 10 Marks)
12. Implement the Boolean function using Multiplexer F(w,x,y,z) = ∑(2,3,5,6,11,14,15) (2015 Nov, 8 marks)

VI. Introduction to HDL – HDL Models of Combinational circuits.

2 Marks:
1.What is meant by Test bench? (2013 May)
2. Write the HDL description of the full adder circuit (2011 May)
3. What do you mean by HDL? (2010 May)
4. Write a dataflow description of a 2-to-1 line mux using a conditional operator. (2010 Dec)

16 Marks:
1. Write the HDL description of the circuit specified by the following Boolean function x= AB+C , y = C’
(2010 May, 6 Marks)
2. Construct a BCD adder circuit and write a HDL program module from the same. (2008 May, 16 Marks)
3. Write a HDL code for binary to octal encoder (2013 May, 6 marks)

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UNIT II- COMBINATIONAL LOGIC
Syllabus:

Combinational Circuits – Analysis and Design Procedures – Circuits for Arithmetic Operations,
Code Conversion – Decoders and Encoders – Multiplexers and Demultiplexers – Introduction to
HDL – HDL Modelsof Combinational circuits.

Text Books and Reference Books:

1. Morris Mano M. and Michael D. Ciletti, “Digital Design”, IV Edition, Pearson Education, 2008
(Pg No: 125 to 164)

REFERENCES:

1. John F. Wakerly, “Digital Design Principles and Practices”, Fourth Edition, Pearson
Education,2007.
2. Charles H. Roth Jr, “Fundamentals of Logic Design”, Fifth Edition – Jaico Publishing House,
Mumbai, 2003.
3. Donald D. Givone, “Digital Principles and Design”, Tata Mcgraw Hill, 2003.
4. Kharate G. K., “Digital Electronics”, Oxford University Press, 2010.

Introduction

Logic circuit for digital systems may be combinational or sequential.

i) Combinational circuit:
1. A combinational circuit consists of logic gates whose outputs at any time are determined from only the
present combination of inputs.
2. A combinational circuit performs an operation that can be specified logically by a set of Boolean functions.
ii) Sequential circuit:
1. In contrast, sequential circuits employ storage elements in addition to logic gates.
2. Their outputs are a function of the inputs and the state of the storage elements.
3. Because the state of the storage elements is a function of previous inputs, the outputs of a sequential circuit
depend not only on present values of inputs, but also on past inputs, and the circuit behavior must be
specified by a time sequence of inputs and internal states.
Combinational circuits:

1. A combinational circuit consists of an interconnection of logic gates.

2. The logic gates react to the values of the signals at their inputs and produce the value of the output signal.
3. A combinational circuit can have n number of inputs and m number of outputs.
4. The n input binary variables come from an external source; the m output variables are produced by the
internal combinational logic circuit.

5. For n input variables, there are 2 n possible combinations of the binary inputs.
6. For each possible input combination, there is one possible value for each output variable.
7. Thus, a combinational circuit can be specified with a truth table that lists the output values for each
combination of input variables
8. A combinational circuit also can be described by m Boolean functions, one for each output variable.
9. Combinational logic is used in computer circuits to perform Boolean algebra on input signals and on stored
data (For example, the part of an arithmetic logic unit(ALU), that does mathematical calculations is
constructed using combinational logic).
10. Other circuits used in computers, such as half adders, full adders, half subtractors, full subtractors,
multiplexers, de-multiplexers, encoders and decoders are also made by using combinational logic.

Analysis Procedure
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1. The analysis of a combinational circuit requires that we determine the functionthat thecircuit implements.
2. The analysis can be performed manually by finding the Booleanfunctions or truth table or by using a
computer simulation program.
3. The first step in the analysis is to make sure that the given circuit is combinationaland not sequential.
4. The diagram of a combinational circuit has logic gates with nofeedback paths or memory elements.
5. To obtain the output Boolean functions from a logic diagram,
i) Label all gate outputs that are a function of input variables with arbitrary symbols. Determine the
Boolean functions for each gate output.
ii) Label the gates that are a function of input variables and previously labeled gateswith other arbitrary
symbols. Find the Boolean functions for these gates.
iii) Repeat the process outlined in step 2 until the outputs of the circuit are obtained.
iv) By repeated substitution of previously defined functions, obtain the outputBoolean functions in terms
of input variables.
For analysis, let us consider the logic diagram:

The circuit has three binary inputs— A, B, and C and two binaryoutputs— F1 and F2.
The Boolean functions for these threeoutputs are

Next, we consider outputs of gates that are a function of already defined symbols:

The derivation of the truth table for a circuit is a straightforward process once theoutput
Boolean functions are known.
1. Determine the number
of input variables in the
circuit. For n inputs, form the
2npossible input combinations
and list the binary numbers from 0 to (2n - 1) in atable.
2. Label the outputs of selected gates with arbitrary symbols.
3. Obtain the truth table for the outputs of those gates which are a function of theinput variables only.

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4. Proceed to obtain the truth table for the outputs of those gates which are a functionof previously defined
values until the columns for all outputs are determined
Truth Table for the Logic Diagram of Fig

Design Procedure
The procedure involves the following steps:
1. From the specifications of the circuit, determine the required number of inputsand outputs and assign a
symbol to each.
2. Derive the truth table that defines the required relationship between inputs andoutputs.
3. Obtain the simplified Boolean functions for each output as a function of the inputvariables.
4. Draw the logic diagram and verify the correctness of the design (manually or bysimulation).

CIRCUITS FOR ARITHMETIC OPERATIONS

1. Digital computers perform a variety of information-processing tasks.
2. Among the functions encountered are the various arithmetic operations.
3. The most basic arithmetic operation is the addition of two binary digits.
4. A combinational circuit that performs the addition of two bits is called a half adder .
5. One that performs the addition of three bits (two significant bits and a previous carry) is a full adder .
Half Adder:
1. It is the basic building block for addition of two single bit numbers.
2. Half adder is a combinational logic circuit with two inputs and two outputs.
3. This circuit has two inputs A and B and two outputs sum and carry.
Block Diagram: Truth Table:

K-Map:

B 0 1 B 0 1
A A
0 0 1 0 0 0
1 1 0 1 0 1
Sum = 𝐴𝐵̅ + 𝐴̅𝐵 = 𝐴 ⊕ 𝐵 Carry = AB

Logic Diagram:

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Full Adder:
1. A full adder is a combinational circuit that forms the arithmetic sum of three bits.
2. Itconsists of three inputs and two outputs.
3. Three input variables are A, B, Cin and the two outputs are sum ‘s’ and carry ‘C0’
Block Diagram: Truth Table:

K-Map:

Logic Diagram:

Implementation of Full Adder Using Half Adders:

1. A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers.
2. It can be constructed with full adders connected in cascade, with the output carryfrom each full adder
connected to the input carry of the next full adder in the chain.
Block Diagram: Logic Diagram

HALF SUBTRACTOR:

Truth Table:

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K-Map:
B 0 1 B 0 1
A A
0 0 1 0 0 1
1 1 0 1 0 0
Diff = 𝐴 ⊕ 𝐵 Borrow= A’B

Logic Diagram:

Full Subtractor:
Truth Table: K-Map:

Logic
Diagram:

Implementation Of Full Subtractor Using Half Subtractor

Block Diagram: Logic Diagram

Parallel Adder: (Ripple Carry Adder)

1. A single full adder is capable of adding two 1 bit numbers and an input carry.
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2. To add binary numbers with more than one bit, additional full-adders are required.
3. A binary parallel adder is a digital circuit that produces the arithmetic sum of two binary numbers in
parallel.
4. It consists of full-adders connected in a chain, with the output carry from each full-adder connected to the
input carry of the next full-adder in the chain.
5. The block diagram for n –bit parallel adder:

The block diagram for 4-bit

parallel adder is:

Parallel Subtractor:
✓ A binary parallel subtractor is a
digital circuit that produces the arithmetic difference of two binary numbers in parallel.
✓ It consists of full-subtractors connected in a chain, with the output carry from each full-subtractor connected
to the input carry of the next full-subtractor in the chain.
✓ A 4 bit parallel subtractor can be implemented by cascading four full subtractors in parallel.
✓ It has 4 difference outputs and 4 borrow outputs.

Parallel Adder /
Subtractor:

1. The addition and subtraction operations can be combined into one circuit with one common binary adder.
2. This is done by including an exclusive OR gate with each full adder as shown:

3. The Mode ‘M’ controls the

operation of the circuit:
o When M=0, the circuit is an adder, we have 𝐵 ⊕ 0 = 𝐵, the circuit performs addition
o When M=1, the circuit becomes subtractor, i.e., 𝐵 ⊕ 1 = 𝐵̅ , the circuit performs A plus the 2’s
complement of B i.e., A - B

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Serial Adder:
1. In the serial adder, the addition operation is done by bit-by-bit.
2. The serial adder requires simple circuit than a parallel
adder.
Theoperation of the serial adder is as follows:
i) Two shift registers A and B are used to store the
numbers to be added serially.
ii) A single full adder is used, to add one pair of bits at a
time, along with the carry.
iii) The D-flip flop is used to store the carry output of the
full adder, so that it can be added to the next significant
position of the numbers in the registers.
iv) The contents of the shift registers shift from left to
right and their outputs starting from A0 and B0 are fed
into a single full adder along with the output of the D-
flip flop upon application of each clock pulse.
v) The sum output of the full adder is fed to MSB bit (S3)
of the sum register.
vi) For each succeeding clock pulse, the contents of the both shift registers are shifted once to the right and
new carry bit are transferred to sum register and D-flip flop respectively.
vii) This process continues until all the pairs of bits are added.

Serial Subtractor:
1. A serial subtractor can be obtained by converting the
full adder by feeding the output B’ into the full adder
instead of B.
2. Intially setting the D flip flop to 1 instead of 0.
3. Difference register instead of sum register.
The operation of the serial subtractor is as follows:
i) 2’s complement subtraction method is used in
the serial subtractor.
ii) The subtrahend is stored in the ‘B’ register
and the minuend stored in ‘A’ register.
iii) The subtrahend is converted into 1’s
complement number by adding a NOT gate
with B register and get 2’s complement
number by adding 1 through Cin.
iv) The 2’s complement of subtrahend to the
minuend by the full adder and the result is
stored in the difference register.
Comparison Between Serial And Parallel Adder:

Serial adder Parallel adder

1) Slower 1) Faster
2) It uses shift registers 2) It uses registers with parallel load capacity
3) It requires one full adder circuit. 3) No. of full adder circuit is equal to no. of bits in
binary adder.
4) It is sequential circuit. 4)It is a combinational circuit
5) Time required for addition depends on number of 5)Time required does not depend on the number of bits
bits.

Carry Look Ahead Adder: (CLA)

Why CLA?
1. The parallel adder is a ripple carry type , in which the carry output of each full-adder stage is connected to
the carry input of the next higher-order stage.
2. Therefore, the sum and carry outputs of any stage cannot be produced until the input carry occurs; this leads
to a time delay in the addition process.
3. This delay is known as carry propagation delay.
4. This delay is more if the adder circuit adds greater number of bits.

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What is CLA?
1. To speed up the addition process and to eliminate the inter stage carry delay, look ahead carry addition is
used.
2. This method utilizes logic gates to look at the lower order bits of the augend and addend to see if a higher-
order carry is to be generated.
Consider the full adder circuit using two half adders,

In this adder, the two functions are used:

i) Carry Generate ii) Carry propagate
From the fig, 𝑃𝑖 = 𝐴𝑖 ⊕ 𝐵𝑖 , 𝐺𝑖 = 𝐴𝑖 𝐵𝑖
The output sum and carry can be expressed as:𝑆𝑖 = 𝑃𝑖 ⊕ 𝐶𝑖 , 𝐶𝑖+1 = 𝑃𝑖 𝐶𝑖 + 𝐺𝑖
where, Gi is called a carry generate and it produces on carry when both Ai and Bi are one.
Pi is called carry propagate, because it is associated with the propagation of the carry from C i to Ci+1

Now the Boolean function for the carry output of each stage can be written as:

✓ From the above function, it is seen that C4 does not

have to wait for C3 and C2 to propagate.
✓ The Boolean function of the output carry can be implemented as shown in Fig 1. below:
✓ Using a look-ahead carry generator, we can construct a 4-bit parallel adder with carry look ahead adder
scheme. (shown in Fig 2.)The outputs of first Ex-OR gate generates Pi and AND gate generates Gi.
✓ IC 74182 is used as carry look ahead generator

Fig 1: Implementation of Output carry

Boolean Function
Fig 2: Construction of 4 bit parallel adder
using Carry lookahead Generator 11
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BCD ADDER
1. A BCD adder is a circuit that adds two BCD digits and produces a sum digit also in BCD.
2. BCD numbers use 10 digits, 0 to 9 which are represented in the binary from 0000 t0 1001.
3. Three cases in BCD addition.
i) Sum Equals or less than 9 with carry 0.
Let us consider addition of 6 and 3 in BCD
6 0110 ---- BCD for 6
3 0011 ---- BCD for 3
1001 ---- BCD for 9
The addition is carried out as in normal binary addition and the sum is 1001.
ii) Sum greater than 9 (10 to 15) with carry 0.
Let us consider addition of 6 and 8 in BCD
6 0110 ---- BCD for 6
8 1000 ---- BCD for 8
1110 ---- (14) --------------------- Invalid BCD number
∴The sum 1110 is an invalid BCD number (digit exceeds 9).
Whenever this occurs, the sum has to be corrected by the addition of six (0110) in the invalid BCD
number, as shown below
14 1110 ---- BCD for 14
0110 ---- Add ‘6’ for correction
0001 0100 ---- (14)
1 4 ------ BCD for 14.
After addition of ‘6’ carry is produced into the second decimal position.
iii) Sum from 16 to 18 with carry 1.
Let us consider addition of ‘8’ and ‘9’ in BCD
8 1000 ---------- BCD for 8
9 1001 ---------- BCD for 9
00010001---- (17) --------------------- Invalid BCD number.
In this case, result (0001 0001) is valid BCD number, but it is incorrect.
To get the correct BCD result correction factor of 6 has to be added to the least significant digit sum,
as shown below.
8 1000 ---------- BCD for 8
9 1001 ---------- BCD for 9
0001 0001---- (17) --------------------- Invalid BCD number.
0000 0110 --------------- Add ‘6’
0001 0111 --------------- 17
4. Thus to implement BCD we require,
(i) 4-bit binary adder for initial addition.
(ii) Logic circuit to detect sum greater than 9.
(iii) One more 4-bit adder to add 01102 in the sum if the sum is greater than ‘9’ or carry is ‘1’.
The logic circuit to detect sum greater than 9 can be determined by simplifying the Boolean expression of given
truth table.

Y = S3S2+S3S1

Y=1 indicates sum is greater than 9.

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Circuit Diagram of BCD Adder
As shown in the figure, the two BCD numbers,
together with input carry, are first added in the top 4-
bit binary adder to produce a binary sum.
When the output carry is equal to zero (i.e., when
sum <9 and Cout = 0) nothing is added to the binary
Sum.
When it is equal to one (i.e., when sum > 9 or
Cout =1), binary 0110 is added to the binary sum
through the bottom 4-bit binary adder.
The output carry generated from the bottom
binary adder can be ignored, since it supplies
information already available at the output-carry
terminal.

Parity Generator and Checker:

1. A parity bit is an extra bit included with a binary message to make the number of 1’s either odd or even.
2. The circuit that generates the parity bit in the transmitter is called a parity generator.
3. The circuit that checks the parity in the receiver is called a parity checker.
Even parity Generator
As an example, consider a three-bit message to be transmitted together with an even-parity bit. The three bits—
A, B, and C constitute the message and are the inputs to the circuit. The paritybit P is the output. For even parity,
the bit P must be generated to make the total number of 1’s (including P ) even.

Even parity checker

The three bits in the message, together with the parity bit, are transmitted to theirdestination, where they are
applied to a parity-checker circuit to check for possibleerrors in the transmission.
Since the information was transmitted with even parity, thefour bits received must have an even number of 1’s.
An error occurs during the transmissionif the four bits received have an odd number of 1’s, indicating that one bit
haschanged in value during transmission.
The output of the parity checker, denoted byC , will be equal to 1 if an error occurs—that is, if the four bits
received have an oddnumber of 1’s.

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Logic Diagram:

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Magnitude Comparator
1. The comparison of two numbers is an operation that determines whether one numberis greater than, less
than, or equal to the other number.
2. Magnitude comparator is a combinational circuit that
compares two numbers, A and B, and determines their
relative magnitudes
3. The outcome of comparison is specified by three binary
variables that indicate whether A>B, A=B, or A<B.
For an n-bit magnitude comparator, the fig shows →
One bit Magnitude comparator:

Two bit Magnitude comparator:

Truth Table: K-Map:

Logic Diagram:

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4-bit Magnitude Comparator

Consider two numbers, A and B , with four digits each. Write the coefficients of the numbers in descending
order of significance:
A = A3 A2 A1 A0
B = B3 B2 B1 B0
Each subscripted letter represents one of the digits in the number
The circuit possesses 28 (256) combinations, therefore it can be designed algorithmically.
Design of the EQ output (A = B) in 4-bit magnitude comparator
When the numbers are binary, the digits are either 1 or 0, and the equality of each pair of bits can be
expressed logically with an exclusive-NOR function as xi = AiBi + A’iB’i for i = 0, 1, 2, 3 where xi = 1 only if the
pair of bits in position i are equal (i.e., if both are 1 or both are 0).

So, Define Xi= (AiBi)+ (Ai’ Bi’)

Thus Xi = 1 iff Ai = Bi
for all i =0, 1, 2 and 3
Xi = 0 iff Ai ≠ Bi
Condition for A= B
EQ=1 (i.e., A=B) iff
1. A3=B3 → (X3 = 1), and
2. A2=B2 → (X2 = 1), and
3. A1=B1 → (X1 = 1), and
4. A0=B0 → (X0 = 1).
Thus, EQ=1 iff X3 X2 X1 X0 = 1.
In other words, EQ = X3 X2 X1 X0

Design of the GT(Greater Than) output (A > B) in 4-bit magnitude comparator

If A3 > B3, then A > B (GT=1) irrespective of the relative values of the other bits of A & B.
Consider, for example, A = 1000 and B = 0111 where A > B.
̅𝟑 = 1
This can be stated as GT=1 if A3𝐁

If A3 = B3 (X3 = 1), we compare the next significant pair of bits (A2 & B2).
If A2 > B2 then A > B (GT=1) irrespective of the relative values of the other bits of A & B.
Consider, for example, A = 0100 and B = 0011 where A > B.
̅𝟐 = 1
This can be stated as GT=1 if X3A2𝐁

If A3 = B3 (X3 = 1) and A2 = B2 (X2 = 1), we compare the next significant pair of bits (A1 & B1).
If A1 > B1 then A > B (GT=1) irrespective of the relative values of the remaining bits A0 & B0.
Consider, for example, A = 0010 and B = 0001 where A > B
̅𝟏 = 1
This can be stated as GT=1 if X3 X2A1𝐁

If A3 = B3 (X3 = 1) and A2 = B2 (X2 = 1) and A1 = B1 (X1 = 1), we compare the next pair of bits (A0 &
B0).
̅ 𝟎 =1
If A0 > B0 then A > B (GT=1). This can be stated as GT=1 if X3.X2.X1.A0.𝐁
To summarize, GT =1 (A > B) IFF:
1. A3𝐁̅𝟑= 1 (or)
2. ̅
X3A2𝐁𝟐 = 1 (or)
3. ̅ 𝟏 = 1, (or)
X3 X2A1𝐁
4. ̅ 𝟎 =1
X3 X2 X1 A0.𝐁
̅ 𝟑 +X3A2𝐁
In other words, GT =A3𝐁 ̅ 𝟐 + X3 X2A1𝐁
̅ 𝟏 + X3 X2 X1 A0.𝐁
̅𝟎

Design of the LT output (A < B) in 4-bit magnitude comparator

In the same manner as above, we can derive the expression of the LT (A < B) output
LT = 𝐀 ̅ 𝟑 B3 + X3𝐀
̅ 𝟐 B2 + X3 X2𝐀
̅ 𝟏 B1+ X3 X2 X1 𝐀̅ 𝟎 B0

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Logic Diagram:
The equations are: EQ = X3 X2 X1 X0,
GT =A3B ̅3 +X3A2B ̅2 + X3 X2A1B̅1+ X3 X2 X1 A0.B̅0 ,
̅ 3 B3 + X3A
LT = A ̅ 2 B2 + X3 X2A
̅1B1+ X3 X2 X1 A
̅ 0 B0

CODE CONVERSION

1. A code converter is a logic circuit that changes data presented in one type of binary code to another type of
binary code
2. The following type of code conversions are possible:
1. BCD to Excess-3 Converter
2. Excess-3 to BCD
3. Binary to Gray converter
4. Gray to Binary converter
5. BCD to Gray code converter
6. Gray code to BCD converter
7. Binary to BCD converter
8. BCD to Binary converter.

1. BCD to Excess-3 Converter:

Truth Table:

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K-Map: Logic Diagram:

Excess-3 to BCD Converter:

Truth Table: K-Map:

Logic Diagram:

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Binary to Gray code converter:

INPUT ( BINARY) OUTPUTS (GRAY

CODE)

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

K-Map: Logic Diagram:

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INPUT ( GRAY OUTPUTS

CODE) (BINARY )

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1 Gray to Binary
converter:
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1

0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

1 0 0 0 1 1 1 1

1 0 0 1 1 1 1 0

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 0 1 0 1 1 K-Map

1 1 1 1 1 0 1 0

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Logic Diagram:

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BCD to Gray Code Converter:

Logic Diagram:

Gray to BCD Code:

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Logic Diagram:

BCD to Binary Converter:

Truth Table:

K-Map:

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Logic Diagram:

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DECODERS:

1. Decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2 n
unique output lines.
2. For example if the number of input lines n=3, then the number of output lines, m=23=8

Types:
1. 2 to 4 decoder
2. 3 to 8 decoder
3. 4 to 16 decoder
2 to 4 DECODER:

2 TO 4 LINE DECODER(Using AND Gateswith Enable Input)

Many devices have an additional enable input, which is used to “activate” or “deactivate” the device.
• For a decoder,
– EN=1 activates the decoder, so it behaves as specified earlier. Exactly one of the outputs will be 1.
– EN=0 “deactivates” the decoder. By convention, that means all of the decoder’s outputs are 0.
In this table, note that whenever EN=0, the outputs are always 0, regardless of inputs S1 and S0.

Reduced truth table

2 to 4 decoder using NAND gate:

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3 to 8 line
decoder:

3 to 8 line
decoder
with enable
input☺

4 to 16 line Decoder:

1. Decoders with enable inputs can be connected together to form a larger decoder circuit.
2. Fig 1shows two 3-to-8 line decodes with enable inputs connected to form a 4 to 16 line decoder.
3. When w=0, the top decoder is enabled and the other is disabled. The bottom decoder outputs are all 0’s , and
the top eight outputs generate min-terms 0000 to 0111.
4. When w=1, the enable conditions are reversed. The bottom decoder outputs generate min-terms 1000 to
1111, while the outputs of the top decoder are all 0’s.
Truth table of 4 to 16 decoder with two 3 to 8 decoders:
Logic Diagram of 4 to 16 decoder with two 3 to 8 decoders:

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4 to 16 decoder:
Truth Table:

Logic Diagram:

Implementatio of 4 to 16 Decoder using 2 to 4 Decoders

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BCD TO SEVEN SEGMENT DISPLAY DECODER:

• A seven segment display is normally used for displaying any one of the decimal digits from 0 to 9.
• A BCD to seven segment decoder accepts decimal digits in BCD and generates the corresponding seven
segment code.

Truth Table:

Decimal Inputs Outputs

Digits A B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1
10 1 0 1 0 x x x x x x x
11 1 0 1 1 x x x x x x x
12 1 1 0 0 x x x x x x x
13 1 1 0 1 x x x x x x x
14 1 1 1 0 x x x x x x x
15 1 1 1 1 x x x x x x x

K-Map Simplification:

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Logic Diagram:

Implementatio of 5 to 32 Decoder using 3 to 8 and 2 to 4 Decoders

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BCD TO DECIMAL DECODER:

Truth Table:

Inputs Outputs Decimal

A B C D Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 No
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 0 0 0 1 0 1
0 0 1 0 0 0 0 0 0 0 0 1 0 0 2
0 0 1 1 0 0 0 0 0 0 1 0 0 0 3
0 1 0 0 0 0 0 0 0 1 0 0 0 0 4
0 1 0 1 0 0 0 0 1 0 0 0 0 0 5
0 1 1 0 0 0 0 1 0 0 0 0 0 0 6
0 1 1 1 0 0 1 0 0 0 0 0 0 0 7
1 0 0 0 0 1 0 0 0 0 0 0 0 0 8
1 0 0 1 1 0 0 0 0 0 0 0 0 0 9
1 0 1 0 0 0 0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0 0 0 0 0 0 0
Invalid
1 1 0 0 0 0 0 0 0 0 0 0 0 0
(Don’t
1 1 0 1 0 0 0 0 0 0 0 0 0 0
cares)
1 1 1 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0 0 0 0

Logic Diagram:

Implementation Of Full Adder Using Decoders

Implement S(x,y,z) = ∑ ( 1,2,4,7) and C(x,y,z)= ∑ (3,5,6,7).

Applications of Decoders:

1. Used in Counter systems.

2. Used in Analog-to-digital converters
3. It can be used to drive a display system
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ENCODER:

1. An encoder is a combinational logic circuit that performs a inverse operation

of decoder.
2. An encoder has 2 n input lines and n output lines.
3. The output lines generate the binary code corresponding to the input value.
Types:
• 4 to 2 line Encoder
• 8 to 3 line Encoder[ Octal to Binary]
• 16 to 4 line Encoder[ Hexadecimal to Binary]
• Decimal to BCD Encoder
• Priority Encoder
4 To 2 Line Encoder

The input is 4 and the output is 2. It accepts totally 4 inputs and produces a 2-bit output code according
to the activated input.

8 to 3 ENCODER:
Block Diagram:

Truth Table:

Logic Diagram:

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16 to 4 ENCODER:

Truth Table

Logic Diagram:

Decimal TO BCD Encoder:

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Truth Table: Logic Diagram:

PRIORITY ENCODER:

1. This is a special type of encoder.

2. Priority is given to the input lines.
3. If two or more input lines are 1 at the same time,
then the input line with highest priority will be considered.
4. The Priority Encoder allocates a priority level to
each input.
5. The priority encoders output corresponds to the
currently active input which has the highest priority.
6. So when an input with a higher priority is present,
all other inputs with a lower priority will be ignored.

Truth Table: D3 D2 D1 D0 X Y V (Enable)

0 0 0 0 X X 0
0 0 0 1 0 0 1
0 0 1 0 0 1 1
0 0 1 1 0 1 1
0 1 0 0 1 0 1
0 1 0 1 1 0 1
0 1 1 0 1 0 1
0 1 1 1 1 0 1
1 0 0 0 1 1 1
1 0 0 1 1 1 1
1 0 1 0 1 1 1
1 0 1 1 1 1 1
Truth Table for Priority Encoder 1 1 0 0 1 1 1
1 1 0 1 1 1 1
1 1 1 0 1 1 1
1 1 1 1 1 1 1
K-Map:
Truth Table (Enhanced)

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MULTIPLEXER (Also called as Data selector)
1. Multiplexer is a digital switch.
2. It allows digital information from several sources to be routed at single output
line.
3. A multiplexer (or mux) is a device that selects one of
4. the several analog or digital input signals and forwards the selected input into a
single line.
5. A multiplexer of 2n inputs has n select lines, which are used to select which input
line to send to the output.

4-to-1 Multiplexer

8 to 1 MULTIPLEXER:

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Implementation Table:

3. Implement the function F(A,B,C,D) = ∑0,1,3,4,8,9,15) using a multiplexer

4. Design a combinational logic using a suitable multiplexer to

realize the following Boolean expression. Y=AD’+B’C+BC’D’

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Solution:Here instead of minterms, maxterms are specified. Thus we

have to circle maxterms which are not included in the Boolean
function.

Implementation Table

DEMULTIPLEXERS:(abbreviated as demux)

✓ The demultiplexer performs the exact opposite function of Multiplexer.

✓ A Demultiplexer is a circuit that receives information on a single line and transmits this information on one
of 2n possible output lines.
✓ The selection of specific output line is controlled by the values of n selection lines.

Truth Table: Block Diagram:

Logic Diagram:

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