Beruflich Dokumente
Kultur Dokumente
BY
DR. SUPRATIM GUPTA
2
COURSE OUT LINE
• Essential Reading:
• Datasheets of various chips (Intel 8085, 8086, 8051: AT89S8252), ADCs, DACs
• Ramesh S. Gaonkar, Microprocessor Architecture, Programming, and Applications with 8085,
Penram International, 6th Ed., 2013
• Douglas V. Hall, Microprocessors and Interfacing: Programming and Hardware, Tata McGraw-
Hill, 2nd Ed. (revised), 2006
• Supplementary Reading:
• Datasheets of various accessory IC components
• Myke Predko, Programming and Customizing the 8051 Microcontroller, McGrawHill, 1st Ed.
1999
• M. Morris Mano, Computer System Architecture, PHI, 3rd Ed., 2007 4
GRADING POLICY
5
CHAPTER – 1: OVERVIEW OF EMBEDDED SYSTEM (ES)
6
DEFINITION OF EMBEDDED SYSTEM
7
THE PROGRAMMABLE COMPUTERS
Digital Processor
A D
D A
C C
Sensors Actuators
10
15
MICROPROCESSOR & BUS ARCHITECTURE
• Arithmetic/Logic Unit (ALU): It
Input / Output performs addition, subtraction,
AND, OR and Exclusive OR
ALU Register Array
• Register Array: B, C, D, E, H, L;
System Bus
they are used to store data
temporarily
Memory
Control Unit • Control Unit: It provides
ROM RAM
necessary timing & control
signal
Microprocessor
16
MICROPROCESSOR & BUS ARCHITECTURE
• Memory: It stores binary
Input / Output information as instruction &
data
ALU Register Array
• I/O: Connect peripheral
System Bus
devices
2. The Memory
• Stores binary information, called instructions & data
• Provides the instructions or data to the MP on request
• Stores results of computation & data for the microprocessor
18
PIN OUT & SIGNAL FLOW DIAGRAM
19
FUNCTIONAL BLOCK DIAGRAM
20
INTERRUPT PRIORITY, VECTOR ADDRESS, SENSITIVITY
NOTES:
1. The processor pushes the PC on the stack before branching to the indicated address. 21
2. The address branched to depends on the instruction provided to the CPU when the
interrupt is acknowleged.
PIN DESCRIPTION
22
PIN DESCRIPTION
23
PIN DESCRIPTION
24
POWER-ON RESET CIRCUIT
26
DRIVING THE & INPUTS FOR CLOCK
Sources of clock
• Crystal Oscillator
• LC Tuned Circuit
• RC Network
• External Clock Source
27
DRIVING THE & INPUTS FOR CLOCK
28
THE MINIMUM SYSTEM
Features
• 2K Bytes EPROM
• 256 Bytes RAM
• 1 Timer/Counter
• 4 8-bit I/O port
• 1 6-bit I/O port
• 4 Interrupt levels
• Serial in / Serial out ports
29
THE MINIMUM SYSTEM WITH STANDARD I/O
30
THE MINIMUM SYSTEM WITH MEMORY MAPPED I/O
31
STATIC MOS RAM WITH I/O PORTS & TIMER (8156H)
• 256 words x 8-bits
• Single +5V power supply
• Internal address latch
• 2 programmable 8-bit I/O ports
• 1 programmable 6-bit I/O port
• Programmable 14-bit binary
counter/timer
• Multiplexed address and data bus
32
STATIC MOS RAM WITH I/O PORTS & TIMER (8156H)
33
STATIC MOS RAM WITH I/O PORTS & TIMER (8156H)
34
STATIC MOS RAM WITH I/O PORTS & TIMER (8156H)
35
STATIC MOS RAM WITH I/O PORTS & TIMER (8156H)
36
STATIC MOS RAM WITH I/O PORTS & TIMER (8156H)
37
STATIC MOS RAM WITH I/O PORTS & TIMER (8156H)
38
STATIC MOS RAM WITH I/O PORTS & TIMER (8156H)
40
EPROM WITH I/O PORTS (8755A)
41
EPROM WITH I/O PORTS (8755A)
42
EPROM WITH I/O PORTS (8755A)
43
EPROM WITH I/O PORTS (8755A)
44
CHAPTER – 2: 8085 MICROPROCESSOR
PROGRAMMING
45
INSTRUCTION FETCH OPERATION
46
MACHINE CYCLE
47
MACHINE CYCLE
• Machine Cycle:
• Time period for a process to perform basic
operation like op-code fetching, memory
reading/writing, I/O reading/writing etc.
49
PROGRAMMING MODEL
50
INSTRUCTION FORMAT
51
OPCODE FORMAT
52
EXAMPLES OF INSTRUCTION
53
DATA FORMAT
54
INSTRUCTION CLASSIFICATION
55
THE FOLLOWING ABBREVIATIONS ARE USED IN THE
DESCRIPTION OF THE INSTRUCTION SET:
Flags
Reg. = 8080A/8085 Register S= Sign
Mem. = Memory Location Z = Zero
R = Register AC = Auxiliary Carry
Rs = Register Source P = Parity
Rd = Register Destination CY = Carry
M = Memory
( ) = Contents of
XX = Random Information 56
INSTRUCTION SET: DATA TRANSFER
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected
Flags
B 06 NO FLAG
C 0E
Reg., Data 2 7 D 16
E 1E
1. Write data to a register MVI 2
H 26
L 2E
M, Data M 36
3 10
A 3E
57
INSTRUCTION SET: DATA TRANSFER
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected
Flags
MOV Rd, Rs 1 4 NO FLAG
Read content of the source register and MOV M, Rs
2. 1 See below
write it to destination register
2 7
MOV Rd, M
B 40 41 42 43 44 45 46 47
Destination Location
C 48 49 4A 4B 4C 4D 4E 4F
D 50 51 52 53 54 55 56 57
E 58 59 5A 5B 5C 5D 5E 5F
H 60 61 62 63 64 65 66 67
L 68 69 6A 6B 6C 6D 6E 6F
M 70 71 72 73 74 75 76 77 58
A 78 79 7A 7B 7C 7D 7E 7F
INSTRUCTION SET: DATA TRANSFER
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected
Flags
3. Read the content of the memory LDA 16-bit Add. 3 4 13 3A No Flag
location given by 16-bit address
and write to Accumulator
Reg. Hex
Pair Code
4. Write 16-bit data to register LXI Reg. pair, 3 3 10 BC 01 No Flag
pair or stack 16-bit data
DE 11
HL 21
Stack Operation
SP 31
59
INSTRUCTION SET: DATA TRANSFER
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected
Flags
5. Reads the content of the memory LHLD 16-bit Add. 3 5 16 2A No Flag
location given by 16-bit address
and writes to L. Then reads
content of the next memory
location (+1) and writes to H
Reg. Hex
Pair Code
6. Reads the content of the memory LDAX B/D Reg. 1 2 7 BC 0A No Flag
location pointed by content of pair
BC/DE and writes to A
DE 1A
60
INSTRUCTION SET: DATA TRANSFER
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected
Flags
7. The content of A is written in the STA 16-bit Add. 3 4 13 32 No Flag
memory location given by 16-bit
address
Reg. Hex
Pair Code
8. Writes the content of A in the STAX B/D Reg. 1 2 7 BC 02 No Flag
memory location pointed by pair
content of BC/DE
DE 12
9. the content of L is written in the SHLD 16-bit Add. 3 5 16 22 No Flag
memory location given by 16-bit
address and that of H is written
in the next memory location (+1)
61
INSTRUCTION SET: DATA TRANSFER
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected
Flags
10. Content of H & L is written into SPHL - 1 1 6 F9 No Flag
SP as higher & lower bytes
respectively
11. Content of H is exchanged with XCHG - 1 1 4 EB No Flag
D and that of L is exchanged
with E
12. Content of L is exchanged with XTHL - 1 5 16 E3 No Flag
memory location pointed by
content of SP and that of H is
exchanged with next memory
location (SP + 1). But content of
SP does not changed
13. Content of H & L is written into PCHL - 1 1 6 E9 No Flag
PC as higher & lower bytes
respectively 62
INSTRUCTION SET: DATA TRANSFER
Sl.No Description Opcode Operand Byte M-Cycles T-States Reg. Hex Affected
Pair Code Flags
14. PUSH Reg. pair 1 3 12 BC C5 No Flag
SP → SP - 1
Content of the higher order
register (B, D, H, A) is written DE D5
into the memory location pointed
by SP.
SP → SP - 1 HL E5
63
INSTRUCTION SET: DATA TRANSFER
Sl.No Description Opcode Operand Byte M-Cycles T-States Reg. Hex Affected
Pair Code Flags
15. The content of the memory POP Reg. pair 1 3 10 BC C1 No Flag
location pointed by SP is written
into the lower order register (C,
E, L, PSW) is written into. DE D1
SP → SP + 1
The content of the memory HL E1
location pointed by SP is written
into the higher order register (B,
D, H, A). PSW F1
SP → SP + 1
64
INSTRUCTION SET: DATA TRANSFER
Sl.No Description Opcode Operand Byte M-Cycles T-States Reg. Hex Affected
Pair Code Flags
16. The content of the memory POP Reg. pair 1 3 10 BC C1 No Flag
location pointed by SP is written
into the lower order register (C,
E, L, PSW) is written into. DE D1
SP → SP + 1
The content of the memory HL E1
location pointed by SP is written
into the higher order register (B,
D, H, A). PSW F1
SP → SP + 1
65
ADDRESSING MODES
• Immediate: MVI A, 20H (8-bit data); LXI SP, 2700H (16-bit data)
• Register: MOV A, B; SPHL (content of HL -> SP); ADD C (A + C -> A)
• Direct: LDA 2000H ( Content at 2000H address -> A); SHLD 3000H (HL->3000H)
• Indirect: LDAX B (content of memory pointed by BC reg. pair -> A); MOV M, A (A -> Memory
location pointed by content in HL reg. pair)
• Implied: CMA (A’); RAL (rotate content of A left through carry)
• Index Mode: Address of operand in memory is generated by adding base-address and a offset or
displacement
LXI H, Base_addr ; Load the base address
LXI B, Offset/Displacement ; Load offset or displacement
DAD B ; Gives addition of HL and BC register pairs in HL
MOV A, M ; Load the data from memory in accumulator
66
INSTRUCTION SET: ARITHMETIC OPERATIONS
Sl.No Description Opcode Operand Byte M- T-States Hex Code Affected
Cycles Flags
17. Add 8-bit data with content of ADI 8-bit 2 2 7 C6 All
A. Write the result in A. data
18. Add content of registers (B, C, ADD Reg. 1 1 4 Re Hex All
D, E, H, L, A) or that in Mem. 1 2 7 g
memory location pointed by M B 80
with content of A. Write the
result in A. C 81
D 82
E 83
H 84
L 85
M 86
A 87 67
INSTRUCTION SET: ARITHMETIC OPERATIONS
Sl.N Description Opcode Operand Byte M- T-States Hex Code Affected
o Cycles Flags
19. Add 8-bit data with content of ACI 8-bit 2 2 7 CE All
A and Carry (CY in PSW). data
Write the result in A.
20. Add content of registers (B, C, ADC Reg. 1 1 4 Re Hex All
D, E, H, L, A) or that in memory Mem. 1 2 7 g
location pointed by M with B 88
content of A and Carry (CY in
PSW). Write the result in A. C 89
D 8A
E 8B
H 8C
L 8D
M 8E
68
A 8F
INSTRUCTION SET: ARITHMETIC OPERATIONS
Sl.No Description Opcode Operand Byte M- T-States Hex Code Affected
Cycles Flags
21. 8-bit data and Carry (CY in SBI 8-bit 2 2 7 DE All
PSW) are subtracted from data
content of A and write the
result in A.
22. The content of registers (B, C, SBB Reg. 1 1 4 Re Hex All
D, E, H, L, A) or that in Mem. 1 2 7 g
memory location pointed by M B 98
and Carry (CY in PSW) are
subtracted from the content of C 99
A and the result is written in D 9A
A. E 9B
H 9C
L 9D
69
M 9E
A 9F
INSTRUCTION SET: ARITHMETIC OPERATIONS
Sl.No Description Opcode Operand Byte M- T-States Hex Code Affected
Cycles Flags
23. 8-bit data is subtracted from SUI 8-bit 2 2 7 D6 All
content of A and write the data
result in A.
24. The content of registers (B, C, SUB Reg. 1 1 4 Re Hex All
D, E, H, L, A) or that in Mem. 1 2 7 g
memory location pointed by M B 90
is subtracted from the content
of A and the result is written C 91
the result in A. D 92
E 93
H 94
L 95
M 96
70
A 97
INSTRUCTION SET: ARITHMETIC OPERATIONS
Sl.No Description Opcode Operand Byte M- T- Reg. Hex Affected
Cycles States Pair Code Flags
25. Add content of register pair DAD Reg. pair 1 3 10 BC 09 No Flag
(BC, DE, HL, SP) with content
of HL and write it in HL.
DE 19
Stack Operation
HL 29
SP 39
71
INSTRUCTION SET: ARITHMETIC OPERATIONS
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected Flags
26. The hexadecimal content of A is DAA - 1 1 4 27 ALL Flags, Only
converted to two 4-bit binary- instruction to use AC
coded (BCD) digits. flag internally.
1. If the value of the low-order four bits ( - ) in the accumulator is greater than 9 or if AC flag is set, the instruction
adds 06H (i. e. adding 6 to low-order four bits).
2. If the value of the high-order four bits ( - ) in the accumulator is greater than 9 or if the CY flag is set, the
instruction adds 60H (i. e. adding 6 to high-order four bits).
Example:
Add decimal no. 85 and 68 . So, will perform addition in HEX (or binary) 44H + 55H = 99H.
But we want to generate decimal values in BCD format and will use DAA
= 85 = 1000 0101
= 68 = 0110 1000
= = 1110 1101 72
+ 66 = 0110 0110
= 53 = 0101 0011 ; =1
INSTRUCTION SET: INCREMENT OPERATION (+ 1)
Sl.No Description Opcode Operand Byte M-Cycles T-States Reg. Hex Affected
Flags
27. The content of registers (B, C, INR Reg. 1 1 4 B 04 S, Z, P, AC
D, E, H, L, A) or that in Mem. 1 3 10 C 0C
memory location pointed by M
is increased by 1and the result D 14
is written in same place i.e. E 1C
register of memory location. H 24
L 2C
M 34
A 3C
28. The content of register pair INX Reg. pair 1 1 6 B 03 No flag
(BC, DE, HL) is increased by D 13
1and the result is written in
same place i.e. register of Stack Operation H 23
73
memory location. SP 33
INSTRUCTION SET: DECREMENT OPERATION (- 1)
Sl.No Description Opcode Operand Byte M-Cycles T-States Reg. Hex Affected
Flags
29. The content of registers (B, C, DCR Reg. 1 1 4 B 05 S, Z, P, AC
D, E, H, L, A) or that in Mem. 1 3 10 C 0D
memory location pointed by M
is decreased by 1and the D 15
result is written in same place E 1D
i.e. register of memory H 25
location.
L 2D
M 35
A 3D
30. The content of register pair INX Reg. pair 1 1 6 B 0B No flag
(BC, DE, HL) is decreased by D 1B
1and the result is written in
same place i.e. register of Stack Operation H 2B
74
memory location. SP 3B
INSTRUCTION SET: LOGICAL OPERATIONS
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected
Flags
31. 8-bit data is logically ANDed ANI 8-bit 2 2 7 E6 S, Z, P are
with content of A and the data modified, CY
result is written in A. is reset and
AC is set.
32. The content of registers (B, C, ANA Reg. 1 1 4 Reg Hex S, Z, P are
D, E, H, L, A) or that in Mem. 1 2 7 B A0 modified, CY
memory location pointed by M is reset and
is logically ANDed with the C A1 AC is set.
content of A and the result is D A2
written in A. E A3
H A4
L A5
M A6
75
A A7
INSTRUCTION SET: LOGICAL OPERATIONS
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected
Flags
33. 8-bit data is logically ORed ORI 8-bit 2 2 7 F6 S, Z, P are
with content of A and the data modified, CY
result is written in A. & AC are
reset.
34. The content of registers (B, C, ORA Reg. 1 1 4 Reg Hex S, Z, P are
D, E, H, L, A) or that in Mem. 1 2 7 B B0 modified, CY
memory location pointed by M & AC are
is logically ORed with the C B1 reset.
content of A and the result is D B2
written in A. E B3
H B4
L B5
M B6
76
A B7
INSTRUCTION SET: LOGICAL OPERATIONS
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected
Flags
35. 8-bit data is logically XORed XRI 8-bit 2 2 7 F6 S, Z, P are
with content of A and the data modified, CY
result is written in A. & AC are
reset.
36. The content of registers (B, C, XRA Reg. 1 1 4 Reg Hex S, Z, P are
D, E, H, L, A) or that in Mem. 1 2 7 B A8 modified, CY
memory location pointed by M & AC are
is logically XORed with the C A9 reset.
content of A and the result is D AA
written in A. E AB
H AC
L AD
M AE
77
A AF
INSTRUCTION SET: LOGICAL OPERATIONS
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected Flags
37. If (A) < Data then CY = 1, Z = 0, CPI 8-bit 2 2 7 FE ALL
data
If (A) = Data then CY = 0, Z = 1,
If (A) > Data then CY = 0, Z = 0,
38. If (A) < (Reg./Mem.) then CY = 1, CMP Reg. 1 1 4 Reg Hex All
Z = 0, Mem. 1 2 7
B B8
If (A) = (Reg./Mem.) then CY = 0, C B9
Z = 1,
D BA
If (A) > (Reg./Mem.) then CY = 0,
Z = 0, E BB
H BC
L BD
M BE
A BF
78
INSTRUCTION SET: COMPLEMENT
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected
Flags
39. Content of A is complemented CMA - 1 1 4 2F No Flag
and written in is A i.e. 1’s
complement
40. CY bit is complemented / CMC - 1 1 4 3F Only CY
toggled
41. CY bit is set STC - 1 1 4 37 Only CY
79
INSTRUCTION SET: BIT ROTATION
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected Flags
42. CY and each bit of the content RAL - 1 1 4 17 Only CY
of A (i.e. total 9 bits) are
rotated left by 1 position. D7 of
A moves to CY and CY moves to
D0 of A.
43. CY and each bit of the content RAR - 1 1 4 1F Only CY
of A (i.e. total 9 bits) are
rotated right by 1 position. D0
of A moves to CY and CY moves
to D7 of A.
44. Each bit of the content of is RLC - 1 1 4 07 Only CY
rotated left by 1 position. D7 of
A moves to CY and D0 of A.
45. Each bit of the content of is RRC - 1 1 4 0F Only CY
rotated right by 1 position. D0
of A moves to CY and D7 of A. 80
INSTRUCTION SET: JUMPING TO MEMORY LOCATION
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected Flags
46. The 16-bit address written in PC JMP 16-bit 3 3 10 C3 No Flag
unconditionally /PC points to the address
given 16-bit address.
47. PC points to the given 16-bit JC 16-bit 3 3 if true 10 if true DA No Flag
address if CY = 1 address 2 if false 7 if false
PC points to the given 16-bit JNC D2
address if CY = 0
PC points to the given 16-bit JP F2
address if S = 0
PC points to the given 16-bit JM FA
address if S = 1
PC points to the given 16-bit JPE EA
address if P = 1 (Even Parity)
PC points to the given 16-bit JPO E2
address if P = 0 (Odd Parity)
PC points to the given 16-bit JZ CA
address if Z = 1
81
PC points to the given 16-bit JNZ C2
address if Z = 0
INSTRUCTION SET: CALL SUBROUTINE
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected Flags
48. PC points to the given 16-bit CALL 16-bit 3 5 18 CD No Flag
address location after pushing its address
current content –address of next
instruction –on stack.
49. PC points to the given 16-bit CC 16-bit 3 5 if true 18 if true DC No Flag
address if CY = 1 followed by push address 2 if false 9 if false
PC points to the given 16-bit CNC D4
address if CY = 0 followed by push
PC points to the given 16-bit CP F4
address if S = 0 followed by push
PC points to the given 16-bit CM FC
address if S = 1 followed by push
PC points to the given 16-bit CPE EC
address if P = 1 followed by push
PC points to the given 16-bit CPO E4
address if P = 0 followed by push
PC points to the given 16-bit CZ CC
address if Z = 1 followed by push 82
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected Flags
50. Program sequence is transferred RET - 1 3 10 C9 No Flag
from subroutine to call program; it is
equivalent to POP PC.
51. Equivalent to POP PC if CY = 1 RC - 1 3 if true 12 if true D8 No Flag
1 if false 6 if false
Equivalent to POP PC if CY = 0 RNC D0
Equivalent to POP PC if S = 0 RP F0
Equivalent to POP PC if S = 1 RM F8
Equivalent to POP PC if P = 1 RPE E8
Equivalent to POP PC if P = 0 RPO E0
Equivalent to POP PC if Z = 1 RZ C8
Equivalent to POP PC if Z = 0 RNZ C0
83
INSTRUCTION SET: INPUT & OUTPUT
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected Flags
52. The binary values at 8-bit port IN 8-bit 2 3 10 DB No Flag
is read and written in A; the port
same port address is placed on add.
both lower byte (AD0-AD7) and
higher bytes (A8-A15) of system
bus during execution
53. The content of A is written on OUT 8-bit 2 3 10 D3 No Flag
the 8-bit port; the same port port
address is placed on both lower add.
byte (AD0-AD7) and higher
bytes (A8-A15) of system bus
during execution
84
INSTRUCTION SET: MACHINE CONTROL
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected Resart
Flags Add. (H)
54. PC points to an address location RST 0 1 3 12 C7 No Flag 0000
in page 0 of memory associated 1 CF 0008
to each of the 8 restart
instruction, after pushing its 2 D7 0010
current content –address of next 3 DF 0018
instruction –on stack. 4 E7 0020
5 EF 0028
6 F7 0030
7 FF 0038
55. Enables interrupts EI - 1 1 4 FB
56. Disables interrupt DI - 1 1 4 F3
85
INSTRUCTION SET: MACHINE CONTROL
86
INSTRUCTION SET: MACHINE CONTROL
87
INSTRUCTION SET: MACHINE CONTROL
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected
Flags
57. Set Interrupt Mask SIM - 1 1 4 30 No Flag
88
INSTRUCTION SET: MACHINE CONTROL
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected
Flags
58. Read Interrupt Mask RIM - 1 1 4 20 No Flag
89
INSTRUCTION SET: MACHINE CONTROL
Sl.No Description Opcode Operand Byte M-Cycles T-States Hex Code Affected
Flags
59. Gives 1 clock period delay /No NOP - 1 1 4 00 No flag
operation
60. The processor halts & enters into HLT - 1 2 or 5 or 76 No flag
wait state more more
90