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Registration Form Course Coordinators fromAcademy

Name of the Applicant (first, last):  Prof. Ratnajit Bhattacharjee


………………………………………………………. Affix passport Principal Investigator,
………………………………………………………. size E&ICT Academy, IIT Guwahati.
Father’s Name:………………………………………. photograph  Dr. Gaurav Trivedi An Initiative of
Mother’s Name:…………………………................... Co-Principal Investigator, Ministry of Electronics & Information Technology
Gender:……...………………………………..………………………………. E&ICT Academy, IIT Guwahati. (MeitY),
Date of Birth:…………...………………………………….............................. Government of India
Experts from VSD
Designation: Electronics & ICT Academy
……………………………………....................................................................  Mr. Kunal Ghosh IIT Guwahati, Assam
Highest Qualification: ………………………………………………………. Director and Co-founder
Name and Address of the Organization/Institute:…………………………… VLSI System Design (VSD) Corp. Pvt.
Online Training Programme on
……………………………………………………………………………….. Course Contents VLSI System Design using open source EDA
Postal Address:……………………………………………………………….
( 23 – 27 September, 2019)
……………………………………………………………………………….  Day 1: To study the importance of standard cell library
Category : (GEN/OBC/SC/ST/Others)………………………………………. and design & characterize one cell using MAGIC
City/town:………………………………………………...………………….. Layout tool and ngSPICE for SPICE simulations.
Email:…………………………………………………………….................... (Theory – 3 hours, Lab – 3 hours)
 Day 2: To study various components of RISC-V
Phone Number:……………………………………………………………….. microprocessor based SoC and review all components
Mobile Number:………………………………………………….................... using MAGIC Layout tool.
Transaction ID:………………………………………………………………. (Theory – 2 hours, Lab – 4 hours)
Signature of the  Day 3: To do pre-layout timing analysis of SoC using
Applicant:………………………………………………….............................
OpenSTA, chip planning using MAGIC and block-level
placement/routing using qflow RTL2GDS opensource
..........................................................................................................................
EDA toolchain.
Organized in association with
Designation....................................................................................................... (Theory – 2 hours, Lab – 4 hours)
 Day 4: To do hierarchical placement/routing using pads in association with
Course Outcome and blocks, and perform sign-off checks viz.
LVS/DRC using Magic.
(Theory – 1 hour, Lab – 5 hours)
 Build, Verify and PNR any design, for which you have
 Day 5: To perform post-layout timing analysis using
an RTL
OpenSTA and engineering change order (ECO) using
 Do entire floor planning of chip using open-source EDA
Tritonsizer.
tools
(Theory - 3 hours, Lab – 3 hours) VLSI System Design (VSD) Corp. Pvt.
 Characterize any post-layout design in terms of Ltd.
frequency, net count, instance count, runtime and many
more Registration Fee
 Run a full physical design flow from RTL design to Course Date: 23 – 27 September, 2019
GDSII, making it ready for tape-out.  Rs. 2,500/- (@ Rs. 500/- per module) for Faculties, Last Date of Registration: 16/09/2019
 Students will be able to do a real full chip static timing Industry Personnel, Student & Research scholars. (Online Registration Link will be open from 20.08.2019)
analysis with $0 spent, as designs and tools used in this
workshop are open-source.
Objective of the Course About E&ICT Academy About VLSI System Design Corporation Pvt.
Building a chip is like building a city... .
Ltd.
Electronics and ICT Academy is an initiative of Ministry
We will review major components of chip designing and VSD is supporting a community where more than millions of
move from "chip designing" to "chip planning" of Electronics & Information Technology (MeitY), Govt.
people learn, share, and work together to build a chip. At VSD,
Chip Planning involves lot of decision making like, analog of India for Faculty/ Research Scholar Development where we always promote “open source,” we’re promoting about
peripheral (ADC, DAC, POR, etc.), digital peripheral Programme. a proven method of collaborating to create technology. The
(UART, flash controller), memory mapping, top level Academy has planned short term training programmes on freedom to see the design, to learn from it, to ask questions and
connections like pad-frame, level-shifters, GPIO and many offer improvements: This is the open source way.
fundamental and advanced topics in IT, Electronics &
more. Our Initiatives - “Design at $0” is an initiative driven by our team
Do you want to know what it is like to build a city? Did you Communication, Product Design, Manufacturing with at VSD. Working in open environment is much easier process as
know there is no standard definition for GPIOs? That’s the hands on training and project work. all the resources are openly available, but here arises the loophole.
whole point of designing an SOC. Figuring out what things Indian Institute of Technology Guwahati, the sixth When ample resources are available, its highly confusing where to
you are going to control outside of the CPU and memory begin and how to use them in correct sense?
member of the IIT fraternity, was established in 1994. The
mapping them. Our team has been working towards this niche field, to organize all
If you look at any microcontroller e.g. PIC microcontroller, academic programme of IIT Guwahati commenced in
the open source in a systematic way so any person interested to
the only way to know how you access their ADC or their 1995. design chip just has to land on our page and begin the journey
UART is to go look at their documentation and find out towards developing a chip at ZERO cost.
where’s the memory map address for this Also, we are working towards "how he can earn through that
Finally, we take the chip forward and implement using end- design?"
to-end open-source EDA tools. It means, you can start Current Reach – As of 2019, VSD and its partners have released
innovating on a design, build RTL and do 28 online VLSI courses and was successfully able to teach ~18000
synth/PD/LVS/DRC all using open source EDA framework. to ~20000 students around 135 countries in 42 different languages,
through its unique info-graphical and technology mediated
Contact Details learning techniques. Below image shows the geographical spread
of VSD online courses
For more details or any queries please contact
Project Manager,
E&ICT Academy, IIT Guwahati
Who Can Attend
Email: eictacad@iitg.ac.in, eictacad@gmail.com Programme is open to Faculties, Research Scholars, PG &
Phone No: +91-3612583182 UG Students from Universities, Colleges & Schools. Industry
Mobile No: +91 7086502139 Personnel working in the concerned/allied discipline may also
(Working Hours 9:30 am to 5:30 pm) apply.
https:/ www.facebook.com/eictacadguwahati
How to Apply Contact Details from VSD
Mode of Payment: Online Only
Mr. Kunal Ghosh
(RTGS/NEFT) Online – The participants may log on to the E&ICT Director and Co-founder
Academy, IIT Guwahati website: VLSI System Design (VSD) Corp. Pvt.
For Online Transfer http://eictacad@iitg.ac.in and fill up the google doc
Bank Name : State Bank of India Email: vsd@vlsisystemdesign.com
application form.
Account Name: IIT Guwahati R and D E and ICT
Academy For details of the programme and course
Account No. : 36071160089 Contact Hours for the Course
30 Hrs (Theory & Hands-on) contents etc., please log on to Electronics and
IFSC Code : SBIN0014262
Bank Name : State Bank of India ICT Academy website:
Bank Address: IIT Guwahati, GHY- 39. http://eict.iitg.ac.in/index.html