Experiment-1

Aim: To Verify a. Demorgan’s theorem for 2 variables

b. The sum-of products & product-of-sum expressions using universal gates

a. Demorgan’s theorem for 2 variables:

Theorem:
Complement of any Boolean expression is found by DeMorgan's theorem. It allows large
inversion bars on a Boolean expression may be broken up into the smaller inversion bars over
individual variables, if the sign between the variables is changed. The DeMorgan's first theorem
and second theorem are as below:

Theorem: 1. “Complement of product is equal to sum of complements”.

i.e. ̅̅̅̅̅̅̅
A ∙B = A̅ +B ̅ --------1

2. “Complement of sum is equal to product of complements”.

i.e. ̅̅̅̅̅̅̅
A+B= A ̅ ∙ B̅ --------2

Equation 1 is verified as in below Logic diagram & Truth Table:

̅̅̅̅̅̅
Y1=A∙B
A
B

̅ +B
Y2=A ̅

A B ̅̅̅̅̅̅ Y2=A
Y1=A∙B ̅ +B
̅
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0

Equation 2 is verified as in below Logic diagram & Truth Table: -

̅̅̅̅̅̅̅
Y2=A+B
A
B

̅ ∙B
Y1=A ̅

E&CE Dept.,SLNCE,Raichur 1
 A B Y1=A̅ ∙B ̅̅̅̅̅̅̅
̅ Y2=A+B
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0

Components required: Digital Trainer Kit, Patch cords

IC’s required:
1. IC 7404- Hex inverter- 1 no
2. IC 7432- Quad 2-inpur OR gate – 1 no
3. IC 7408- Quad 2-input AND gate- 1 no

b. Verify sum-of products & product-of-sum expressions using universal gates

Principle:
Gates NAND and NOR are known as universal gates, because any logic gates or Boolean
expression can be realized by either NAND or NOR gate alone. Each product term in the SOP
expression is called minterm and each sum term in the POS expression is called maxterm. SOP
expression can be economically realized using NAND gates and POS expression can be
economically realized using NOR gates

Given SOP Expression is f (a, b, c) = Σm (3, 5, 6, 7)

= a b̅ c̅ + a b̅ c + a b c̅+ a b c

a b c x
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

Simplifying above using K-map:

bc
a 00 01 11 10
0 0 0 1 0
1 0 1 1 1

∴ f (a,b,c) = ab + ac + bc

E&CE Dept.,SLNCE,Raichur 2
Implementing above simplified equation using
1. NAND gates:

a
b

2. NOR gates:
a
b

IC’s required:
1. IC 7404 -Hex inverter- 1 no
2. IC 7400- Quad 2-input NAND gate – 1 no
3. IC 7410- Triple 3-input NAND gate- 1 no
4. IC 7402- Quad 2-input NOR gate – 2 no
3. IC 7427- Triple 3-input NOR gate- 1 no

Given POS Expression is g (a, b, c) = Σm (0, 1, 2, 4)

=(a + b + c)(a + b + c̅)(a + b̅ + c)(a̅ + b + c)

Simplifying using K-map:

bc
00 01 11 10
a
0 0 0 1 0
1 0 1 1 1

∴ Simplified equation, g (a, b, c) = (a + b) (a + c)(b + c)

E&CE Dept.,SLNCE,Raichur 3
Implementing above simplified equation using
1. NAND gates:

a
b

2. NOR gates:
a
b

Components required: Digital Trainer Kit, Patch cords

IC’s required:
1. IC 7404 -Hex inverter- 1 no
2. IC 7400- Quad 2-input NAND gate – 2 no
3. IC 7410- Triple 3-input NAND gate – 1 no
4. IC 7402- Quad 2-input NOR gate – 2 no
5. IC 7427- Triple 3-input NOR gate- 1 no

Procedure:
1. Rig up the circuit as per the circuit diagram
2. Give logical inputs as per the respective truth table
3. Observe the logical output & verify with your truth table

Result:
DeMorgans theorem and postulate of Boolean algebra are verified. Sum of products and
product of sum expressions are realized using universal gates.

E&CE Dept.,SLNCE,Raichur 4
 Experiment-2

Aim: To Design & Implement a. Full Adder (FA) using basic logic gates
b. Full Subtractor (FS) using basic logic gates

a. Full Adder (FA) using basic logic gates

Theory:
Full Adder is a logical circuit, which performs addition of three bits (i.e. addition of two
bits with previous carry) and provides an output with a Sum and Carry. It can be built using 2-
half adders and an OR gate

a. FA Truth Table: -
Inputs Output
A B Cin Sum (S) Carry (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Boolean Expression for Output Sum, S is given by

bc
a 00 01 11 10
0 0 1 0 1
1 1 0 1 0

̅ B Cin+A B
∴ S=A ̅ in+A B Cin or
̅ Cin+A B C A⊕B ⊕Cin
Boolean Expression for Output Carry, Cout is given by

bc
a 00 01 11 10
0 0 0 1 0
1 0 1 1 1

∴ Cout=A B +B Cin+A Cin

Logic Diagram of FA using basic gates & XOR: -

1
A 3
B
2 4 S
6
Cin
5

4
6
1
1 3 Cout
3 5
2
2

E&CE Dept.,SLNCE,Raichur 5
b. Full Subtractor (FS) using basic logic gates

Theory:
Full Subtractor is a logical circuit, which performs Subtraction of three bits and provides
an output with a Difference and Borrow, It can be built using 2-half Subtractor and an OR gate.

a. FS Truth Table
Inputs Output
A B Bin Difference (D) Borrow (Bout)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Boolean Expression for Output Difference, D is given by

B Bin
A 00 01 11 10
0 0 1 0 1
1 1 0 1 0

̅B
∴ D=A ̅BB
̅ Bin+A ̅in+A B
̅ ̅̅̅̅
Bin+A B Bin or A⊕B ⊕Bin

Boolean Expression for Borrow, Bout is given by

B Bin
A 00 01 11 10
0 0 1 0 0
1 1 1 1 0

∴ Bout = A̅ Bin + A̅ B + B Bin

Logic Diagram of FS using basic gates & XOR: -

1
A 3
B 4 D
2
6
Bin
1 3 5

4 4
2 6
1
1 3 Bout
3 5
2
2

E&CE Dept.,SLNCE,Raichur 6
Components required: Digital Trainer Kit, Patch cords

IC’s required:
1. IC 7404-Hex Inverter- 1 no
2. IC 7411- Triple 3-input AND gate – 2 no
3. IC 7486- Quad 2-input XOR gate – 1 no
5. IC 7425 –Dual 4-input NOR gate – 1 no

Procedure:
1. Rig up the circuit as per the circuit diagram
2. Give logical inputs as per the respective truth table
3. Observe the logical output & verify with truth table

Result:
The Logic circuit of Full Adder and Subtractor was constructed and the truth table was
verified.

E&CE Dept.,SLNCE,Raichur 7
 Experiment- 3

Aim: To Design & implement 4-bit Parallel Adder/Subtractor using IC 7483

Principle:
IC 7483 performs the addition of two 4-bit binary numbers A3 A2 A1 A0 and B3 B2 B1
B0 and carry input Cin to give the output S3 S2 S1 S0 and carry out Cout. In order to add two
numbers A3A2 A1A0 and B3B2B1B0, the two numbers are given to input terminals 1, 3, 8, 10
and 16, 4,7,11 of the IC 7483 and carry Cin to the terminal 13 is set to zero. To subtract two
numbers by two’s complement method Cin is set to ‘1’ which add’s the 2’s complement of the
second number to each of the four bits of the first numbers. The difference is taken from S3 S2
S1 S0 & if carry generated indicates difference is negative.

Logic Diagram:
B3 B2 B1 B0
0/1
0: For Parallel Adder
1: For Parallel Subtractor

A3 A2 A1 A0

1 3 8 10 16 4 7 11
VCC 5
7483 CIN
GND 12
14 15 2 6 9

GND
GND
COUT S2
S3 S1 S0

Components required: Digital Trainer Kit, Patch cords

IC’s required:
1. IC 7483- Parallel Adder/Subtractor- 1 no
2. IC 7486-Quad 2-input XOR gate-1 no

Observation and calculations:

4 Bit adder operations:
1. Let A = 1100 (A4 A3 A2 A1), B = 0011 (B4B3 B2 B1) Then
Sum (S4 S3 S2 S1) = 1111 and Cout = 0 (With S = 0 and Cin = 0).
2. Let A = 1001 (A4 A3 A2 A1), B = 1101(B4B3 B2 B1) Then
Sum (S4 S3 S2 S1) = 0110 and Cout = 1 (With S = 0 and Cin = 0).

4 Bit Subtractor operations:

1. Let A = 1001 (A4 A3 A2 A1), B = 0011 (B4B3 B2 B1) Then
1’s complement of subtrahend is 1100
2’s complement of subtrahend is 1100+1 =1101
1001(A4 A3 A2 A1) +1101 (B4 B3 B2 B1) = 0110 (S4 S3 S2 S1) with Cout = 1
indicating the result is positive & is in normal form.

E&CE Dept.,SLNCE,Raichur 8
 2. Let A = 0010 (A4 A3 A2 A1), B = 0011 (B4B3 B2 B1) Then
1’s complement of subtrahend is 1100
2’s complement of subtrahend is 1100+1=1101
0010 (A4 A3 A2 A1) +1101 (B4 B3 B2 B1) = 1111 (S4 S3 S2 S1) with Cout = 0
indicating the result is negative & is in 2’s complement form.

Procedure:
1. Connect ground and Vcc to 7483 IC from trainer kit through patch cords.
2. Connect inputs A3 A3 A2 A0 and B3 B2 B1 B0 to logic input switches.
3. Connect Cin from pin no.13 to logic 0 to add numbers or to logic 1 subtract numbers
4. Connect S0, S1, S2, S3 and carry out (CY0) from pin nos. 9, 6, 2, 15 and 14 to the output
led’s.

Result:
The operations of Full Adder & Full Subtractor using IC 7483 are studied.

E&CE Dept.,SLNCE,Raichur 9
 Experiment-4

Aim: To Design and implement 4-bit comparator using IC 7485

Principle:
A comparator used to compare two 4-bit words. The two 4-bit numbers are word A:
A3A2A1A0, and word B: B3 B2B1B0. So the circuit has 8 inputs and 3 binary outputs: A>B,
A=B and A<B.
Circuit:
B3 1 16 Vcc

(A<B)in 2 I 15 A3

(A=B)in 3 C 14 B2
Vcc
(A>B)in 4 7 13 A2

(A>B)out 5 4 12 A1

(A=B)out B1
6 8 11
(A<B)out 7 5 10 A0

GND B0
8 9

Truth Table:
A B Output
A3 A2 A1 A0 B3 B2 B1 B0 A>B A<B A=B
0 0 0 0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 1 0 1 0
0 1 1 0 0 0 1 0 1 0 0

Components required: Digital Trainer Kit, Patch cords

IC’s required:
1. IC 7485-01 no’s

Procedure:
1. Check all the components for their working.
2. Insert the appropriate ICs into the IC base.
3. Make connections as shown in the circuit diagram
4. Verify the Truth Table and observe the outputs.

Result:
The operation of 4-bit Magnitude comparator is studied.

E&CE Dept.,SLNCE,Raichur 10
 Experiment-5

Aim: To Realize a. 4:1 Multiplexer using gates

b. 3-Variable function using IC 74151 (8:1 MUX)

a. 4:1 Multiplexer using gates

Principle:
A multiplexer (MUX) is a many to one device. It allows input from many different
sources to be transmitted to a common destination. The 4-to1 multiplexer has four inputs (D0,
D1, D2, and D3) as well as two selector inputs (A and B). With the selector inputs it is possible to
switch one of the inputs to the output (Y).

Design:
Truth Table:
Select Inputs Data Inputs Output
A B D3 D2 D1 D0 Y
0 0 0 0 0 X D0 (may be 0 or 1)
0 1 0 0 X 0 D1 (may be 0 or 1)
1 0 0 X 0 0 D2 (may be 0 or 1)
1 1 X 0 0 0 D3 (may be 0 or 1)

∴ Y=A ̅B̅ D0 + A̅ B D1 + A B
̅ D2 + A B D3
Implementing above equation using logic gates as below:
Circuit:
A B
1 3

2 4 1
2 12
D0 13

3
6
D1 4
5
1
6
2
9 10 4
D2 10
5
11

D3 1
12
2
13

Components required: Digital Trainer Kit, Patch cords

IC’s required:
1. IC 7410- Triple 3-input NAND gate- 2 no
2. IC 7420- Dual 4-input NAND gate – 1 no
3. IC 7404- Hex Inverter- 1 no

Procedure:
1. Rig up the circuit as per the circuit diagram
2. Give logical inputs as per the respective truth table
3. Vary the inputs A & B with data inputs (Dx) connected to 1 or 0 & verify truth table

Result:
Realization of 4:1 Mux is done successfully.
E&CE Dept.,SLNCE,Raichur 11
b. 3-Variable function using IC 74151 (8:1 MUX)
Let the function is, f (x, y, z) = Σm (1, 2, 4, 5, 7)

Truth Table:

̅
E x y z f
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1

Logic Diagram:
Vcc

D0
4 16 Vcc
D1 3
D2 2 I
6 NC
D3 1 C
D4 15 7
D5 14 4
5 f
D6 13 1
D7 12 5
A 11 1
z
y B 10

x C 9
Enable 7 8

Components required: Digital Trainer Kit, Patch cords

IC’s required:
1. IC 74151- Multiplexer (8:1)

Procedure:
1. Rig up the circuit as per the circuit diagram
2. Give logical inputs as per the respective truth table
3. Vary the inputs A & B with data inputs (Dx) connected to 1 or 0 & verify truth table

Result:
Realization of 3-variable function using IC 74151(8:1) Multiplexer has been done

E&CE Dept.,SLNCE,Raichur 12
 Experiment-6

Aim: To Realize 1:8 Demux and 3:8 decoder using IC 74138

Principle:
A decoder is a combinational circuit that converts binary information from n input lines to
a maximum of 2n unique output lines. A 3: 8 decoder has 3-inputs and & 8 active low output
lines.
If IC 74138 enabled, 3 binary select inputs (A, B, and C) determine which one of the
outputs will go low. If enable input G1 is held low or either G2 or G3 is held high, the decoding
function is inhibited and all the 8 outputs go high.

Pinout of 74138:

Circuit:
C B A

1 2 3
16
Vcc

I 15 Y0

C 14 Y1

7 13 Y2
4 12 Y3
1 11 Y4
Vcc 3 10 Y5
G1 6
8 9 Y6
G2 5
7 Y7
G3 4
8

E&CE Dept.,SLNCE,Raichur 13
Truth Table:
Inputs
Outputs
Enable Select
G1 ̅2
G ̅3
G C B A ̅
Y0 ̅
Y1 ̅
Y2 ̅
Y3 ̅
Y4 ̅
Y5 ̅
Y6 ̅
Y7
1 0 0 0 0 0 0 1 1 1 1 1 1 1
1 0 0 0 0 1 1 0 1 1 1 1 1 1
1 0 0 0 1 0 1 1 0 1 1 1 1 1
1 0 0 0 1 1 1 1 1 0 1 1 1 1
1 0 0 1 0 0 1 1 1 1 0 1 1 1
1 0 0 1 0 1 1 1 1 1 1 0 1 1
1 0 0 1 1 0 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0

Components required: Digital Trainer Kit, Patch cords

IC’s required:
1. IC 74138- Decoder (3:8) - 1 no

Procedure:
1. Rig up the circuit as per the circuit diagram.
2. Give logical inputs as per the respective truth table.
3. Vary the inputs A, B, C & check the selected output.

Result:
Realization of 3:8 Decoder using IC 74138 is done.

E&CE Dept.,SLNCE,Raichur 14
 Experiment -7

Aim: Realization of S R Flip Flop and JK Clocked Flip Flop using NAND gates

1. S R Flip Flop

Theory:
The SR flip-flop, also known as a SR Latch, is one of the most basic sequential logic
circuit. SR flip-flop is a one-bit memory bistable device that has two inputs, one which will
“SET” the device (meaning the output = “1”), and is labelled S and another which will “RESET”
the device (meaning the output = “0”), labelled R. The simplest way to make any basic single bit
set-reset SR flip-flop is to connect together a pair of cross-coupled 2-input NAND, to form a Set-
Reset Bistable also known as an active LOW SR NAND Gate Latch.

Logic Diagram:
1
S 3 9
8 Q
2
10

Clock Input
12 11 ̅
Q
4 6
R 13
5

Truth Table:
Inputs Output
Operation
Clk S R Qn+1
0 X X Qn No Change
1 0 0 Qn No Change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 - Intermediate

Theory:
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR
type is defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-
flop (note that in a JK flip-flop, the letter J is for set and the letter K is for clear). When logic 1
inputs are applied to both J and K simultaneously, the flip-flop switches to its complement state,
i.e., if Q=1, it switches to Q=0 and vice versa.

Logic Diagram:

1
2 12 1
J 3 Q
13
2

Clock Input
4 ̅
Q
3 6 6
K 4
5
5

E&CE Dept.,SLNCE,Raichur 15
Truth Table:

Inputs Output
Operation
Clk J K Qn+1
0 X X Qn No Change
1 0 0 Qn No Change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 ̅n
Q Toggle

Components required: Digital Trainer Kit, Patch cords

IC’s required:
1. IC 7400- Quad 2-input NAND gate – 1 no
2. IC 7410- Triple 3-input NAND gate – 2 no

Procedure:
1. Connections are made as shown in the Logic diagrams, using the pin details of
different IC’s used.
2. Switch on the power supply of the Trainer Kit.
3. Verify the Truth Tables of SR and JK FF by applying clock.

Result:
Thus the truth table for clocked SR FF & JK FF are verified.

E&CE Dept.,SLNCE,Raichur 16
 Experiment -8

Aim: To Realize the following shift registers using IC 7474

a. SISO b. SIPO c. PISO d. PIPO

Theory:
In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in
which the output of each flip-flop is connected to the 'data' input of the next flip-flop in the chain,
resulting in a circuit that shifts by one position the 'bit array' stored in it, 'shifting in' the data
present at its input and 'shifting out' the last bit in the array, at each transition of the clock input.
Shift register IC’s are generally provided with a clear or reset connection so that they can be
“SET” or “RESET” as required. Generally, shift registers operate in one of four different modes
with the basic movement of data through a shift register being:

1. Serial-in to Parallel-out (SIPO): The register is loaded with serial data, one bit at a time, with
the stored data being available at the output in parallel form.

2. Serial-in to Serial-out (SISO): The data is shifted serially “IN” and “OUT” of the register, one
bit at a time in either a left or right direction under clock control.

3. Parallel-in to Serial-out (PISO): The parallel data is loaded into the register simultaneously
and is shifted out of the register serially one bit at a time under clock control.

4. Parallel-in to Parallel-out (PIPO): The parallel data is loaded simultaneously into the register,
and transferred together to their respective outputs by the same clock pulse.

Components required: Digital Trainer Kit, Patch cords

IC’s required:
1. IC 7474- Dual D Flip-flop – 2 no
2. IC 7404- Hex Inverter- 1 no
3. IC 7408- Quad 2-input AND gate- 2 no
4. IC 7432- Quad 2-input OR gate- 1 no

1. Serial-in to Serial-out (SISO):

Serial Output
Pre Pre Pre Pre
4 10 2 10
2 5 12 9 2 5 12 9
D1 Q1 D2 Q2 D3 Q3 D4 Q4
Serial Input
Clk Clk Clk Clk
3 ̅1
Q 11 ̅2
Q 3 ̅3
Q 11 ̅4
Q
1 13 1 13
Clr Clr Clr Clr
Clock

E&CE Dept.,SLNCE,Raichur 17
 Function Table:
pre
̅̅̅̅̅ ̅̅̅̅
clr clk D Q1 Q2 Q3 Q4
1 0 0 0 0 0 0 0
1 1 1 1 1 0 0 0
1 1 1 1 1 1 0 0
1 1 1 0 0 1 1 0
1 1 1 1 1 0 1 1
1 1 1 - 0 1 0 1
1 1 1 - 0 0 1 0
1 1 1 - 0 0 0 1

Procedure:
1. Clear all flip flops of register by applying pre̅̅̅̅̅ =1, ̅clr
̅̅̅ =0 so that Q1 Q2 Q3 Q4=0000, then apply
̅̅̅̅̅ =1, ̅clr
pre ̅̅̅ =1 to enable flip flops of shift register.

2. Apply input to Serial input (D1) of FF1 for ex: 1011 and apply clock. With the application of
individual clock pulse the data is shifted from one flip flop to other. After four clock pulses data
1011 is written into shift register (Outputs of all flip flops).

3. Apply another three clock pulses to read stored data serially out from Q4 of FF4. The operation
is as shown in table.

2. Serial-in to Parallel-out (SISO): Parallel Output

Q1 Q2 Q3 Q4

Pre Pre Pre Pre

4 10 4 10
2 5 12 9 2 5 12 9
D1 Q1 D2 Q2 D3 Q3 D4 Q4
Serial Input
Clk Clk Clk Clk
3 ̅1
Q 11 ̅2
Q 3 ̅3
Q 11 ̅4
Q
1 13 1 13
Clr Clr Clr Clr
Clock Input

Function Table:
pre
̅̅̅̅̅ ̅̅̅̅
clr clk D Q1 Q2 Q3 Q4
1 0 0 0 0 0 0 0
1 1 1 1 1 0 0 0
1 1 1 1 1 1 0 0
1 1 1 0 0 1 1 0
1 1 1 1 1 0 1 1

Procedure:
̅̅̅̅̅ =1, ̅clr
1. Clear all flip flops of register by applying pre ̅̅̅ =0 so that Q1 Q2 Q3 Q4=0000, then apply
pre ̅̅̅̅ =1 to enable flip flops of shift register.
̅̅̅̅̅ =1, clr

2. Apply input to Serial input (D1) of FF1 for ex: 1011 and apply clock. With the application of
individual clock pulse the data is shifted from one flip flop to other. After four clock pulses data
1011 is written into shift register (Outputs of all flip flops).

3. The data entered in serial form in above step 2 is read in parallel from outputs i.e Q 1 Q2 Q3 Q4
of flip-flops with no clock pulse requirement.
E&CE Dept.,SLNCE,Raichur 18
 3. Parallel-in to Serial-out (PISO): Parallel Input

̅̅̅̅̅̅
Load/ shift D2 D3 D4

1 2
1 2 4 5 9 10 12 13 1 2 4 5

3 6 8 11 3 6
1 2 4 5 9 10
Serial
Output
Pre 3 Pre 6 Pre 8 Pre
6
D1
4 10 4 10 9
2 D1 Q1 5 12 D2 Q2 9 2 D3 Q3 5 12 D4 Q4
Clk Clk Clk Clk
3 ̅1
Q ̅2
Q 3 ̅3
Q 11 ̅4
Q
11
1 13 1 13
Clr Clr Clr Clr
Clock

Function Table:
pre
̅̅̅̅̅ ̅clr
̅̅̅ clk D Q1 Q2 Q3 Q4
1 0 0 0 0 0 0 0
1 1 1 1 1 0 1 1
1 1 1 - 0 1 0 1
1 1 1 - 0 0 1 0
1 1 1 - 0 0 0 1
Procedure:
̅̅̅̅̅ =1, ̅clr
1. Clear all flip flops of register by applying pre ̅̅̅ =0 so that Q1 Q2 Q3 Q4=0000, then apply
pre ̅̅̅̅ =1 to enable flip flops of shift register.
̅̅̅̅̅ =1, clr

2. Parallel Data Ex: 1011 is entered by applying data direct to inputs of all flip flops i.e D1 D2 D3
D4 = 1011. The entered data can be read serially at FF4 output Q4 after applying three clock
pulses as shown in the function table.
Parallel Input
4. Parallel-in to Parallel-out (PIPO):

D1 D2 D3 D4

Pre Pre Pre Pre

2 2 2
4 10 4 10
2 D1 Q1 5 12 D2 Q2 9 2 D3 Q3 5 12 D4 Q4 9
Clk Clk Clk Clk
3 ̅1
Q ̅2
Q 3 ̅3
Q 11 ̅4
Q
11
1 13 1 13
Clr Clr Clr 2 Clr
Clock

Q1 Q2 Q3 Q4

Parallel Output

E&CE Dept.,SLNCE,Raichur 19
Function Table:
pre
̅̅̅̅̅ ̅̅̅̅
clr clk D Q1 Q2 Q3 Q4
1 0 0 0 0 0 0 0
1 1 1 1 1 0 1 1

Procedure:
̅̅̅̅̅ =1, ̅clr
1. Clear all flip flops of register by applying pre ̅̅̅ =0 so that Q1 Q2 Q3 Q4=0000, then apply
pre ̅̅̅̅ =1 to enable flip flops of shift register.
̅̅̅̅̅ =1, clr

2. Parallel Data Ex: 1011 is be entered by applying data direct to inputs of all flip flops i.e. Q1 Q2
Q3 Q4 = 1011.

3. The above entered Parallel data is read at output of each flip-flop without applying clock pulse
as shown in function table

Result:
The performance of shift registers using D FF are set up and studied.

E&CE Dept.,SLNCE,Raichur 20
 Experiment -9

Aim: To Realize Ring Counter and Johnson Counter using IC 7476

Ring Counter:
It is made by connecting Q & Q ̅ output of one JK FF to J&K input of next FF
respectively. The output of final FF is connected to the input of first FF. To start the counter the
first FF is set by using preset facility and the remaining FF are reset input. When the clock
arrives, the set condition continues to shift around the ring

Logic Diagram:
Q1 Q2 Q3 Q4

Pre Pre Pre Pre

2 7 2 7
4 15 9 11 4 15 9 11
J1 Q1 J2 Q2 J3 Q3 J4 Q4
1
1 6 1 6
Clk Clk Clk Clk
2
K1 ̅1
Q 12
K2 ̅2
Q K3 ̅3
Q ̅4
16 14 10 16 14 12 K4 Q
3 8 3 8
Clr Clr Clr Clr
Clock

Timing Sequence:

Function table:
pre
̅̅̅̅̅ ̅̅̅̅
clr Clk Q1 Q2 Q3 Q4
0 1 0 1 0 0 0
1 1 1 0 1 0 0
1 1 1 0 0 1 0
1 1 1 0 0 0 1
1 1 1 1 0 0 0

Components required: Digital Trainer Kit, Patch cords

IC’s required:
1. IC 7476- Dual JK Flip Flop- 2 no

Procedure:
̅̅̅̅ =0 & pre
1. Initially all FF’s are cleared by making clr ̅̅̅̅̅ =1.
2. pre
̅̅̅̅̅ pin of first FF is made zero to set Q1=1 & later pre̅̅̅̅̅ is raised high.
3. Note down the state of the ring counter on the truth table for successive clock.

E&CE Dept.,SLNCE,Raichur 21
 Johnson counter (Twisted ring counter)
The Johnson counter is built by making a small change in the ring counter circuit. The Q ̅
and Q of the last FFS are connected to the J and K input of the first FF respectively. This is the
Johnson counter

Logic Diagram:
Q1 Q2 Q3 Q4

Pre Pre Pre Pre

2 7 2 7
4 15 9 11 4 15 9
J1 Q1 J2 Q2 J3 Q3 J4 Q4
1 6 1 6
Clk Clk Clk Clk
̅1 14
K1 Q K2 ̅2
Q K3 ̅3
Q K4 ̅4
Q
16 14 12 10 16 14 12
3 8 3 8
Clr Clr Clr Clr
Clock

Timing Sequence:

Function table:
pre
̅̅̅̅̅ ̅clr
̅̅̅ Clk Q1 Q2 Q3 Q4
1 1 0 0 0 0 0
1 1 1 1 0 0 0
1 1 1 1 1 0 0
1 1 1 1 1 1 0
1 1 1 1 1 1 1
1 1 1 0 1 1 1
1 1 1 0 0 1 1
1 1 1 0 0 0 1

Procedure:
1. Initially all FF’s are cleared by making ̅clr̅̅̅ =0 & pre
̅̅̅̅̅ =1.
2. Complement Output Q ̅ 4 of FF4 is set to ‘1’ which is input to FF1 as per logic diagram.
3. Note down the state of the counter on the truth table for successive clock pulses.

Result:
The Realization of Ring Counter and Johnson Counter using IC 7476 are studied.

E&CE Dept.,SLNCE,Raichur 22
 Experiment -10

Aim: Realize the Mod-10 counter using IC 7490

Theory:
Counter is a sequential logic device whose function is to count by advancing the contents
of the counter by one count with each clock pulse. The 74LS90 integrated circuit is basically a
MOD-10 decade counter that produces a BCD output code. The 74LS90 consists of four master-
slave JK flip-flops internally connected to provide a MOD-2 (count-to-2) counter and a MOD-5
(count-to-5) counter.

Pin out of IC 7490:

BD Input 1 14 Input A

R0(1) 2 13 NC

R0(2) 3 IC 12 QA
NC 4 7490 11 QD

Vcc 5 10 GND

Rg(1) 6 9 QB
Rg(2) 7 8 QC

Logic Diagram:
BCD Output
Vcc QA QB QC QD

5 1 12 9 8 11

Clk 14

14 R12 R23 GND

10 S1 6 S2 7

Truth Table:
Clock Outputs
pulse QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0

E&CE Dept.,SLNCE,Raichur 23
Expected Waveform:

Components required: Digital Trainer Kit, Patch cords

IC’s required:
1. IC 7490- 1 no

Procedure:
1. Connections are made as shown in the circuit diagram using 7490.
2. Apply the clock pulse and verify the truth table

Result:
The Mod-10 Counter using IC 7490 is studied.

E&CE Dept.,SLNCE,Raichur 24
 Experiment -11

Aim: Simulate Full- Adder using simulation tool (Multisim 10).

Logic Diagram:
1
A 3
B
2 4 S
6
Cin
5

4
6
1 Cout
1 3
3 5
2
2

Truth Table:
Inputs Output
A B Cin Sum (S) Carry (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Simulation Tool used: Multisim 10.1

Procedure:
1. Connections are done as per the circuit diagram in the software & truth table is
verified.

Result:
Successfully simulated the circuit of full adder using simulation tool

E&CE Dept.,SLNCE,Raichur 25
 Experiment -12

Aim: Simulate Mod-8 Synchronous UP & DOWN Counter using simulation tool
(Multisim10).

Principle: The circuit is a simple 3-bit Up/Down synchronous counter using JK flip-flops
configured to operate as toggle or T-type flip-flops giving a maximum count of zero (000) to
seven (111) and back to zero again. Then the 3-Bit counter advances upward in sequence
(0,1,2,3,4,5,6,7) or downwards in reverse sequence (7,6,5,4,3,2,1,0).

Logic Diagram: QA (LSB) QB QC (MSB)

̅̅̅̅̅̅̅̅
Up/Down

Logic ‘1’ Pre Pre Pre

JA QA JB QB JC QC
Clk Clk Clk
KA ̅A
Q KB ̅B
Q KC ̅C
Q

Clr Clr Clr

Simulation Tool used: Multisim 10.1

Procedure:
1. Connections are done as per the circuit diagram in the software & function is
verified.

Result:
Successfully simulated Mod-8 Synchronous Up/Down counter using simulation tool.

E&CE Dept.,SLNCE,Raichur 26