17/07/2019 Suresh's official blog...

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Min pulse width violation and fixing
http://tech.tdzire.com/what-is-minimum-pulse-width-check-and-pulse-absorption/
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It is important for clock signal to ensure proper performance/functionality of sequential
cells.
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Definition: ►
► 2019 (1)
This check ensures the width of clock should be more than min specified value.
▼
▼ 2018 (33)
►
► July (6)
Ensures that width of the clock signal is wide enough for the cell's internal operations to
complete. i.e,. ►
► June (4)
It is min pulse width of the clock it has to maintain to get a stable output you need. ►
► May (2)
►
► March (4)
Impact:
▼
▼ January (17)
It can't capture at the edge of clock signal. So data may miss at that point.
Clocks
Why does it shrink: List of STA Topics
Due to unequal rise and fall delays of combinational cells. Constraints - brief commands
from start to end
Detailed explanation: Intel interview
Let us assume a clock entering a buffer. If the rise delay of that buffer is more than fall
AMD interview
delay, the output clock will have less width than the input.
Temperature vs delay in lower
technologies
See the following figure which illustrates the same. So think of. what will happen to the
same clock signal, when it passes through a series of same type of buffers. The width of CPPR
the clock signal keeps decreasing, and at a point when the buffer delay is more than the Cross talk effects
clock pulse width, the clock pulse gets absorbed. This is known as Pulse absorption. So
Constraints validation
it is important to perform MPW check.
What are the sing-off checks for
STA during TapeOu...
ETM (Extracted TIming Model):
How to read spef:
RC corners
Min pulse width violation and
fixing
Design Rule Checks: max
trans, max cap
Timing Exceptions
Interview Queries

►
► 2017 (45)
►
► 2010 (8)

How to fix:
Keep symmetry rise and fall delays clock tree cells.

How to constrain in PT:

set timing_enable_clock_constraints true

#define min/max pulse widths

set_pulse_clock_min_width
set_pulse_clock_max_width

#Remove/ignore MPW checks at particular sequential cells

remove_min_pulse_width

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17/07/2019 Suresh's official blog...: Min pulse width violation and fixing
Query:
If asymmetric rise and fall delay cells present in the data path, what checks will be
violated?
- Data path delay means it is arrival time. If arrival time increases, setup violation
comes otherwise hold violation comes.

From other website:

In ETS(or TEMPUS as the newest Cadence tool for STA is called), you will see
a report like this:

1
2
3 ------------------------------------------------------
4
5
6 SEQUENTIAL CLOCK PULS
7

------------------------------------------------------

Pin Required Actua

Pulse Width Wi

------------------------------------------------------

clk_ctrl_reg/CP (high) 0.3202 2.9

In this example, the clock period is 6ns with a duty cycle of 50%.i.e. Here, the
clock signal at clk_ctrl_reg/CP should be high at least for 0.3202ns (please note
that the default time unit is ps in TEMPUS). The actual signal is high for
2.9731ns. Hence there is no minimum pulse width violation at the CP pin for
src_clk.

Constraining the design

Now, let us see how you can specify this constraint for your design.

1. Using .lib file

Minimum pulse width depends on the technology node and the standard
cell library design. You will have these modeled in your .lib file. Look
for timing_type : min_pulse_width; in your liberty file. These
will be defined for clock, reset and preset pins of a flop, or the enable pin of
a latch.

1
2
3 pin (CP) {
4
5
6 clock : true;
7
8
9 direction : input;
10
11
12 max_transition : 2.5;
13
14
15 capacitance : 0.00774191;
16
17
18

timing () {

related_pin : "CP";

timing_type : min_pulse_width;

rise_constraint (mpw_constraint) {

index_1 ("0.1, 0.6, 1.3, 1.9, 2.5");

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17/07/2019 Suresh's official blog...: Min pulse width violation and fixing

values ("0.131, 0.800, 1.596, 2.392, 3.066

fall_constraint (mpw_constraint) {

index_1 ("0.1, 0.6, 1.3, 1.9, 2.5");

values ( "0.361, 0.800, 1.596, 2.392, 3.06

The index_1 is the transition at pin CP, and the last value in the table is the
max_transition of the pin. The values denote the minimum pulse width
values for the pin transition specified.

2. SDC command ‘set_min_pulse_width’

To specifically set the minimum pulse width constraint, you can use the
command set_min_pulse_width

1
2
set_min_pulse_width -high 3.0 [all_clocks]

set_min_pulse_width -low 2.0 [all_clocks]

If neither high now low is specified the constraint applies to both high and
low signal levels.

Reporting the violations

You can use in majority of STA tool, report_timing or a similar command.

report_timing -check_type pulse_width

You can also use the command report_min_pulse_width in TEMPUS to

report the pulse width values.

Posted by sureshkodam at 9:20 PM

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