PROGRAM 7

AIM:-
VHDL Code For 1 Bit Comparator By Data Flow Modelling, Structural
Modelling And Behavioural Modelling
APPARATUS:- Xilinx ISE 14.7
SYSTEM DESCRIPTION:-
A digital comparator or magnitude comparator is a hardware electronic device that takes two
numbers as input in binary form and determine whether one number is greater than, less than
or equal to the other number. Comparators are used in a central processing units (CPU) and
microcontrollers. Examples of digital comparator include the CMOS 4063 and 4585 and the
TTL 7485 and 74682-’89.
The analog equivalent of digital comparator is the voltage comparator. Many
microcontrollers have analog comparators on some of their inputs that can be read or trigger
an interrupt.

LOGIC DIAGRAM:

TRUTH TABLE:
SCHEMATIC:

VHDL CODE IN BEHAVIOURAL STYLE

entity comparator is
Port ( a,b : in STD_LOGIC;
e: in STD_LOGIC;
x,y,z : out STD_LOGIC);
end comparator;

architecture Behavioral of comparator is

begin
process(a,b,e)
begin
if(e = '1') then
if (a>b) then
x<= '1';y<= '0';z<= '0';
elsif (a=b) then
x<= '0';y<= '1';z<= '0';
elsif (a<b) then
x<= '0';y<= '0';z<= '1';
else
x <='X';y<='X'; z <= 'X';
end if ;
end if;
end process ;

end Behavioral;

VHDL CODE IN STRUCTURAL STYLE

Entity comparator_1_bit is

Port(a,b:in STD_LOGIC;

agb,aeb,alb:out STD_LOGIC );

End comparator_1_bit;

Architecture comparator_1_bit_structure of comparator_1_bit is

Component and

Port(INO,IN1:in STD_LOGIC;

OUT: out STD_LOGIC );

End component;

Component xnor2

Port(in2,in3:in STD_LOGIC;

Out1:out STD_LOGIC);

End component;

Component not1

Port(in4:in STD_LOGIC;

Out4:out STD_LOGIC);

End component;

Signal U1,U2 STD_LOGIC;

Begin

A0: and2 port map(a,U2,agb);

A1: and2 port map(U1, b,alb);

N0: not1 port map(a,U1);

N1:not1 port map(b,U2);

X0:xnor2 port map(a,b,aeb);

End comparator_1_bit_structure;

VHDL CODE IN DATAFLOW STYLE

Entity comparator_1_bit is

Port(a,b:in STD_LOGIC;

Result:out STD_LOGIC);

End comparator_1_bit;
Architecture comparator_1_bit_data of comparator_1_bit is

Begin

Result<=”100” when (a>b)else

“010” when(a=b)else

“001”;

End comparator_1_bit_data;

OUTPUT:
PROGRAM 8
AIM:-
VHDL Code For 4 Bit Comparator By Data Flow Modelling, Structural
Modelling And Behavioural Modelling
APPARATUS:- Xilinx ISE 14.7
SYSTEM DESCRIPTION:-
A digital comparator or magnitude comparator is a hardware electronic device that takes two
numbers as input in binary form and determine whether one number is greater than, less than
or equal to the other number. Comparators are used in a central processing units (CPU) and
microcontrollers. Examples of digital comparator include the CMOS 4063 and 4585 and the
TTL 7485 and 74682-’89.
The analog equivalent of digital comparator is the voltage comparator. Many
microcontrollers have analog comparators on some of their inputs that can be read or trigger
an interrupt.

LOGIC DIAGRAM:
TRUTH TABLE:

SCHEMATIC:
VHDL CODE IN BEHAVIOURAL STYLE
entitycomparator_four is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
e : in STD_LOGIC;
x : out STD_LOGIC;
y : out STD_LOGIC;
z : out STD_LOGIC);
endcomparator_four;

architecture Behavioral of comparator_four is

begin
process(a,b,e)
begin
if(e = '1') then
if(a>b)
then x<='1'; y<='0';z<='0';

elsif(a<b)
then x<='0'; y<='0';z<='1';
else
x<='0'; y<='1';z<='0';
end if;
else
x <= 'X';
y <= 'X';
z <= 'X';
end if;
end process;
end Behavioral;

VHDL CODE IN STRUCTURAL STYLE

library ieee;
use ieee.std_logic_1164.all;
entity comp4 is
port(aeqbin,agtbin,altbin:in std_logic;
a,b:in std_logic_vector(3 downto 0);
aeqbout,agtbout,altbout:out std_logic);
end comp4;
architecture comp4_arch of comp4 is
component and2
port(a,b:in std_logic;y:out std_logic);
end component;

component and3
port(a,b,c:in std_logic;y:out std_logic);
end component;

component and4
port(a,b,c,d:in std_logic;y:out std_logic);
end component;

component and5
port(a,b,c,d,e:in std_logic;y:out std_logic);
end component;
component nand2
port(a,b:in std_logic; y:out std_logic);
end component;

component nor2
port(a,b:in std_logic;y:out std_logic);
end component;
component nor6
port(a,b,c,d,e,f:in std_logic; y:out std_logic);
end component;
signal s,p:std_logic_vector(3 downto 0);
signal r:std_logic_vector(7 downto 0);
signal q:std_logic_vector(11 downto 0);
begin
L1:nand2 port map(a(0),b(0),s(0));
L2:nand2 port map(a(1),b(1),s(1));
L3:nand2 port map(a(2),b(2),s(2));
L4:nand2 port map(a(3),b(3),s(3));
L5:and2 port map(s(3),a(3),r(0));
L6:and2 port map(s(3),b(3),r(1));
L7:and2 port map(s(2),a(2),r(2));
L8:and2 port map(s(2),b(2),r(3));
L9:and2 port map(s(1),a(1),r(4));
L10:and2 port map(s(1),b(1),r(5));
L11:and2 port map(s(0),a(0),r(6));
L12:and2 port map(s(0),b(0),r(7));
L13:nor2 port map(r(0),r(1),p(0));
L14:nor2 port map(r(2),r(3),p(1));
L15:nor2 port map(r(4),r(5),p(2));
L16:nor2 port map(r(6),r(7),p(3));
L17:and2 port map(s(3),b(3),q(0));
L18:and3 port map(p(0),s(2),b(2),q(1));
L19:and4 port map(b(1),s(1),p(0),p(1),q(2));
L20:and5 port map(b(0),s(0),p(0),p(1),p(2),q(3));
L21:and5 port map(p(0),p(1),p(2),p(3),altbin,q(4));
L22:and5 port map(p(0),p(1),p(2),p(3),aeqbin,q(5));
L23:and5 port map(p(0),p(1),p(2),p(3),aeqbin,q(6));
L24:and5 port map(p(0),p(1),p(2),p(3),agtbin,q(7));
L25:and5 port map(a(0),s(0),p(0),p(1),p(2),q(8));
L26:and4 port map(a(1),s(1),p(0),p(1),q(9));
L27:and3 port map(a(2),s(2),p(0),q(10));
L28:and2 port map(a(3),s(3),q(11));
L29:and5 port map(p(0),p(1),p(2),p(3),aeqbin,aeqbout);
L30:nor6 port map(q(0),q(1),q(2),q(3),q(4),q(5),agtbout);
L31:nor6 port map(q(6),q(7),q(8),q(9),q(10),q(11),altbout);
end comp4_arch;

OUTPUT: