EE310: Introduction to VLSI Design

Lecture-1

Dr. Gaurav Trivedi

Department of Electronics and
Electrical Engineering
IIT Guwahati
trivedi@iitg.ernet.in
*Adapted from Rabaey’s Digital Integrated
Circuits, ©2002, J. Rabaey et al.]
 Historical Facts:
Transistor Revolution
Transistor –Bardeen (Bell Labs) in 1947
Bipolar transistor – Schockley in 1949
First bipolar digital logic gate – Harris in 1956
First monolithic IC – Jack Kilby in 1959
First commercial IC logic gates – Fairchild 1960
TTL – 1962 into the 1990’s
ECL – 1974 into the 1980’s
Why is designing digital ICs different today than
it was before?

Will it change in future?

The First Computer

The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470
ENIAC - The first electronic computer (1946)
The Transistor Revolution

First transistor
Bell Labs, 1948
The First Integrated Circuits

Bipolar logic
1960’s

ECL 3-input Gate

Motorola 1966
 Intel 4004 Micro-Processor

First microprocessor (1971)

For Busicom calculator
Characteristics
10 mm process
2300 transistors
400 – 800 kHz
4-bit word size
16-pin DIP package
Masks hand cut from Rubylith
Drawn with color pencils
1 metal, 1 poly (jumpers)
Diagonal lines (!)
 Intel 8008 Micro-Processor
8-bit follow-on (1972)
Dumb terminals
Characteristics
10 mm process
3500 transistors
500 – 800 kHz
8-bit word size
18-pin DIP package
Note 8-bit datapaths
Individual transistors visible
 Intel 8080 Micro-Processor
16-bit address bus (1974)
Used in Altair computer
(early hobbyist PC)
Characteristics
6 mm process
4500 transistors
2 MHz
8-bit word size
40-pin DIP package
 Intel 8086/8088 Micro-Processor
16-bit processor (1978-9)
IBM PC and PC XT
Revolutionary products
Introduced x86 ISA
Characteristics
3 mm process
29k transistors
5-10 MHz
16-bit word size
40-pin DIP package
Microcode ROM
 Intel 80286 Micro-Processor
Virtual memory (1982)
IBM PC AT
Characteristics
1.5 mm process
134k transistors
6-12 MHz
16-bit word size
68-pin PGA
Regular datapaths and ROMs
Bitslices clearly visible
 Intel 80386 Micro-Processor
32-bit processor (1985)
Modern x86 ISA
Characteristics
1.5-1 mm process
275k transistors
16-33 MHz
32-bit word size
100-pin PGA
32-bit datapath, microcode
ROM, synthesized control
 Intel 80486 Micro-Processor
Pipelining (1989)
Floating point unit
8 KB cache
Characteristics
1-0.6 mm process
1.2M transistors
25-100 MHz
32-bit word size
168-pin PGA
Cache, Integer datapath, FPU, microcode,
synthesized control
 Intel Pentium Micro-Processor
Superscalar (1993)
2 instructions per cycle
Separate 8KB I$ & D$
Characteristics
0.8-0.35 mm process
3.2M transistors
60-300 MHz
32-bit word size
296-pin PGA
Caches, datapath, FPU, control
 Intel Pentium Pro / II / III
Micro-Processor
Dynamic execution (1995-9)
3 micro-ops / cycle
Out of order execution
16-32 KB I$ & D$
Multimedia instructions
PIII adds 256+ KB L2$
Characteristics
0.6-0.18 mm process
5.5M-28M transistors
166-1000 MHz
32-bit word size
MCM / SECC
 Intel Pentium 4 Micro-Processor
Deep pipeline (2001)
Very fast clock
256-1024 KB L2$
Characteristics
180 – 65 nm process
42-125M transistors
1.4-3.4 GHz
Up to 160 W
32/64-bit word size
478-pin PGA
Units start to become invisible on
this scale
 Intel Pentium M Micro-Processor
Pentium III derivative
Better power efficiency
1-2 MB L2$
Characteristics
130 – 90 nm process
140M transistors
0.9-2.3 GHz
6-25 W
32-bit word size
478-pin PGA
Cache dominates chip area
 Intel Core2 Duo Micro-Processor
Dual core (2006)
1-2 MB L2$ / core
Characteristics
65-45 nm process
291M transistors
1.6-3+ GHz
65 W
32/64 bit word size
775 pin LGA
Much better performance/power
efficiency
 Intel Core i7 Micro-Processor
Quad core (& more)
Refinement of Core architecture
2 MB L3$ / core
Characteristics
45-32 nm process
731M transistors
2.66-3.33+ GHz
Up to 130 W
32/64 bit word size
1366-pin LGA
Multithreading
On-die memory controller
 Intel Atom Micro-Processor
Low power CPU for netbooks
Pentium-style architecture
512KB+ L2$
Characteristics
45-32 nm process
47M transistors
0.8-1.8+ GHz
1.4-13 W
32/64-bit word size
441-pin FCBGA
Low voltage (0.7 – 1.1 V) operation
Excellent performance/power
 Comparison of Processors
104 increase in transistor count, clock frequency over 3 decades!
State-of-the Art: Lead Microprocessors
 Moore’s Law

 In1965, Gordon Moore noted that the

number of transistors on a chip doubled
every 18 to 24 months.

 He made a prediction that semiconductor

technology will double its effectiveness every
18 months
 LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1959
1960
1961
1962

Electronics, April 19, 1965.

1963
1964
1965
1966
1967
1968
1969
1970
Moore’s Law

1971
1972
1973
1974
1975
Evolution in Complexity
 Transistor Counts
1 Billion Transistors
K
1,000,000

100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected

Courtesy, Intel
Moore’s law in Microprocessors

1000

100
2X growth in 1.96 years!
Transistors (MT)

10
P6
Pentium® proc
1 486
386
0.1 286
8086Microprocessors double every 2 years
8085 on Lead
Transistors
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year

Courtesy, Intel
 Die Size Growth
100
Die size (mm)

P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

1
1970 1980 1990 2000 2010
Year
Die size grows by 14% to satisfy Moore’s Law

Courtesy, Intel
 Frequency
10000
Doubles every
1000 2 years
Frequency (Mhz)

P6
100
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Lead Microprocessors frequency doubles every 2 years

Courtesy, Intel
 Power Dissipation
100

P6
Pentium ® proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Lead Microprocessors power continues to increase

Courtesy, Intel
Power will be a major problem
100000
18KW
10000 5KW
1.5KW
500W
Power (Watts)

1000
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004

0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power delivery and dissipation will be prohibitive

Courtesy, Intel
 Power density
10000
Rocket
Nozzle
Power Density (W/cm2)

1000
Nuclear
Reactor
100

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
286 486
8080
1
1970 1980 1990 2000 2010
Year

Power density too high to keep junctions at low temp

Courtesy, Intel
 Not Only Microprocessors
Cell
Phone

Small Power
Signal RF RF

Digital Cellular Market

(Phones Shipped) Power
Management

1996 1997 1998 1999 2000

Analog
Units 48M 86M 162M 260M 435M Baseband

Digital Baseband
(DSP + MCU)

(data from Texas Instruments)

 Productivity Trends
(M)
10,000
10,000,000 100,000
100,000,000
1,000 Logic Tr./Chip 10,000
1,000,000 10,000,000
Tr./Staff Month.
Logic Transistor per Chip

(K) Trans./Staff - Mo.

100
100,000 1,000
1,000,000
Complexity

Productivity
58%/Yr. compounded
10,00010 Complexity growth rate
100
100,000

1,0001 10
10,000
x x
0.1
100 1
1,000
xx
x
21%/Yr. compound
x x Productivity growth rate
x
0.01
10 0.1
100
0.001
1 0.01
10
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
2007
2009
Source: Sematech

Complexity outpaces design productivity

Courtesy, ITRS Roadmap

 Major Design Challenges

• Microscopic issues • Macroscopic issues

ultra-high speeds – time-to-market
power dissipation and supply – design complexity
rail drop (millions of gates)
growing importance of – high levels of abstractions
interconnect – reuse and IP, portability
noise, crosstalk – systems on a chip (SoC)
reliability, manufacturability – tool interoperability
clock distribution

Year Tech. Complexity Frequency 3 Yr. Design Staff Costs

Staff Size
1997 0.35 13 M Tr. 400 MHz 210 $90 M
1998 0.25 20 M Tr. 500 MHz 270 $120 M
1999 0.18 32 M Tr. 600 MHz 360 $160 M
2002 0.13 130 M Tr. 800 MHz 800 $360 M
 Technology Directions: SIA Roadmap

Year 1999 2002 2005 2008 2011 2014

Feature size (nm) 180 130 100 70 50 35
Mtrans/cm2 7 14-26 47 115 284 701
Chip size (mm2) 170 170-214 235 269 308 354
Signal pins/chip 768 1024 1024 1280 1408 1472
Clock rate (MHz) 600 800 1100 1400 1800 2200
Wiring levels 6-7 7-8 8-9 9 9-10 10
Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.6
High-perf power (W) 90 130 160 170 174 183
Battery power (W) 1.4 2.0 2.4 2.0 2.2 2.4

For Cost-Performance MPU (L1 on-chip SRAM cache; 32KB/1999 doubling every
two years)

http://www.itrs.net/ntrs/publntrs.nsf
 Why Scaling?
• Technology shrinks by ~0.7 per generation
• With every generation can integrate 2x more
functions on a chip; chip cost does not increase
significantly
• Cost of a function decreases by 2x
• But …
• How to design chips with more and more functions?
• Design engineering population does not double every
two years…
• Hence, a need for more efficient design methods
• Exploit different levels of abstraction
Design Abstraction Levels
SYSTEM

MODULE
+

GATE

CIRCUIT
Vin Vout

DEVICE
G
S D
n+ n+
 Design Metrics

• How to evaluate performance of a digital

circuit (gate, block, …)?
• Cost
• Reliability
• Scalability
• Speed (delay, operating frequency)
• Power dissipation
• Energy to perform a function
 Cost of Integrated Circuits

• NRE (non-recurrent engineering) costs

• design time and effort, mask generation
• one-time cost factor
• Recurrent costs
• silicon processing, packaging, test
• proportional to volume
• proportional to chip area
NRE Cost is Increasing

42
 Die Cost

Single die

Wafer

Going up to 12” (30cm)

From http://www.amd.com
 Cost per Transistor

cost:
¢-per-transistor
1
0.1 Fabrication capital cost per transistor (Moore’s law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012
 Yield
No. of good chips per wafer
Y 100%
Total number of chips per wafer
Wafer cost
Die cost 
Dies per wafer  Die yield
  wafer diameter/2 2   wafer diameter
Dies per wafer  
die area 2  die area
 Defects


 defects per unit area  die area 
die yield  1  
  
 is approximately 3

die cost  f (die area) 4

 Some Examples (1994)
Chip Metal Line Wafer Def./ Area Dies/ Yield Die
layers width cost cm2 mm2 wafer cost
386DX 2 0.90 $900 1.0 43 360 71% $4

486 DX2 3 0.80 $1200 1.0 81 181 54% $12

Power PC 4 0.80 $1700 1.3 121 115 28% $53

601
HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73

DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149

Super Sparc 3 0.70 $1700 1.6 256 48 13% $272

Pentium 3 0.80 $1500 1.5 296 40 9% $417

 Reliability―
Noise in Digital Integrated Circuits

v ( t) V DD
i ( t)

Inductive coupling Capacitive coupling Power and ground

noise
 Reliability
Noise in Digital Integrated Circuits
Noise – unwanted variations of voltages and currents at the logic nodes
 from two wires placed side by side
 capacitive coupling v(t)
- voltage change on one wire can
influence signal on the neighboring wire
- cross talk
 inductive coupling i(t)

- current change on one wire can

influence signal on the neighboring wire

VDD
 from noise on the power and ground supply rails
 can influence signal levels in the gate
 Example of Capacitive Coupling
Signal wire glitches as large as 80% of the supply voltage will be
common due to crosstalk between neighboring wires as feature sizes
continue to scale

Crosstalk vs. Technology

Pulsed Signal
0.12m CMOS
0.16m CMOS

Black line quiet

Red lines pulsed 0.25m CMOS
Glitches strength vs technology 0.35m CMOS

From Dunlop, Lucent, 2000

 Static Gate Behavior
• Steady-state parameters of a gate – static behavior – tell
how robust a circuit is with respect to both variations in the
manufacturing process and to noise disturbances.
• Digital circuits perform operations on Boolean variables
x {0,1}
• A logical variable is associated with a nominal voltage level
for each logic state
1  VOH and 0  VOL

VOH = ! (VOL)
V(x) V(y)
VOL = ! (VOH)

 Difference between VOH and VOL is the logic or signal swing Vsw
 DC Operation
Voltage Transfer Characteristics (VTC)
 Plot of output voltage as a function of the input voltage

V(y) V(x) V(y)

f
VOH = f (VIL)
V(y)=V(x)

Switching Threshold
VM

VOL = f (VIH)

VIL VIH V(x)

Mapping Logic Levels to the Voltage
Domain
 The regions of acceptable high and low voltages are delimited
by VIH and VIL that represent the points on the VTC curve
where the gain = -1

V(y)
"1" VOH Slope = -1
VOH
VIH

Undefined
Region
Slope = -1
VIL
VOL
"0" VOL
VIL VIH V(x)
 Noise Margins
 For robust circuits, want the “0” and “1” intervals to be a s
large as possible
VDD VDD

VOH "1"
NMH = VOH - VIH
VIH
Noise Margin High Undefined
Region
Noise Margin Low VIL
NML = VIL - VOL
VOL
"0"
Gnd Gnd
Gate Output Gate Input

 Large noise margins are desirable, but not sufficient …

 Noise Budget

 Allocates gross noise margin to expected

sources of noise
 Sources: supply noise, cross talk,
interference, offset
 Differentiate between fixed and
proportional noise sources
 Key Reliability Properties
 Absolute noise margin values are deceptive
a floating node is more easily disturbed than a node
driven by a low impedance (in terms of voltage)
 Noise immunity is the more important metric –
the capability to suppress noise sources
 Key metrics: Noise transfer functions, Output impedance
of the driver and input impedance of the receiver;
 The Regenerative Property
 A gate with regenerative property ensure that a disturbed
signal converges back to a nominal voltage level

v0 v1 v2 v3 v4 v5 v6

v2
5

v0
V (volts)

1 v1

-1
0 2 4 6 8 10
t (nsec)
 Conditions for Regeneration
v0 v1 v2 v3 v4 v5 v6

v1 = f(v0)  v1 = finv(v2)

v3 f(v) finv(v)
v1 v1
v3
finv(v) f(v)

v2 v0 v0 v2

Regenerative Gate Nonregenerative Gate

 To be regenerative, the VTC must have a transient region with

a gain greater than 1 (in absolute value) bordered by two valid
zones where the gain is smaller than 1. Such a gate has two
stable operating points.
 Noise Immunity
 Noise margin expresses the ability of a circuit to overpower a
noise source
 noise sources: supply noise, cross talk, interference, offset

 Absolute noise margin values are deceptive

 a floating node is more easily disturbed than a node driven by a low
impedance (in terms of voltage)
 Noise immunity expresses the ability of the system to
process and transmit information correctly in the presence
of noise

 For good noise immunity, the signal swing (i.e., the

difference between VOH and VOL) and the noise margin have
to be large enough to overpower the impact of fixed sources
of noise
Ring Oscillator

T = 2 x tp x N
 Directivity
 A gate must be undirectional: changes in an output
level should not appear at any unchanging input of
the same circuit
 In real circuits full directivity is an illusion (e.g., due to
capacitive coupling between inputs and outputs)

 Key metrics: output impedance of the driver and

input impedance of the receiver
 ideally, the output impedance of the driver should be
zero
 input impedance of the receiver should be infinity
 Fan-In and Fan-Out
 Fan-out – number of load gates
connected to the output of the
driving gate
 gates with large fan-out are slower
N

 Fan-in – the number of inputs to

the gate M
 gates with large fan-in are bigger and
slower
 The Ideal Gate

V out

Ri = 
Ro = 0
Fanout = 
g=
NMH = NML = VDD/2

V in
 Delay Definitions
Vin Vout

Vin
Propagation delay?
input
waveform

Vout

output
signal slopes?
waveform

t
 Delay Definitions
Vin Vout

Vin
Propagation delay
input 50% tp = (tpHL + tpLH)/2
waveform

t
tpHL tpLH
Vout
90%
output
50% signal slopes
waveform
10%
t
tf tr
 Modeling Propagation Delay
Model circuit as first-order RC network

vout (t) = (1 – e–t/)V

R
vout
where  = RC

C
Time to reach 50% point is
vin
t = ln(2)  = 0.69 

Time to reach 90% point is

t = ln(9)  = 2.2 

 Matches the delay of an inverter gate

 A First-Order RC Network

R
vout

vin C

tp = ln (2)  = 0.69 RC

Important model – matches delay of inverter

 A First-Order RC Network
Vdd
E0->1 = C LVdd2
R PMOS i
vout supply
A1 NETWORK

vAinN CVLout
CL
NMOS
NETWORK

T T Vdd
E 0  1 =  P  t  dt = V dd  i sup ply t  dt = Vdd  CL dV out = C L  V dd 2
0 0 0

T T Vdd
1 2
E = P  t  dt =  V i  t dt =  C V dV = --- C  V
ca p cap out ca p L out out 2 L dd
0 0 0
 Power and Energy Dissipation
• Propagation delay and the power consumption of a gate are
related
• Propagation delay is (mostly) determined by the speed at
which a given amount of energy can be stored on the gate
capacitors
• the faster the energy transfer (higher power dissipation) the faster
the gate
 For a given technology and gate topology, the product of the
power consumption and the propagation delay is a constant
 Power-delay product (PDP) – energy consumed by the gate per
switching event

 An ideal gate is one that is fast and consumes little energy, so

the ultimate quality metric is
 Energy-delay product (EDP) = power-delay 2
 Power Dissipation

Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)

Peak power:
Ppeak = Vsupplyipeak

Average power:
1 t T Vsupply t T
Pave   p(t )dt   isupply t dt
T t T t
 Energy and Energy-Delay

Power-Delay Product (PDP) =

E = Energy per operation = Pav  tp

Energy-Delay Product (EDP) =

quality metric of gate = E  tp
 Summary
 Digital integrated circuits have come a long way
and still have quite some potential left for the
coming decades
 Some interesting challenges ahead
 Getting a clear perspective on the challenges and
potential solutions is the purpose of this book
 Understanding the design metrics that govern
digital design is crucial
 Cost, reliability, speed, power and energy dissipation
Thank You