Design of a Continuous Time Equalizer Circuit

(CTLE).
Danilo Ramı́rez Gómez Oscar Danilo Olejua Santos Juan Diego Ramirez Ardila
2155009 2151032 2152125

Abstract—The transmission of information is currently com- • Minimum power.

posed of multiple factors with intrinsic problems that have been
solved over time and the advance of technology, in this article we
To do this, we initially found the gain equation, Vou/Vin,
will touch a specific one and provide an effective and implemented which is:
solution for the loss of information at high speeds. 1
−gm(S + RsCs )
Av = (1)
I. I NTRODUCTION 1 1+ gmRs
Cl(S + RdCl )(S + RsCs
2
)
The increase in transmission speed is directly related to the
complexity of the system, while operating at small frequencies By means of this equation we can determine the poles and
the signal is not affected, but when we operate at high frequen- zeros as follows:
cies where bandwidth is insufficient, where there is crosstalk
and reflection we lose information and must compensate this
effect. We need a circuit that operating at low frequencies does 1
Zero = (2)
not modify the gain, while at high frequency increases it to RsCs
reduce the attenuation caused by the factors mentioned, having
clear the objective we design a circuit equalizer continuous
time that meets the specifications required. 1
P ole1 = (3)
RdCl
II. D ESIGN AND CONSIDERATIONS .
For the present report, we sought to perform a CTLE (Fig. 1)
that complied with certain minimum design conditions, which
1 + gmRs
2
they were: P ole2 = ( ) (4)
RsCs

To obtain the values of Rs and Cs we replace in (2) the zero

by 2 [MHz] and clear from there RsCs

1
2 ∗ 106 = (5)
RsCs

RsCs = 0.5 ∗ 10−6 (6)

We chose Cs → 2.2 [nF] ; Rs → 220 [Ω]

RsCs = 0.484 ∗ 10−6 (7)

we observe that (7) is approximately (6)

To obtain the values of Rd and Cl we replace in (3)

Pole1 by 16 [MHz] and clear from there RdCl
Fig. 1. CTLE Schematic.
1
• Peaking frecuency > 2.5 [M hz] 16 ∗ 106 = (8)
RdCl
• DC band min =1[M HZ]
• Gain DC range : -4[dB] < ADC < 1[dB] RdCl = 62.5 ∗ 10−9 (9)
 and was presented for the project was:
We chose Cd → 414 pF ; Rs → 150 RD = 150[Ω], RS = 220[Ω] and CS = 2.2[nF ],
RM IRROR = 1[kΩ] and VCC = 11.8[V ] from which the gain
RdCl = 62.1 ∗ 10−9 (10) graph in dB was obtained (Fig 3) and their respective value
in Fig. 4.
Second: RD = 20[Ω], RS = 41[Ω] and CS = 4[nF ],
we observe that (10) is approximately (9) RM IRROR = 1[kΩ] and VCC = 11.8[V ], los cuales se ven en
Fig 5 and Fig 6.
A. Assembling third: RD = 100[Ω], RS = 120[Ω] and CS = 4[nF ],
RM IRROR = 1[kΩ] and VCC = 11.8[V ], it is evident in Fig
The assembly was done in two phases, in protoboard and 7 and 8.
in PCB 2 tests.
Which were tabulated in the Table I the values in protoboard.

TABLE I
P ROTOBOARD VALUES

Av [dB] frecuency [kHz] Input [mV] Output [mV]

-1.6 0.015 390 322
-1.6 0.1 390 322
-1.8 1 400 324
-1.8 10 392 318
-1.6 100 390 324
-1.5 400 398 332
-1.5 500 398 334
-1.14 600 390 342
-1.07 700 396 350
-0.8 900 400 362
-0.6 1000 400 372 Fig. 3. Gain dB: Configuration ONE
0.56 1400 371 396
0.67 1600 372 402
0.84 1800 370 408
0.92 2000 358 402
1.16 3000 334 382
1.96 4000 276 346
1.32 4500 280 326
0.8 5000 288 316 Fig. 4. Gain values dB: Configuration ONE

B. Simulation

Fig. 5. Gain dB: Configuration two

Fig. 2. Equalizer simulation

For the simulation of the project, the CADENCE CAP-

TURE tool was used, for which we proposed the circuit in Fig. 6. Gain values dB: Configuration two
Fig. 2).
Several considerations were made of drain resistors, source
and source capacitor. The first configuration that was used,
 IV. C ONCLUSIONS
• Problems were presented at the time of mounting our
equalizer circuit on the protoboard, which had a pair of
defective nodes, so we limited the progress in the proper
development of CTLE.

• It was possible to evidence great variations in the values

Fig. 7. Gain dB: Configuration three
Fig. 8. Gain values dB: Configuration three
• An important aspect to take into account is the excess
III. R ESULTS AND ANALYSIS .
The values of Table I, can be better seen in the plot Fig9.
obtained from the experimentation in comparison to
the simulation, different factors affect this measure,
some of these were the resistances and capacitances
generated by the same protoboard, the resistances of
the cables that were used, the ground connection was
not optimal, and finally, and a little more important is
that the characterization of a transistor is very dicficl,
because by effects of manufactures do not have the same
characteristics.
current or voltage at which the transistors could be fed,
thus causing a possible damage to the device, so we
must design the differential with the transistors that gives
us the closest possible resemblance for better quality in
the results

Fig. 9. Ganancia experimental.