Energy of Formation of Step Junctions at Nano Dimensions

A Thesis

Presented to the

Graduate Faculty of the

University of Louisiana at Lafayette

In Partial Fulfillment of the

Requirements for the Degree

Master of Science

Prasanna Ulhas Kawatkar

Fall 2013
 UMI Number: 1553878

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 Energy of Formation of Step Junctions at Nano Dimensions

Prasanna Ulhas Kawatkar

APPROVED:

R. P. Jindal, Chair Mohammad Madani

Professor of Electrical and Computer Associate Professor of Electrical and
Engineering Computer Engineering

Zhongqi Pan Cherif Aissi

Associate Professor of Electrical and Professor of Industrial Technology
Computer Engineering

____________________ _____
Mary Farmer-Kaiser
Interim Dean of the Graduate School
 DEDICATION

Dedicated to my Parents
 ACKNOWLEDGMENTS

First and foremost, I would like to acknowledge my advisor, Prof. R. P. Jindal. He has

been a great mentor with his management skills and enthusiasm. I owe many thanks to him

for keeping faith in me and making me a responsible person. I cannot forget his continued

support and care on my study and career. Without his guidance and support, my research

would not have been possible.

I am thankful to the Department of Electrical and Computer Engineering for providing

me with all the necessary research facilities. I would also like to thank Mr. Shelby Williams

for his help in resolving computer and software issues.

I would also like to thank my thesis committee, Dr. Madani, Dr. Pan, and Dr. Aissi for

their valuable time and patience in reading my thesis.

Specially, I am indebted to my parents for their faith and encouragement.

 TABLE OF CONTENTS

DEDICATION ......................................................................................................................... iv

ACKNOWLEDGMENTS ......................................................................................................... v

LIST OF FIGURES ................................................................................................................ viii

LIST OF ABBREVIATIONS .................................................................................................. ix

1. INTRODUCTION ................................................................................................................ 1
1.1 General Overview ...................................................................................................... 1
1.2 Motivation and Objectives ......................................................................................... 2
1.3 Organization of Thesis ............................................................................................... 3

2. EVOLUTION OF MOSFET................................................................................................. 5
2.1 Why FinFET’s ........................................................................................................... 5
2.2 FinFET Structure ....................................................................................................... 6
2.3 Advantages of FinFET ............................................................................................... 7
2.4 Future of FinFET ....................................................................................................... 8

3. PHYSICS OF STEP JUNCTION DIODES ......................................................................... 9

3.1 p-n Junction Diode ..................................................................................................... 9
3.1.1 Under Equilibrium ........................................................................................ 9
3.1.2 Under Forward Bias .................................................................................... 12
3.1.3 Under Reverse Bias..................................................................................... 13
+
3.2 n -n Junction Diode ................................................................................................ 14
3.2.1 Under Equilibrium ...................................................................................... 14
3.2.2 Under Forward Bias .................................................................................... 16
3.2.3 Under Reverse Bias..................................................................................... 17

4. EVALUATION OF ENERGY RELEASED IN RECOMBINATION .............................. 19

4.1 Physics of p − n Junctions ...................................................................................... 19
4.2 Computation of Areal Carrier Density..................................................................... 22
4.3 Graphical Representation ......................................................................................... 23
4.4 Surface Density Elevation and Surface Density Depression Graphical
Description ............................................................................................................... 24
4.5 Example for Energy Released during Recombination in Case of Symmetric p-n
Junction .................................................................................................................... 32

5. EVALUATION OF ENERGY STORED IN THE ELECTRIC FIELD ............................ 35

5.1 Electric Field E Calculation on n-side.................................................................... 36
5.2 Electric Field E Calculation on p-side..................................................................... 37
5.3 Calculating Width w of Depletion Region .............................................................. 38
5.4 Calculating Energy Stored in the Field .................................................................... 39
 5.5 Solution for Energy Stored in the Field in Case of Symmetric p-n Junction .......... 40
5.6 Behavior of Energy of Formation of a Junction as a Function of Doping............... 41

6. CALCULATING RISE IN TEMPERATURE DUE TO ENERGY OF FORMATION .... 45

7. CONCLUSION .................................................................................................................... 47

8. FUTURE WORK ................................................................................................................. 48

REFERENCES ........................................................................................................................ 49

APPENDIX A: MATLAB CODE........................................................................................... 51

APPENDIX B: INDEPENDENT VERIFICATION METHOD ............................................. 54

ABSTRACT ............................................................................................................................ 57

BIOGRAPHICAL SKETCH ................................................................................................... 58

vii
 LIST OF FIGURES

Fig. 1. 3-D Tri-gate transistor form conducting channels on three sides of a vertical fin
structure providing "fully depleted" operation.......................................................7

Fig. 2. Band diagram for the p-n junction diode at equilibrium........................................10

Fig. 3. Band diagram for the p-n junction diode under forward bias.................................12

Fig. 4. Band diagram for the p-n junction diode under reverse bias..................................13

+
Fig. 5. Band diagram for the n - n diode under equilibrium...........................................15

+
Fig. 6. Band diagram for the n - n diode under forward bias...........................................16

+
Fig. 7. Band diagram for the n - n diode under reverse bias............................................17

Fig. 8. Two symmetrically doped p-n semiconductor samples before contact.................19

Fig. 9. Two symmetrically doped p and n semiconductor samples after contact..............20

Fig. 10. (a) p-n junction under depletion approximation, (b) Electron and hole carrier
density profile.......................................................................................................21

Fig. 11. Surface density elevation log |∆N/N0| vs. log (W)................................................24

Fig. 12. Surface density depression log |∆N/N0| vs. log (W)..............................................25

Fig. 13. Surface density elevation log |∆N/N0| vs. W.........................................................26

Fig. 14. Surface density depression log |∆N/N0| vs. W......................................................27

Fig. 15. Surface density elevation |∆N/N0| vs. log (W)......................................................28

Fig. 16. Surface density depression |∆N/N0| vs. log (W)....................................................29

Fig. 17. Surface density elevation |∆N/N0| vs. W...............................................................30

Fig. 18. Surface density depression |∆N/N0| vs. W.............................................................31

Fig. 19. n-p type junction with depletion width.................................................................36

Fig. 20. Energy vs. U20+U10 (a) at U10 = 5, (b) at U20 = 10...............................................42

Fig. 21. Energy vs. U20+U10 (c) at U10 = 5, (d) at U20 = 10...............................................43

Fig. 22. Rise in temperature ∆T vs. sample length l..........................................................46

 LIST OF ABBREVIATIONS

CMOS C Complementary metal-oxide semiconductor

4
c
C Capacitance (Faradays)

CP Specific heat for constant pressure

Eg Band-gap

E vac Vacuum energy level for the semiconductor

b Conduction band energy level on p-side

E Cp s

EVp Valence band energy level on p-side

E Fp Fermi energy level on p-side

E ip Intrinsic energy level on p-side

b Conduction band energy level on n-side

E Cn s

EVn Valence band energy level on n-side

E Fn Fermi energy level on n-side

E in Intrinsic energy level on n-side

E Cn + b Conduction band energy level on n+-side

s

EVn + Valence band energy level on n+-side

E Fn + Fermi energy level on n+-side

E in + Intrinsic energy level on n+-side

Erecomb Energy / unit area released during recombination

Efield semi Energy / unit area stored in the electric field

Ejunction formation Total energy/ unit area released

h Planck’s constant = 6.63 × 10-34 J.s

k
kB b
Boltzmann constant = 1.3807 × 10-23 J / o K

L De Extrinsic Debye length

l Length of the sample

MOSFET m Metal-oxide semiconductor field-effect transistor

o

NA Acceptor concentration cm −3

ND Donor concentration cm −3

P I Hole density
1
n
q I Elementary electronic charge = 1.602 x 10-19 C
1
n
Q Total charge in the semiconductor

R Resistance

T t Absolute temperature in degree Kelvin

T
T0 0
Reference temperature in degree Kelvin = 300 o K

∆T Change in temperature

ε Permittivity

ε0 Vacuum permittivity

εr Relative permittivity

U 20 Normalized bulk potential of side 2, to the right of the junction

U 10 Normalized bulk potential of side 1, to the left of the junction

Vbi Built in voltage (barrier potential)

x
VT y Source-referenced threshold voltage of a MOSFET
c

VDD Positive supply voltage

W Band bending

w Total depletion width

wn Depletion width on n-side

wp Depletion width on p-side

ρ Density of Silicon

∆N n1 Change in areal electron density on the left side of the junction

∆N n 2 Change in areal electron density on the right side of the junction

∆N p1 Change in areal density of holes on the left side of the junction

∆N p 2 Change in areal density of holes on the right side of the junction

∆N n 0 Normalization factor

∆N p 0 Normalization factor

∆N Total number of electrons lost in the sample

∆P Total number of holes lost in the sample

xi
 1. INTRODUCTION

1.1 General Overview

Planar transistors have been the important building block of integrated circuits for

decades, during which the size of transistors has steadily decreased. In the early days of

the microelectronics revolution, the device dimensions were in 10's of micrometers.

Hence one could get away with the concept of average doping, because the devices where

so big in size that the graininess of the device did not matter. However, since the device

dimensions have shrunk in the nano regime, the discrete nature of atomic doping is

manifesting itself. Previously, one could get away with something but now it is breaking

down. We have very small devices of point doping with dimensional and material

parameter variability [1]. Now, technology has reached nanoscale regime and

incorporating nanotechnology in future research work like considering individual living

cell in the context of information processing [2]. Later, in chapter 2, we discuss more

about nanotechnology and its uses.

We are shrinking the device to improve the performance, speed and lower the cost

of the transistor. But as the size decreases, planar transistors increasingly suffer from

short-channel effect, especially “off-state” leakage current, which increases the idle

power required by the device. We are now moving to multi gate devices. In a multi gate

device, the channel is surrounded by the same gate on multiple surfaces, allowing the

gate to have more control over the channel. Later, in chapter 3, we will be discussing

more about the transition from MOSFET to FinFET, which is a type of multi-gate device.
1.2 Motivation and Objectives

Basically, we have an intrinsic semiconductor, and when we dope it with

pentavelant impurity we get a n-type semiconductor. And when we dope it with a

trivalent impurity we get a p-type semiconductor. When we get these two semiconductors

together we form a p-n junction. This is just a hypothetical experiment. In reality we

never bring them together.

The electrons which are majority carriers on the n side will diffuse from high to

low concentration. It means from n-side to p-side due to the concentration gradient.

Similarly, holes which are the majority carriers on p-side will diffuse from p-side to the

n-side. In this process some of these carriers will recombine to form the junction in

between or we can also call it as depletion region. This loss of carriers in the sample is

tantamount to liberation of energy. In addition, there is energy stored in the electric field

that is generated due to the charge separation across the metallurgical junction. To our

knowledge no text book or research paper published so far discuss the energy

considerations in the formation of a p-n junction. We ask the question is it really true.

Because the sample when you start out with, it is neutral then what happens after the

depletion region is formed. Were do those carriers go? We addressed this issue and

calculate if the energy is liberated or absorbed for p-n and high-low junctions. To

evaluate the net loss of carriers, we need to calculate the change in the areal concentration

of electrons and holes on the two sides of the junction. A previous [3]-[6] has addressed

this problem applicable to both the step junction and uniform doped surfaces. We are

using these analyses to calculate the energy of formation for p-n junction.

2
 The purpose of this thesis is to analyze if the energy is liberated or absorbed and

what is the consequence of that on the sample. If all the carriers are counted, before we

had all electrons are equal to the fixed donor ions and some number of them moved to the

other side and thereby exposing some donor ions. Similarly, all holes are equal to the

fixed acceptor ions and some of them move to the other side and thereby exposing some

acceptor ions. But we find to very good approximation that depletion region which has no

carriers at all it means that the carriers are lost. In this thesis we have estimated that how

many carriers are lost and want to verify if there is a real loss or not.

1.3 Organization of Thesis

This dissertation is organized in order to show how the hypothetical experiment of

forming a p-n junction can be used for calculating the energy of formation for p-n

junction.

Chapter 1: In chapter 1 we start with a brief introduction on the history of planar

transistors along with the current status. We also discuss the drawbacks and how to

reduce them including the motivation and objectives.

Chapter2: In chapter 2 we description the evolution of transistor from MOSFETs to

FinFETs. We also describe FinFET's structure and advantages.

Chapter 3: In chapter 3 we give a detailed description on physics of diode and the types

of diodes which include p-n diode and n+-n diode with their respective operation

principle.

Chapter 4: In chapter 4 we give a detailed description and evaluation of energy released

in recombination.

Chapter 5: In chapter 5 we give a detailed description and evaluation of energy stored in

electric field.

3
Chapter 6: In chapter 6 we calculate the rise in temperature due to energy of formation.

Chapter 7: In chapter 7 we have a detailed conclusion and important findings from

present thesis work followed by future scope of thesis.

4
 2. EVOLUTION OF MOSFET

The idea of multi-gate transistor was first introduced by Sekigawa and Hayashi

[7]. Later, Hu, King-Liu and Bokor proposed a nonplanar, double-gate transistor built on

an SOI substrate, based on the earlier transistor design and termed it as FinFET. The

distinguishing characteristic of the FinFET is that the conducting channel is wrapped by a

thin silicon "fin", which forms the gate of the device. The thickness of the fin (measured

in the direction from source to drain) determines the effective channel length of the

device.

2.1 Why FinFET’s

The market is pushing constantly to increase the density of transistor on chip and

the performances in term of speed and reduce power consumption. This scaling has been

going on for almost 60 years and is captured by the famous Moor's law. However, there

seems to be a technology limit for the planar transistor with length below 20nm, the

electrical parameters start degrading and the silicon process variations impact heavily in

the performances [8]. The main reason of this degradation is due to the planar structure

itself. Several short channel effects such as threshold voltage (VT ) roll off and drain

induced barrier lowering (DIBL), increasing leakage current such as sub threshold S/D

leakage, gate direct tunneling leakage, and hot carrier effects that result in device

degradation is plaguing the industry. Reducing the power supply VDD helps reduce power

and hot carrier effects, but worsens performance. Performance can be improved back by

lowering VT but at the cost of worsening Source Drain leakage. To reduce DIBL and

increase adequate channel control by the gate, the oxide thickness can be reduced, but

that increases gate leakage. Solving one problem leads to another. Efforts are on to find a

suitable high-K gate dielectric so that a physical thicker oxide can be used to help reduce

5
gate leakage and yet have adequate channel control, but this search has not been

successful to the point of being usable [9]. There are problems with band alignment with

respect to Si and/or thermal instability problems and/or interface states problems with Si.

The thermal instability problem has led researchers to search for metal gate electrodes

instead of polysilicon because insufficient activation leads to poly depletion effect. But

metal gates with suitable work function haven't been to the point of being usable. In the

absence of this polysilicon continues to be used, whose work function demands that VT

beset by high channel doping. High channel doping in turn leads to random dopant

fluctuations at small gate lengths as well as increased impurity scattering and therefore

reduce mobility. Indeed, it is felt that instead of planar MOSFETs, a double or tri gate

device will be needed at gate length below 20nm in order to be able to continue forth on

the shrinking path.

2.2 FinFET Structure

The solution seems to be indeed the three dimensional approach, in which

the channel between source and drain is built as a three dimensional bar on top of the

silicon substrate, called fin. The gate electrode is then wrapped around the channel, so the

gate can control the channel electric field. In this structure, the gate can control much

better the electrical field in the 3D channel.

Several options and enhancement are proposed. FinFET can be built on silicon on

insulator (SOI) with a further reduction of current leakage. Also, there can be several gate

electrodes on each side which leads to reduced leakage effects and an enhanced drive

current.

6
 3 D FinFET

Drain

Gate

Source

Oxide Oxide

Silicon Substrate

Fig. 1. 3-D Tri-gate transistor form conducting channels on three sides of a vertical fin
structure providing "fully depleted" operation.

2.3 Advantages of FinFET

FinFET technology impacts all the electrical parameters of the transistor and can

have benefit in power consumption (static and dynamic), speed and voltage supply range.

FinFET also improve the always challenging tradeoff between performance and power,

FinFET can go faster with the same amount of power, compared to the planar equivalent,

or save power at the same speed. Following are the promised advantages over planar

transistor [10]:

• Higher drain current

• Up to 37% switching speed

• Lower switching voltage

• Less than half the dynamic power

• 90% less static leakage current

7
 The above points reach with a low cost impact. Leading foundries estimate the

additional processing cost of 3D devices to be 2% to 5% higher than that of the

corresponding planar wafer fabrication.

2.4 Future of FinFET

Almost all the big players in the semiconductor eco-system are focusing on the

FinFET technology, so news, announcements and updates come out every day. The

FinFET era started in 2011, when Intel unveiled the new 3-D transistor technology at the

22nm node (now in production). Intel plans are to ramp up its second generation FinFET

devices at 14nm by year's end and move to 11nm by 2015.

Silicon foundries are already defining their plans with FinFET technology.

GLOBALFOUNDRIES will deliver 14nm FinFET by 2014 and 10nm FinFET by 2015.

TSMC is planning to deliver 16nm FinFET by 2014. Maybe we are at the beginning of

the new era. FinFET can potentially determinate a big step forward in the never ending

effort to reduce power consumption, to increase switching speed and number of

transistors with a cost reduction.

The devices are becoming smaller and smaller, so the dimensions are getting in

nanoscales and the junctions are becoming very shallow. When we go to the nanoscale

we are looking at the things in very fundamental manner and one of the idea is when a

junction is made, then what are the energies involved in it. So with such small nanoscale

structures the energy considerations in these junctions become important. As any energy

exchanges can make a noticeable change in the temperature of the device. In next few

chapters we are examining this fundamental point.

8
 3. PHYSICS OF STEP JUNCTION DIODES

The basic building block of a transistor such as BJT or MOSFET is a diode. The

operation principle of such device is derived based on the fundamental operation of

various types of diodes such as p-n diode and n+-n diode. Understanding the physics of

diodes, which is the basic foundation for any transistor, is therefore very important.

Knowing the physics involved in various diodes become a prime candidate for majority

of the commercial products. Before we discuss the energy of formation of junctions we

will review the physics of diode. Diodes are classified based on the material and doping

concentration used for the junction formation [11], [12]. These are discussed below.

3.1 p-n Junction Diode

This section describes the physics involved in a p-n junction diode when it is

under equilibrium, forward bias and reverse bias. A p-type semiconductor is formed by

doping an intrinsic semiconductor with group-III elements such as boron, gallium and an

n- type semiconductor is formed by doping intrinsic semiconductor with group-V

elements such as phosphorous, arsenic. A p-n junction is formed by bringing a p-type

material in a very close contact with an n-type material. But in reality, it is formed by

diffusing p-type atoms into an n-type semiconductor material.

3.1.1 Under Equilibrium

When a p-type material is brought in contact with an n-type material, electrons

starts flowing from n-type material to p-type material since the electron concentration is

more in n-type material compared to that in p-type material leaving behind positively

charged donor atoms near the junction. Simultaneously, holes start flowing from p-type

material to n-type material since their concentration is more in p-type material compared
to n-type material leaving behind negatively charged acceptor atoms near the junction.

As a result, an electric field is developed near the junction due to these immobile charge

carriers and the region is termed as depletion region. And this built-in field induces a drift

force on electrons in a direction opposite to the diffusion of electron from n-type to p-

type material. Similarly, this field induces a drift force on holes in a direction opposite to

the diffusion of holes from p-type to n-type material. Diffusion current continues to flow

since there is a gradient in the carrier concentration on both sides of the junction and at

the same time drift current flows due to the presence of built-in electric field. At

equilibrium, the drift and diffusion currents due to individual carriers cancel each other

and as a result the net current flow is zero. The band diagram for p-n diode under

equilibrium is shown in Fig. 2.

p - type Semiconductor n - type Semiconductor

ECp

qVbi
Eip
ECn
EFp
EVp EFn

Ein
Junction

EVn
Depletion
Region

Fig. 2. Band diagram for the p-n junction diode at equilibrium.

10
 Where E g is the energy gap of the semiconductor material, E C is the conduction

band energy, EV is the valence band energy, E F is the Fermi energy level and E i is the

intrinsic energy level, qVbi is the built-in energy barrier across the junction, and Vbi is the

built-in voltage. The subscript n indicates n-type semiconductor while the subscript p

indicates p-type semiconductor.

11
3.1.2 Under Forward Bias

A p-n junction diode is forward biased, when the n-type material is made negative

relative to the p-type material.

p-type Semiconductor n-type Semiconductor

Va
Va < 0
E Cp
q(Vbi +Va)
E ip E Cn
E Fn
E Fp
E Vp E in

Junction
E Vn
Depletion
Region

Fig. 3. Band diagram for the p-n junction diode under forward bias.

Where Va is the applied external bias.

Since negative bias is applied to the n-type material, the Fermi level for n-type

material moves up and as a result the built-in potential barrier near the junction decreases

by the applied voltage. Hence more electrons in n-type material have enough energy to

cross the space charge region and enter p-type where they become excess minority

carriers and are subject to diffusion and recombination mechanism. At the same time,

holes in p-type material cross the space charge region to n-type material where they

become excess minority carriers and are subject to diffusion and recombination

12
mechanism. As a result significant current flows in the forward biased p-n junction diode.

The Band diagram of a p-n junction diode under forward bias is shown in Fig. 3.

3.1.3 Under Reverse Bias

p - type Semiconductor n - type Semiconductor

Va
Va > 0
ECp

Eip q(Vbi +Va)

EFp
ECn
EVp
EFn

Ein
Junction
EVn

Depletion
Region
Fig. 4. Band diagram for the p-n junction diode under reverse bias.

A p-n junction diode is reverse biased when the n-type material is made more

positive relative to the p-type material. Since positive bias is applied to the n-type

material, the Fermi level for n-type material moves down and as a result the built-in

potential barrier near the junction increases by the applied voltage. This increased

potential barrier near the junction continues to hold back holes in the p-type material and

electrons in the n-type material from crossing the space charge region. But a very small

number of holes on the n-side diffuse to the junction and are swept by the field to the p-

13
side. At the same time, electrons on the p-side diffuse to the junction and are swept by the

field to the n-side. As a result, a little current flows across the junction and is known as

minority carrier diffusion current. The band diagram of a p-n junction diode under

reverse bias is shown in Fig. 4.

The strength of the electric field across the depletion region also increases with

the increased reverse bias voltage. When this electric field increases beyond a critical

value, the depletion region breaks down and large current flows in the circuit. This

breakdown is known as avalanche or Zener break down.

3.2 n+-n Junction Diode

Understanding the electrical characteristics of n+-n diode gained importance in

recent years since it can be viewed to be formed in the source-channel junction of an n-

channel MOSFET.

3.2.1 Under Equilibrium

When n+ material is bought in contact with n-type material, electrons starts

diffusing from n+ material to n-type material since the electron concentration in n+

material is large compared to that in n-type material leaving behind positively charged

donor atoms near the junction. At the same time, holes in n-type material start diffusing

toward n+ material since their concentration is more in n material compared to that in n+-

type material.

14
 E
-
-
n+- type Semiconductor - n- type Semiconductor
-
-
-

ECn
ECn+ qVbi
EFn
EFn+
Ein

Ein+
EVn

Junction
EVn+
Depletion
Region
Fig. 5. Band diagram for the n + - n diode under equilibrium.

As a result of the ionized donor atoms in n+ material, a built-in potential is

developed near the junction. And this potential induces a drift force on electron in

direction opposite to the diffusion o electrons from n+ region to n-type material. At

equilibrium, the diffusion current of electrons is equal to the drift current of electrons and

as a result zero current flows in the junction. The energy band diagram for n+-n diode in

equilibrium is shown in Fig. 5 where the subscript n indicates n-type semiconductor

material while the subscript n+ indicates n+ semiconductor material.

15
3.2.2 Under Forward Bias

E
--
+
n -type Semiconductor -- n-type Semiconductor
--
-
-

Va
Va > 0

ECn+ qVbi
EFn+
E Cn

Ein+
E Fn

E in
EVn+
Junction
Depletion E Vn
Region
Fig. 6. Band diagram for the n + - n diode under forward bias.

An n+-n diode is forward biased, when n-side is made positive relative to the n+

side. When n-side is made positive the Fermi level on n-side moves down and this

applied voltage will be dropped completely across the low doped n-type material. This

induces an electric field in n-type material which causes the net drift of electrons from n+

material to n-type material. As a result, a significant current flows in n+-n diode under

forward bias. The energy band diagram for n+-n diode under forward bias is as shown in

Fig. 6.

16
3.2.3 Under Reverse Bias

E
--
+
n - type Semiconductor -- n - type Semiconductor
--
--

Va
Va < 0 E Cn

E Fn

qVbi E in
ECn+
EFn+
E Vn
Ein+

EVn+
Junction

Depletion
Region
Fig. 7. Band diagram for the n + - n diode under reverse bias.

An n+-n diode is reverse biased, when n-side is made negative relative to the n+

side. When n-side is made negative, the Fermi level on n-side moves up and this applied

voltage will be dropped completely across the low doped n-type material. This induces an

electric field in n-type material which causes the net drift of electrons from n-type

material to n+ material. As a result, significant current flows in n+-n diode under reverse

bias and this current is equal in magnitude to the current flow in forward bias of the same

voltage. The energy band diagram for n+-n diode under reverse bias is as shown in Fig. 7.

Similar explanation holds for the p+-p junction diode case.

17
 In the following section we will look at energy released in recombination and

energy stored in the electric field for the p-n junction case. And then we will calculate

what is the net energy change due to the p-n junction formation.

18
 4. EVALUATION OF ENERGY RELEASED IN RECOMBINATION

4.1 Physics of p − n Junctions

We begin by looking at n-type and p-type regions which are physically separated,

n - type Silicon p - type Silicon

E vac E vac

χn Φn γn χp Φp γp

E Cn E Cp

E Fn
qV bi Eg
Eg E Fp

E Vn E Vp
Fig. 8. Two symmetrically doped p-n semiconductor samples before contact.

and electrically neutral in every microscopic region as shown in Fig. 8. By electrically

neutral we mean that there is no region having more positive charges than negative, a

situation that will change when the materials are in contact. The energy band diagram of

each of the two isolated semiconductors is given in Fig. 9. The electron affinity χ , the

ionization potential γ , and the energy gap E g are indicated for each material. The

subscript n indicates n-type semiconductor while the subscript p indicates p-type

semiconductor. Also shown is an additional parameter, the work function Φ . The work

function is equal to the energy difference between the vacuum level and the Fermi level

[12].
 Because of the assumption of space charge neutrality everywhere, the energy

required for an electron to escape the material is the same in any region. Therefore, the

vacuum level is same for either material at any position. It is convenient to choose the

vacuum level as reference for each material on the edge facing the other material.

Now consider a general step junction with end regions of infinite length and with

uniform values of extrinsic doping on either side of the junction.

E vac

E vac

E Cp
E Cn qV bi Eg
E ip
E Fn E Fp
E in
Eg E Vp
qV bi
E Vn

n - type Silicon p - type Silicon

Fig. 9. Two symmetrically doped p and n semiconductor samples after contact.

Upon contact between the two materials, electrons flow (diffuse) from the n-type

semiconductor to the p-type semiconductor because there is a higher concentration of

electrons on the n side than on the p side. As the electrons move toward the p-type

region, they leave behind ionized donors (positive charged) that are locked into the

20
crystal lattice. At the same time, holes flow from the p semiconductor to the n

semiconductor, leaving behind ionized acceptors (negatively charged). This separation of

charges set up an electric field E , as shown in Fig. 9.

n-type Silicon p-type Silicon

(quasi neutral) (quasi neutral)

(a)

nn pp

Density

pn
np

x
(b)

Fig. 10. (a) p-n junction under depletion approximation, (b) Electron and hole carrier
density profile.

Fig. 10 shows us the electron and hole density on either side of the junction.

where subscript n denotes electron density on N side and p denotes electron density on

p side [13]

n = ni e ( EF − Ei ) kT or = ni e − qψ kT
or = ni eU 20 (1)

where U 20 = Normalized bulk potential of side 2, to the right of the junction [4].

W = U 20 − U where the normalized potential U is defined by the relations

n = ni eU or p = n i e −U

21
4.2 Computation of Areal Carrier Density

We compute the number of charges per unit area near the semiconductor junction

in the form of excess holes and electrons which could be positive or negative for various

values of surface potential. The change in the areal density of electrons and holes on the

right hand side of the junction is given by [4]

∞ (2)
(
∆N n 2 = ni ∫ eU − eU 20 dx )
0

where the origin of the x axis is placed at the junction. Similarly, for holes,

∞ (3)
(
∆N p 2 = n ∫ e −U − e −U 20 dx )
0

where ∆N n 2 = Change in areal density of electrons on the right hand side of the junction

∆N p 2 = Change in areal density of holes on the right hand side of the junction

Its is convenient to use for normalization [4] the number of carriers of a given type

present in the region in a junction of Debye length thick,

∆N p 0 = LDe ni e −U 20 (4)

∆N n 0 = LDe ni eU 20

12
 ε (k T q ) 1 
were LDe = B  extrinsic Debye length [13] and
 2qni CoshU 0 

∆N p 0 , ∆N n 0 = normalization factor

The magnitude of the normalized change in areal density change for holes is [4]
∞

∆N p 2
(
ni ∫ e −U − e −U 20 dx )
0
= (5)
∆N p 0 LDe ni e −U 20 ∞ ∞

∫ (e )dx dx
∫( )
U 20 −U W
= −1 = e −1
0
LDe 0
LDe

22
where W = U 20 − U is the band bending

Similarly the magnitude of the normalized change in areal density changes for electron is

∞ ∞ ∞
(
n i ∫ e U − e U 20 dx = ) ∫ (e
U −U 20
−1)dx
=
dx
∫ (1 − e ) L
−W

∆N n 2 0 LDe
= 0 0 De
(6)
∆N n 0 L De n i e U 20

Since our device is symmetrically doped device ∆N n1 = ∆N p 2 carrier density and

∆N p1 = ∆N n 2 carrier density.

4.3 Graphical Representation

A curve can be generated for different values of U 20 . Where in each of those

curves will be representing the normalized number of excess carriers per unit area. The

number of excess carriers per unit area is calculated from (5) and (6) by integrating from

a point where the potential is W to a point deep in the bulk region of the sample [4]. By

looking at the Fig. 11 - Fig. 18 which are shown later on, there are two different physical

situations :

1. There is a density elevation of majority carriers near the junction and simultaneously

density depression of minority carriers. For example on U 20 = −15 side which is a p-type

sample. There is a density elevation of holes which is a majority carrier and

simultaneously density depression of electrons which is a minority carrier.

2. There is a densit elevation of minority carriers near the junction and simultaneously

density depression of majority carriers. For example on U 20 = −15 side which is a p-type

sample. There is a density elevation of electrons which is a minority carrier and

simultaneously density depression of holes which is a majority carrier.

23
 Also, until know we have associaed (5) with holes and (6) with electrons. But due

to the hole electron symmetry, we can see that one equation can be transformed into

another by just changing the sign of W and U 20 simultaneously. Also, to denote the

condition with respect to the density of either carrier types, we have introduced elevtaion

and depletion terms.

4.4 Surface Density Elevation and Surface Density Depression Graphical Description

[Holes in p-type] Accumulation

Surface Density Elevation [Electrons in n-type] Set
102

Accumulation Set Depletion Set

U20=15 [Holes in n-type]

[Electrons in p-
U20=5 U20=20 type]
10 U20=10
U20=0
W

10-1
10-1 10 103 105 107 109 1011 1013 1015
|∆N/∆N0|

Fig. 11. Surface density elevation log |∆N/N0| vs. log (W).

In Fig. 11 we plot log ∆N ∆N 0 against log(W ) for different values of U 20 . This

plot is been plotted from (5) and it describes density elevation of either carrier types. The

signs of U 20 is being dropped in view of the dual utility of the curve. In the plot we see

U 20 = 0 devides two cases. For the curve labeled "depletion set," the carrier whose

density elevation is being examined is a minority carrier, and the action of the fixed ionic
24
charge that is present causes the substantial dispersion of the curves. The "accumulation

set" is a single curve very near to the U 20 = 0 curve and represents majority carrier

density elevation. Since these majority carriers completely mask the fixed charges in

density, this set is independent to U 20 .

Surface Density Depression

[Holes in n-type] [Holes in p-type]
[Electrons in p-type] [Electrons in n-type]
Accumulation Set Depletion Set
102
U20=0 U20=5 U20=10

Accumulation Set
U20=15

10 U20=20
W

10-2
10-1 1 10
|∆N/∆N0|

Fig. 12. Surface density depression log |∆N/N0| vs. log (W).

In Fig. 12 we plot log ∆N ∆N 0 against log(W ) for different values of U 20 . This

plot is been plotted from (6) and it describes density depression of either carrier types.

The signs of U 20 is being dropped in view of the dual utility of the curve. In the plot we

see U 20 = 0 devides two cases. The depletion set presents the case where fixd ionic

charges dominate the behavior, and it is the density of majority carriers that is been

depressed. The curve labeled accumulation set describes the depression of minority

carrier density that accompanies majority carrier accumulation accounting for its slight

25
dependence on U 20 . Thus Fig. 11 and Fig. 12, each with two sets, cover all of the

possibilities that exist.

[Holes in p-type]
Surface Density Elevation [Electrons in n-type] Accumulation Set
100

Depletion Set
[Holes in n-type]
75 [Electrons in p-
type]
Accumulation Set

50
W

U20=15

U20=20
U20=10
25
U20=5

U20=0

0
10-1 10 103 105 107 109 1011 1013 1015
|∆N/∆N0|
Fig. 13. Surface density elevation log |∆N/N0| vs. W.

In Fig. 13 we plot log ∆N ∆N 0 against W for different values of U 20 . This plot

is been plotted from (6) simillar to Fig. 11 and it describes density elevation of either

carrier types. The only difference between Fig. 11 and Fig. 13 is that here we have plot

the y-axis on linear scale. So in this figure we can find ∆N / ∆N 0 at lower values of W .

26
 Surface Density Depression
[Holes in n-type] [Holes in p-type]
[Electrons in p-type] Accumulation Set Depletion Set [Electrons in n-type]
50
U20=20

U20=15
40

U20=10

30
Accumulation Set
U20=5
W

20
U20=0

10

0
0.1 1 10
|∆N/∆N0|

Fig. 14. Surface density depression log |∆N/N0| vs. W.

In Fig. 14 we plot log ∆N ∆N 0 against W for different values of U 20 . This plot

is been plotted from (8) simillar to Fig. 12 and it describes density depression of either

carrier types. The only difference between Fig. 12 and Fig. 14 is that here we have plot

the y-axis on linear scale. So in this figure we can find ∆N / ∆N 0 at different lower

values of W .

27
 Surface Density Elevation [Holes in p-type]
[Electrons in n-type]
100 Accumulation
Accumulation Set
Set

Depletion Set
[Holes in n-type]
[Electrons in p-
type]
W

U20=0 U20=5 U20=10 U20=15 U20=20

10
0 1X1014 2X1014 3X1014 4X1014 5X1014 6X1014 7X1014 8X1014 9X1014 1X1015
|∆N/∆N0|

Fig. 15. Surface density elevation |∆N/N0| vs. log (W).

In Fig. 15 we plot ∆N ∆N 0 against log(W ) for different values of U 20 . This plot

is been plotted from (6) simillar to Fig. 11and it describes density elevation of either

carrier types. The only difference between Fig. 11 and Fig. 15 is that here we have plot

the x-axis on linear scale. So in this figure we can find ∆N / ∆N 0 at different higher

values of W .

28
 [Holes in n-type] [Holes in p-type]
[Electrons in p-type] [Electrons in n-type] Surface Density Depression
Accumulation Set Depletion Set
102 U20=20
U20=0 U20=5 U20=10 U20=15

Accumulation
Set
10
W

10-2

0 1 2 3 4 5 6 7 8 9 10
|∆N/∆N0|

Fig. 16. Surface density depression |∆N/N0| vs. log (W).

In Fig. 16 we plot ∆N ∆N 0 against log (W ) for different values of U 20 . This plot

is been plotted from (8) simillar to Fig. 12 and it describes density depression of either

carrier types. The only difference between Fig. 12 and Fig. 16 is that here we have plot

the x-axis on linear scale. So in this figure we can find ∆N / ∆N 0 at different higher

values of W .

29
 [Holes in p-type]
Surface Density Elevation [Electrons in n-type]
Accumulation Set Accumulation Set
70

Depletion Set
60 [Holes in n-type]
[Electrons in p-
type]
50
W

40

U20=0 U20=5 U20=10 U20=15 U20=20

30

20
0 1X1014 2X1014 3X1014 4X1014 5X1014 6X1014 7X1014 8X1014 9X1014 1X1015
|∆N/∆N0|

Fig. 17. Surface density elevation |∆N/N0| vs. W.

In Fig. 17 we plot ∆N ∆N 0 against W for different values of U 20 . This plot is

been plotted from (6) simillar to Fig. 11and it describes density elevation of either carrier

types. The only difference between Fig. 11 and Fig. 17 is that here we have plot the x-

axis and y-axis on linear scale. So in this figure we can find ∆N / ∆N 0 at different values

of W .

30
 [Holes in n-type] [Holes in p-type]
Surface Density Depression
[Electrons in p-type] [Electrons in n-type]

Accumulation Set Depletion Set

50
U20=20
45 U20=15
U20=10
40
U20=5
35
U20=0
30
Accumulation
W

25 Set
20

15

10

0
0 1 2 3 4 5 6 7 8 9
|∆N/∆N0|

Fig. 18. Surface density depression |∆N/N0| vs. W.

In Fig. 18 we plot ∆N ∆N 0 against W for different values of U 20 . This plot is

been plotted from (8) simillar to Fig. 12 and it describes density depression of either

carrier types. The only difference between Fig. 12 and Fig. 18 is that here we have plot

the x-axis and y-axis on linear scale. So in this figure we can find ∆N / ∆N 0 at different

values of W .

31
4.5 Example for Energy Released during Recombination in Case of Symmetric p-n
Junction

For example U 20 = −15

W = U 20 − U

W J = U 20 − U J

Calculation of U J which is the normalized potential at the junction from the following

equation [5]

cosh U 20 − cosh U 10 + U 10 sinh U 10 − U 20 sinh U 20

UJ =
sinh U 10 − sinh U 20 (7)

cosh (− 15) − cosh (15) + (15)sinh (15) − (−15) sinh (− 15)

UJ = =0
sinh (15) − sinh U (− 15)

U = U J = 0 In our case because it is a symmetric doped PN Junction

W J = −15 − 0

Now we calculate L De as follows

12
 ε (k T q ) 1 
LDe = B 
 2qni CoshU 0 

12
 1.04 × 10 −12 F / cm 1 1 
LDe = 0.0259V × × × 
 2 × 1.6 × 10 C−19 10
1 × 10 cm −3
Cosh(U 0 ) 

Substituting U 0 = U 20 = −15 in above we get

LDe = 2.27 × 10 −6 cm

Surface Density Elevation :

32
 ∞
(
ni ∫ eU − eU 20 dx )
∆N n 2 0
= ∞ ∞
∆N n 0 LDe ni eU 20 (8)
∫ (e )
dx dx
∫ (1 − e ) L
U −U 20 −W
= −1 =
0
LDe 0 De

log10 W J = log10 15 = 1.1734

From Fig. 11 Surface density elevation for log10 W = 1.1734 and U 20 = 15

∆N n 2
= 6.4378 × 10 5
∆N n 0

∆N n 0 = LDe × ni × eU 20
= 6.96 × 10 −3 cm −3

∆N n 2 = 6.4378 × 10 5 × ∆N n 0 (9)

= 4.4758 ×10 3 cm −2

Surface Density Depression :

∆N p 2
(
ni ∫ e −U − e −U 20 dx ) ∞ ∞ (10)
∫ (e ) Ldx ∫ (e ) Ldx
0 U 20 −U W
= = −1 = −1
∆N p 0 LDe ni e −U 20 0 De 0 De

log10 W J = log10 15 = 1.1768

From Fig. 12 surface density elevation for log10 W = 1.1768 and U 20 = −15

∆N p 2
= 5.2967
∆N p 0

∆N p 0 = LDe × ni × eU 20 = 7.43 × 1010 cm −2

∆N p 2 = 5.2967 × ∆N p 0 = −3.9327 × 1011 cm −2 (11)

The negative sign denotes that there is a decrease in the areal density for holes.

33
Since our device is symmetrically doped device ∆N n1 = ∆N p 2 majority carrier density

and ∆N p1 = ∆N n 2 minority carrier density.

From (9) and (11) we can see that there is a difference between the electron densities, so

we have lost few electrons. So we term this deference as the energy released during

recombination.

∆N = ∆N n1 + ∆N n 2 = −3.9327 × 1011 cm −2 (12)

Energy released during recombination is given by

Erecomb = no. of carrier density x band gap energy x q

Erecomb = −3.9327 × 1011 cm −3 × 1.11eV × 1.69 × 10 −19 C

(13)
= −6.99 × 10 −8 J / cm 2

= −6.99 × 10 −8 × 6.24 × 1018 eV / cm 2 = −4.36 × 1011 eV / cm 2

So from (13) we see that Erecomb is a negative quantity, which means that the

energy is lost. In next chapter 7 we will examine Erecomb as function of U 20 + U 10 .

This calculations is also been verified by another method as shown in appendix B.

34
 5. EVALUATION OF ENERGY STORED IN THE ELECTRIC FIELD

Consider a general step junction with end regions of infinite length and with uniform

values of extrinsic doping on either side of the junction. Upon contact between the two

materials, electrons flow (diffuse) from the n-type semiconductor to the p-type

semiconductor because there is a higher concentration of electrons on the n side than on the p

side. As the electrons move toward the p-type region, they leave behind ionized donors

(positive charged) that are locked into the crystal lattice. At the same time, holes flow from

the p semiconductor to the n semiconductor, leaving behind ionized acceptors (negatively

charged). This separation of charges set up an electric field E , as shown in Fig. 9 from

chapter 6. So there is some amount of energy which is stored in the field, in this section we

are going to calculate the energy (Efield semi) stored in the electric field.

Energy stored in the infinite section of the semiconductor is given by [14]

∞
Energy = ∫ 1 2 × εE 2 (x ) Adx (14)
0

For simplicity we are using depletion approximation for estimating the electric field

in the sample [15]. It is an idealization of the actual charge distribution in the depletion

region that originates from the fact that the majority carrier has been removed. We say this

region is "depleted" of majority carriers. It facilitates the use of Poisson's equation because

we can obtain a closed-form solution. When using depletion approximation, we are assuming

that the carrier concentration ( n and p ) is negligible compared to the net doping

concentration ( N A and N D ) in the region straddling the metallurgical junction, otherwise

35
known as the depletion region. Outside this region, it is assumed that the net charge density is

zero.

5.1 Electric Field E Calculation on n-side

n-type silicon p-type silicon

xn x0 xp

wn wp

w
Fig. 19. n-p type junction with depletion width.

Electric field on n-side is given by [13]

ND
E=q (x − xn ) xn ≤ x ≤ x0 (15)
ε

∞ xn x0
(16)
I 1 = ∫ E 2 dx = ∫ E 2 dx + ∫ E 2 dx
0 0 xn

As we are using depletion approximation [15]. The electric field is confined to the

junction region and there is no electric field in the quasi-neutral region. So the electric field is

zero from 0 ≤ x ≤ x n and by substituting (15) in (16) we get

x0
(17)
= (qN D ε ) ∫ (x − x ) dx + 0
2 2
n
xn

by solving the integral in (17) we get

36
 x0
( x − xn )3
= (qN D ε) 2

3 xn

2
1  qN 
[
=  D  ( x0 − xn ) − ( xn − xn )
3 ε 
3 3
] (18)

From Fig. 19 we see that wn = x0 − xn , substituting in (18) we get

2
1  qN 
=  D  (wn )
3

3 ε 

2
wn3  qN D 
I1 =
3  ε  (19)

5.2 Electric Field E Calculation on p-side

Electric field on p side is given by [13]

ND
E=q
ε
(x p − x) x0 ≤ x ≤ x p
(20)

∞ xp ∞
= ∫ E dx = ∫ E dx + ∫ E 2 dx
2 2
(21)
0 x0 xp

As we are using depletion approximation [15]. The electric field is confined to the

junction region and there is no electric field in the quasi-neutral region. So electric field is

zero from x p ≤ x ≤ ∞ and by substituting (20) in (21) we get

xp

= (qN A ε ) ∫ (x − x ) dx + 0
2 2
p
(22)
x0

By solving the integral in (22) we get

37
 xp
( − x + x p )3
= (qN A ε )
2

−3 x0

2
1  qN 
3 ε 
[
= −  A  (− x p + x p ) − (− x0 + x p )
3 3
] (23)

From Fig. 9 we see that wn = x p − x0 , substituting in (23) we get

2
1  qN A 
 − (w p )
3
=− 
3 ε 

w 3p  qN A  2
I2 =
3  ε  (24)

5.3 Calculating Width w of Depletion Region

The built in voltage Vbi or barrier potential for p-n junction is given as follows [13]
N N  (25)
Vbi = k B T q × ln A 2 D 
 ni 

Where,
k B = Boltzmann constant = 1.3807 × 10 −23 J / o K
T = temperature in degree Kelvin = 300 o K
q = electron charge = 1.602 × 10 −19 C
N A = acceptor concentration cm −3
N D = donor concentration cm −3
ni = carrier density of intrinsic semiconductor
It can be seen that Vbi is purely function of temperature and doping.

Now w = wn + w p [13]
Where, w = total width of the depletion region
wn = width of the depletion region on the n-side

38
 1
 2εVbi  N A  1  2 (26)
wn =    
 q  N D  N A + N D 

Where, w p = width of the depletion region on the p-side

1
 2εVbi  N D  1  2 (27)
wp =    
 q  N A   N A + N D 

5.4 Calculating Energy Stored in the Field

From (14) we get

∞
Efield semi = ∫ 1 2 × ε E 2 t ox A dx
0

∞
1 1
× = ε ∫ E dx eV / cm
2 2
Efield semi
A 2 0 (28)

So by substituting E 2 = I 1 + I 2 in (28) we get

∞ ∞
1 1 1
× = ε ∫ I 1 dx + ε ∫ I 2 dx eV / cm
2
Efield semi
A 2 0 2 0 (29)

And then substituting the values of I 1 and I 2 from (19) and (24) in (29) we get

2 2
1 1 w 3 n  qN D  1 w 3 p  qN A 
Efield semi × = ε× + ε ×
A 2 3  ε  2 3  ε  (30)

39
5.5 Solution for Energy Stored in the Field in Case of Symmetric p-n Junction

Lets find the energy absorbed in the field in case of symmetric p-n junction where
U 10 = 15 and U 20 = −15

Various parameters have been evaluated below

N D = ni eU10 = 3.26 × 1016 cm −3

N A = ni e −U 10 = 3.26 × 1016 cm −3

N N 
Vbi = k B T q × ln A 2 D  = 0.776 V
 ni 

1
 2εVbi  N A  1  2
wn =     = 1.44 × 10 −6 cm
 q N
 D  A N + N D 

1
 2εVbi  N D  1  2
wp =     = 1.44 × 10 −6 cm
 q N
 A  A N + N D 

2
w 3  qN 
I 1 = n  D  = 11.39 V
3  ε 

w 3p  qN A  2
I2 = = 11.39 V
3  ε 

Now by substituting the above parameter values in (30) we get

1
Efield semi × = 1.18 × 10 −11 J cm 2 (31)
A

So from (31) we see that Erecomb is a positive quantity, which is stored in the electric field.

40
5.6 Behavior of Energy of Formation of a Junction as a Function of Doping

Ejunction formation = Erecomb + Efield semi

From (13) and (31) we see that

Erecomb = −6.99 × 10 −8 J / cm 2 and Efield semi = 1.18 × 10 −11 J cm 2

Therefore, Ejunction formation = −6.99 × 10 −8 J / cm 2

So from (13) and (31) we see that the total Ejunction formation is a negative quantity, which means

Ejunction formation < 0 and the energy is released. So because of the energy is released in form of

heat the sample become hot.

We have plotted the Energy curves at different U10 values. From all the four plots we

see that they behave the same at the symmetric region. The curve starts diverging when we

get close to the symmetric case. From the figure we can see that the energy stored in the

electric field is less than the energy released by recombination. Also if we see the energy

release during recombination, it increases linearly but after the symmetric case it starts

becoming independent of doping. But in case of energy stored in the electric field it starts

increasing linearly with the increase in the doping. The linear increase in the energy is

because the electric field increases with the doping. Also we can see as the U10 value

increases the energy is delayed.

In Fig. 20-(a) we have plot energy vs. U 20 + U10 stored in the electric field and

energy released during recombination for U10 = 5 .

41
 Energy vs. U20 + U 10 at U10 = 5
Energy stored in Electric Field Energy released during Recombination

5X10-10

4X10-10
Energy (J/cm2)

3X10-10

2X10-10

1X10-10

0
-20 -15 -10 -5 0 5

U20 + U10

(a)
.
Energy vs. U20 + U10 at U 10 = 10
Energy stored in Electric Field Energy released during Recombination

8X10-9

7X10-9

6X10-9
Energy (J/cm2)

5X10-9

4X10-9

3X10-9

2X10-9

1X10-9

-15 -10 -5 0 5 100

U20 + U10

(b)

Fig. 20. Energy vs. U20+ U10 (a) at U 10 =5, (b) at U 10 =10.

In Fig. 20-(b) we have plot energy vs. U 20 + U10 stored in the electric field and energy

released during recombination for U 10 = 10 .

42
 Energy vs. U20 + U10 at U10 = 15
Energy stored in Electric Field Energy released during Recombination
1.2X10-7

1X10-7

8X10-7
Energy (J/cm 2)

6X10-7

4X10-7

2X10-7

0
-10 -5 0 5 10 15
U20 + U10

(c)

Energy vs. U20 + U 10 at U 10 = 20

Energy stored in Electric Field Energy released during Recombination

1.6X10-6

1.4X10-6

1.2X10-6

1X10-6
Energy (J/cm 2)

8X10-6

6X10-6

4X10-6

2X10-6

-5 0 5 10 15 20
U20 + U10

(d)

Fig. 21. Energy vs. U20+ U10 (c) at U 10 =15, (d) at U 10 =20.

In Fig. 21-(c) we have plot energy vs. U 20 + U10 stored in the electric field and energy

released during recombination for U 10 = 15 .

43
 In Fig. 21-(d) we have plot energy vs. U 20 + U10 stored in the electric field and energy

released during recombination for U 10 = 20 .

44
6. CALCULATING RISE IN TEMPERATURE DUE TO ENERGY OF FORMATION

Energy as heat passes from a warm body with higher temperature to a cold body with

lower temperature. Also according to the second law of thermodynamics, this is stated as

follow. For any process occurring in a closed system the entropy increases for an irreversible

system and remains constant for a reversible system, but never decreases. We have calculated

the net energy liberated in the sample. This energy is released in the form of heat energy. So

in this section we are going to calculate the total heat energy lost at different sample length.

Density of silicon ρ is 2.329 g / cm 3 is given by the following formulae where mass

m is

m = ρ × Volume g
(32)

As we are varying the sample length from 10 um to 1 nm

We can calculate the mass as follows

m = ρ × area × l g
(33)

( )
Specific heat of silicon is C P = 0.7 J g o K is the amount of heat required to raise

the temperature of one kilogram of a substance by one degree Celsius (or Kelvin). Or specific

heat is the amount of heat per unit mass required to raise the temperature by one degree

Celsius (or Kelvin).

Q
CP = J / g oK
m × ∆T (34)

So to calculate the rise in temperature ∆T we use (33) and (34)

Q o
∆T = K
m × CP (35)
 Q area o
∆T = K
ρ × l × CP

In our case we have

∆T = Ejunction formation / ρ × l × CP o K

In Fig. 22 we plot rise in temperature ∆T vs. sample length l.

450

400
Rise in Temperature ∆T m K
O

350

300

250

200

150

100

50

0
0 20 40 60 80 100

Sample Length l nm

Fig. 22. Rise in temperature ∆T vs. sample length l.

From Fig. 21 we see that the change is temperature ∆T is not changing very much

for long sample length from 40nm and above. But as the sample size becomes smaller below

40nm we see the rise in the change in temperature ∆T . And for the sample length smaller

than 10nm the change in temperature ∆T has started increasing drastically.

46
 7. CONCLUSION

We have shown that the formation of a step junction results in a release of energy due

to the recombination of holes and electrons in the semiconductor. Depending upon the size of

the sample, this can produce a significant rise in the sample temperature. This is the first time

this effect has been analyzed. This effect is not important for traditional consumer

electronics. However, as we delve into biological applications related to nano cell dynamics

in living systems such energy interactions may play an important role.

 8. FUTURE WORK

In this work we have used depletion approximation for evaluating the energy stored

in electric field. So the next step will be to perform numerical integration for evaluating this

energy. Also, this analysis can be extended to the channel formation case in MOS

capacitance.
 REFERENCES

[1] R. P. Jindal, “Harnessing a few to do the work of a million: The technological

challenge,” ICEE Dig., India, Dec. 2012.

[2] V. V. Zhirnov, R. K. Cavin, “Future microsystems for information processing: Limits

and lessons from the living systems,” IEEE J. Electron Devices Society, vol. 1, no. 2,

pp. 29-47, Apr. 2013.

[3] R. H. Kingston and S. F. Neustadter, “ Calculation of the Space Charge, Electric

Field, and Free Carrier Concentration at the Surface of a Semiconductor ,” J. Appl.

Phys., vol. 26, no. 6, pp. 718-720, 1955.

[4] R. P. Jindal, R. M. Warner, “An extended and unified solution for the semiconductor

surface problem at equilibrium,” J. Appl. Phys, vol. 52, no. 12, pp.7427-7432, Dec.

1981.

[5] R. P. Jindal, R. M. Warner, “A general solution for step junctions with infinite

extrinsic end regions at equilibrium,” IEEE Trans. Electron Devices, vol. 28, no. 3,

pp.348-351, Dec. 1981.

[6] R. P. Jindal, “Bulk and surface effects on noise behavior of semiconductor devices,”

Ph. D. Thesis, Univ. of Minnesota, Mar. 1981.

[7] T. Sekigawa, Y. Hayashi, “XMOS Transistor for a 3D-IC,” Solid-State Electron,

vol.27, no. 7, pp. 827-830, 1994.

[8] K. Schuegraf, M. C. Abraham, “Semiconductor Logic Technology Innovation to

Achieve Sub-10 nm Manufacturing,” IEEE J. Electron Devices Society, vol. 1, no. 3,

pp. 66-75, 2013.

[9] C. Ortolland, T. Hoffmann, “Optimized ultra-low thermal budget process flow for

advanced High-K / Metal gate first CMOS using laser-annealing technology,” VLSI

Technology Symposium Dig., pp. 38-39, Jun. 2009.

[10] Dunga, Chenming Hu, “Modeling advanced FET technology in compact model,”

IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 1971-1978, Aug. 2006.

[11] L. Kakumanu, “Investigation of the noise behavior of semiconductor diodes,”

Master's Thesis, Univ. of Louisiana at Lafayette, Lafayette, Apr. 2011.

[12] Anderson and Anderson, “Fundamental of Semiconductor Devices,” 2nd ed., New

York, McGraw Hill, Aug. 2005.

[13] R. M. Warner and B. L. Grung, “Fundamental for the Integrated-Circuit Engineer,”

New York, John Wiley, Aug. 1990.

[14] R. Resnick, D. Halliday, “Fundamental of Physics,” New York, John Wiley, Oct.

2001.

[15] W. Shockley, “Theory of p-n junctions in semiconductors and p-n junction

transistors,” Bell Syst. Tech. J., vol. 28, pp. 435, 1949.

50
 APPENDIX A: MATLAB CODE

# Matlab code for evaluating Surface density elevation and surface density depression,

b(1) = 0.001;% initiaal value for w

i=1;

u20=1;% u20

inte(1)=0;% surface elevation density

inte2(1)=0;% surface depression density

c=exp(u20)+exp(-u20);

for i=1:366666; % loop running from 1 to 3666666

if b<1 % enter the loop only till b

d(i)=((exp(u20))*((exp(-b(i)))-1+b(i)))+((exp(-u20))*((exp(b(i)))-1-b(i)));

e(i)=sqrt(c/d(i));

f(i)=(exp(b(i)))-1;

g(i)=(e(i)*f(i))*(1/sqrt(2));

j(i)=(1-(exp(-b(i))));

h(i)=(e(i)*j(i))*(1/sqrt(2));

b(i+1) = b(i) + 0.00001;

if i<2

inte(i+1)=inte(i)+(0.001*g(i)/1);

inte2(i+1)=inte2(i)+(0.001*h(i)/1);

else

inte(i+1)=inte(i)+(0.00001*(g(i-1)+g(i))/2);
inte2(i+1)=inte2(i)+(0.00001*(h(i-1)+h(i))/2);

end

else

d(i)=((exp(u20))*((exp(-b(i)))-1+b(i)))+((exp(-u20))*((exp(b(i)))-1-b(i)));

e(i)=sqrt(c/d(i));

f(i)=exp(b(i))-1;

g(i)=(e(i)*f(i))*(1/sqrt(2));

j(i)=(1-(exp(-b(i))));

b(i+1) = b(i) + 0.0001;

h(i)=(e(i)*j(i))*(1/sqrt(2));

inte(i+1)=inte(i)+(0.0001*(g(i-1)+g(i))/2);

inte2(i+1)=inte2(i)+(0.0001*(h(i-1)+h(i))/2);

end

end

# Plotting Section

we=b';InteEle=inte'; InteDep=inte2';

horzcat(we,InteEle,InteDep);

coc=horzcat(we,InteEle,InteDep);

figure(1)

loglog(inte,b);xlabel('Surface density elevation');ylabel('W');title('Surface density elevation');

figure(2)

52
loglog(inte2,b);xlabel('Surface density depression');ylabel('W');title('Surface density

depression');

# Program ends

53
 APPENDIX B: INDEPENDENT VERIFICATION METHOD

In this section we are comparing the results for total charge in the semiconductor
evaluated using numerical integration vs. total charge evaluated by solving the electric field
equation.

Following is the method for evaluating the total charge by solving the electric field
equation. Now we can evaluate electric field analytically at the junction without any
approximation. A well known expression obtained by integrating Poisson-Boltzmann
equation is as follows [5]. We get net charge from Poisson-Boltzmann equation and then we
get the electric field

dW
= ( ) 2 
( )
 eU 20 e −W − 1 + W + e −U 20 (e W − 1 − W 

12

d ( x / L De )  eU 20 + e −U 20 
(36)

By substituting W = qψ k B T we get

d  qψ 
 k B T 
= ( )
2 
( )
 eU 20 e −W − 1 + W + e −U 20 (eW − 1 − W 

12

LDe
dx  eU 20 + e −U 20 

By rearranging the equation we get the electric field

dψ 
= ( ) ( )
 e U 20 e −W − 1 + W + e −U 20 (e W − 1 − W
2 


12
 k T
L De  × B
dx   e U 20 + e −U 20   q (37)
 

We know that the total charge in semiconductor is given by

Q =ε×E


Q = E ×ε =  ( ) ( )
 eU 20 e −W − 1 + W + e −U 20 (eW − 1 − W
2 


12
 kT
LDe  × B × ε
  eU 20 + e −U 20   q
 

The total charge in the semiconductor consist of ∆N and ∆P . By integrating we get

∞ ∞
Q = ∫ ( p − p 0 ) − ∫ (n − n0 )dx
0 0
Which can be written as follows
 ∞ ∞
Q = ∫ δp − ∫ δn
0 0
In our case we have
∞

∫ δ p = ∆N
0
p2 − ∆N n 2 on U10 side

∫ δ n = ∆N
0
p1 − ∆N n1 on U20 side

For example

U 10 = 20
U 20 = 0

cosh U 20 − cosh U 10 + U 10 sinh U 10 − U 20 sinh U 20

UJ =
sinh U 10 − sinh U 20

U J = 19
W J = U 20 − U J
Doping = nie (−U10 ) × 2.06 × 101

Calculating Debye length [13]

12
 ∈ k BT 1 
LDe = 
 2qni q cosh U 10 

L De = 1.87 × 10 −9

We have the field profile which is as follows

dW
= ( )
2 
( )
 eU 20 e −W − 1 + W + e −U 20 (eW − 1 − W 

12

d ( x / LDe )  eU 20 + e −U 20 

dW
After substituting the values we get = 0.857763882
d ( x L De )

dW
And after substituting Debye length value we get = 0.857763882
dx

55
 dψ
By multiplying k B T q the electric field = 1.19 × 10 7
dx

Now as we know the total charge is given by Q = E × ε

Q = 1.19 × 107 × 11.8 × 8.85 × 10 −12

By substituting the values we get

Q = 1.248969 × 10 −3 C
(38)

Now from the analytical calculation we have

∆N n1 = −7.7635772 × 1015
∆N n1 × q = −1.2421724 × 10 −3 C
∆N p1 = 5.5278946 × 10 −2
∆N p1 × q = 8.8446314 × 10 −21 C

And the difference is given by

∆N p1 − ∆N n1 = 1.2421724 × 10 −3 C
(39)

So if we compare (38) and (39) we see that the results match with each other over
0.006 × 10 −3 decimal places. Also we can see the total charge evaluated by solving the electric
field is more than the total charge evaluated by numerical integration.

56
Kawatkar, Prasanna. Bachelor of Engineering, University of Mumbai, Spring 2008; Master
of Science, University of Louisiana at Lafayette, Fall 2013
Major: Telecommunication
Title of Thesis: Energy of Formation of Step Junctions at Nano Dimensions
Thesis Director: Dr. R. P. Jindal
Pages in Thesis: 57; Words in Abstract: 70

ABSTRACT

Planar transistors have been the important building block of integrated circuits for

decades, during which the size of transistors has steadily decreased. We will evaluate energy

released due to recombination and also evaluate energy stored in the electric field for the step

junction case, and then calculate the net energy of formation for the step junction. Also, we

have calculated the change in temperature due to the energy of formation.

 BIOGRAPHICAL SKETCH

Prasanna U. Kawatkar was born in Maharashtra, India on November 7, 1986. He

received his Bachelor of Engineering from Mumbai University in May 2008. In August of

2009, he joined the Department of Electrical and Computer engineering to pursue a degree in

Telecommunication program at the University of Louisiana at Lafayette. He will earn a

Master of Science in Telecommunication in December 2013. His current research involves

analyzing energy of formation for step junctions at nano dimensions.