A B C D E

1 1

Compal confidential 2

Schematics Document
Mobile AMD S1G3 CPU with ATI
3
RS880M(NB) & SB710(SB) core logic 3

2009-03-15
REV:0.3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 1 of 56
A B C D E
 A B C D E

Compal Confidential
Consumer AMD 14" UMA - Ripley 2.0 (NBW20)
Accelerometer Thermal Sensor
72QFN
1
ST LIS302DLTR ADM1032ARMZ AMD S1G3 CPU DDR2-SO-DIMM X2 1

Page 30 Page 6 DDR2 800MHz 1.8V BANK 0, 1, 2, 3 Page 8, 9 Clock Generator

Dual Channel SLG8SP626VTR
Fan conn
638-PIN uFCPGA 638 Page 15
Page 4
Page 4, 5, 6, 7
Side-Port DDR2 SDRAM
Hyper Transport Link 1024Mbits(64Mbx16)
Page 12
16X16

USB conn x2 daughter board

Page 31
LVDS Panel ATI RS880M
Interface Page 17 DDR2 400MHz BT Conn Page 31 New Module
CRT
Page 16 Page 10, 11, 12, 13, 14
2 Mini-Card WWAN
Page 26
2

USB2.0 X12
HDMI A-Link Express II
Page 18
4X PCI-E
USB conn x1
Page 31

PCI-E BUS*5 Azalia (HDA I/F)

USB WebCam
SATA Master-1 Module
ATI SB710 SATA Master-2
Page 17

SATA Slave
CardReader Realtek Mini-Card*2 Express Card FingerPrinter AES1610
JMicron 8102E(10/100M) WLAN & WWAN
SATA Slave Module
Page 26 Page 19, 20, 21, 22, 23 USBx1 page 35
JMB385-LGEZ0A
Page 27 Page 25 Page 26
MDC V1.5 daughter board
Page 34

RJ45/11 CONN LPC BUS Audio CKT

3
CardReader Socket Page 25 AMP & Audio Jack
3

Codec_IDT9271B7
Page 27 Page 28 TPA6017A2 Page 29

KBC SATA HDD Connector

ENE KB926-C0 Page 24
Page 33

Docking CONN. LED SATA ODD Connector

Page 24

*RJ-45(LED*2) P41 Touch Pad CONN.

Page 34
Int.KBD
Page 33
*RJ-11(Pass Through) Multi-Bay HDD/ODD Option Connector
*CRT Page 24
*COMPOSITE Video Out
RTC CKT.
*S-VIDEO OUT Page 19
Consumer IR SPI SPI ROM e-SATA Connector
*SPDIF MX25L1605
Page 34 Page 31
*Headphone/Line Out L/R Power OK CKT. AM2C-12G
Page 32
*Stereo Mic L/R P35
4
*Volume Control 4

*Consumer IR
*USB x1 Power On/Off CKT.
*DC JACK P35
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

DC/DC Interface CKT. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Page 35 Page 36 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 2 of 56
A B C D E
 A B C D E

Symbol Note : 1.0/1.0a

For Riply PA-> PA@, RP@
: means Digital Ground For Riply PR-> PR@, RP@, PRM@
For Rachman UMA-> RM@, PRM@
O MEANS ON X MEANS OFF
Voltage Rails RP10@
Z ZZ
RM10@
Z ZZ
: means Analog Ground
1 PCB for 1.0/1.0a 1

L Layout Notes

PCB-Ripley MB PCB-Rachman UMA MB

+5VS Please see VGA@ as no install. No support RX780M. DAZ=DAZ03Y00201 DAZ=DAZ03Y00101
+3VS
+1.5VS : Question Area Mark.(Wait check) RP11@,RM11@:For 1.A PCB
power
plane +0.9V RP10@,RM10@:For 1.0 PCB.
+VCCP "*" as default BOM setting
+5VALW +1.8V +CPU_CORE *PA@ : means install when Ripley PA. U3 U15

+B PR@ : means install when Ripley PR.

SB700
+3VALW +VGA_CORE RM@ : means install when Rachman. RS780
+2.5VS *RP@ : means install when Ripley. RS780 R1 SB700 R1
RS780R1@ SBR1@
State +1.8VS SIDE@ : means install when SidePort support.
+1.2VS @ : means just reserve , no build
+0.9VGA 45@ : Install when 45 level Assy

2 R3 NB and SB: RS780R3@,SBR3@ 2

R1 NB and SB: RS780R1@,SBR1@

S0
O O O O
RP11@ RM11@
1.1 Z ZZ Z ZZ
S1
O O O O For Riply PA-> PA@, RP@,RPZ@ PCB for 1.1
S3 For Riply PR-> PR@, RP@, PRM@,RPZ@
O O O X For Rachman UMA-> RM@, PRM@,RMZ@ PCB-Ripley MB PCB-Rachman UMA MB
DAZ=DAZ03Y00203 DAZ=DAZ03Y00102
S5 S4/AC 2.0
O O X X RP@ RM@ X76
Z ZZ Z ZZ

S5 S4/ Battery only For Riply PA-> PA@/RP@/RPZ@

O X X X PCB for 2.0
X76
S5 S4/AC & Battery For Rachman UMA-> RM@/PRM@/RMZ@ PCB-Ripley MB PCB-Rachman UMA MB
don't exist X X X X SMBUS Control Table
DAZ=DAZ09000102 DAZ=DAZ09100102

THERMAL
SERIAL SENSOR
SOURCE INVERTER BATT EEPROM CPU & SODIMM CLK CHIP MINI CARD LCD HDMI G-Sensor
ADM1032 I / II Slot 2
3 3
SMB_EC_CK1
I2C / SMBUS ADDRESSING KB926 X V V VCPU X X X X X X
SMB_EC_DA1
SMB_EC_CK2
DEVICE HEX ADDRESS SMB_EC_DA2
KB926 X X X V
ADM1032 X X X X X X
DDR SO-DIMM 0 A0 10100000 I2C_CLK
DDR SO-DIMM 1 A4 10100100 I2C_DATA
RS780M
X X X X X X X V X X
CL OCK GENERATOR (EXT.) D2 11010010 DDC_CLK0
DDC_DATA0
RS780M X X X X X X X X V X
DDC_CLK1
EC SM Bus1 address EC SM Bus2 address DDC_DATA1
RS780M X X X X X X X X X X
SCL0
Device HEX Address Device HEX Address
SDA0
SB700 X X X X V V X X X X
Smart Battery 16H 0001 011X b CPU 98H 1001 100X b SCL1
24C16 A0H 1010 000X b ADI1032-2 CPU 9AH 1001 101X b SDA1
SB700 X X X X X X V X X X
SCL2
SDA2
SB700 X X X X X X X X X V
4 4
SCL3
SDA3
SB700 X X X X X X X X X X
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 3 of 56
A B C D E
 A B C D E

1 1

+1.2V_HT
VLDT CAP.
250 mil

1 1 1 1 1 1
C1 C2 C3 C4 C5 C6
H_CADIP[0..15] H_CADOP[0..15] 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
<10> H_CADIP[0..15] H_CADOP[0..15] <10>
H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2
<10> H_CADIN[0..15] H_CADON[0..15] <10>

Near CPU Socket

+1.2V_HT
JCPUA

VLDT=500mA D1 HT LINK AE2 +VLDT_B 1 2

VLDT_A0 VLDT_B0 C7 4.7U_0805_10V4Z
D2 VLDT_A1 VLDT_B1 AE3
D3 AE4 If VLDT is connected only on one side, one
VLDT_A2 VLDT_B2 4.7uF cap should be added to the island
D4 AE5
VLDT_A3 VLDT_B3 side.
H_CADIP0 E3 AD1 H_CADOP0
H _CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 AC1
H_CADIP1 L0_CADIN_L0 L0_CADOUT_L0 H_CADOP1
E1 L0_CADIN_H1 L0_CADOUT_H1 AC2
H _CADIN1 F1 AC3 H_CADON1
H_CADIP2 L0_CADIN_L1 L0_CADOUT_L1 H_CADOP2
G3 AB1
H _CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 AA1
2 H_CADIP3 L0_CADIN_L2 L0_CADOUT_L2 H_CADOP3 2
G1 L0_CADIN_H3 L0_CADOUT_H3 AA2
H _CADIN3 H1 AA3 H_CADON3
H_CADIP4 L0_CADIN_L3 L0_CADOUT_L3 H_CADOP4
J1 W2
H _CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
H_CADIP5 L3 V1 H_CADOP5
H _CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 U1
H_CADIP6 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP6
L1 L0_CADIN_H6 L0_CADOUT_H6 U2
H _CADIN6 M1 U3 H_CADON6
H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H _CADIN7 N2 R1 H_CADON7
H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
H _CADIN8 F5 AD3 H_CADON8
H_CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP9
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5
H _CADIN9 F4 AC5 H_CADON9
H_CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP10
G5 AB4
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 AB3
H_CADIP11 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP11
H3 AB5
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 AA5
H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12
K3 Y5
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
H_CADIP13 L5 V4 H_CADOP13
H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13
M5 V3
H_CADIP14 L0_CADIN_L13 L0_CADOUT_L13 H_CADOP14
M3 V5
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 U5
H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15
N5 T4
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15 +5VS
P5 T3
L0_CADIN_L15 L0_CADOUT_L15
J3 Y1
<10>
<10>
H_CLKIP0
H_CLKIN0 J2
J5
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKOUT_H0
L0_CLKOUT_L0
W1
Y4
H_CLKOP0
H_CLKON0
<10>
<10> PWM Fan Control circuit JP2
<10> H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 <10>

1
<10> H_CLKIN1 K5 Y3 H_CLKON1 <10> 1 1 1
L0_CLKIN_L1 L0_CLKOUT_L1 C8 C9 1
2
3 D1 0.1U_0402_16V4Z 2 3
<10> H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 <10>
P1 R3 CH751H-40PT_SOD323-2 4.7U_0805_10V4Z 3
<10> H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 <10> 2 2 GND
<10> H_CTLIP1 P3 T5 H_CTLOP1 <10> 4

2
L0_CTLIN_H1 L0_CTLOUT_H1 GND
<10> H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 <10>
ACES_88231-02001
+VCC_FAN CONN@
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@

1
2
5
6

1
Athlon 64 S1
Processor Socket D Q1 @ D2
9/20 SP07000DM00/SP07000EQ00 G
3 RLZ5.1B_LL34
<33> FAN_PWM S SI3456BDV-T1-E3_TSOP6

2
4
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 HT I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 4 of 56
A B C D E
 A B C D E

Processor DDR2 Memory Interface

PLACE CLOSE TO PROCESSOR
1 WITHIN 1.5 INCH 1
JCPUC
<9> DDR_B_D[63..0]
MEM:DATA
DDR_A_CLK0 DDR_B_D0 DDR_A_D0 DDR_A_D[63..0] <8>
C11 MB_DATA0 MA_DATA0 G12
1 DDR_B_D1 A11 F12 DDR_A_D1
DDR_B_D2 MB_DATA1 MA_DATA1 DDR_A_D2
A14 H14
C10 DDR_B_D3 MB_DATA2 MA_DATA2 DDR_A_D3
B14 MB_DATA3 MA_DATA3 G14
1.5P_0402_50V9C DDR_B_D4 G11 H11 DDR_A_D4
DDR_A_CLK#0 2 DDR_B_D5 MB_DATA4 MA_DATA4 DDR_A_D5
E11 MB_DATA5 MA_DATA5 H12
DDR_B_D6 D12 C13 DDR_A_D6
DDR_A_CLK1 DDR_B_D7 MB_DATA6 MA_DATA6 DDR_A_D7
A13 E13
DDR_B_D8 MB_DATA7 MA_DATA7 DDR_A_D8
1 A15 MB_DATA8 MA_DATA8 H15
DDR_B_D9 A16 E15 DDR_A_D9
C11 DDR_B_D10 MB_DATA9 MA_DATA9 DDR_A_D10
A19 MB_DATA10 MA_DATA10 E17
1.5P_0402_50V9C DDR_B_D11 A20 H17 DDR_A_D11
DDR_A_CLK#1 2 DDR_B_D12 MB_DATA11 MA_DATA11 DDR_A_D12
C14 E14
+1.8V DDR_B_D13 MB_DATA12 MA_DATA12 DDR_A_D13
D14 F14
DDR_B_D14 MB_DATA13 MA_DATA13 DDR_A_D14
C18 MB_DATA14 MA_DATA14 C17
DDR_B_CLK0 DDR_B_D15 D18 G17 DDR_A_D15
MB_DATA15 MA_DATA15

2
1 DDR_B_D16 D20 G18 DDR_A_D16
R1 DDR_B_D17 MB_DATA16 MA_DATA16 DDR_A_D17
A21 C19
C14 DDR_B_D18 MB_DATA17 MA_DATA17 DDR_A_D18
D24 D22
1.5P_0402_50V9C 1K_0402_1% DDR_B_D19 MB_DATA18 MA_DATA18 DDR_A_D19
C25 E20
DDR_B_CLK#0 2 DDR_B_D20 MB_DATA19 MA_DATA19 DDR_A_D20
B20 E18

1
+MCH_REF DDR_B_D21 MB_DATA20 MA_DATA20 DDR_A_D21
C20 MB_DATA21 MA_DATA21 F18
DDR_B_CLK1 DDR_B_D22 B24 B22 DDR_A_D22
MB_DATA22 MA_DATA22

2
1 1 1 DDR_B_D23 C24 C23 DDR_A_D23
R2 C12 C13 DDR_B_D24 MB_DATA23 MA_DATA23 DDR_A_D24
E23 F20
C15 DDR_B_D25 MB_DATA24 MA_DATA24 DDR_A_D25
E24 F22
1.5P_0402_50V9C 1K_0402_1% DDR_B_D26 MB_DATA25 MA_DATA25 DDR_A_D26
G25 MB_DATA26 MA_DATA26 H24
DDR_B_CLK#1 2 2 2 DDR_B_D27 G26 J19 DDR_A_D27

1
1000P_0402_25V8J DDR_B_D28 MB_DATA27 MA_DATA27 DDR_A_D28
C26 E21
0.1U_0402_16V4Z DDR_B_D29 MB_DATA28 MA_DATA28 DDR_A_D29
D26 E22
2 DDR_B_D30 MB_DATA29 MA_DATA29 DDR_A_D30 2
G23 MB_DATA30 MA_DATA30 H20
+0.9V +0.9V DDR_B_D31 G24 H22 DDR_A_D31
JCPUB DDR_B_D32 MB_DATA31 MA_DATA31 DDR_A_D32
AA24 Y24
DDR_B_D33 MB_DATA32 MA_DATA32 DDR_A_D33
AA23 MB_DATA33 MA_DATA33 AB24
D10 W10 DDR_B_D34 AD24 AB22 DDR_A_D34
VTT1 MEM:CMD/CTRL/CLK VTT5 DDR_B_D35 MB_DATA34 MA_DATA34 DDR_A_D35
Place them close to CPU within 1" C10
VTT2 VTT6
AC10 AE24
MB_DATA35 MA_DATA35
AA21
B10 AB10 DDR_B_D36 AA26 W22 DDR_A_D36
VTT3 VTT7 DDR_B_D37 MB_DATA36 MA_DATA36 DDR_A_D37
AD10 AA10 AA25 W21
R4 39.2_0402_1% VTT4 VTT8 DDR_B_D38 MB_DATA37 MA_DATA37 DDR_A_D38
VTT9 A10 AD26 MB_DATA38 MA_DATA38 Y22
1 2 AF10 DDR_B_D39 AE25 AA22 DDR_A_D39
MEMZP VTT_SENSE DDR_B_D40 MB_DATA39 MA_DATA39 DDR_A_D40
+1.8V 1 2 AE10 MEMZN VTT_SENSE Y10 PAD T1 AC22 MB_DATA40 MA_DATA40 Y20
R3 39.2_0402_1% DDR_B_D41 AD22 AA20 DDR_A_D41
+MCH_REF DDR_B_D42 MB_DATA41 MA_DATA41 DDR_A_D42
T2 PAD H16 RSVD_M1 MEMVREF W17 AE20 MB_DATA42 MA_DATA42 AA18
DDR_B_D43 AF20 AB18 DDR_A_D43
DDR_A_ODT0 DDR_B_D44 MB_DATA43 MA_DATA43 DDR_A_D44
<8> DDR_A_ODT0 T19 B18 PAD T3 AF24 AB21
DDR_A_ODT1 MA0_ODT0 RSVD_M2 DDR_B_D45 MB_DATA44 MA_DATA44 DDR_A_D45
<8> DDR_A_ODT1 V22 AF23 AD21
MA0_ODT1 DDR_B_ODT0 DDR_B_D46 MB_DATA45 MA_DATA45 DDR_A_D46
U21 W26 DDR_B_ODT0 <9> AC20 AD19
MA1_ODT0 MB0_ODT0 DDR_B_ODT1 DDR_B_D47 MB_DATA46 MA_DATA46 DDR_A_D47
V19 W23 DDR_B_ODT1 <9> AD20 Y18
MA1_ODT1 MB0_ODT1 DDR_B_D48 MB_DATA47 MA_DATA47 DDR_A_D48
Y26 AD18 AD17
DDR_CS0_DIMMA# MB1_ODT0 DDR_B_D49 MB_DATA48 MA_DATA48 DDR_A_D49
<8> DDR_CS0_DIMMA# T20 MA0_CS_L0 AE18 MB_DATA49 MA_DATA49 W16
DDR_CS1_DIMMA# U19 V26 DDR_CS0_DIMMB# DDR_B_D50 AC14 W14 DDR_A_D50
<8> DDR_CS1_DIMMA# MA0_CS_L1 MB0_CS_L0 DDR_CS0_DIMMB# <9> MB_DATA50 MA_DATA50
U20 W25 DDR_CS1_DIMMB# DDR_B_D51 AD14 Y14 DDR_A_D51
MA1_CS_L0 MB0_CS_L1 DDR_CS1_DIMMB# <9> DDR_B_D52 MB_DATA51 MA_DATA51 DDR_A_D52
V20 U22 AF19 Y17
MA1_CS_L1 MB1_CS_L0 DDR_B_D53 MB_DATA52 MA_DATA52 DDR_A_D53
AC18 AB17
DDR_CKE0_DIMMA DDR_CKE0_DIMMB DDR_B_D54 MB_DATA53 MA_DATA53 DDR_A_D54
<8> DDR_CKE0_DIMMA J22 J25 DDR_CKE0_DIMMB <9> AF16 AB15
DDR_CKE1_DIMMA MA_CKE0 MB_CKE0 DDR_CKE1_DIMMB DDR_B_D55 MB_DATA54 MA_DATA54 DDR_A_D55
<8> DDR_CKE1_DIMMA J20 H26 DDR_CKE1_DIMMB <9> AF15 AD15
MA_CKE1 MB_CKE1 DDR_B_D56 MB_DATA55 MA_DATA55 DDR_A_D56
AF13 MB_DATA56 MA_DATA56 AB13
N19 P22 DDR_B_D57 AC12 AD13 DDR_A_D57
MA_CLK_H5 MB_CLK_H5 DDR_B_D58 MB_DATA57 MA_DATA57 DDR_A_D58
N20 R22 AB11 Y12
DDR_A_CLK0 MA_CLK_L5 MB_CLK_L5 DDR_B_CLK0 DDR_B_D59 MB_DATA58 MA_DATA58 DDR_A_D59
<8> DDR_A_CLK0 E16 A17 DDR_B_CLK0 <9> Y11 W11
DDR_A_CLK#0 MA_CLK_H1 MB_CLK_H1 DDR_B_CLK#0 DDR_B_D60 MB_DATA59 MA_DATA59 DDR_A_D60
<8> DDR_A_CLK#0 F16 A18 DDR_B_CLK#0 <9> AE14 AB14
DDR_A_CLK1 MA_CLK_L1 MB_CLK_L1 DDR_B_CLK1 DDR_B_D61 MB_DATA60 MA_DATA60 DDR_A_D61
<8> DDR_A_CLK1 Y16 AF18 DDR_B_CLK1 <9> AF14 AA14
3 DDR_A_CLK#1 MA_CLK_H7 MB_CLK_H7 DDR_B_CLK#1 DDR_B_D62 MB_DATA61 MA_DATA61 DDR_A_D62 3
<8> DDR_A_CLK#1 AA16 MA_CLK_L7 MB_CLK_L7 AF17 DDR_B_CLK#1 <9> AF11 MB_DATA62 MA_DATA62 AB12
P19 R26 DDR_B_D63 AD11 AA12 DDR_A_D63
MA_CLK_H4 MB_CLK_H4 MB_DATA63 MA_DATA63
P20 R25 <9> DDR_B_DM[7..0] DDR_A_DM[7..0] <8>
MA_CLK_L4 MB_CLK_L4 DDR_B_DM0 DDR_A_DM0
<8> DDR_A_MA[15..0] DDR_B_MA[15..0] <9> A12 MB_DM0 MA_DM0 E12
DDR_A_MA0 N21 P24 DDR_B_MA0 DDR_B_DM1 B16 C15 DDR_A_DM1
DDR_A_MA1 MA_ADD0 MB_ADD0 DDR_B_MA1 DDR_B_DM2 MB_DM1 MA_DM1 DDR_A_DM2
M20 N24 A22 E19
DDR_A_MA2 MA_ADD1 MB_ADD1 DDR_B_MA2 DDR_B_DM3 MB_DM2 MA_DM2 DDR_A_DM3
N22 P26 E25 F24
DDR_A_MA3 MA_ADD2 MB_ADD2 DDR_B_MA3 DDR_B_DM4 MB_DM3 MA_DM3 DDR_A_DM4
M19 N23 AB26 AC24
DDR_A_MA4 MA_ADD3 MB_ADD3 DDR_B_MA4 DDR_B_DM5 MB_DM4 MA_DM4 DDR_A_DM5
M22 N26 AE22 Y19
DDR_A_MA5 MA_ADD4 MB_ADD4 DDR_B_MA5 DDR_B_DM6 MB_DM5 MA_DM5 DDR_A_DM6
L20 MA_ADD5 MB_ADD5 L23 AC16 MB_DM6 MA_DM6 AB16
DDR_A_MA6 M24 N25 DDR_B_MA6 DDR_B_DM7 AD12 Y13 DDR_A_DM7
DDR_A_MA7 MA_ADD6 MB_ADD6 DDR_B_MA7 MB_DM7 MA_DM7
L21 L24
DDR_A_MA8 MA_ADD7 MB_ADD7 DDR_B_MA8 DDR_B_DQS0 DDR_A_DQS0
L19 MA_ADD8 MB_ADD8 M26 <9> DDR_B_DQS0 C12 MB_DQS_H0 MA_DQS_H0 G13 DDR_A_DQS0 <8>
DDR_A_MA9 K22 K26 DDR_B_MA9 DDR_B_DQS#0 B12 H13 DDR_A_DQS#0
MA_ADD9 MB_ADD9 <9> DDR_B_DQS#0 MB_DQS_L0 MA_DQS_L0 DDR_A_DQS#0 <8>
DDR_A_MA10 R21 T26 DDR_B_MA10 DDR_B_DQS1 D16 G16 DDR_A_DQS1
DDR_A_MA11 MA_ADD10 MB_ADD10 DDR_B_MA11 <9> DDR_B_DQS1 DDR_B_DQS#1 MB_DQS_H1 MA_DQS_H1 DDR_A_DQS#1 DDR_A_DQS1 <8>
L22 L26 <9> DDR_B_DQS#1 C16 G15 DDR_A_DQS#1 <8>
DDR_A_MA12 MA_ADD11 MB_ADD11 DDR_B_MA12 DDR_B_DQS2 MB_DQS_L1 MA_DQS_L1 DDR_A_DQS2
K20 L25 <9> DDR_B_DQS2 A24 C22 DDR_A_DQS2 <8>
DDR_A_MA13 MA_ADD12 MB_ADD12 DDR_B_MA13 DDR_B_DQS#2 MB_DQS_H2 MA_DQS_H2 DDR_A_DQS#2
V24 W24 <9> DDR_B_DQS#2 A23 C21 DDR_A_DQS#2 <8>
DDR_A_MA14 MA_ADD13 MB_ADD13 DDR_B_MA14 DDR_B_DQS3 MB_DQS_L2 MA_DQS_L2 DDR_A_DQS3
K24 J23 <9> DDR_B_DQS3 F26 G22 DDR_A_DQS3 <8>
DDR_A_MA15 MA_ADD14 MB_ADD14 DDR_B_MA15 DDR_B_DQS#3 MB_DQS_H3 MA_DQS_H3 DDR_A_DQS#3
K19 J24 <9> DDR_B_DQS#3 E26 G21 DDR_A_DQS#3 <8>
MA_ADD15 MB_ADD15 DDR_B_DQS4 MB_DQS_L3 MA_DQS_L3 DDR_A_DQS4
<9> DDR_B_DQS4 AC25 AD23 DDR_A_DQS4 <8>
DDR_A_BS#0 DDR_B_BS#0 DDR_B_DQS#4 MB_DQS_H4 MA_DQS_H4 DDR_A_DQS#4
<8> DDR_A_BS#0 R20 MA_BANK0 MB_BANK0 R24 DDR_B_BS#0 <9> <9> DDR_B_DQS#4 AC26 MB_DQS_L4 MA_DQS_L4 AC23 DDR_A_DQS#4 <8>
DDR_A_BS#1 R23 U26 DDR_B_BS#1 DDR_B_DQS5 AF21 AB19 DDR_A_DQS5
<8> DDR_A_BS#1 DDR_A_BS#2 MA_BANK1 MB_BANK1 DDR_B_BS#2 DDR_B_BS#1 <9> <9> DDR_B_DQS5 DDR_B_DQS#5 MB_DQS_H5 MA_DQS_H5 DDR_A_DQS#5 DDR_A_DQS5 <8>
<8> DDR_A_BS#2 J21 MA_BANK2 MB_BANK2 J26 DDR_B_BS#2 <9> <9> DDR_B_DQS#5 AF22 MB_DQS_L5 MA_DQS_L5 AB20 DDR_A_DQS#5 <8>
DDR_B_DQS6 AE16 Y15 DDR_A_DQS6
<9> DDR_B_DQS6 MB_DQS_H6 MA_DQS_H6 DDR_A_DQS6 <8>
DDR_A_RAS# R19 U25 DDR_B_RAS# DDR_B_DQS#6 AD16 W15 DDR_A_DQS#6
<8> DDR_A_RAS# MA_RAS_L MB_RAS_L DDR_B_RAS# <9> <9> DDR_B_DQS#6 MB_DQS_L6 MA_DQS_L6 DDR_A_DQS#6 <8>
DDR_A_CAS# T22 U24 DDR_B_CAS# DDR_B_DQS7 AF12 W12 DDR_A_DQS7
<8> DDR_A_CAS# DDR_A_WE# MA_CAS_L MB_CAS_L DDR_B_WE# DDR_B_CAS# <9> <9> DDR_B_DQS7 DDR_B_DQS#7 MB_DQS_H7 MA_DQS_H7 DDR_A_DQS#7 DDR_A_DQS7 <8>
<8> DDR_A_WE# T24 U23 DDR_B_WE# <9> <9> DDR_B_DQS#7 AE12 W13 DDR_A_DQS#7 <8>
MA_WE_L MB_WE_L MB_DQS_L7 MA_DQS_L7

FOX_PZ6382A-284S-41F_GRIFFIN FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1 Athlon 64 S1
4 Processor Processor Socket 4
Socket CONN@

CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 DDRII I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 5 of 56
A B C D E
 A B C D E

+2.5VDDA VDDA=300mA
L1
+2.5VS 1 2 3300P_0402_50V7K 1 2
02/27 Change net name to EN0.
+1.8V
1 FBM_L11_201209_300L_0805 R10 10K_0402_5% @ R6 0_0402_5%
1 1 1 1 2 1 2 EN0 <37,39>
@ C16 + R5 300_0402_5%

2
B
100U_D2_10VM 4.7U_0805_10V4Z C17 C18 C19 Q3 1 2 H_THERMTRIP#_EC <33>
0.22U_0603_16V4Z R16 0_0402_5%
2 2 2 2

C
CPU_THERMTRIP#_R 3 1 1 2 H_THERMTRIP# <20>
PMBT3904_SOT23 R7 0_0402_5%

JCPUD
+1.8V 2 1
F8 M11 R11 @ 10K_0402_5%
1 VDDA1 KEY1 1
Place close to CPU wihtin 1.5" F9 VDDA2 KEY2 W18 1 2

2
B
R9 300_0402_5% @ MMBT3904_NL_SOT23-3
1 2 3900P_0402_50V7K CPU_CLKIN_SC_P A9 A6 CPU_SVC Q2
<15> CLK_CPU_BCLK CLKIN_H SVC CPU_SVC <43>

E
C20 CPU_CLKIN_SC_N A8 A4 CPU_SVD CPU_PRO CHOT#_1.8 3 1
CLKIN_L SVD CPU_SVD <43> H_PROCHOT# <19>

C
LDT_RST#
0718 Silego -- 216 ohm R8 H_PWRGD_CPU
B7
A7
RESET_L 02/12 Remove R59. 1
@ R59
2
0_0402_5%
169_0402_1% LDT_STOP# PWROK CPU_THERMTRIP#_R
F10 LDTSTOP_L THERMTRIP_L AF6
CPU_LDT_REQ# C6 AC7 CPU_PROCHOT#_1.8 R17 +1.8V

2
LDTREQ_L PROCHOT_L CPU_MEMHOT#_1.8V
<15> CLK_CPU_BCLK# 1 2 AA8 2 1 +1.8V
C21 3900P_0402_50V7K CPU_SIC MEMHOT_L R22 1K_0402_5%
AF4 SIC
Address:100_1100 CPU_SID AF5 @ 300_0402_5% CPU_SVC 1 2
SID THERMDC_CPU CPU_SVD
AE6 ALERT_L THERMDC W7 1 2
W8 THERMDA_CPU R23 1K_0402_5%
R13 THERMDA
1 2 44.2_0402_1% CPU_HTREF0 R6
HT_REF0
+1.2V_HT R14 1 2 44.2_0402_1% CPU_HTREF1 P6
HT_REF1
0718 AMD --> 1K ohm
CPU_VDD0_FB_H
<43> CPU_VDD0_FB_H
<43> CPU_VDD0_FB_L CPU_VDD0_FB_L
F6
E6
VDD0_FB_H VDDIO_FB_H
W9
Y9
PAD
PAD
T42
T43
+1.8V sense no support
VDD0_FB_L VDDIO_FB_L +CPU_CORE_NB
CPU_VDD1_FB_H Y6 H6 VDD_NB_FB_H
CPU_VDD1_FB_L AB6 VDD1_FB_H VDDNB_FB_H VDD_NB_FB_L VDD_NB_FB_H <43>
G6 R484 10_0402_5%
VDD1_FB_L VDDNB_FB_L VDD_NB_FB_L <43> VDD_NB_FB_H 1 2
CPU_DBRDY G10 VDD_NB_FB_L 1 2
CPU_TMS DBRDY CPU_DBREQ# R485 10_0402_5%
AA9 E10
CPU_TCK TMS DBREQ_L
AC9 TCK
CPU_TRST# AD9 AE9 CPU_TDO Close to CPU
CPU_TDI TRST_L TDO
AF9
TDI
+1.8VS T4 PAD CPU_TEST23_TSTUPD AD7 J7 CPU_TEST28_H_PLLCHRZ_P route as differential
+CPU_CORE_0 TEST23 TEST28_H CPU_TEST28_L_PLLCHRZ_N PAD T5
TEST28_L
H8 PAD T6 as short as possible
R487 10_0402_5% CPU_TEST19_PLLTEST0 H10 testpoint under package
TEST18
2

2 2
1 2 CPU_VDD0_FB_H CPU_TEST18_PLLTEST1 G9 TEST19 TEST17 D7 CPU_TEST17_BP3
PAD T7
R15 1 2 CPU_VDD0_FB_L E7 CPU_TEST16_BP2
PAD T8
R486 10_0402_5% T9 PAD CPU_TEST25_H_BYPASSCLK_H TEST16 CPU_TEST15_BP1
300_0402_5% E9 F7 PAD T10
T11 PAD CPU_TEST25_L_BYPASSCLK_L TEST25_H TEST15 CPU_TEST14_BP0
E8 TEST25_L TEST14 C7 PAD T12
Close to CPU
1

LDT_RST# CPU_TEST21_SCANEN AB8 C3

<19> LDT_RST# TEST21 TEST7
CPU_TEST20_SCANCLK2 AF7 K8
+CPU_CORE_0 CPU_TEST24_SCANCLK1 TEST20 TEST10
1 AE7
C22 @ R489 10_0402_5% CPU_TEST22_SCANSHIFTEN TEST24
AE8 TEST22 TEST8 C4
0.01U_0402_25V4Z 1 2 CPU_VDD1_FB_H CPU_TEST12_SCANSHIFTENB AC8
TEST12
@ 1 2 CPU_VDD1_FB_L CPU_TEST27_SINGLECHAIN AF8 TEST27
2 CPU_TEST29_H_FBCLKOUT_P
C9 PAD T13
@R488 10_0402_5% R25 TEST29_H CPU_TEST29_L_FBCLKOUT_N
1 2 0_0402_5% C2 TEST9 TEST29_L C8 PAD T14
AA6
TEST6
Reserve the R488 and R489 for S1G3 CPU
A3 H18
+1.8VS RSVD1 RSVD10
A5 H19
RSVD2 RSVD9
B3 AA7
RSVD3 RSVD8
1 2 B5 D5
RSVD4 RSVD7
2

@ C1 C5
R21 @ C939 0.1U_0402_16V4Z RSVD5 RSVD6
300_0402_5% R175
@ R814 FOX_PZ6382A-284S-41F_GRIFFIN
+3VS 2 1 2 1 CONN@
1

H_PWRGD_CPU 2.09V for Gate

<19> H_PWRGD_CPU
20K_0402_5% 34.8K_0402_1%~N
1
C23
02/15 Follow Trinity design.
2
G

0.1U_0402_16V7K
2
CPU_SID 3 1 SMB_EC_DA1
02/15 Change R18 and R19
SMB_EC_DA1 <32,33,34,37>
3 R18 @ from 390 to 2.2K ohm. 3
S

+1.8V 2 1 Q127
2.2K_0402_5% FDV301N_NL_SOT23-3
+1.8VS R19
03/04 Reserve R175, R814, C939, Q127 and Q129.
+1.8V 2 1
2
G

2.2K_0402_5% FDV301N_NL_SOT23-3
2

R36 CPU_SIC @ Q129 3 1 SMB_EC_CK1 SMB_EC_CK1 <32,33,34,37> +1.8V

S

300_0402_5%
EC is PU to 5VALW
1

LDT_STOP# FDV301N, the Vgs is:

<11,19> LDT_STOP# +1.8V CPU_TEST27_SINGLECHAIN
min = 0.65V R24 1 2 @ 300_0402_5%
1 Typ = 0.85V
C25
Max = 1.5V
HDT Connector
@ 220_0402_5% R37

@ 220_0402_5% R38

@ 220_0402_5% R39

@ 220_0402_5% R40

300_0402_5% R41
0.01U_0402_25V4Z CPU_TEST21_SCANEN R26 1 2 300_0402_5%
@ +3VS CPU_TEST20_SCANCLK2 R27 2 1 @ 300_0402_5%
1

1
2 CPU_TEST24_SCANCLK1 R28 2 1 300_0402_5%
CPU_TEST22_SCANSHIFTEN R29 2 1 @ 300_0402_5%
JP3 CPU_TEST12_SCANSHIFTENB R31 2 1 @ 300_0402_5%
0.1U_0402_16V4Z

1 CPU_TEST15_BP1 R32 2 1 @ 300_0402_5%

1 2 CPU_TEST14_BP0
0718 AMD , need check with AMD R33 2 1 @ 300_0402_5%
2

C26 3 4 CPU_TEST19_PLLTEST0 R34 @ 300_0402_5%

2 1
CPU_DBREQ# 5 6 CPU_TEST18_PLLTEST1 R35 @ 300_0402_5%
7 8 2 1
+1.8VS 2 CPU_DBRDY
U2 CPU_TCK 9 10
CPU_TMS 11 12 +3VS
1 VDD SCLK 8 SMB_EC_CK2 <33> 13 14
2

CPU_TDI
R30 THERMDA_CPU 2 CPU_TRST# 15 16
C27 7 SMB_EC_DA2 <33>
D+ SDATA 17 18

5
300_0402_5% CPU_TDO U1
THERMDC_CPU 3 19 20 LDT_RST#
6 2

P
100P_0402_25V8K D- ALERT# 21 22 HDT_RST# 4 B
1

4 CPU_LDT_REQ# 23 24 Y 4
CPU_LDT_REQ# <11,19> 4 5 1 SB_PWRGD <20,33,43>
THERM# GND 26 A

G
2200p change to NOTE: HDT TERMINATION IS REQUIRED
1 100p FOR REV. Ax SILICON ONLY. @ NC7SZ08P5X_NL_SC70-5

3
C24 ADM1032ARMZ-2REEL_MSOP8 CONN@ SAMTEC_ASP-68200-07
0.01U_0402_25V4Z 9/20 SP020016900
@ Address:100_1101
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 CTRL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 6 of 56
A B C D E
 A B C D E

01/18 Change the net name from +CPU_CORE_1 to +CPU_CORE_0

18A/720mil/36vias JCPUF
VDD(+CPU_CORE) decoupling. L +CPU_CORE_0 +CPU_CORE_0
AA4 VSS1 VSS66 J6
JCPUE AA11 J8
VSS2 VSS67
01/18 Change the net name from +CPU_CORE_1 to +CPU_CORE_0 AA13 VSS3 VSS68 J10
G4 VDD0_1 VDD1_1 P8 AA15 VSS4 VSS69 J12
H2 VDD0_2 VDD1_2 P10 AA17 VSS5 VSS70 J14
+CPU_CORE_0 +CPU_CORE_0 J9 R4 AA19 J16
VDD0_3 VDD1_3 VSS6 VSS71
J11 R7 AB2 J18
VDD0_4 VDD1_4 VSS7 VSS72
J13 VDD0_5 VDD1_5 R9 AB7 VSS8 VSS73 K2
J15 R11 AB9 K7
VDD0_6 VDD1_6 VSS9 VSS74
1 1 1 1 K6 VDD0_7 VDD1_7 T2 AB23 VSS10 VSS75 K9
K10 T6 AB25 K11
+ C30 + C28 + C31 + C29 VDD0_8 VDD1_8 VSS11 VSS76
K12 VDD0_9 VDD1_9 T8 AC11 VSS12 VSS77 K13
1 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 1
K14 VDD0_10 VDD1_10 T10 AC13 VSS13 VSS78 K15
L4 VDD0_11 VDD1_11 T12 AC15 VSS14 VSS79 K17
2 2 2 2 L7 T14 AC17 L6
VDD0_12 VDD1_12 VSS15 VSS80
L9 U7 AC19 L8
VDD0_13 VDD1_13 VSS16 VSS81
Near CPU Socket L11
L13
VDD0_14
VDD0_15
VDD1_14
VDD1_15
U9
U11
AC21
AD6
VSS17
VSS18
VSS82
VSS83
L10
L12
L15 U13 AD8 L14
VDD0_16 VDD1_16 VSS19 VSS84
Tigris platform will be 4A M2 VDD0_17 VDD1_17 U15 AD25 VSS20 VSS85 L16
M6 VDD0_18 VDD1_18 V6 AE11 VSS21 VSS86 L18
M8 V8 AE13 M7
+CPU_CORE_0 VDD0_19 VDD1_19 VSS22 VSS87
M10 VDD0_20 VDD1_20 V10 AE15 VSS23 VSS88 M9
+CPU_CORE_0
L 4A/160mil/8vias N7
VDD0_21 VDD1_21
V12 AE17
VSS24 VSS89
AC6
N9 VDD0_22 VDD1_22 V14 AE19 VSS25 VSS90 M17
+CPU_CORE_NB N11 W4 AE21 N4
VDD0_23 VDD1_23 VSS26 VSS91
1 1 1 1 Y2 AE23 N8
C32 C33 C34 C35 VDD1_24 VSS27 VSS92
1 1 1 1 K16 AC4 B4 N10
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M C36 C37 C38 C39 VDDNB_1 VDD1_25 +1.8V VSS28 VSS93
M16 VDDNB_2 VDD1_26 AD2 B6 VSS29 VSS94 N16
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M P16 B8 N18
2 2 2 2 VDDNB_3 VSS30 VSS95
T16 VDDNB_4 VDDIO27 Y25 B9 VSS31 VSS96 P2
2 2 2 2 +1.8V V16 V25 B11 P7
VDDNB_5 VDDIO26 VSS32 VSS97
V23 B13 P9
+CPU_CORE_0 VDDIO25 VSS33 VSS98
H25 V21 B15 P11
+CPU_CORE_0 VDDIO1 VDDIO24 VSS34 VSS99
J17 VDDIO2 VDDIO23 V18 B17 VSS35 VSS100 P17
K18 VDDIO3 VDDIO22 U17 B19 VSS36 VSS101 R8
L 3A/120mil/6vias K21
VDDIO4 VDDIO21
T25 B21
VSS37 VSS102
R10
1 1 1 1 1 1 K23 VDDIO5 VDDIO20 T23 B23 VSS38 VSS103 R16
C40 C41 C42 C43 C44 C45 K25 T21 B25 R18
0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J VDDIO6 VDDIO19 VSS39 VSS104
L17 T18 D6 T7
VDDIO7 VDDIO18 VSS40 VSS105
M18 VDDIO8 VDDIO17 R17 D8 VSS41 VSS106 T9
2 2 2 2 2 2 M21 P25 D9 T11
VDDIO9 VDDIO16 VSS42 VSS107
Under CPU Socket M23
M25
VDDIO10
VDDIO11
VDDIO15
VDDIO14
P23
P21
D11
D13
VSS43
VSS44
VSS108
VSS109
T13
T15
2 2
N17 VDDIO12 VDDIO13 P18 D15 VSS45 VSS110 T17
D17 U4
VSS46 VSS111
D19 U6
FOX_PZ6382A-284S-41F_GRIFFIN VSS47 VSS112
D21 VSS48 VSS113 U8
Athlon 64 S1 D23 U10
Processor Socket VSS49 VSS114
D25 U12
CONN@ VSS50 VSS115
E4 VSS51 VSS116 U14
F2 U16
VSS52 VSS117
F11 VSS53 VSS118 U18
F13 V2
VSS54 VSS119
F15 V7
+CPU_CORE_NB decoupling. F17
F19
VSS55
VSS56
VSS57
VSS120
VSS121
VSS122
V9
V11
F21 V13
VDDIO decoupling. +CPU_CORE_NB
F23
F25
VSS58
VSS59
VSS60
VSS123
VSS124
VSS125
V15
V17
H7 W6
VSS61 VSS126
H9 Y21
VSS62 VSS127
1 1 1 @ H21
VSS63 VSS128
Y23
+1.8V C52 C53 C54 H23 N6
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M VSS64 VSS129
J4
VSS65
2 2 2 FOX_PZ6382A-284S-41F_GRIFFIN
1 1 1 1 1 1 Athlon 64 S1
C46 C47 C48 C49 C50 C51 Processor Socket
22U_0805_6.3V6M 22U_0805_6.3V6M CONN@
0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2

+0.9V
3 Under CPU Socket Near Power Supply 3

VTT decoupling. 1
C: Change to NBO CAP
+ C59
220U_Y_4VM
2
Between CPU Socket and DIMM
+1.8V

+0.9V
1 1 1 1
C55 C56 C57 C58
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z
2 2 2 2 1 1 1 1 1 1 1 1
C66 C67 C68 C69 C70 C71 C72 C73
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J

180PF Qt'y follow the distance between 2 2 2 2 2 2 2 2

+1.8V +1.8V CPU socket and DIMM0. <2.5inch>

1 1 1 1 1 1
Near CPU Socket Right side.
C60 C61 C62 C63 C64 C65 +0.9V
0.01U_0402_25V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2
A: Add C165 and C176 1 1 1 1 1 1 1 1
to follow AMD Layout C79 C80 C81 C82 C83 C84 C85 C86
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
+1.8V review recommand for
EMI 2 2 2 2 2 2 2 2
4 4

1
C: Change to NBO CAP
1 1 1 1
+ C78 Near CPU Socket Left side.
C74 C75 C76 C77 220U_Y_4VM
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z
2 2 2 2 2 @

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 PWR & GND
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 7 of 56
A B C D E
 A B C D E

+V_DDR_MCH_REF

+1.8V JP4 +1.8V +0.9V +1.8V

1 2 RP1
VREF VSS DDR_A_D4 D DR_A_D[0..63] DDR_A_MA14
3 VSS DQ4 4 DDR_A_D[0..63] <5> 8 1 1 2
DDR_A_D0 5 6 DDR_A_D5 DDR_A_MA11 7 2 C87 0.1U_0402_16V4Z
DDR_A_D1 DQ0 DQ5 DDR_A_DM[0..7] DDR_A_MA7
7 DQ1 VSS 8 DDR_A_DM[0..7] <5> 6 3 1 2
9 10 DDR_A_DM0 DDR_A_MA6 5 4 C88 0.1U_0402_16V4Z
DDR_A_DQS#0 VSS DM0 D DR_A_DQS[0..7]
11 DQS0# VSS 12
1 DDR_A_DQS0 DDR_A_D6 DDR_A_DQS[0..7] <5> 47_0804_8P4R_5% 1
13 DQS0 DQ6 14
15 16 DDR_A_D7 DDR_A_MA[0..15] RP2
VSS DQ7 DDR_A_MA[0..15] <5>
DDR_A_D2 17 18 DDR_CKE0_DIMMA 8 1 1 2
DDR_A_D3 DQ2 VSS DDR_A_D12 DDR_A_DQS#[0..7] DDR_A_BS#2 C90 0.1U_0402_16V4Z
19 20 7 2
DQ3 DQ12 DDR_A_D13 DDR_A_DQS#[0..7] <5> DDR_CKE1_DIMMA
21 22 6 3 1 2
DDR_A_D8 VSS DQ13 DDR_A_MA15 C89 0.1U_0402_16V4Z
23 DQ8 VSS 24 5 4
DDR_A_D9 25 26 DDR_A_DM1
DQ9 DM1 47_0804_8P4R_5%
27 VSS VSS 28
DDR_A_DQS#1 29 30 RP3
DQS1# CK0 DDR_A_CLK0 <5>
DDR_A_DQS1 31 32 DDR_A_MA4 8 1 1 2
DQS1 CK0# DDR_A_CLK#0 <5> DDR_A_MA2
33 34 7 2 C91 0.1U_0402_16V4Z
DDR_A_D10 VSS VSS DDR_A_D14 DDR_A_BS#1
35 36 6 3 1 2
DDR_A_D11 DQ10 DQ14 DDR_A_D15 +1.8V DDR_A_MA0 C92 0.1U_0402_16V4Z
37 DQ11 DQ15 38 5 4
39 40
VSS VSS 47_0804_8P4R_5%

2
RP4
41 42 R43 DDR_A_MA5 8 1 1 2
DDR_A_D16 VSS VSS DDR_A_D20 1K_0402_1% DDR_A_MA8 C93 0.1U_0402_16V4Z
43 44 7 2
DDR_A_D17 DQ16 DQ20 DDR_A_D21 DDR_A_MA9
45 DQ17 DQ21 46 6 3 1 2
47 48 DDR_A_MA12 5 4 C94 0.1U_0402_16V4Z

1
DDR_A_DQS#2 VSS VSS +V_DDR_MCH_REF
49 50 +V_DDR_MCH_REF <9>
DDR_A_DQS2 DQS2# NC DDR_A_DM2 47_0804_8P4R_5%
51 52
DQS2 DM2 RP5
53 VSS VSS 54 1 1

2
DDR_A_D18 55 56 DDR_A_D22 C95 C96 DDR_A_BS#0 8 1 1 2
DDR_A_D19 DQ18 DQ22 DDR_A_D23 R44 DDR_A_MA10 C98 0.1U_0402_16V4Z
57 58 7 2
DQ19 DQ23 1K_0402_1% DDR_A_MA1
59 VSS VSS 60 6 3 1 2
DDR_A_D24 61 62 DDR_A_D28 2 2 DDR_A_MA3 5 4 C97 0.1U_0402_16V4Z
DDR_A_D25 DQ24 DQ28 DDR_A_D29 1000P_0402_25V8J
63 64

1
DQ25 DQ29 47_0804_8P4R_5%
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3 0.1U_0402_16V4Z RP6
DM3 DQS3# DDR_A_DQS3 DDR_A_ODT1
69 70 8 1 1 2
NC DQS3 DDR_CS1_DIMMA# C100 0.1U_0402_16V4Z
71 72 7 2
2 DDR_A_D26 VSS VSS DDR_A_D30 DDR_A_WE# 2
73 DQ26 DQ30 74 6 3 1 2
DDR_A_D27 75 76 DDR_A_D31 DDR_A_CAS# 5 4 C99 0.1U_0402_16V4Z
DQ27 DQ31
77 78
DDR_CKE0_DIMMA VSS VSS DDR_CKE1_DIMMA 47_0804_8P4R_5%
<5> DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA <5>
81 82 RP7
VDD VDD DDR_A_MA15 DDR_CS0_DIMMA#
83 84 8 1 1 2
DDR_A_BS#2 NC NC/A15 DDR_A_MA14 DDR_A_RAS# C102 0.1U_0402_16V4Z
<5> DDR_A_BS#2 85 BA2 NC/A14 86 7 2
87 88 DDR_A_MA13 6 3 1 2
DDR_A_MA12 VDD VDD DDR_A_MA11 DDR_A_ODT0 C101 0.1U_0402_16V4Z
89 A12 A11 90 5 4
DDR_A_MA9 91 92 DDR_A_MA7
DDR_A_MA8 A9 A7 DDR_A_MA6 47_0804_8P4R_5%
93 A8 A6 94
95
VDD VDD
96 Cross between +1.8V and +0.9V power plan
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 100
DDR_A_MA1 A3 A2 DDR_A_MA0
101 102
A1 A0
103 104
DDR_A_MA10 VDD VDD DDR_A_BS#1
105 106 DDR_A_BS#1 <5>
DDR_A_BS#0 A10/AP BA1 DDR_A_RAS#
<5> DDR_A_BS#0 107 108 DDR_A_RAS# <5>
DDR_A_WE# BA0 RAS# DDR_CS0_DIMMA#
<5> DDR_A_WE# 109 110 DDR_CS0_DIMMA# <5>
WE# S0#
111 VDD VDD 112
DDR_A_CAS# 113 114 DDR_A_ODT0
<5> DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 <5>
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<5> DDR_CS1_DIMMA# NC/S1# NC/A13
117 118
DDR_A_ODT1 VDD VDD
<5> DDR_A_ODT1 119 120
NC/ODT1 NC
121 122
DDR_A_D32 VSS VSS DDR_A_D36
123 124
DDR_A_D33 DQ32 DQ36 DDR_A_D37
125 DQ33 DQ37 126
127 128
DDR_A_DQS#4 VSS VSS DDR_A_DM4
129 130
DDR_A_DQS4 DQS4# DM4
131 132
DQS4 VSS DDR_A_D38
133 134
DDR_A_D34 VSS DQ38 DDR_A_D39
135 136
3 DDR_A_D35 DQ34 DQ39 3
137 DQ35 VSS 138
139 140 DDR_A_D44
DDR_A_D40 VSS DQ44 DDR_A_D45
141 142
DDR_A_D41 DQ40 DQ45
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 148
DM5 DQS5
149 150
DDR_A_D42 VSS VSS DDR_A_D46
151 152
DDR_A_D43 DQ42 DQ46 DDR_A_D47
153 154
DQ43 DQ47
155 VSS VSS 156
DDR_A_D48 157 158 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
159 160
DQ49 DQ53
161 VSS VSS 162
163 164 DDR_A_CLK1 <5>
NC,TEST CK1
165 VSS CK1# 166 DDR_A_CLK#1 <5>
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 170
DQS6 DM6
171 172
DDR_A_D50 VSS VSS DDR_A_D54
173 174
DDR_A_D51 DQ50 DQ54 DDR_A_D55
175 176
DQ51 DQ55
177 178
DDR_A_D56 VSS VSS DDR_A_D60
179 DQ56 DQ60 180
DDR_A_D57 181 182 DDR_A_D61
DQ57 DQ61
183 VSS VSS 184
DDR_A_DM7 185 186 DDR_A_DQS#7
DM7 DQS7# DDR_A_DQS7
187 188
DDR_A_D58 VSS DQS7
189 DQ58 VSS 190
DDR_A_D59 191 192 DDR_A_D62
DQ59 DQ62 DDR_A_D63
193 194
VSS DQ63
<9,15,20,30> SMB_CK_DAT0 195 196
SDA VSS
<9,15,20,30> SMB_CK_CLK0 197 198
SCL SA0
+3VS 199 VDDSPD SA1 200
4 4
1
C103 FOX_AS0A426-N8RN-7F
0.1U_0402_16V4Z CONN@
2 9/20 SP07000BZ00/SP07000EU00
DDR2 SOCKET H9.2 (REV)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII SO-DIMM 0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 8 of 56
A B C D E
 A B C D E

+1.8V +1.8V +0.9V +1.8V

JP5 RP8
1 2 D DR_B_D[0..63] DDR_B_MA6 8 1 2 1
<8> +V_DDR_MCH_REF VREF VSS DDR_B_D4 DDR_B_D[0..63] <5> DDR_B_MA2
3 4 7 2 C105 0.1U_0402_16V4Z
DDR_B_D0 VSS DQ4 DDR_B_D5 DDR_B_DM[0..7] DDR_B_MA0
5 6 DDR_B_DM[0..7] <5> 6 3 1 2
DDR_B_D1 DQ0 DQ5 DDR_CS0_DIMMB# C106 0.1U_0402_16V4Z
7 DQ1 VSS 8 5 4
1 9 10 DDR_B_DM0 D DR_B_DQS[0..7]
C104 DDR_B_DQS#0 VSS DM0 DDR_B_DQS[0..7] <5> 47_0804_8P4R_5%
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6 DDR_B_MA[0..15]
DQS0 DQ6 DDR_B_MA[0..15] <5>
15 16 DDR_B_D7 RP9
1 2 DDR_B_D2 VSS DQ7 DDR_B_DQS#[0..7] DDR_B_MA14 1
17 DQ2 VSS 18 DDR_B_DQS#[0..7] <5> 8 1 2 1
1000P_0402_25V8J DDR_B_D3 19 20 DDR_B_D12 DDR_B_MA11 7 2 C108 0.1U_0402_16V4Z
DQ3 DQ12 DDR_B_D9 DDR_B_MA7
21 VSS DQ13 22 6 3 1 2
DDR_B_D8 23 24 DDR_B_MA4 5 4 C107 0.1U_0402_16V4Z
DDR_B_D13 DQ8 VSS DDR_B_DM1
25 26
DQ9 DM1 47_0804_8P4R_5%
27 VSS VSS 28
DDR_B_DQS#1 29 30
DDR_B_DQS1 DQS1# CK0 DDR_B_CLK0 <5>
31 32 RP10
DQS1 CK0# DDR_B_CLK#0 <5> DDR_CKE1_DIMMB
33 VSS VSS 34 8 1 2 1
DDR_B_D10 35 36 DDR_B_D14 DDR_B_MA15 7 2 C109 0.1U_0402_16V4Z
DDR_B_D11 DQ10 DQ14 DDR_B_D15 DDR_CKE0_DIMMB
37 DQ11 DQ15 38 6 3 1 2
39 40 DDR_B_BS#2 5 4 C110 0.1U_0402_16V4Z
VSS VSS
47_0804_8P4R_5%
41 42
DDR_B_D21 VSS VSS DDR_B_D20 RP11
43 44
DDR_B_D17 DQ16 DQ20 DDR_B_D16 DDR_B_MA5
45 DQ17 DQ21 46 8 1 2 1
47 48 DDR_B_MA8 7 2 C111 0.1U_0402_16V4Z
DDR_B_DQS#2 VSS VSS DDR_B_MA9
49 DQS2# NC 50 6 3 1 2
DDR_B_DQS2 51 52 DDR_B_DM2 DDR_B_MA12 5 4 C112 0.1U_0402_16V4Z
DQS2 DM2
53 54
DDR_B_D18 VSS VSS DDR_B_D22 47_0804_8P4R_5%
55 56
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 60 RP12
DDR_B_D24 VSS VSS DDR_B_D28 DDR_B_MA10
61 62 8 1 2 1
DDR_B_D25 DQ24 DQ28 DDR_B_D29 DDR_B_BS#0 C114 0.1U_0402_16V4Z
63 DQ25 DQ29 64 7 2
65 66 DDR_B_MA1 6 3 1 2
DDR_B_DM3 VSS VSS DDR_B_DQS#3 DDR_B_MA3 C113 0.1U_0402_16V4Z
67 68 5 4
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 72 47_0804_8P4R_5%
DDR_B_D26 VSS VSS DDR_B_D30
73 74
DDR_B_D27 DQ26 DQ30 DDR_B_D31 RP13
75 76
2 DQ27 DQ31 DDR_B_ODT1 2
77 VSS VSS 78 8 1 2 1
DDR_CKE0_DIMMB 79 80 DDR_CKE1_DIMMB DDR_CS1_DIMMB# 7 2 C116 0.1U_0402_16V4Z
<5> DDR_CKE0_DIMMB CKE0 NC/CKE1 DDR_CKE1_DIMMB <5> DDR_B_CAS#
81 82 6 3 1 2
VDD VDD DDR_B_MA15 DDR_B_WE# C115 0.1U_0402_16V4Z
83 NC NC/A15 84 5 4
DDR_B_BS#2 85 86 DDR_B_MA14
<5> DDR_B_BS#2 BA2 NC/A14
87 88 47_0804_8P4R_5%
DDR_B_MA12 VDD VDD DDR_B_MA11
89 A12 A11 90
DDR_B_MA9 91 92 DDR_B_MA7 RP14
DDR_B_MA8 A9 A7 DDR_B_MA6 DDR_B_RAS#
93 A8 A6 94 8 1 2 1
95 96 DDR_B_BS#1 7 2 C118 0.1U_0402_16V4Z
DDR_B_MA5 VDD VDD DDR_B_MA4 DDR_B_ODT0
97 A5 A4 98 6 3 1 2
DDR_B_MA3 99 100 DDR_B_MA2 DDR_B_MA13 5 4 C117 0.1U_0402_16V4Z
DDR_B_MA1 A3 A2 DDR_B_MA0
101 A1 A0 102
103 104 47_0804_8P4R_5%
DDR_B_MA10 VDD VDD DDR_B_BS#1
105
A10/AP BA1
106 DDR_B_BS#1 <5> Cross between +1.8V and +0.9V power plan
DDR_B_BS#0 107 108 DDR_B_RAS#
<5> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <5>
DDR_B_WE# 109 110 DDR_CS0_DIMMB#
<5> DDR_B_WE# WE# S0# DDR_CS0_DIMMB# <5>
111 112
DDR_B_CAS# VDD VDD DDR_B_ODT0
<5> DDR_B_CAS# 113 114 DDR_B_ODT0 <5>
DDR_CS1_DIMMB# CAS# ODT0 DDR_B_MA13
<5> DDR_CS1_DIMMB# 115 NC/S1# NC/A13 116
117 118
DDR_B_ODT1 VDD VDD
<5> DDR_B_ODT1 119 120
NC/ODT1 NC
121 122
DDR_B_D32 VSS VSS DDR_B_D36
123 124
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 126
DQ33 DQ37
127 128
DDR_B_DQS#4 VSS VSS DDR_B_DM4
129 DQS4# DM4 130
DDR_B_DQS4 131 132
DQS4 VSS DDR_B_D38
133 134
DDR_B_D34 VSS DQ38 DDR_B_D39
135 136
DDR_B_D35 DQ34 DQ39
137 138
DQ35 VSS DDR_B_D44
139 140
3 DDR_B_D40 VSS DQ44 DDR_B_D45 3
141 DQ40 DQ45 142
DDR_B_D41 143 144
DQ41 VSS DDR_B_DQS#5
145 146
DDR_B_DM5 VSS DQS5# DDR_B_DQS5
147 DM5 DQS5 148
149 150
DDR_B_D42 VSS VSS DDR_B_D46
151 152
DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 154
DQ43 DQ47
155 156
DDR_B_D48 VSS VSS DDR_B_D52
157 158
DDR_B_D49 DQ48 DQ52 DDR_B_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 DDR_B_CLK1 <5>
NC,TEST CK1
165 VSS CK1# 166 DDR_B_CLK#1 <5>
DDR_B_DQS#6 167 168
DDR_B_DQS6 DQS6# VSS DDR_B_DM6
169 DQS6 DM6 170
171 172
DDR_B_D50 VSS VSS DDR_B_D54
173 174
DDR_B_D51 DQ50 DQ54 DDR_B_D55
175 176
DQ51 DQ55
177 178
DDR_B_D56 VSS VSS DDR_B_D60
179 180
DDR_B_D57 DQ56 DQ60 DDR_B_D61
181 182
DQ57 DQ61
183 VSS VSS 184
DDR_B_DM7 185 186 DDR_B_DQS#7
DM7 DQS7# DDR_B_DQS7
187 VSS DQS7 188
DDR_B_D58 189 190
DDR_B_D59 DQ58 VSS DDR_B_D62
191 192
DQ59 DQ62 DDR_B_D63
193 VSS DQ63 194
<8,15,20,30> SMB_CK_DAT0 195 196
SDA VSS
<8,15,20,30> SMB_CK_CLK0 197 198 +3VS
SCL SAO
199 200
+3VS VDDSPD SA1
1 201 202
GND GND
4 C119 TYCO_292527-4 4
0.1U_0402_16V4Z CONN@
2
9/20 SP07000ET00/SP07000GN00

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII SO-DIMM 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 9 of 56
A B C D E
 A B C D E

U3B
D4 GFX_RX0P GFX_TX0P A5 TMDS_B_DATA2 <18>
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5 TMDS_B_DATA2# <18>
A3 GFX_RX1P GFX_TX1P A4 TMDS_B_DATA1 <18>
B3 GFX_RX1N GFX_TX1N B4 TMDS_B_DATA1# <18>
C2 C3 TMDS_B_DATA0 <18>
GFX_RX2P GFX_TX2P
C1 GFX_RX2N GFX_TX2N B2 TMDS_B_DATA0# <18>
E5 D1 TMDS_B_CLK <18>
GFX_RX3P GFX_TX3P
F5 GFX_RX3N GFX_TX3N D2 TMDS_B_CLK# <18>
G5 E2
GFX_RX4P GFX_TX4P
G6 GFX_RX4N GFX_TX4N E1
1 1
H5 GFX_RX5P GFX_TX5P F4
H6 GFX_RX5N GFX_TX5N F3
J6 GFX_RX6P GFX_TX6P F1
J5 F2
GFX_RX6N GFX_TX6N
J7 H4
GFX_RX7P GFX_TX7P
J8 GFX_RX7N GFX_TX7N H3
L5 H1
GFX_RX8P GFX_TX8P
L6 GFX_RX8N GFX_TX8N H2
M8 GFX_RX9P GFX_TX9P J2
L8 J1
GFX_RX9N GFX_TX9N
P7 K4

PCIE I/F GFX

GFX_RX10P GFX_TX10P
M7 K3
GFX_RX10N GFX_TX10N
P5 GFX_RX11P GFX_TX11P K1
M5 K2
GFX_RX11N GFX_TX11N
R8 M4
GFX_RX12P GFX_TX12P
P8 M3
GFX_RX12N GFX_TX12N
R6 GFX_RX13P GFX_TX13P M1
R5 M2
GFX_RX13N GFX_TX13N
P4 GFX_RX14P GFX_TX14P N2
P3 N1
GFX_RX14N GFX_TX14N
T4 P1
GFX_RX15P GFX_TX15P
T3 P2
GFX_RX15N GFX_TX15N
AE3 AC1 PCIE_ITX_PRX_P0 C152 1 2 0.1U_0402_16V7K New Card
<26> PCIE_PTX_C_IRX_P0 GPP_RX0P GPP_TX0P PCIE_ITX_PRX_N0 PCIE_ITX_C_PRX_P0 <26>
AD4 AC2 C153 1 2 0.1U_0402_16V7K
<26> PCIE_PTX_C_IRX_N0 GPP_RX0N GPP_TX0N PCIE_ITX_C_PRX_N0 <26>
AE2 AB4 PCIE_ITX_PRX_P1 C154 1 2 0.1U_0402_16V7K CardReader
<27> PCIE_PTX_C_IRX_P1 GPP_RX1P GPP_TX1P PCIE_ITX_PRX_N1 PCIE_ITX_C_PRX_P1 <27>
AD3 AB3 C155 1 2 0.1U_0402_16V7K
<27> PCIE_PTX_C_IRX_N1 GPP_RX1N GPP_TX1N PCIE_ITX_PRX_P2 PCIE_ITX_C_PRX_N1 <27>
AD1 AA2 C156 1 2 0.1U_0402_16V7K
<26> PCIE_PTX_C_IRX_P2 GPP_RX2P GPP_TX2P PCIE_ITX_C_PRX_P2 <26>
AD2 PCIE I/F GPP GPP_TX2N AA1 PCIE_ITX_PRX_N2 C157 1 2 0.1U_0402_16V7K WLAN
<26> PCIE_PTX_C_IRX_N2 GPP_RX2N PCIE_ITX_C_PRX_N2 <26>
V5 Y1 PCIE_ITX_PRX_P3 C158 1 2 0.1U_0402_16V7K
<25> PCIE_PTX_C_IRX_P3 GPP_RX3P GPP_TX3P PCIE_ITX_PRX_N3 PCIE_ITX_C_PRX_P3 <25>
<25> PCIE_PTX_C_IRX_N3 W6
GPP_RX3N GPP_TX3N
Y2 C159 1 2 0.1U_0402_16V7K PCIE_ITX_C_PRX_N3 <25> LAN10/100
U5 Y4
2 GPP_RX4P GPP_TX4P H_CADOP[0..15] H_CADIP[0..15] 2
U6 GPP_RX4N GPP_TX4N Y3 <4> H_CADOP[0..15] H_CADIP[0..15] <4>
U8 V1 PCIE_ITX_PRX_P5 C160 1 2 0.1U_0402_16V7K
<26> PCIE_PTX_C_IRX_P5 GPP_RX5P GPP_TX5P PCIE_ITX_PRX_N5 PCIE_ITX_C_PRX_P5 <26> H_CADON[0..15] H_CADIN[0..15]
<26> PCIE_PTX_C_IRX_N5 U7
GPP_RX5N GPP_TX5N
V2 C161 1 2 0.1U_0402_16V7K PCIE_ITX_C_PRX_N5 <26> TV Tuner<4> H_CADON[0..15] H_CADIN[0..15] <4>
<19> SB_RX0P AA8 AD7 SB_TX0P_C C162 1 2 0.1U_0402_16V7K
SB_RX0P SB_TX0P SB_TX0N_C SB_TX0P <19>
<19> SB_RX0N Y8 AE7 C163 1 2 0.1U_0402_16V7K
SB_RX0N SB_TX0N SB_TX0N <19>
<19> SB_RX1P AA7 AE6 SB_TX1P_C C164 1 2 0.1U_0402_16V7K
SB_RX1P SB_TX1P SB_TX1P <19>
<19> SB_RX1N Y7 AD6 SB_TX1N_C C165 1 2 0.1U_0402_16V7K U3A
SB_RX1N SB_TX1N SB_TX2P_C SB_TX1N <19> H_CADOP0 H_CADIP0
<19> SB_RX2P AA5 PCIE I/F SB AB6 C166 1 2 0.1U_0402_16V7K Y25 D24
SB_RX2P SB_TX2P SB_TX2N_C SB_TX2P <19> H_CADON0 HT_RXCAD0P HT_TXCAD0P H _CADIN0
<19> SB_RX2N AA6 AC6 C168 1 2 0.1U_0402_16V7K Y24 PART 1 OF 6 D25
SB_RX2N SB_TX2N SB_TX3P_C SB_TX2N <19> H_CADOP1 HT_RXCAD0N HT_TXCAD0N H_CADIP1
<19> SB_RX3P W5 AD5 C169 1 2 0.1U_0402_16V7K V22 E24
SB_RX3P SB_TX3P SB_TX3P <19> HT_RXCAD1P HT_TXCAD1P
<19> SB_RX3N Y5 AE5 SB_TX3N_C C167 1 2 0.1U_0402_16V7K H_CADON1 V23 E25 H _CADIN1
SB_RX3N SB_TX3N SB_TX3N <19> HT_RXCAD1N HT_TXCAD1N
H_CADOP2 V25 F24 H_CADIP2
R55 1.27K_0402_1% H_CADON2 HT_RXCAD2P HT_TXCAD2P H _CADIN2
AC8 1 2 V24 F25
PCE_CALRP(PCE_BCALRP) R56 2K_0402_1% H_CADOP3 HT_RXCAD2N HT_TXCAD2N H_CADIP3
AB8 1 2 +1.1VS U24 F23
PCE_CALRN(PCE_BCALRN) H_CADON3 HT_RXCAD3P HT_TXCAD3P H _CADIN3
U25 F22
H_CADOP4 HT_RXCAD3N HT_TXCAD3N H_CADIP4
RS880M_FCBGA528 H_CADON4
T25
HT_RXCAD4P HT_TXCAD4P
H23
H _CADIN4
T24 H22
H_CADOP5 HT_RXCAD4N HT_TXCAD4N H_CADIP5
RS780M Display Port Support (muxed on GFX) P22
HT_RXCAD5P HT_TXCAD5P
J25
H_CADON5 P23 J24 H _CADIN5

HYPER TRANSPORT CPU I/F

H_CADOP6 HT_RXCAD5N HT_TXCAD5N H_CADIP6
P25 K24
GFX_TX0,TX1,TX2 and TX3 H_CADON6 HT_RXCAD6P HT_TXCAD6P H _CADIN6
P24 K25
DP0 H_CADOP7 HT_RXCAD6N HT_TXCAD6N H_CADIP7
N24 K23
AUX0 and HPD0 H_CADON7 HT_RXCAD7P HT_TXCAD7P H _CADIN7
N25 K22
HT_RXCAD7N HT_TXCAD7N
H_CADOP8 AC24 F21 H_CADIP8
GFX_TX4,TX5,TX6 and TX7 H_CADON8 HT_RXCAD8P HT_TXCAD8P H _CADIN8
AC25 HT_RXCAD8N HT_TXCAD8N G21
DP1 H_CADOP9 AB25 G20 H_CADIP9
AUX1 and HPD1 H_CADON9 HT_RXCAD9P HT_TXCAD9P H _CADIN9
AB24 H21
H_CADOP10 HT_RXCAD9N HT_TXCAD9N H_CADIP10
AA24 J20
H_CADON10 HT_RXCAD10P HT_TXCAD10P H_CADIN10
AA25 J21
H_CADOP11 HT_RXCAD10N HT_TXCAD10N H_CADIP11
9/20 SA00001ZG00(A11) S IC 216-0674001-00/RS780M FCBGA528P 0FH Y22 J18
3 H_CADON11 HT_RXCAD11P HT_TXCAD11P H_CADIN11 3
Y23 HT_RXCAD11N HT_TXCAD11N K17
H_CADOP12 W21 L19 H_CADIP12
H_CADON12 HT_RXCAD12P HT_TXCAD12P H_CADIN12
W20 J19
H_CADOP13 HT_RXCAD12N HT_TXCAD12N H_CADIP13
V21 HT_RXCAD13P HT_TXCAD13P M19
H_CADON13 V20 L18 H_CADIN13
H_CADOP14 HT_RXCAD13N HT_TXCAD13N H_CADIP14
U20 M21
H_CADON14 HT_RXCAD14P HT_TXCAD14P H_CADIN14
U21 P21
H_CADOP15 HT_RXCAD14N HT_TXCAD14N H_CADIP15
U19 P18
H_CADON15 HT_RXCAD15P HT_TXCAD15P H_CADIN15
U18 M18
HT_RXCAD15N HT_TXCAD15N

<4> H_CLKOP0 T22 HT_RXCLK0P HT_TXCLK0P H24 H_CLKIP0 <4>

<4> H_CLKON0 T23 H25 H_CLKIN0 <4>
HT_RXCLK0N HT_TXCLK0N
<4> H_CLKOP1 AB23 HT_RXCLK1P HT_TXCLK1P L21 H_CLKIP1 <4>
<4> H_CLKON1 AA22 L20 H_CLKIN1 <4>
HT_RXCLK1N HT_TXCLK1N
H_CTLOP0 M22 M24 H_CTLIP0
<4> H_CTLOP0 HT_RXCTL0P HT_TXCTL0P H_CTLIP0 <4>
H_CTLON0 M23 M25 H_CTLIN0
<4> H_CTLON0 H_CTLOP1 HT_RXCTL0N HT_TXCTL0N H_CTLIP1 H_CTLIN0 <4>
<4> H_CTLOP1 R21 P19 H_CTLIP1 <4>
H_CTLON1 HT_RXCTL1P HT_TXCTL1P H_CTLIN1
<4> H_CTLON1 R20 R18 H_CTLIN1 <4>
HT_RXCTL1N HT_TXCTL1N
1 R57 2 301_0402_1% C23 B24 1 R58 2 301_0402_1%
HT_RXCALP HT_TXCALP
A24 HT_RXCALN HT_TXCALN B25

0718 Place within 1" RS880M_FCBGA528 0718 Place within 1"

layout 1:2 layout 1:2

NEED CHECK R68 & R69 WITH AMD

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS880-HT/PCIE
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 10 of 56
A B C D E
 A B C D E

1 1

+3VS
L2 AVDD=100mA
1 2 +AVDD1
+1.8VS BLM18PG121SN1D_0603 1
L4
+AVDD2 C170
+1.8VS 0_0603_5% 2.2U_0603_6.3V4Z
R67 1 2
L6
1 2 NB_LDTSTOP# 1 2 +AVDDQ C172
<6,19> LDT_STOP#
BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z U3C
0_0402_5% 2
1 F12 AVDD1(NC) A22 LVDS_A0+ <17>
TXOUT_L0P(NC)
E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC)
B22 LVDS_A0- <17>
C175 F14 AVDDDI(NC) A21 LVDS_A1+ <17>
2.2U_0603_6.3V4Z TXOUT_L1P(NC)
R68 G15 B21 LVDS_A1- <17>
2 AVSSDI(NC) TXOUT_L1N(NC)
H15 AVDDQ(NC) TXOUT_L2P(NC) B20 LVDS_A2+ <17>
1 2 NB_ALLOW_LDTSTOP H14 AVSSQ(NC) A20 LVDS_A2- <17>
<6,19> CPU_LDT_REQ# TXOUT_L2N(DBG_GPIO0)
A19
0_0402_5% T46 PAD TV_CRMA TXOUT_L3P(NC)
E17 B19
T47 PAD TV_LUMA C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2)
F17 Y(DFT_GPIO2)

CRT/TVOUT
T48 PAD TV_COMPS F15 COMP_Pb(DFT_GPIO4) B18
R ED TXOUT_U0P(NC)
@
1
R62
2
150_0402_1% R ED TXOUT_U0N(NC)
A18 PA_RS780A4
<16> RED G18 RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3) A17
1 2 GREEN G17 REDb(NC)
TXOUT_U1N(PCIE_RESET_GPIO2)
B17 placement close to NB ball
@ R63 150_0402_1% GREEN E18 GREEN(DFT_GPIO1) D20
<16> GREEN TXOUT_U2P(NC)
1 2 BLUE F18 GREENb(NC) D21
@ R64 150_0402_1% BLUE TXOUT_U2N(NC)
<16> BLUE E19 BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) D18
F19 BLUEb(NC) D19
TXOUT_U3N(NC)
2 +1.1VS L9 CR T_HSYNC A11 B16 2
<14,16> CRT_HSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1) LVDS_ACLK+ <17>
1 2 CRT_VSYNC B11 A16 LVDS_ACLK- <17>
<14,16> CRT_VSYNC DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3)
BLM18PG121SN1D_0603 1 F8 D16
+1.8VS <16> UMA_CRT_CLK DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4)
L7 C178 E8 D17
<16> UMA_CRT_DAT DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1)
1 2
BLM18PG121SN1D_0603 1 2.2U_0603_6.3V4Z R65 1 2 715_0402_1% G14 L3
+1.8VS L10 C176 2 DAC_RSET(PWM_GPIO1) +VDDLTP18
VDDLTP18(NC) A13 1 2 +1.8VS
1 2 +NB_PLLVDD A12 B13 1 1 BLM18PG121SN1D_0603
BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z +NB_HTPVDD PLLVDD(NC) VSSLTP18(NC)
1 D14 PLLVDD18(NC)
+1.8VS L11 C179 2 B12 A15 +VDDLT18 C171 C1120

LVTM
PLLVSS(NC) VDDLT18_1(NC) 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z
1 2 B15

PLL PWR
BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z +VDDA18HTPLL VDDLT18_2(NC) 2 L5 2
1 H17 A14
2 VDDA18HTPLL VDDLT33_1(NC)
VDDLT33_2(NC) B14 1 2 +1.8VS
C180 +VDDA18PCIEPLL D7 1 1 BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z VDDA18PCIEPLL1
E7 C14
2 R66 0_0402_5% VDDA18PCIEPLL2 VSSLT1(VSS) C173 C174
D15
NB_RESET# VSSLT2(VSS) 0.1U_0402_16V4Z 4.7U_0805_10V4Z
<14,19,25,26,27,32,33> PLT_RST# 1 2 D8 C16
NB_PWRGD SYSRESETb VSSLT3(VSS) 2 2
<20> NB_PWRGD A10 C18
NB_LDTSTOP# POWERGOOD VSSLT4(VSS)
C10
NB_ALLOW_LDTSTOP C12 LDTSTOPb VSSLT5(VSS)
C20
L 0.08A/10mil/1vias
+1.8VS 1 2 E20

PM
R371 300_0402_5% ALLOW_LDTSTOP VSSLT6(VSS)
C22
VSSLT7(VSS)
<15> CLK_NBHT C25
HT_REFCLKP Ripely 2.0 support Veri-Bright function
<15> CLK_NBHT# C24
HT_REFCLKN
E11

CLOCKs
<15> NB_OSC_14.318M REFCLK_P/OSCIN(OSCIN)
F11 E9 R69 1 2 0_0402_5% UMA_ENVDD <17>
REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) NB_PWM
LVDS_BLON(PCE_RCALRP) F7 NB_PWM <17>
+1.1VS 1 2 1 2 T2 G12 1 2 0_0402_5% ENBKL <33>
<15> NBGFX_CLK GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2)
R71 R72 T1 R73
<15> NBGFX_CLK# GFX_REFCLKN
4.7K_0402_5% 4.7K_0402_5%
U1 1 2 @ R1085 1 2 0_0402_5% ENBKL
GPP_REFCLKP R1072 100K_0402_5%
U2
3 GPP_REFCLKN 3

<15> CLK_SBLINK_BCLK V4 GPPSB_REFCLKP(SB_REFCLKP) 1 2

V3 @ R1086 100K_0402_5%
<15> CLK_SBLINK_BCLK# GPPSB_REFCLKN(SB_REFCLKN)

<17> LCD_DDC_CLK B9
I2C_CLK
<17> LCD_DDC_DAT A9
B8
I2C_DATA MIS. TMDS_HPD(NC)
D9
D10
HPD <18>
<18> HDMIDAT_UMA DDC_DATA0/AUX0N(NC) HPD(NC)
<18> HDMICLK_UMA A8
DDC_CLK0/AUX0P(NC) SUS_STAT_R# <14> Strap pin
<14> RS780_DFT_GPIO_0 B7 D12 1 2 SUS_STAT# <20>
DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5)
Strap pin A7 DDC_DATA1/AUX1N(NC)
R77 0_0402_5%
THERMALDIODE_P AE8 NB_THERMAL_DA PAD T49
+3VS 2 1 B10 AD8 NB_THERMAL_DC PAD T50 NB temp to SB
R88 10K_0402_5% STRP_DATA THERMALDIODE_N
G11 D13 1 2
RSVD TESTMODE R80
C8 1.8K_0402_5%
<14> AUX_CAL AUX_CAL(NC)
Strap pin
RS880M_FCBGA528
R Veri-Bright Non Veri-Bright
R73 @
R1072 @
R1085 @
R1086 @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS880 VEDIO/CLK GEN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 11 of 56
A B C D E
 A B C D E

U3D
U61 PAR 4 OF 6
MEM_BA0 L2 B9 MEM_DQ12 MEM_A0 AB12 AA18 MEM_DQ0
MEM_BA1 BA0 DQ15 MEM_DQ13 MEM_A1 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1
L3 B1 AE16 AA20
BA1 DQ14 MEM_DQ9 MEM_A2 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) MEM_DQ2
DQ13 D9 V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19
MEM_A12 R2 D1 MEM_DQ14 MEM_A3 AE15 Y19 MEM_DQ3
MEM_A11 A12 DQ12 MEM_DQ15 MEM_A4 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) MEM_DQ4
P7 A11 DQ11 D3 AA12 MEM_A4(NC) MEM_DQ4(NC) V17
1 MEM_A10 MEM_DQ8 MEM_A5 MEM_DQ5 1
M2 A10/AP DQ10 D7 AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17
MEM_A9 P3 C2 MEM_DQ10 MEM_A6 AB14 AA15 MEM_DQ6
MEM_A8 A9 DQ9 MEM_DQ11 MEM_A7 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7
P8 A8 DQ8 C8 AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
MEM_A7 P2 F9 MEM_DQ5 MEM_A8 AD13 AC20 MEM_DQ8
MEM_A6 A7 DQ7 MEM_DQ2 MEM_A9 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9
N7 F1 AD15 AD19
A6 DQ6 MEM_A9(NC) MEM_DQ9/DVO_D5(NC)

SBD_MEM/DVO_I/F
MEM_A5 N3 H9 MEM_DQ6 MEM_A10 AC16 AE22 MEM_DQ10
MEM_A4 A5 DQ5 MEM_DQ1 MEM_A11 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) MEM_DQ11
N8 H1 AE13 AC18
MEM_A3 A4 DQ4 MEM_DQ0 MEM_A12 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) MEM_DQ12
N2 A3 DQ3 H3 AC14 MEM_A12(NC) MEM_DQ12(NC) AB20
MEM_A2 M7 H7 MEM_DQ4 Y14 AD22 MEM_DQ13
MEM_A1 A2 DQ2 MEM_DQ3 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) MEM_DQ14
M3 G2 AC22
MEM_A0 A1 DQ1 MEM_DQ7 MEM_BA0 MEM_DQ14/DVO_D10(NC) MEM_DQ15
M8 A0 DQ0 G8 AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
1

MEM_BA1 AE17
R91 MEM_BA2 MEM_BA1(NC) MEM_DQS_P0
+1.8V_MEM_VDDQ AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17
MEM_CLKN K8 A9 W18 MEM_DQS_N0 MEM_COMP_P and MEM_COMP_N trace
100_0402_1% MEM_CLKP CK VDDQ MEM_RAS# MEM_DQS0N/DVO_IDCKN(NC) MEM_DQS_P1
J8 C1 W12 AD20
CK VDDQ
C3 MEM_CAS# Y12
MEM_RASb(NC) MEM_DQS1P(NC)
AE21 MEM_DQS_N1 width >=10mils and 10mils spacing from
2

VDDQ MEM_CASb(NC) MEM_DQS1N(NC)

MEM_CKE K2 CKE VDDQ C7 MEM_WE# AD18 MEM_WEb(NC) other Signals in X,Y,Z directions
C9 MEM_CS# AB13 W17 MEM_DM0
VDDQ MEM_CKE MEM_CSb(NC) MEM_DM0(NC) MEM_DM1 +1.8VS
VDDQ E9 AB18 MEM_CKE(NC) MEM_DM1/DVO_D8(NC) AE19
G1 MEM_ODT V14 L12
VDDQ MEM_ODT(NC) L13
MEM_CS# L8 G3 AE23 +1.8V_IOPLLVDD 1 2
CS VDDQ MEM_CLKP IOPLLVDD18(NC) +NB_IOPLLVDD
G7 V15 AE24 1 2 +1.1VS
MEM_WE# VDDQ MEM_CLKN MEM_CKP(NC) IOPLLVDD(NC) 0_0603_5% 0_0603_5%
K3 WE VDDQ G9 W14 MEM_CKN(NC) 1 1
IOPLLVSS(NC) AD23 1
MEM_RAS# K7 A1 2 1 MEM_COMP_P AE12 C181 C183
RAS VDD R92 40.2_0402_1% MEM_COMPP(NC) +MEM_VREF1 2.2U_0603_6.3V4Z C182 2.2U_0603_6.3V4Z
VDD E1 AD12 MEM_COMPN(NC) MEM_VREF(NC) AE18
MEM_CAS# L7 J9 2 1 MEM_COMP_N 2 0.1U_0402_16V4Z 2
CAS VDD +1.8V_MEM_VDDQ 2
M9 R93 40.2_0402_1% RS880M_FCBGA528
MEM_DM0 VDD
F3 LDM VDD R1
MEM_DM1 B3 UDM +1.8V_MEM_VDDQ
+VDDL
VDDL
J1 02/15 Change L12 and L13 from bead to 0 ohm resistor.
2 MEM_ODT K9
VSSDL
J7 1
C184
02/15 Remove L96. 2
ODT
1U_0603_10V6K
MEM_DQS_P0 2
MEM_DQS_N0
F7 LDQS Layout Note: 50 mil for VSSDL
E8 LDQS VSSQ A7
B2
VSSQ
VSSQ B8
D2
MEM_DQS_P1 VSSQ
B7 UDQS VSSQ D8
MEM_DQS_N1 A8 E7
UDQS VSSQ
VSSQ F2
F8
+MEM_VREF VSSQ
J2 VREF VSSQ H2
H8
VSSQ
A2
NC
E2 A3
MEM_BA2 NC VSS
L1 E3
NC VSS
R3 J3
NC VSS
R7 N1
NC VSS
R8 NC VSS P9
Support 8M x 16bit x 8 bank side port
HY5PS561621AFP-25_FBGA84

9/20 SA000012G20 S IC D2 32M16 HY5PS121621CFP-25 FBGA 84P

3 3
Side Port disable,VREF need
connect to +1.8VS for DDR2
+1.8V_MEM_VDDQ +1.8V_MEM_VDDQ
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

2
1K_0402_1%

1K_0402_1%

1 1
+1.8V_MEM_VDDQ
+1.8VS
C195

C196
R96

R97

L15
2 2
1 2
1

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

22U_0805_6.3V6M
0_0805_5%
+MEM_VREF +MEM_VREF1
2 2 1 1 1 220 ohm @ 100MHz,2A
0.1U_0402_16V4Z

0.1U_0402_16V4Z

C608

C607

C201

C202

C203
1 1
2

1 1 2 2 2
1K_0402_1%

1K_0402_1%
C199

C200

2 2
R98

R99
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS880 Side-Port DDR2 SDRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 12 of 56
A B C D E
 A B C D E

U3F
1 1
A25 VSSAHT1 VSSAPCIE1 A2
D23 VSSAHT2 PART 6/6 VSSAPCIE2 B1
E22 VSSAHT3 VSSAPCIE3 D3
G22 D5
VSSAHT4 VSSAPCIE4
L 0.6A/50mil/4vias G24
VSSAHT5 VSSAPCIE5
E4
G25 VSSAHT6 VSSAPCIE6 G1
L16 2A H19
VSSAHT7 VSSAPCIE7
G2
2 1 +VDDHT J22 G4
+1.1VS VSSAHT8 VSSAPCIE8
0.1U_0402_16V4Z 0.1U_0402_16V4Z L17 H7
0_0805_5% VSSAHT9 VSSAPCIE9
1 C206 1 1 C2081 1 L22
VSSAHT10 VSSAPCIE10
J4
C210 0.7A/60mil/4vias L17 L24 R7
C209 L 1 2 +1.1VS L25
VSSAHT11
VSSAHT12
VSSAPCIE11
VSSAPCIE12
L1
4.7U_0805_10V4Z
2 2
C207
2 2 2
0.1U_0402_16V4Z
U3E VDDA_12=2.5A FBMA-L11-201209-221LMA30T_0805 M20 VSSAHT13 VSSAPCIE13 L2
N22 L4
0.1U_0402_16V4Z +VDDA11PCIE VSSAHT14 VSSAPCIE14
J17 A6 P20 L7
VDDHT_1 VDDPCIE_1 C211 10U_0805_10V4Z VSSAHT15 VSSAPCIE15
K16
VDDHT_2 PART 5/6 VDDPCIE_2
B6 R19
VSSAHT16 VSSAPCIE16
M6

L18 L 0.45A/40mil/3vias L16 VDDHT_3 VDDPCIE_3 C6

C212 10U_0805_10V4Z
R22 VSSAHT17 VSSAPCIE17 N4
M16 D6 R24 P6
+VDDHTRX VDDHT_4 VDDPCIE_4 VSSAHT18 VSSAPCIE18
2 1 2A P16 VDDHT_5 VDDPCIE_5 E6 R25 VSSAHT19 VSSAPCIE19 R1
0.1U_0402_16V4Z 0.1U_0402_16V4Z R16 F6 C220 1 2 1U_0402_6.3V4Z H20 R2
0_0805_5% VDDHT_6 VDDPCIE_6 VSSAHT20 VSSAPCIE20
1 1 1 C217 1 1 T16
VDDHT_7 VDDPCIE_7
G7 C219 1 2 1U_0402_6.3V4Z U22
VSSAHT21 VSSAPCIE21
R4
C214 C218 H8 C222 1 2 1U_0402_6.3V4Z V19 V7
C215 VDDPCIE_8 C221 1U_0402_6.3V4Z VSSAHT22 VSSAPCIE22
H18 J9 1 2 W22 U4

GROUND
4.7U_0805_10V4Z C216 0.1U_0402_16V4Z VDDHTRX_1 VDDPCIE_9 C224 0.1U_0402_16V4Z VSSAHT23 VSSAPCIE23
G19 VDDHTRX_2 VDDPCIE_10 K9 2 1 W24 VSSAHT24 VSSAPCIE24 V8
2 2 2 2 2 F20 M9 C223 2 1 0.1U_0402_16V4Z W25 V6
0.1U_0402_16V4Z VDDHTRX_3 VDDPCIE_11 VSSAHT25 VSSAPCIE25
E21 VDDHTRX_4 VDDPCIE_12 L9 Y21 VSSAHT26 VSSAPCIE26 W1
D22 P9 AD25 W2
VDDHTRX_5 VDDPCIE_13 VSSAHT27 VSSAPCIE27
B23 R9 W4
VDDHTRX_6 VDDPCIE_14 VSSAPCIE28
L 0.5A/50mil/4vias A23 VDDHTRX_7 VDDPCIE_15 T9 L12 VSS11 VSSAPCIE29 W7
L19 V9 M14 W8
+VDDHTTX VDDPCIE_16 VSS12 VSSAPCIE30
+1.2V_HT 2 1 2A AE25
VDDHTTX_1 VDDPCIE_17
U9 N13
VSS13 VSSAPCIE31
Y6
AD24 PJP604 P12 AA4
2 0_0805_5% VDDHTTX_2 VSS14 VSSAPCIE32 2
1 1 1 1 1 AC23 VDDHTTX_3 VDDC_1 K12 +1.1VS 1 2 +NB_VDDC P15 VSS15 VSSAPCIE33 AB5
AB22 J14 R11 AB1
C225 C226 C227 C228 C229 VDDHTTX_4 VDDC_2 PAD-OPEN 4x4m VSS16 VSSAPCIE34
AA21 U16 R14 AB7
VDDHTTX_5 VDDC_3 VSS17 VSSAPCIE35
Y20 VDDHTTX_6 VDDC_4 J11 T12 VSS18 VSSAPCIE36 AC3
2 2 2 2 2 W19 K15 U14 AC4
VDDHTTX_7 VDDC_5 VSS19 VSSAPCIE37
V18 M12
L 7A/280mil/16vias VDD_CORE=5A U11 AE1

POWER
VDDHTTX_8 VDDC_6 VSS20 VSSAPCIE38
U17 VDDHTTX_9 VDDC_7 L14 U15 VSS21 VSSAPCIE39 AE4
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z T17 L11 330U_D2E_2.5VM_R15 V12 AB2
0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDHTTX_10 VDDC_8 VSS22 VSSAPCIE40
R17 VDDHTTX_11 VDDC_9 M13 W11 VSS23
P17 M15 W15
VDDHTTX_12 VDDC_10 VSS24
L 0.25A/30mil/2vias M17 VDDHTTX_13 VDDC_11 N12 AC12 VSS25 VSS1 AE14

C247

C240

C241

C242

C243

C230

C231

C244

C232

C233

C245
L22 2A VDDC_12
N14 1 AA14
VSS26 VSS2
D11
2 1 +VDDA18PCIE J10 P11 1 1 1 1 1 1 1 1 1 1 1 C234 Y18 G8
+1.8VS VDDA18PCIE_1 VDDC_13 + VSS27 VSS3
P10 P13 AB11 E14
0_0805_5% VDDA18PCIE_2 VDDC_14 VSS28 VSS4
1 1 1 1 1 1 K10 P14 AB15 E15
VDDA18PCIE_3 VDDC_15 VSS29 VSS5

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z

10U_0805_10V4Z
M10 R12 AB17 J15
C235 C246 C236 C237 C238 C239 VDDA18PCIE_4 VDDC_16 2 2 2 2 2 2 2 2 2 2 2 2 VSS30 VSS6
L10 R15 AB19 J12
4.7U_0805_10V4Z VDDA18PCIE_5 VDDC_17 VSS31 VSS7
W9 T11 AE20 K14
2 2 2 2 2 2 VDDA18PCIE_6 VDDC_18 VSS32 VSS8
H9 T15 AB21 M11
VDDA18PCIE_7 VDDC_19 VSS33 VSS9
T10 VDDA18PCIE_8 VDDC_20 U12 K11 VSS34 VSS10 L15
R10 T14
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDA18PCIE_9 VDDC_21 RS880M_FCBGA528
Y9 J16
0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDA18PCIE_10 VDDC_22
AA9
VDDA18PCIE_11
AB9 AE10
VDDA18PCIE_12 VDD_MEM1(NC) +1.8VS
AD9 AA11
VDDA18PCIE_13 VDD_MEM2(NC)
AE9 Y11
VDDA18PCIE_14 VDD_MEM3(NC)
U10 VDDA18PCIE_15 VDD_MEM4(NC) AD10
AB10 C249 2 1 4.7U_0805_10V4Z
VDD_MEM5(NC) C248 0.1U_0402_16V4Z
+1.8VS F9 AC10 2 1
VDD18_1 VDD_MEM6(NC) C597 0.1U_0402_16V4Z
G9 2 1
VDD18_2
1 2 +1.8V_VDD_SP AE11 H11 0.15A/30mil/2vias C598 2 1 0.1U_0402_16V4Z
3
+1.8VS
R1051 0_0603_5% AD11
VDD18_MEM1(NC)
VDD18_MEM2(NC)
VDD33_1(NC)
VDD33_2(NC)
H12 L C599 2 1 0.1U_0402_16V4Z
3

1 1 RS880M_FCBGA528
C251 +3VS
1U_0402_6.3V4Z C252
1U_0402_6.3V4Z 1 2
2 2 0.1U_0402_16V4Z C250
1 2
0.1U_0402_16V4Z C253

+1.8VS L Just for RS780M A11 version boot issue

U64
1 6 +3VS
VIN VCNTL
1 2 5
C1064 GND NC
1

3 7 1
@ 10U_0805_10V4Z VREF NC C1065
2 R1015 4 VOUT NC 8
1K_0402_1% @ 1U_0603_10V6K
9 2
2

TP
@ G2992F1U_SO8
@ +VREF1.35V

+1.35VS
1

Q163 R1016
@ 2N7002_SOT23-3 2 1
1

4 D @ 3K_0402_5% C1067 4

<36> VLDT_EN# 1 2 2
2

R1017 @ 0_0402_5% G C1066 @ 10U_0805_10V4Z

S 1 2
2
3

C1068
@ 0.1U_0402_16V7K @ 0.1U_0402_16V7K
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS880 PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 13 of 56
A B C D E
 A B C D E

1 1
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
RS780 DFT_GPIO5 mux at CRT_VSYNC pull low to 3K
<11,16> CRT_VSYNC 2 1 +3VS Enables the Test Debug Bus using GPIO.
R101 1K_0402_5% 1 : Disable (RS780) Enable (RX780)
2 1 0 : Enable (RS780) Disable (RX780)
R102 @ 1K_0402_5%
PIN: RX780:NB_TV_C; RS740: RS740_DFT_GPIO5; RS780: VSYNC#

2 2

DFT_GPIO1: LOAD_EEPROM_STRAPS

<11> AUX_CAL 1 2
@ R104 150_0402_1% Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
D4 @ CH751H-40PT_SOD323-2
0 : I2C Master can load strap values from EEPROM if connected, or use
RS780 DFT_GPIO1 <11> SUS_STAT_R# 2 1 PLT_RST# <11,19,25,26,27,32,33>
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.

3 3

DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb

<11> RS780_DFT_GPIO_0 2 1
@ R105 1K_0402_5% RX780: Enables the Test Debug Bus using PCIE bus
1 : Disable ( Can still be enabled using nbcfg register access )
0 : Enable
RS780 use HSYNC to enable SIDE PORT (internal pull high)
RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS740/RS780)
<11,16> CRT_HSYNC 2 1 0 : Enable (RS740/RS780)
R107 3K_0402_5%

2 1 +3VS
R1064 3K_0402_5%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS880 STRAPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 14 of 56
A B C D E
 A B C D E

+3VS +3VS_CLK
R167
+1.2V_HT +VDDCLK_IO
1 2
R168 0_0805_5% 1 1 1 1 1 1 1 1
1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C445 C446 C447 C448 C449 C450 @ C451
0_0805_5% C444
1 1 1 1 1 1
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z
C452 C453 C454 C455 C456 C457 2 2 2 2 2 2 2 2
10U_0805_10V4Z
2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1
C458 C459 C460 C461
1 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2

EMI Caps for single end clock.

CLK_48M_USB

R170 1 2 33_0402_5% OSC_14M_NB NB_OSC_14.318M

CLK_48M_USB <20>
1
1 2 RX780 1.8V 75R/100R CLK_14M_SIO
R379 158_0402_1% NB_OSC_14.318M <11> C1074
1

+3VS_CLK
CLK_XTAL_OUT @ 1 R380 2 RS780 1.1V 200R/100R 12P_0402_50V8J
R1105 175_0402_1% 90.9_0402_1% 2
2 1
CLK_XTAL_IN R1106
CLK_14M_SB <19> 2
110_0402_5% 01/23 14.318MHz For SB710 reference C1076
Y2 CLK_NBHT <11>

+3VS_CLK
+3VS_CLK
NB_OSC_14.318M_R
C1123 2
CLK_NBHT# <11> NB
12P_0402_50V8J

CLK_48M_USB_R
2 1 1 2

CLK_XTAL_OUT
1 2 +3VS_CLK C1075
CLK_CPU_BCLK <6>

CLK_XTAL_IN
14.31818MHZ_20P_6X1430004201 R174 8.2K_0402_5% 12P_0402_50V8J

SEL_SATA
1U_0402_6.3V4Z

2
27M_SEL
1 1
2 C464 C465 CLK_CPU_BCLK_R R186 2
1 2
R946 0_0402_1% @ 261_0402_1% CPU
22P_0402_50V8J 22P_0402_50V8J CLK_CPU_BCLK#_R 1 2
2 2 R945 0_0402_1%

1
+3VS_CLK
CLK_CPU_BCLK# <6>

73

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
Routing the trace at least 10mil U10
1

VSS_48
48MHz_0
48MHz_1
VDD_48

REF_0/SEL_HTT66

REF_2/SEL_27

HTT_0/66M_0
HTT_0#/66M_1

PD#
CPU_K8_0
CPU_K8_0#
XTAL_OUT

VSS_REF

VDD_REF
VDD_HTT

VSS_HTT
REF_1/SEL_SATA
GND

XTAL_IN
C1106
0.1U_0603_25V7K
2
<8,9,20,30> SMB_CK_CLK0 1 SCL VDD_CPU 54 +3VS_CLK
<8,9,20,30> SMB_CK_DAT0 2 53 +VDDCLK_IO
SDA VDD_CPU_I/O
+3VS_CLK 3 52
VDD_DOT VSS_CPU CLKREQ_NCARD#
4 51
SRC_7#/27M CLKREQ_1# CLKREQ_MCARD2# CLKREQ_NCARD# <26>
5 50
SRC_7/27M_SS CLKREQ_2# CLKREQ_MCARD2# <26>
6 49 +3VS_CLK
VSS_DOT VDD_A
7 48
SRC_5# VSS_A
8 SRC_5 VSS_SATA 47
PA_RS7X0A1 <11> CLK_SBLINK_BCLK# 9
SRC_4# SRC_6/SATA
46 CLK_SBSRC_BCLK <19> PA_RS7X0A1
SB LINK <11> CLK_SBLINK_BCLK 10
SRC_4 SRC_6#/SATA#
45 CLK_SBSRC_BCLK# <19> SB SRC
11 44 +3VS_CLK
VSS_SRC VDD_SATA CLKREQ_MCARD1#
+VDDCLK_IO 12 43 CLKREQ_MCARD1# <26>
VDD_SRC_IO CLKREQ_3# CLKREQ4
<26> CLK_PCIE_MCARD1# 13 42
SRC_3# CLKREQ_4#
MiniCard_1 <26> CLK_PCIE_MCARD1 14
SRC_3 SB_SRC_SLOW#
41 1 2 +3VS_CLK
<26> CLK_PCIE_MCARD2# 15 40 R372 10K_0402_5% For ICS need to pull high.
SRC_2# SB_SRC_0
MiniCard_2 <26> CLK_PCIE_MCARD2 16
SRC_2 SB_SRC_0#
39 For SLG is NC
+3VS_CLK 17 38 +3VS_CLK
VDD_SRC VDD_SB_SRC
+VDDCLK_IO 18 37 +VDDCLK_IO
VDD_SRC_IO VDD_SB_SRC_IO

VSS_SB_SRC
VDD_ATIG_IO
ATIGCLK_2#

ATIGCLK_1#

ATIGCLK_0#
CLKREQ_0#

SB_SRC_1#
ATIGCLK_2

ATIGCLK_1

ATIGCLK_0

SB_SRC_1
VDD_ATIG
3 3

VSS_ATIG
VSS_SRC
SRC_1#

SRC_0#
SRC_1

SRC_0

SLG8SP626VTR_QFN72_10x10
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CLKREQ_NCARD# 1 2
+3VS_CLK +3VS_CLK
R324 8.2K_0402_5%
CLKREQ_MCARD2# 1 2
R325 8.2K_0402_5%
CLKREQ_MCARD1# 1 2
2

R326 8.2K_0402_5%
+VDDCLK_IO
+3VS_CLK

@ R179 CLKREQ_LAN# 1 2
8.2K_0402_5% R1039 8.2K_0402_5%
CLKREQ4 1 2
R1045 @ 8.2K_0402_5%
NBGFX_CLK <11>
1

+3VS_CLK
SEL_SATA NBGFX_CLK# <11> NB GFX
CLK_PCIE_MCARD0 <27>
CLK_PCIE_MCARD0# <27> Card Reader
2

CLKREQ_LAN#
CLKREQ_LAN# <25>
R181 R180
CLK_PCIE_LAN <25>
8.2K_0402_5% 8.2K_0402_5% GLAN NB CLOCK INPUT TABLE
CLK_PCIE_LAN# <25>
NB CLOCKS RX780 RS780
CLK_PCIE_NCARD <26>
1

27M_SEL New Card

CLK_PCIE_NCARD# <26>
HT_REFCLKP
100M DIFF 100M DIFF
HT_REFCLKN 100M DIFF 100M DIFF

1 configure as SATA output 1 * configure as 27M and 27M_SS output REFCLK_P

4 SEL_SATA 27M_SEL 14M SE (1.8V) 14M SE (1.1V) 4
*
0 configure as normal SRC(SRC_6) output 0 configure as SRC_7 output REFCLK_N NC v r ef
* default * default
GFX_REFCLK 100M DIFF 100M DIFF(IN/OUT)*

Use voltage divider resistor R379 & R380 to pull low

NB_OSC_14.318M
1 configure as single-ended 66MHz output Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
0* configure as differential 100MHz output
* default
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 15 of 56
A B C D E
 A B C D E

1
CRT CONNECTOR 1

+5VS +R_CRT_VCC +CRT_VCC

D36 F2
2 1 1 2

1
@ D35 @ D37 @ D34 1
RB491D_SOT23 1A_6VDC_MINISMDC110
C475
0.1U_0402_16V4Z
+3VS 2
DAN217_SC59 DAN217_SC59DAN217_SC59

3
JCRT
6
L47 RGND
11 ID0
<11> RED R ED 1 2 RED_L 1
BLM15AG121SN1D_0402 Red
7
L48 D_DDCDATA GGND
12
GREEN GREEN_L SDA
<11> GREEN 1 2 2 Green
BLM15AG121SN1D_0402 8
L49 H S YNC BGND +CRT_VCC
13
BLUE BLUE_L Hsync
<11> BLUE 1 2 3 Blue
BLM15AG121SN1D_0402 +CRT_VCC 9
+5V

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K
VSYNC 14 1
Vsync
1 1 1 4 res

1
75_0402_1%

75_0402_1%

75_0402_1%
1 1 1 10 C1107
C471 C859 C469 C858 C476 C472 D_DDCCLK SGND 0.1U_0603_25V7K
15
R214 R211 R217 SCL 2
5
2 2 2 2 GND 2
2 2 2 16

2
GND
17
GND

CONN@ SUYIN_070546FR015S263ZR
RED_L <35>

GREEN_L <35>

+3VS BLUE_L <35>

+CRT_VCC
+CRT_VCC
D_VSYNC <35>
1

1 2 D_HSYNC <35>
R237 R238 C473

5
1
4.7K_0402_5% 4.7K_0402_5% R100 R218 0.1U_0402_16V4Z

OE#
P
2

6.8K_0402_5% 6.8K_0402_5% 2 4 D_HSYNC R240 1 2 0_0603_5% H S YNC

<11,14> CRT_HSYNC
2

A Y

G
<11> UMA_CRT_DAT 1 6 D_DDCDATA U14
D_DDCDATA <35>
Q10A SN74AHCT1G125GW_SOT353-5

3
2N7002DW-7-F_SOT363-6
5

1 2
@ R1023 0_0402_5%
4 3 v0.2 ADD D_DDCCLK 1 2
<11> UMA_CRT_CLK D_DDCCLK <35>

5
1
Q10B @ C477
2N7002DW-7-F_SOT363-6 1 1 0.1U_0402_16V4Z

OE#
P
2 A 4 D_VSYNC R241 1 2 0_0603_5% VSYNC
<11,14> CRT_VSYNC Y
1 2 @ C857 @ C856

10P_0402_50V8J

10P_0402_50V8J
3 @ R1022 0_0402_5% U13 3
470P_0402_50V8J 2 2 470P_0402_50V8J SN74AHCT1G125GW_SOT353-5 1 1

3
v0.2 ADD
@ C474 @ C470
2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 16 of 56
A B C D E
 A B C D E

+5VALW +5VS +USB_CAM USB_VCCA is +3.9V, R892:100K;

R891:215KKohm
G916 Vref=1.25V when U54 install

1
U54

1
PJP4 PJP6
1 PAD-OPEN 2x2m PAD-OPEN 2x2m 1 5 R891 G916-390T1UF 1
VIN VOUT
2 @ 215K_0402_1% C718 install when U54 is
GND
2 L

2
2 3 4 C719 RT9193-39GB
C720 EN BP

1
RT9193-39GB_SOT23-5 1 10U_0805_10V4Z
10U_0805_10V4Z C718 R892 1

1
1
R1013 0.1U_0402_16V4Z @ 100K_0402_1% Close to JLVDS
2 L

2
0_0402_5%
D22

2
@ R1014 4 2 USB20_P5
+USB_CAM VIN IO1
1 2 CAM_SHDN# <21>
0_0402_5% USB20_N5 3 1
IO2 GND
@ PRTR5V0U2X_SOT143-4

+LCDVDD +5VALW

2
2 2
R225 R224 +3VS
220_0402_5% 1M_0402_5%

80mil

6 2

3
S
SI2301BDS-T1-E3_SOT23-3
G
Q45A 2
2N7002DW-7-F_SOT363-6 R222 Q43
2 1 2
100K_0402_5% D
2

1
3
C863 80mil
B+ +LCDVDD
1000P_0402_50V7K
+LCDVDD INVPWR_B+ 5 1
<11> UMA_ENVDD Q45B 1

2
1 2N7002DW-7-F_SOT363-6

4
R276 C487 C491
680P_0402_50V7K L44 C1108 2.2K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z
C479 1 2 680P_0402_50V7K 2
FBMA-L11-201209-221LMA30T_0805 2

1
1
1

C480

680P_0402_50V7K
LVDS CONN Ripely 2.0 Support Veri-Bright function
2

2 JLVDS
1 2 LVDS_A2-
1 2 LVDS_A2- <11>
LVDS_A2- C1056 1 2 @ 10P_0402_50V8J LVDS_A2+ 3 4 LVDS_A2+
3 4 LVDS_A2+ <11>
5 6 LVDS_A1- R1084 1 20_0402_5% INV_PWM
5 6 LVDS_A1- <11> <11> NB_PWM
LVDS_A1- C1057 1 2 @ 10P_0402_50V8J LVDS_A1+ 7 8 LVDS_A1+
3 7 8 LVDS_A1+ <11> 3
9 10 LVDS_A0- LVDS_A0- <11>
LVDS_A0- C1058 LVDS_A0+ 9 10 LVDS_A0+
1 2 @ 10P_0402_50V8J 11 11 12 12 LVDS_A0+ <11> <33> EC_PWM
@ R1078 1 20_0402_5%
USB20_P5 13 14 LVDS_ACLK-
<20> USB20_P5 13 14 LVDS_ACLK- <11>
LVDS_ACLK- C1059 1 2 @ 10P_0402_50V8J LVDS_ACLK+ USB20_N5 15 16 LVDS_ACLK+
<20> USB20_N5 15 16 LVDS_ACLK+ <11>
17 18
17 18
19 20
19 20
21 22
+3VS 21 22 DMIC_DAT +5VS
23 24 DMIC_DAT <28>
23 24 DMIC_CLK R491
25 26 DMIC_CLK <28>
25 26
27 27 28 28 1 2 100_0805_5%
29 30 INV_PWM
29 30
1

C481 31 32 BKOFF#
31 32 BKOFF# <33>
33 34 DAC_BRIG
33 34 DAC_BRIG <33>
35 36 +USB_CAM
2

680P_0402_50V7K 35 36 LCD_DDC_CLK +3VS

37 37 38 38 LCD_DDC_CLK <11>
39 40 LCD_DDC_DAT
39 40 LCD_DDC_DAT <11>

680P_0402_50V7K

680P_0402_50V7K
41 42 BKOFF# 1 2
GND GND @ 4.7K_0402_5% R483
1 1

680P_0402_50V7K

680P_0402_50V7K
ACES_88242-4001

C482

C483
CONN@ LCD_DDC_CLK 1 2
C866

C867
4.7K_0402_5% R274
9/20 SP02000EA00/SP02000BW00 2 2
2

2
@ @ LCD_DDC_DAT 1 2
@ @ 4.7K_0402_5% R275

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN. / WebCam
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 17 of 56
A B C D E
 A B C D E

+3VS +HDMI_5V_OUT

2
R176 R209
4.7K_0402_5% 4.7K_0402_5%
1 R210 R236 1

2
+HDMI_5V_OUT 6.8K_0402_5% 6.8K_0402_5%

1
HDMI_HPD 1 6 HDMI_SDATA
C851 <11> HDMIDAT_UMA Q134A
2
2 1 +3VS 2N7002DW-7-F_SOT363-6

2
R615 2 @ R1019

5
1

5
0.1U_0402_16V4Z 2.2K_0402_5% C850 1 2
1 R628 0_0402_5%

OE#
P
2 4 100K_0402_5% 0.1U_0402_16V4Z 4 3 v0.2 ADD HDMI_SCLK
A Y HPD <11> 1 <11> HDMICLK_UMA Q134B

1
G
U39 2N7002DW-7-F_SOT363-6
SN74AHCT1G125GW_SOT353-5

3
@ R1018
1 2
0_0402_5%
v0.2 ADD

2 2

MP:Update D10 to meet HDMI.

HDMI_CLK+ 1 2 HDMI_R_CK+
@ R112 0_0402_5% D10
+5VS 2 1 +HDMI_5V_OUT
L85
1 2 RB491D_SOT23
1 2
1
4 3 C468
4 3
C507 1 2 0.1U_0402_16V7K HDMI_CLK- WCM-2012-900T_4P 0.1U_0402_16V4Z
<10> TMDS_B_CLK# 2
C508 1 2 0.1U_0402_16V7K HDMI_CLK+ HDMI_CLK- 1 2 HDMI_R_CK-
<10> TMDS_B_CLK
@ R113 0_0402_5%

C655 1 2 0.1U_0402_16V7K HDMI_TX0-

<10> TMDS_B_DATA0# HDMI_TX0+
C675 1 2 0.1U_0402_16V7K
<10> TMDS_B_DATA0
HDMI_TX0+ 1 2 HDMI_R_D0+
@ R115 0_0402_5%
C804 1 2 0.1U_0402_16V7K HDMI_TX1-
<10> TMDS_B_DATA1# HDMI_TX1+
C827 1 2 0.1U_0402_16V7K L86
<10> TMDS_B_DATA1

HDMI_TX2-
1
1 2
2
HDMI Connector
C852 1 2 0.1U_0402_16V7K
<10> TMDS_B_DATA2# HDMI_TX2+ +HDMI_5V_OUT
C853 1 2 0.1U_0402_16V7K 4 3
<10> TMDS_B_DATA2 4 3 JHDMI
WCM-2012-900T_4P 18 +5V
HDMI_TX0- 1 2 HDMI_R_D0- HDMI_SDATA 16 SDA 13
3 HDMI_CLK- HDMI_TX0- HDMI_TX1- HDMI_TX2- @ R116 0_0402_5% HDMI_SCLK CEC 3
15 SCL Reserved 14
HDMI_CLK+ HDMI_TX0+ HDMI_TX1+ HDMI_TX2+ HDMI_HPD 19 HP_DET
2
HDMI_R_CK- GND
12 CK- GND 5
2
1

2
2

HDMI_TX1+ 1 2 HDMI_R_D1+ HDMI_R_CK+ 10 8

R315 R307 R172 @ R117 0_0402_5% HDMI_R_D0- CK+ GND
9 11
D0- GND
2
2

2
2

715_0402_1% 715_0402_1% 715_0402_1% 715_0402_1% HDMI_R_D0+ 7 20

R173 R304 R139 L87 HDMI_R_D1- D0+ GND
6 21
715_0402_1% 715_0402_1% 715_0402_1% 715_0402_1% HDMI_R_D1+ D1- GND
1 2 4 22
1
2

1
1

R297 R141 1 2 HDMI_R_D2- D1+ GND

3 D2- GND 23
+5VS HDMI_R_D2+ 1 17
1
1

1
1

D2+ DDC/CEC_GND
4 3
4 3
WCM-2012-900T_4P CONN@ SUYIN_100042MR019S153ZL
HDMI_TX1- 1 2 HDMI_R_D1-
@ R118 0_0402_5%
1

D
1/19 Use one mos to instead of two dule MOS design
2 Q173
G
S 2N7002_SOT23-3 HDMI_TX2+ 1 2 HDMI_R_D2+
3
2

@ R119 0_0402_5%

R1104 L88
100K_0402_5% 1 2
1 2
1

4 4 3 3

WCM-2012-900T_4P
HDMI_TX2- 1 2 HDMI_R_D2-
@ R120 0_0402_5%
4 4

L Change PCB Footprint from SW_WCM2012F2S_4P to KING_WCM-2012-900T_4P

03/07 Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 18 of 56
A B C D E
 A B C D E

+3VALW
C506
2 1 Check AMD need pull low or not

5
@ 0.1U_0402_16V4Z U16
2 1 2 NB_RST#_R U15A

P
B
Y 4 PLT_RST# PLT_RST# <11,14,25,26,27,32,33>
R300 @ 8.2K_0402_5%
SB700
NB_RST#_R 1 NB_RST#_R N2 P4
A A_RST# PCICLK0

G
@ NC7SZ08P5X_NL_SC70-5 Part 1 of 5 P3
C492 0.1U_0402_16V7K SB_RX0P_C PCICLK1
<10> SB_RX0P 1 2 V23 P1 PCICLK2 <23>
3
C493 0.1U_0402_16V7K SB_RX0N_C PCIE_TX0P PCICLK2 CLK_PCI_SIO_R R301 1 0_0402_5% PCI_CLK3
<10> SB_RX0N 1 2 V22 P2 2

PC I CLKS
SB_RX1P_C PCIE_TX0N PCICLK3 PCI_CLK3 <23>
C494 1 2 0.1U_0402_16V7K V24 T4
<10> SB_RX1P SB_RX1N_C PCIE_TX1P PCICLK4 PCI_CLK4 <23>
C495 1 2 0.1U_0402_16V7K V25 T3
<10> SB_RX1N SB_RX2P_C PCIE_TX1N PCICLK5/GPIO41 PCI_CLK5 <23>
2 1 C496 1 2 0.1U_0402_16V7K U25
<10> SB_RX2P PCIE_TX2P
R312 33_0402_5% C497 1 2 0.1U_0402_16V7K SB_RX2N_C U24
1 <10> SB_RX2N SB_RX3P_C PCIE_TX2N 1
C498 1 2 0.1U_0402_16V7K T23
<10> SB_RX3P SB_RX3N_C PCIE_TX3P
C499 1 2 0.1U_0402_16V7K T22 N1
<10> SB_RX3N PCIE_TX3N PCIRST#
<10> SB_TX0P U22
PCIE_RX0P

PCI EXPRESS INTERFACE

<10> SB_TX0N U21 U2
PCIE_RX0N AD0
<10> SB_TX1P U19 PCIE_RX1P AD1 P7
<10> SB_TX1N V19 V4
PCIE_RX1N AD2
<10> SB_TX2P R20 PCIE_RX2P AD3 T1
<10> SB_TX2N R21 PCIE_RX2N AD4 V3
<10> SB_TX3P R18 U1
PCIE_RX3P AD5
<10> SB_TX3N R17 PCIE_RX3N AD6 V1
V2
R305 AD7
2 1 562_0402_1% T25 PCIE_CALRP AD8 T2
+PCIE_VDDR R306 2 1 2.05K_0402_1% T24 W1
L53 PCIE_CALRN AD9
T9
+SB_PCIEVDD AD10
+1.2V_HT 1 2 P24 R6
BLM18PG121SN1D_0603 PCIE_PVDD AD11
1 1 AD12 R7
P25 R5
C504 C505 PCIE_PVSS AD13
AD14 U8
10U_0805_10V4Z 1U_0402_6.3V4Z U5
2 2 AD15
Y7
AD16
W8
AD17
AD18 V9
Close to SB AD19 Y8
AA8
AD20
AD21 Y4
Y3
AD22 PCI_AD23
Y2 PCI_AD23 <23>
AD23 PCI_AD24
AD24 AA2 PCI_AD24 <23>
AB4 PCI_AD25
AD25 PCI_AD25 <23>
N25 AA1 PCI_AD26
<15> CLK_SBSRC_BCLK PCIE_RCLKP/NB_LNK_CLKP AD26 PCI_AD26 <23>
N24 AB3 PCI_AD27
2 <15> CLK_SBSRC_BCLK# PCIE_RCLKN/NB_LNK_CLKN AD27 PCI_AD27 <23> 2
AB2 PCI_AD28
AD28 PCI_AD28 <23>
K23 AC1
NB_DISP_CLKP AD29
K22 AC2
NB_DISP_CLKN AD30 @ C1085 12P_0402_50V8J
AD31 AD1
M24 W2 CLK_PCI_SIO2 1 2
NB_HT_CLKP CBE0#
M25 U7
NB_HT_CLKN CBE1# C1086 12P_0402_50V8J
AA7

PCI INTERFACE
CBE2# CLK_PCI_SIO
P17 Y1 1 2
CPU_HT_CLKP CBE3#
M18 CPU_HT_CLKN FRAME# AA6
W5 C1087 12P_0402_50V8J
DEVSEL# CLK_PCI_EC
M23 SLT_GFX_CLKP IRDY# AA5 1 2
M22 Y5
SLT_GFX_CLKN TRDY#
PAR U6
J19 W6
GPP_CLK0P STOP#
J18 W4
GPP_CLK0N PERR#
V7 PCI_SERR# <33>
SERR#
L20 AC3
GPP_CLK1P REQ0#
L19 AD4
@ R314 20M_0402_5% GPP_CLK1N REQ1#
AB7
REQ2#
1 2 M19 GPP_CLK2P REQ3#/GPIO70 AE6
M20 AB6 PAD T15
GPP_CLK2N REQ4#/GPIO71
C643 AD2
GNT0#
01/23 14.318MHz for SB710 reference N22
GPP_CLK3P GNT1#
AE4
1 2 SB_32KHI P22 AD5
GPP_CLK3N GNT2#

CLO CK GENERATOR
AC6
GNT3#/GPIO72 LPCCLK1
18P_0402_50V8J Y3 1 2 L18 AE5 PAD T16 R308 1 2 33_0402_5% CLK_PCI_SIO CLK_PCI_SIO <32>
25M_48M_66M_OSC GNT4#/GPIO73
1

4 3 R1107 0_0402_5% AD6 PAD T17

R389 OSC NC CLKRUN#
V5
LOCK#
1 2 <15> CLK_14M_SB 2 1 J21
20M_0402_5% OSC NC @ R1108 0_0402_5% 14M_X1
AD3
32.768KHZ_12.5PF_Q13MC14610050_10PPM INTE#/GPIO33
C652 AC4
2

INTF#/GPIO34
AE2
3 SB_32KHO INTG#/GPIO35 3
1 2 2 1 J20 14M_X2 INTH#/GPIO36 AE3 PCI_PIRQH# R967 2 1 0_0402_5% ACCEL_INT <30>
@ R1109 1K_0402_5%
18P_0402_50V8J R302 33_0402_5%
LPCCLK0 G22 CLK_PCI_EC_R 1 2 CLK_PCI_EC CLK_PCI_EC <23,33>
Close to SB E22 LPCCLK1 LPCCLK1 <23>
SB_32KHI LPCCLK1
A3
X1 LAD0
H24 LPC_AD0 <32,33> STRAP PIN
LAD1
H23 LPC_AD1 <32,33> EC & Debug
J25 LPC_AD2 <32,33>
LAD2
J24 LPC_AD3 <32,33>
LAD3
+1.8VS 2 1 CPU_LDT_REQ# SB_32KHO B3 X2 LFRAME# H25 LPC_FRAME# <32,33>
RTC XTAL

L PC

R318 @ 10K_0402_5% H22 PAD T18

LDRQ0#
AB8 LPC_DRQ# <32>
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65 AD7
2 1 H_PROCHOT# V15
+3VS SERIRQ SIRQ <32,33>
R319 10K_0402_5%
CPU_LDT_REQ# F23
<6,11> CPU_LDT_REQ# ALLOW_LDTSTP
H_PROCHOT# F24 C3 RTC_CLK <23> STRAP PIN
<6> H_PROCHOT# H_PWRGD PROCHOT# RTCCLK
<43> H_PWRGD F22 C2
LDT_PG INTRUDER_ALERT# +3VL
<6,11> LDT_STOP# G25 B2 +SB_VBAT
LDT_STP# VBAT +SB_VBAT +RTCVCC_R +RTCVCC
G24
C PU

<6> LDT_RST# LDT_RST# +RTCBATT

R311 R316 R317 D42
1 2 H_PWRGD_SB 120_0402_5% 120_0402_5% 2
<6> H_PWRGD_CPU
RTC

1 2 1 2 1 R876 JBATT1
0_0402_5% 218-0660011 A14 SB7_FCBGA528 1 1 3 1 2 W=20mils 1
W=20mils 1
W=20mils 2
2

2
R1079 9/20 SA00001S510 S IC 218S7EALA11FG SB700 BGA 528P SB 0FH C509 C510 DAN202U_SC70 1K_0402_5% 3
J1 GND
1 2 4

2
<43> H_PWRGD 2 2 GND
@ JUMP_43X39
0_0402_5% 1U_0402_6.3V4Z CONN@ ACES_85205-02001

1
+RTCBATT_R
0.1U_0402_16V4Z 9/20 SP020008T00

1
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB710-PCIE/PCI/ACPI/LPC/RTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 19 of 56
A B C D E
 A B C D E

<11> NB_PWRGD
R1052 2 1 NBPWRGD
0_0402_5%
R1053 2 1
@ 100_0402_5%
For SB700 A11 divider to U15D
1.8V for RS & RX780
SB700 Part 4 of 5
E1
PCI_PME#/GEVENT4#
E2 RI#/EXTEVNT0# USBCLK/14M_25M_48M_OSC C8 CLK_48M_USB <15>
1 demo circuit LID use RI# 1
H7 SLP_S2/GPM9#
F5 G8 USB_RCOMP 1 2
+3VS <33> SLP_S3# SLP_S3# USB_RCOMP
G1 11.8K_0402_1% R323

ACPI / WAKE UP EVENTS

<33> SLP_S5# SLP_S5#
H2

USB MISC
SUS_STAT# <33> PWRBTN_OUT# PWR_BTN#
1 2 <6,33,43> SB_PWRGD H1
R388 4.7K_0402_5% SUS_STAT# PWR_GOOD
<11> SUS_STAT# K3 SUS_STAT#
SB_TEST2 H5 E6
SB_TEST1 TEST2 USB_FSD13P
H4 TEST1 USB_FSD13N E7
+3VALW SB_TEST0 H3 TEST0

U SB 1.1
SB_TEST2 <33> GATEA20 Y15
GA20IN/GEVENT0# USB_FSD12P
F7 Touch Screen (delete)
1 2 <33> KB_RST# W15 KBRST#/GEVENT1# USB_FSD12N E8
R320 @ 2.2K_0402_5% K4
SB_TEST1 <33> EC_SCI# LPC_PME#/GEVENT3# USB20_P11
1 2 <33> EC_SMI# K24 LPC_SMI#/EXTEVNT1# USB_HSD11P H11 USB20_P11 <26>
R321 @ 2.2K_0402_5% PAD T19 F1 J10 USB20_N11 USB-11 New Card
SB_TEST0 S3_STATE/GEVENT5# USB_HSD11N USB20_N11 <26>
1 2 J2
R322 @ 2.2K_0402_5% PCIE_WAKE# SYS_RESET#/GPM7# USB20_P10
H6 E11 USB20_P10 <26>
WAKE#/GEVENT8# USB_HSD10P USB20_N10
F2
H_THERMTRIP# J6 BLINK/GPM6# USB_HSD10N F11 USB20_N10 <26> USB-10 MiniCard(TV or WWAN)
+3VS <6> H_THERMTRIP# SMBALERT#/THRMTRIP#/GEVENT2#
NBPWRGD W14 A11
NB_PWRGD USB_HSD9P
SMB_CK_CLK0 EC_RSMRST# USB_HSD9N
B11 USB-9 Card Reader (delete)
R328 1 2 1.2K_0402_5% D3
<33> EC_RSMRST# RSMRST# USB20_P8
C10 USB20_P8 <26>
USB_HSD8P

2
R329 1 2 1.2K_0402_5% SMB_CK_DAT0 SB700 has internal PD D10 USB20_N8 USB-8 MiniCard(WLAN)
USB_HSD8N USB20_N8 <26>
R327
CH751H-40PT_SOD323-2 2.2K_0402_5% AE18 G11 USB20_P7
SATA_IS0#/GPIO10 USB_HSD7P USB20_P7 <31>
1 2 EC_RSMRST# AD18 H12 USB20_N7 USB-7 Fingerprint
+3VALW <39,41> 3/5V_OK CLK_REQ3#/SATA_IS1#/GPIO6 USB_HSD7N USB20_N7 <31>
D58 AA19

1
SMARTVOLT1/SATA_IS2#/GPIO4 USB20_P6
W17 E12 USB20_P6 <31>
R331 SMB_CK_CLK1 CLK_REQ0#/SATA_IS3#/GPIO0 USB_HSD6P USB20_N6
1 2 2.2K_0402_5% V17 CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 USB_HSD6N E14 USB20_N6 <31> USB-6 Bluetooth
W20 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
R332 1 2 2.2K_0402_5% SMB_CK_DAT1 W21 C12 USB20_P5
<28> SB_SPKR

U SB 2.0
SMB_CK_CLK0 SPKR/GPIO2 USB_HSD5P USB20_N5 USB20_P5 <17>
2 <8,9,15,30> SMB_CK_CLK0
SMB_CK_DAT0
AA18
SCL0/GPOC0# USB_HSD5N
D12 USB20_N5 <17> USB-5 USB Camera 2
<8,9,15,30> SMB_CK_DAT0 W18 SDA0/GPOC1#
SMB_CK_CLK1 K1 B12
<26> SMB_CK_CLK1 SMB_CK_DAT1 SCL1/GPOC2# USB_HSD4P
+3VALW <26> SMB_CK_DAT1 K2
SDA1/GPOC3# USB_HSD4N
A12 USB-4 Left side
AA20 DDC1_SCL/GPIO9
+3VS Y18 G12 USB20_P3

GPIO
R83 DDC1_SDA/GPIO8 USB_HSD3P USB20_N3 USB20_P3 <35>
C1
LLB#/GPIO66 USB_HSD3N
G14 USB20_N3 <35> USB-3 Dock
2

1 2 SB_GPIO5 Y19
R540 10K_0402_5% SMARTVOLT2/SHUTDOWN#/GPIO5 USB20_P2
G5 H14 USB20_P2 <31>
10K_0402_5% DDR3_RST#/GEVENT7# USB_HSD2P USB20_N2
USB_HSD2N H15 USB20_N2 <31> USB-2 Left Side
A13 USB20_P1
USB20_P1 <31>
1

USB_HSD1P USB20_N1
PCIE_WAKE# USB_HSD1N
B13 USB20_N1 <31> USB-1 Right side
2 1
<25> LAN_PCIE_WAKE# R993 47_0402_5% USB20_P0
B14 USB20_P0 <31>
USB_HSD0P USB20_N0
<26> MINI_PCIE_WAKE#
2
R994
1
@ 0_0402_5%
B9
USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N
A14 USB20_N0 <31> USB-0 Right side (S/W Debug Port)
B8
USB_OC5#/IR_TX0/GPM5#
A8 A18

USB OC
R82 0_0402_5% USB_OC4#/IR_RX0/GPM4# KSO_16
<33> EC_LID_OUT# A9 B18
EXP_CPPE# USB_OC3#/IR_RX1/GPM3# KSO_17
<26> EXP_CPPE# 1 2 E5 F21
CR_CPPE# USB_OC2#/GPM2# IMC_PWM0/IMC_GPIO10
<27> CR_CPPE# 1 2 F8 USB_OC1#/GPM1# SCL2/IMC_GPIO11 D21
R333 33_0402_5% 1 2 R81 0_0402_5% E4 F19
<28> HDA_BITCLK_CODEC USB_OC0#/GPM0# SDA2/IMC_GPIO12
R334 33_0402_5% 1 2 HDABITCLK 1 2 HDA_BITCLK E20
<34> HDA_BITCLK_MDC SCL3_LV/IMC_GPIO13
R335 33_0402_5% 1 2 R1080 0_0402_5% M1 E21
<34> HDA_SDOUT_MDC AZ_BITCLK SDA3_LV/IMC_GPIO14
R336 33_0402_5% 1 2 HDA_SDOUT M2 E19
<28> HDA_SDOUT_CODEC HDA_SDIN0 AZ_SDOUT IMC_PWM1/IMC_GPIO15
<28> HDA_SDIN0 HDA_SDIN1
J7
AZ_SDIN0/GPIO42 IMC_PWM2/IMC_GPO16
D19 STRAP PIN
GPIO16 <23>
<34> HDA_SDIN1 J8
AZ_SDIN1/GPIO43 IMC_PWM3/IMC_GPO17
E18 STRAP PIN
GPIO17 <23>
L8 AZ_SDIN2/GPIO44

H D AUDIO
M3 G20
R337 33_0402_5% HDA_SYNC AZ_SDIN3/GPIO46 KSI_0
<34> HDA_SYNC_MDC 1 2 L6 G21
R338 33_0402_5% AZ_SYNC KSI_1
<28> HDA_SYNC_CODEC 1 2 M4 D25
AZ_RST# KSI_2
L5 D24
R339 33_0402_5% HDARST# AZ_DOCK_RST#/GPM8# KSI_3
1 2 C25

INTEGRATED uC
3 <28> HDA_RST#_CODEC KSI_4 3
R340 33_0402_5% 1 2 C24
<34> HDA_RST#_MDC KSI_5
PAD T41 KSI_6 B25
C23
KSI_7
<23,33> HDARST#
STRAP PIN KSO_0
B24
B23
KSO_1
A23
KSO_2
C22
KSO_3
A22
KSO_4
KSO_5 B22
KSO_6 B21
C1088 82P_0402_50V8J A21
HDA_BITCLK_CODEC KSO_7
1 2 H19 PS2_DAT KSO_8 D20
H20 C20
C1089 82P_0402_50V8J PS2_CLK KSO_9
H21 A20

INTEGRATED uC
HDA_BITCLK_MDC SPI_CS2#/IMC_GPIO2 KSO_10
1 2 F25 B20
IDE_RST#/F_RST#/IMC_GPO3 KSO_11
B19
C1090 82P_0402_50V8J KSO_12
D22 A19
HDA_SDOUT_MDC PS2KB_DAT KSO_13
1 2 E24 D18
PS2KB_CLK KSO_14
E25 C18
C1091 82P_0402_50V8J PS2M_DAT KSO_15
D23
HDA_SDOUT_CODEC PS2M_CLK
1 2

218-0660011 A14 SB7_FCBGA528

+3VS
@ U66
7 VDD 1 HDA_BITCLK
CLKIN
4 HDABITCLK 4
6 2
@ R1081 CLKOUT NC
2 1 5
10K_0402_5% SSON NC 8
@ R1082 +3VS 03/05 Add SSC circuit for HDA_BITCLK.
1
@C1122 4 3 2 1
GND SS 10K_0402_5%
2

0.1U_0402_16V4Z ASM3P623S00BF-08TR_TSSOP8
2 @ R1083
10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
SB710 USB/AC97
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 20 of 56
A B C D E
 A B C D E

10P_0402_50V8J 2 1 C516 SATA_X1

1
Y4
R341

25MHz_20pF_6X25000017 10M_0402_5%

2
10P_0402_50V8J 2 1 C517 SATA_X2

1 1
U15B

C512 1 2 0.01U_0402_25V7K SATA_STX_DRX_P0 AD9

SB700 AA24
<24> SATA_TXP0 SATA_TX0P IDE_IORDY
<24> SATA_TXN0 C513 1 2 0.01U_0402_25V7K SATA_STX_DRX_N0 AE9 Part 2 of 5 AA25
SATA_TX0N IDE_IRQ
Y22
IDE_A0
<24> SATA_RXN0_C AB10 SATA_RX0N IDE_A1 AB23
<24> SATA_RXP0_C AC10 SATA_RX0P IDE_A2 Y23
IDE_DACK#
AB24 Local Frame Buffer Strapping List
C514 1 2 0.01U_0402_25V7K SATA_STX_DRX_P1 AE10 AD25 Copy from Becks.
<24> SATA_TXP1 SATA_TX1P IDE_DRQ
C515 1 2 0.01U_0402_25V7K SATA_STX_DRX_N1 AD10 AC25
<24> SATA_TXN1 SATA_TX1N IDE_IOR#
IDE_IOW# AC24
<24> SATA_RXN1_C AD11
AE11
SATA_RX1N IDE_CS1#
Y25
Y24
LFB_ID2 LFB_ID1 LFB_ID0
<24> SATA_RXP1_C SATA_RX1P IDE_CS3#
C520 1 2 1000P_0402_50V7K SATA_STX_DRX_P2 AB12 AD24
<31> SATA_TXP2 SATA_TX2P IDE_D0/GPIO15
C521 2 1000P_0402_50V7K SATA_STX_DRX_N2
<31> SATA_TXN2 1 AC12
SATA_TX2N IDE_D1/GPIO16
AD23 Hynix 0 0 0

ATA 66/100/133
IDE_D2/GPIO17 AE22
<31> SATA_RXN2_C AE12 AC22
SATA_RX2N IDE_D3/GPIO18
<31> SATA_RXP2_C AD12 AD21
SATA_RX2P IDE_D4/GPIO19
C518 1 2 0.01U_0402_25V7K SATA_STX_DRX_P3 AD13
IDE_D5/GPIO20
AE20
AB20
Qimonda 0 0 1
<24> SATA_TXP3 SATA_TX3P IDE_D6/GPIO21
C519 1 2 0.01U_0402_25V7K SATA_STX_DRX_N3 AE13 AD19
<24> SATA_TXN3 SATA_TX3N IDE_D7/GPIO22
AE19

SERIAL ATA
IDE_D8/GPIO23
<24> SATA_RXN3_C AB14
AC14
SATA_RX3N IDE_D9/GPIO24 AC20
AD20
Samsung 0 1 0
<24> SATA_RXP3_C SATA_RX3P IDE_D10/GPIO25
AE21
IDE_D11/GPIO26
AE14 SATA_TX4P IDE_D12/GPIO27 AB22
AD14 SATA_TX4N IDE_D13/GPIO28 AD22

AD15
IDE_D14/GPIO29
AE23
AC23
LFB_ID0 to LFB_ID2 got internal PU 10K to S5.
2 SATA_RX4N IDE_D15/GPIO30 2
AE15 SATA_RX4P LFB_ID2 R344 1 2 1K_0402_5%
AB16 R1032
SATA_TX5P LFB_ID1 R367 1
AC16 SATA_TX5N +3VALW 1 2 2 10K_0402_5%
G6 @ 1K_0402_5%
SPI_DI/GPIO12 LFB_ID0 R345 1
AE16 D2 +3VALW 1 2 2 10K_0402_5%
SATA_RX5N SPI_DO/GPIO11 @ 1K_0402_5%
AD16 SATA_RX5P SPI_CLK/GPIO47 D1
F4 R1033

SPI ROM
SATA_CAL SPI_HOLD#/GPIO31
2 1 V12 SATA_CAL SPI_CS1#/GPIO32 F3
R342 1K_0402_1%
SATA_X1 Y12 U15
R343 10K_0402_5% SATA_X1 LAN_RST#/GPIO13
J1
SATA_X2 ROM_RST#/GPIO14
+3VS 1 2 AA12 SATA_X2
M8
FANOUT0/GPIO3
<34> SATA_LED# W11 M5 CR_WAKE# <27>
+1.2V_HT SATA_ACT#/GPIO67 FANOUT1/GPIO48 +3VALW
M7
L54 FANOUT2/GPIO49
2 1 +PLLVDD_SATA AA11 P5
BLM18PG121SN1D_0603 PLLVDD_SATA FANIN0/GPIO50
P8 HDD_HALTLED# <34>
FANIN1/GPIO51

SATA PWR
2 2 W12 XTLVDD_SATA FANIN2/GPIO52 R8 SB_INT_FLASH_SEL

1
C522 C523 C6 THERMAL_DC R1062 1 2 0_0402_5% R1071
1U_0402_6.3V4Z TEMP_COMM
1U_0402_6.3V4Z B6 WLOFF# <26>
1 1 TEMPIN0/GPIO61 150K_0402_5%
A6 BT_COMBO_EN# <26>
TEMPIN1/GPIO62
A5 WWOFF# <26>

2
TEMPIN2/GPIO63
B5 EC_THERM# <33>
TEMPIN3/TALERT#/GPIO64

HW MONITOR
+3VS A4 AC_IN_SB 2 1
VIN0/GPIO53 AC_IN <33,38>
L55 B4 D56
+XTLVDD_SATA VIN1/GPIO54 BT_OFF <31>
2 1 C4 CH751H-40PT_SOD323-2
VIN2/GPIO55 CAM_SHDN# <17>
BLM18PG121SN1D_0603 2 D4
VIN3/GPIO56 LFB_ID0
D5
3 C524 VIN4/GPIO57 LFB_ID1 3
VIN5/GPIO58 D6
1U_0402_6.3V4Z LFB_ID2
1 VIN6/GPIO59 A7
B7
02/18 Add R1071 and D56 to connect to AC_IN.
VIN7/GPIO60
+3VALW
L56
F6 +SB_AVDD 2 1
AVDD BLM18PG121SN1D_0603
1 1
G7
AVSS C526
2.2U_0603_6.3V4Z
2 2
218-0660011 A14 SB7_FCBGA528
C525
0.1U_0402_16V4Z

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB710 SATA/IDE/SPI
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 21 of 56
A B C D E
 A B C D E

L 0.6A/50mil/4vias U15E
U15C 1 2 +1.2VALW
0.45A/40mil/3vias ? R592 @ 0_0805_5%
L SB700 +1.2V_SB_CORE
+3VS L9
M9
VDDQ_1
Part 3 of 5
VDD_1 L15
M12
1
R593
2
0_0805_5%
+1.2V_HT SB700 A2
VDDQ_2 VDD_2 VSS_1
2 1 T15 VDDQ_3 VDD_3 M14 1 2 VSS_2 A25
1 C528 22U_0805_6.3V6M 10U_0805_6.3V6M C529 1
U9 N13 B1

CORE S0
C531 1U_0402_6.3V4Z VDDQ_4 VDD_4 1U_0402_6.3V4Z C532 VSS_3
1 2 U16 VDDQ_5 VDD_5 P12 2 1 VSS_4 D7
C530 1 2 1U_0402_6.3V4Z U17 P14 1U_0402_6.3V4Z 2 1 C534 T10 F20
VDDQ_6 VDD_6 AVSS_SATA_1 VSS_5

PCI/GPIO I/O
C533 1 2 1U_0402_6.3V4Z V8 R11 1U_0402_6.3V4Z 2 1 C538 U10 G19
C549 1U_0402_6.3V4Z VDDQ_7 VDD_7 1U_0402_6.3V4Z C537 AVSS_SATA_2 VSS_6
1 2 W7 R15 2 1 U11 H8
C535 1U_0402_6.3V4Z VDDQ_8 VDD_8 0.1U_0402_16V4Z C527 AVSS_SATA_3 VSS_7
1 2 Y6 VDDQ_9 VDD_9 T16 2 1 U12 AVSS_SATA_4 VSS_8 K9
C539 1 2 1U_0402_6.3V4Z AA4 0.1U_0402_16V4Z 2 1 C540 V11 K11
C541 0.1U_0402_16V4Z VDDQ_10 AVSS_SATA_5 VSS_9
1 2 AB5 VDDQ_11 V14 AVSS_SATA_6 VSS_10 K16
C542 1 2 0.1U_0402_16V4Z AB21 W9 L4
VDDQ_12 AVSS_SATA_7 VSS_11
Y9 L7
AVSS_SATA_8 VSS_12
L 0.45A/30mil/3vias Y11 AVSS_SATA_9 VSS_13 L10

@ 0_0603_5% L 0.3A/30mil/2vias L60

Y14
AVSS_SATA_10 VSS_14
L11
Y17 AVSS_SATA_11 VSS_15 L12
R12 1 2 +3.3V_SB_IDE Y20 L21 +1.2V_CKVDD 2 1 AA9 L14
+3VS VDD33_18_1 CKVDD_1.2V_1 +1.2V_HT AVSS_SATA_12 VSS_16
AA21 L22 0_0805_5% AB9 L16
VDD33_18_2 CKVDD_1.2V_2 AVSS_SATA_13 VSS_17
2 1 AA22 L24 AB11 M6
VDD33_18_3 CKVDD_1.2V_3 AVSS_SATA_14 VSS_18

IDE/FLSH I/O

CLKGEN I/O
C543 @ 22U_0805_6.3V6M AE25 L25 C546 1 2 1U_0402_6.3V4Z AB13 M10
C544 VDD33_18_4 CKVDD_1.2V_4 AVSS_SATA_15 VSS_19
1 2 @ 1U_0402_6.3V4Z C545 1 2 1U_0402_6.3V4Z AB15 M11
C547 AVSS_SATA_16 VSS_20
1 2 @ 1U_0402_6.3V4Z C548 2 1 0.1U_0402_16V4Z AB17 AVSS_SATA_17 VSS_21 M13
C536 1 2 @ 1U_0402_6.3V4Z C551 2 1 0.1U_0402_16V4Z AC8 M15
C550 10U_0805_10V4Z AVSS_SATA_18 VSS_22
1 2 AD8 N4
AVSS_SATA_19 VSS_23
AE8 N12
AVSS_SATA_20 VSS_24
VSS_25 N14
+PCIE_VDDR P6
L61 POWER VSS_26
VSS_27
P9
+1.2V_HT 2 1 VSS_28 P10
0_0805_5% A15 P11
AVSS_USB_1 VSS_29
L 0.8A/50mil/4vias P18
PCIE_VDDR_1 +3VALW
B15
AVSS_USB_2 VSS_30
P13
2 1 P19 PCIE_VDDR_2 L 0.1A/30mil/2vias ? C14 AVSS_USB_3 VSS_31 P15
C552 4.7U_0805_10V4Z P20 D8 R1
C553 1U_0402_6.3V4Z PCIE_VDDR_3 +S5_3V AVSS_USB_4 VSS_32
1 2 P21 A17 1 2 D9 R2
PCIE_VDDR_4 S5_3.3V_1 AVSS_USB_5 VSS_33

A-LINK I/O
C555 1 2 1U_0402_6.3V4Z R22 A24 R564 0_0805_5% D11 R4
2 C554 1U_0402_6.3V4Z PCIE_VDDR_5 S5_3.3V_2 AVSS_USB_6 VSS_34 2
1 2 R24 PCIE_VDDR_6 S5_3.3V_3 B17 1 2 D13 AVSS_USB_7 VSS_35 R9
C558 1U_0402_6.3V4Z 22U_0805_6.3V6M C556

GROUND
1 2 R25 J4 D14 R10
C557 0.1U_0402_16V4Z PCIE_VDDR_7 S5_3.3V_4 1U_0402_6.3V4Z 2 C559 AVSS_USB_8 VSS_36
1 2 J5 1 D15 R12

3.3V_S5 I/O
C560 0.1U_0402_16V4Z S5_3.3V_5 1U_0402_6.3V4Z 2 C561 AVSS_USB_9 VSS_37
1 2 S5_3.3V_6 L1 1 E15 AVSS_USB_10 VSS_38 R14
L2 1U_0402_6.3V4Z 2 1 C562 F12 T11
+1.2V_SATA S5_3.3V_7 0.1U_0402_16V4Z 2 C563 AVSS_USB_11 VSS_39
1 F14 T12
L63 0.1U_0402_16V4Z 2 C564 AVSS_USB_12 VSS_40
1 G9 AVSS_USB_13 VSS_41 T14
+1.2V_HT 2 1 AA14 0.1U_0402_16V4Z 2 1 C565 H9 U4
0_0805_5% AVDD_SATA_1 +1.2VALW AVSS_USB_14 VSS_42
AB18 AVDD_SATA_4 H17 AVSS_USB_15 VSS_43 U14
L <1.25A/50mil/4vias AA15
AVDD_SATA_2 +S5_1.2V L64 0_0603_5%
J9
AVSS_USB_16 VSS_44
V6
2 1 AA17 G2 J11 Y21

CORE S5
AVDD_SATA_3 S5_1.2V_1 AVSS_USB_17 VSS_45

SATA I/O
C566 22U_0805_6.3V6M AC18 G4 J12 AB1
C567 1U_0805_16V7K AVDD_SATA_5 S5_1.2V_2 +1.2VALW 1U_0402_6.3V4Z AVSS_USB_18 VSS_46
1 2 AD17 AVDD_SATA_6 2 1 C569 J14 AVSS_USB_19 VSS_47 AB19
C568 1 2 1U_0805_16V7K AE17 0.1U_0402_16V4Z 2 1 C570 J15 AB25
C571 0.1U_0402_16V4Z AVDD_SATA_7 +1.2_USB L65 0_0603_5% AVSS_USB_20 VSS_48
1 2 K10 AE1
C572 0.1U_0402_16V4Z AVSS_USB_21 VSS_49
1 2 A10 K12 AE24
USB_PHY_1.2V_1 AVSS_USB_22 VSS_50
B10 1 2 K14
USB_PHY_1.2V_2 10U_0805_10V4Z C573 AVSS_USB_23
K15
1U_0402_6.3V4Z 2 C574 AVSS_USB_24
1 P23
1U_0402_6.3V4Z 2 C575 PCIE_CK_VSS_9
L C567,C568 change to 1U_0402 when SI-2 1 PCIE_CK_VSS_10 R16
R19
+AVDD_USB PCIE_CK_VSS_11
T17
L66 PCIE_CK_VSS_12
U18
+V5_VREF 1K_0402_5% 2 PCIE_CK_VSS_13
+3VALW 2 1 A16 AE7 1 R346 +5VS H18 U20
0_0805_5% AVDDTX_0 V5_VREF D14 PCIE_CK_VSS_1 PCIE_CK_VSS_14
B16 J17 V18
L <1.25A/50mil/4vias? C16
AVDDTX_1
AVDDTX_2 AVDDCK_3.3V
J16 +AVDDCK_3.3V
2 2
1 2 +3VS J22
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_15
PCIE_CK_VSS_16
V20
C576 1 2 10U_0805_10V4Z D16 C578 C579 K25 V21
C577 10U_0805_10V4Z AVDDTX_3 +AVDDCK_1.2V0.1U_0402_16V4Z 1U_0603_10V4Z CH751H-40PT_SOD323-2 PCIE_CK_VSS_4 PCIE_CK_VSS_17
1 2 D17 K17 M16 W19
PLL

C580 1U_0402_6.3V4Z AVDDTX_4 AVDDCK_1.2V 1 1 PCIE_CK_VSS_5 PCIE_CK_VSS_18

1 2 E17 M17 W22
AVDDTX_5 PCIE_CK_VSS_6 PCIE_CK_VSS_19
USB I/O

C581 1 2 1U_0402_6.3V4Z F15 E9 +AVDDC M21 W24

C583 0.1U_0402_16V4Z AVDDRX_0 AVDDC PCIE_CK_VSS_7 PCIE_CK_VSS_20
1 2 F17 P16 W25
C582 0.1U_0402_16V4Z AVDDRX_1 L67 PCIE_CK_VSS_8 PCIE_CK_VSS_21
1 2 F18
3 C584 0.1U_0402_16V4Z AVDDRX_2 3
1 2 G15 AVDDRX_3 2 1 +3VALW F9 AVSSC AVSSCK L17
G17 0_0805_5% Part 5 of 5
AVDDRX_4
G18
AVDDRX_5 2.2U_0603_6.3V4Z 2 C585 218-0660011 A14 SB7_FCBGA528
1

0.1U_0402_16V4Z 2 1 C586
218-0660011 A14 SB7_FCBGA528

L68
+AVDDCK_1.2V 2 1 +1.2V_HT
0_0805_5%

2.2U_0603_6.3V4Z 2 1 C587

0.1U_0402_16V4Z 2 1 C588

L69
+AVDDCK_3.3V 2 1 +3VS
0_0805_5%

2.2U_0603_6.3V4Z 2 1 C589

0.1U_0402_16V4Z 2 1 C590

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB710 PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 22 of 56
A B C D E
 A B C D E

REQUIRED STRAPS NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 AZ_RST_CD# LPC_CLK1 RTC_CLK LPC_CLK0 GP17 GP16

PULL BOOTFAIL USE RESERVED RESERVED ENABLE PCI CLKGEN INTERNAL EC Internal pull up
1 HIGH TIMER DEBUG MEM BOOT ENABLED RTC ENABLED 1
ENABLED STRAPS H,H = Reserved
DEFAULT
H,L = SPI ROM
EXT. RTC
PULL BOOTFAIL IGNORE DISABLE PCI CLKGEN (PD on X1, EC
LOW TIMER DEBUG MEM BOOT DISABLED apply DISABLED L,H = LPC ROM (Default)
DISABLED STRAPS 32KHz to DEFAULT L,L = FWH ROM
DEFAULT DEFAULT DEFAULT DEFAULT RTC_CLK)

+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
R356

R347

R348

R349

R350

R351

R352

R353

R354

R355
2.2K_0402_5%

2
@

@
@ @ @ @ @ @ @
<19> PCICLK2
<19> PCI_CLK3
<19> PCI_CLK4
<19> PCI_CLK5
<19,33> CLK_PCI_EC
<19> LPCCLK1
2 <19> RTC_CLK 2
<20,33> HDARST#
<20> GPIO17
<20> GPIO16

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R363

R365

R366
R357

R358

R359

R360

R361

R362

R364
2

2
@ @ @ @

DEBUG STRAPS
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

USE USE PCI USE ACPI USE IDE USE DEFAULT RESERVED
3
PULL LONG PLL BCLK PLL PCIE STRAPS 3
HIGH RESET
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT

PULL USE BYPASS BYPASS BYPASS IDE USE EEPROM

LOW SHORT PCI PLL ACPI PLL PCIE STRAPS
RESET BCLK

<19> PCI_AD28
<19> PCI_AD27
<19> PCI_AD26
<19> PCI_AD25
<19> PCI_AD24
<19> PCI_AD23
1

1
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R373

R374

R375

R376

R377

R378
2

2
@ @ @ @ @ @
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700 STRAPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 23 of 56
A B C D E
 A B C D E

HDD Connector
+5VS JP9

1
GND

0.1U_0402_16V4Z
10U_0805_10V4Z
2 SATA_TXP0
A+ SATA_TXP0 <21>
1 1 1 1 3 SATA_TXN0 SATA_TXN0 <21>
A-

C593

C595
4 0.01U_0402_16V7K
1 GND SATA_RXN0 1
C594 C591
B- 5 2 1 C592 SATA_RXN0_C SATA_RXN0_C <21>
6 SATA_RXP0 2 1 C596 SATA_RXP0_C
2 2 2 2 B+ SATA_RXP0_C <21>
7 0.01U_0402_16V7K
0.1U_0402_16V4Z 0.1U_0402_16V4Z GND
Near CONN side.
V33 8 +3VS_HDD1
Pleace near HD CONN (JP23) V33
9
V33 10
GND 11
+3VS +3VS_HDD1 12
@R1009 GND
GND 13
1 2 14
V5

0.1U_0402_16V4Z
10U_0805_10V4Z
0_0805_5% 15 +5VS
V5
1 1 1 1 16
V5

C1032

C1035
17
@ C1033 @ C1034 GND
18
Reserved
GND 19
@ 2 2 2 2 @ 20
0.1U_0402_16V4Z 0.1U_0402_16V4Z V12
V12 21
22
V12
Pleace near HD CONN (JP23)
CONN@ SUYIN_127072FR022G523_RV

Multi-Bay Connector-option
2 2

+5VS
Max 3A

1 10U_0805_10V4Z
1 1 1 PA@ 1
C600 + C601 C604
C602 C603
PA@ PA@ PA@ 0.1U_0402_16V4Z
2 2 2 2 2 +5VS CONN@ JP10
@ 150U_Y_6.3VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 1
VCC5 GND SATA_TXP1
4 3 SATA_TXP1 <21>
VCC5 TX+ SATA_TXN1
Place close to Multi-Bay 6
VCC5 TX-
5 SATA_TXN1 <21>
8 7 0.01U_0402_16V7K
Connector-option JP10 10
VCC3 GND
9 SATA_RXN1 2 1 C605 SATA_RXN1_C
VCC3 RX- SATA_RXN1_C <21>
12 11 SATA_RXP1 2 1 C606 SATA_RXP1_C
VCC3 RX+ SATA_RXP1_C <21>
14 13 0.01U_0402_16V7K
GND GND
16
GND GND
15
Near CONN side.
18 17
GND GND
TYCO_2023087-3

3 3

CD-ROM Connector
JP11
+5VS
1
GND SATA_TXP3
Placea caps. near ODD CONN. A+ 2 SATA_TXP3 <21>
3 SATA_TXN3
A- SATA_TXN3 <21>
4 0.01U_0402_16V7K
GND SATA_RXN3
5 2 1 C612 SATA_RXN3_C SATA_RXN3_C <21>
B- SATA_RXP3
6 2 1 C611 SATA_RXP3_C SATA_RXP3_C <21>
B+ 0.01U_0402_16V7K
7
GND
0.1U_0402_16V4Z

1U_0603_10V4Z

10U_0805_10V4Z

R970 0_0402_5%
1 1 1 1
Near CONN side.
C613

8 1 2
DP
C614

C615

C616 9
10U_0805_10V4Z V5
10 +5VS
2 2 2 2 V5
11
MD
GND 12
13
GND

CONN@ SUYIN_127382FR013G509ZR
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/CDROM
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 24 of 56
A B C D E
 A B C D E

1 2
+3VALW @ R1067 0_0805_5%

1 2 +3V_LAN
R1055 3.6K_0402_5% 40 mils

S
3 1

D
+3V_LAN

2
2
@ R1056

G
2
LAN_DI 100K_0402_5% @ C1077 Q144
SI2301BDS-T1-E3_SOT23-3
LAN_CS 1

1
<33> LAN_POWER_OFF 1 2
R1057 0_0402_5% 0.1U_0402_16V4Z
1 1
2 1
R1058 10K_0402_5%

+LAN_VDD12
Close to Pin1,37,29
Place Close to Chip Close to Pin10,13,30,36 +3V_LAN
U44

<10> PCIE_PTX_C_IRX_P3 C485 2 1 0.1U_0402_16V7K PCIE_PTX_IRX_P3 20 HSOP LED3/EEDO 33

34 LAN_DI 2 2 2 2
LED2/EEDI/AUX
<10> PCIE_PTX_C_IRX_N3 C488 2 1 0.1U_0402_16V7K PCIE_PTX_IRX_N3 21 HSON LED1/EESK 35 LAN_SK_LAN_LINK# C628 C629 C630 C631 2 2 2
32 LAN_CS C620 C621 C622
EECS 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<10> PCIE_ITX_C_PRX_P3 15 HSIP
38 LAN_ACTIVITY# 1 1 1 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
LED0 1 1 1
<10> PCIE_ITX_C_PRX_N3 16
HSIN LAN_MDI0+
RTL8102EL MDIP0
2
17 3 LAN_MDI0-
<15> CLK_PCIE_LAN REFCLK_P MDIN0
18 5 LAN_MDI1+
<15> CLK_PCIE_LAN# REFCLK_M MDIP1
6 LAN_MDI1-
MDIN1
<15> CLKREQ_LAN# 25 8
CLKREQB NC
9
NC
+3VS <11,14,19,26,27,32,33> PLT_RST# 27
PERSTB NC
11 Close to Pin48
NC 12 Close to Pin45
R1059 1 2 2.49K_0402_1% 46 4
RSET NC
1

R1060 26 48 VCTRL12 VCTRL12 0.1U_0402_16V4Z +LAN_VDD12

<20> LAN_PCIE_WAKE# LANWAKEB VCTRL12A
1K_0402_1% ISOLATEB 28
ISOLATEB
VDDTX 19 +EVDD12 1 2
LAN_X1 41 30 C1080
+LAN_VDD12
2

ISOLATEB LAN_X2 CKXTAL1 DVDD12 C1079

42 36 2 1
CKXTAL2 DVDD12
13
2 DVDD12 2 1 C632 C633 2
DVDD12 10
@ 10U_0805_10V4Z 0.1U_0402_16V4Z @ 10U_0805_10V4Z
R1061 1 2
39
15K_0402_5% NC
23 NC NC 44
24 45 +LAN_VDD12
NC VCTRL12D
7 29 +3V_LAN
GND VDD33
14 GND VDD33 37 Close to Pin19
31
GND +EVDD12
47 GND AVDD33 1
40
NC
22 GNDTX NC 43

RTL8103EL-GR_LQFP48_7X7 2 2
C1082
C1081
1U_0402_6.3V4Z 0.1U_0402_16V4Z
1 1
Y5
LAN_X1 2 1 LAN_X2

25MHz_20pF_6X25000017
1 1
C653 C654

27P_0402_50V8J
2 27P_0402_50V8J 2

3
LAN Conn. 3

U19 JRJ45
+3V_LAN 13 Yellow LED+
LAN_MDI0+ 1 16 RJ45_MIDI0+ RJ45_MIDI0+ <35>
LAN_MDI0- RD+ RX+ RJ45_MIDI0- LAN_ACTIVITY# R391
2 15 RJ45_MIDI0- <35> 2 1 300_0402_5% 14
C648 1 LAN_CT0 RD- RX- RJ45_CT0 Yellow LED-
2 0.01U_0402_16V7K 3 14 75_0402_1% 1 16
CT CT SHLD1
4 13 C1083 1 2 0.01U_0603_100V7-M RJ45_CT0_C 1 R394 2 8
NC NC PR4-
5 12 C1084 1 2 0.01U_0603_100V7-M RJ45_CT1_C 1 2 RJ45_GND C656 9
C647 1 LAN_CT1 NC NC RJ45_CT1 @68P_0402_50V8K DETECT PIN1
2 0.01U_0402_16V7K 6 CT CT 11 R396 7 PR4+
LAN_MDI1+ RJ45_MIDI1+ 75_0402_1% 2
7 TD+ TX+ 10 RJ45_MIDI1+ <35> 1
LAN_MDI1- 8 9 RJ45_MIDI1- C658 RJ45_MIDI1- 6
TD- TX- RJ45_MIDI1- <35> PR2-
1000P_1206_2KV7K 5
NS681680 2 PR3-
4
PR3+
RJ45_MIDI1+ 3
PR2+
RJ45_MIDI0- 2
PR1-
10
LAN_ACTIVITY# RJ45_MIDI0+ DETCET PIN2
2 1 PR1+
LAN_SK_LAN_LINK# 15
@C657 SHLD1
+3V_LAN 11 Green LED+
3 68P_0402_50V8K

2
LAN_SK_LAN_LINK#1 R395 2 1 300_0402_5% 12
Green LED-
FOX_JM36113-P1122-7F
CONN@ LANGND
@ D55 1 1
C661 C662
1

PACDN042Y3R_SOT23-3
4 0.1U_0402_16V4Z 4.7U_0805_10V4Z 4
2 2

9/20 DC234001G00

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTL8111C/8102E 10/100/1000 LAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 25 of 56
A B C D E
 A B C D E

Mini Card Slot 2---WLAN +3VALW Mini Card Slot 1---TV tuner / WWAN / Robson
+3VS Max 1A +3VS_WLAN +1.5VS Max 0.5A +1.5VS_WLAN +3VALW_WLAN +3VS_WLAN
@ R1043 0_0603_5%
2 R407 1 1 R406 2 1 2 +3VALW +3VS Max 2.7A +1.5VS Max 0.5A
0_0805_5% 0_0805_5% R1042 0_0603_5% +3VS_MINI PA@ +3VALW_WWAN PA@ +3VS_MINI PA@ +1.5VS_MINI
1 1 1 1 1 1 1 2 R971 0_0603_5% L78 L79
C665 C666 C668 C669 C670 C667 2 1 1 2 0.01U_0402_16V7K 4.7U_0805_10V4Z 2 1 4.7U_0805_10V4Z
@ R972 0_0603_5% 0_1206_5% 0_0805_5%
0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.01U_0402_16V7K 4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 1 PA@ 1 PA@ 1 PA@ 1 PA@ 1 PA@ 1 PA@ 1
2 2 2 2 2 2 C785 C786 C787 C781 C782 C783
1 1
PA@C671 @ C784
0.1U_0402_16V4Z 0.1U_0402_16V7K
0.1U_0402_16V4Z 2 2 2 2 2 2
1 JP14 2 2 1
MINI_PCIE_WAKE# 1 2 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z
1 2 +3VS_WLAN
CH_DATA 3 4
<31> CH_DATA 3 4
<31> CH_CLK CH_CLK 5 6 +1.5VS_WLAN JP13
5 6
<15> CLKREQ_MCARD2# 7 8 <20> MINI_PCIE_WAKE# 1 2 +3VS_MINI
7 8 1 2
9 9 10 10 3 3 4 4
<15> CLK_PCIE_MCARD2# 11 12 5 6 +1.5VS_MINI
11 12 5 6 UIM_PWR
<15> CLK_PCIE_MCARD2 13 13 14 14 <15> CLKREQ_MCARD1# 7 7 8 8 1 1
15 16 9 10 UIM_DATA PA@
15 16 9 10 UIM_CLK C1093
<15> CLK_PCIE_MCARD1# 11 12
11 12 UIM_RST PA@ 39P_0402_50V8J
<15> CLK_PCIE_MCARD1 13 13 14 14
17 18 15 16 UIM_VPP C1092 2 2
17 18 WL_OFF# 15 16 39P_0402_50V8J
19 19 20 20
21 22 PLT_RST#
21 22
<10> PCIE_PTX_C_IRX_N2 23 24 +3VALW_WLAN 17 18
23 24 17 18 WW_OFF#
<10> PCIE_PTX_C_IRX_P2 25 26 19 20
25 26 Max 0.3A 19 20 PLT_RST# Max 0.3A
27 27 28 28 21 21 22 22
29 30 SMB_CK_CLK1 23 24
29 30 <10> PCIE_PTX_C_IRX_N5 23 24 +3VALW_WWAN
<10> PCIE_ITX_C_PRX_N2 31 32 SMB_CK_DAT1 <10> PCIE_PTX_C_IRX_P5 25 26
31 32 25 26
<10> PCIE_ITX_C_PRX_P2 33 34 27 28
33 34 27 28 SMB_CK_CLK1
35 36 USB20_N8 <20> 29 30 1
35 36 29 30 SMB_CK_DAT1 PA@ C1094
37 38 USB20_P8 <20> <10> PCIE_ITX_C_PRX_N5 31 32
37 38 31 32 39P_0402_50V8J
39 39 40 40 <10> PCIE_ITX_C_PRX_P5 33 33 34 34
+3VS_WLAN R47 1 2 0_0603_5% 41 42 35 36
41 42 WL_LED# 35 36 USB20_N10 <20> 2
43 44 WL_LED# <34> 37 38 USB20_P10 <20>
43 44 PA@ 37 38
45 45 46 46 39 39 40 40
47 48 R401 1 2 0_0603_5% 41 42 WW_LED#
47 48 +3VS_MINI 41 42 WW_LED# <34>
49 50 1 43 44
CH_CLK 49 50 WL_OFF# 43 44
<21> BT_COMBO_EN# 1 R49 2 51 51 52 52 2 1 WLOFF# <21> 45 45 46 46
D59 PA@ C738 47 48
0_0402_5% CH751H-40PT_SOD323-2 39P_0402_50V8J 47 48
G1
G2
G3
G3

49 50
49 50
1

2 51 52
2 R48 CONN@ 51 52 2
53
54
55
56

FOX_AS0B226-S99N-7F

G1
G2
G3
G3
1 1
4.7K_0402_5% PA@
9/20 SP01000HS00/SP01000LX00 CONN@ PA@ C1095 C1096
2

53
54
55
56
FOX_AS0B226-S99N-7F 39P_0402_50V8J 39P_0402_50V8J
9/20 STANDOFF (H=7.5 mm) ES000000D00 2 2
9/20 SP01000HS00/SP01000LX00
WW_OFF# 2 1 WWOFF# <21>
D60 9/20 STANDOFF (H=7.5 mm) ES000000D00
New Card CH751H-40PT_SOD323-2

Express Card Power Switch

+1.5VS
RP@ C681 RP@ U21 @ R1087 0_0603_5%
2 1 0.1U_0402_16V4Z 12 1.5Vin 11 +1.5VS_PEC 1 2
1.5Vout
14 1.5Vin 13
+3VS 1.5Vout Max 0.65A +3VALW +3VS_MINI
RP@ C679 @ Q167
2 1 0.1U_0402_16V4Z 2 3.3Vin 3.3Vout 3 +3VS_PEC
RP@ 4 5 SI2301BDS-T1-E3_SOT23-3
3.3Vin 3.3Vout Max 1.3A
2 1 0.1U_0402_16V4Z
Max 0.275A C680 17 15 1 3

S
D
+3VALW AUX_IN AUX_OUT +3V_PEC
RP@
PLT_RST# 1 R54 2 6 19
<11,14,19,25,27,32,33> PLT_RST# SYSRST# OC#
0_0402_5%

G
2
20 8 PERST#
<33,36,40> SYSON SHDN# PERST#
<33> WWAN_POWER_OFF
<28,33,36,38,41> SUSP# 1 16
STBY# NC
10 7
CPPE# GND
3 EXP_CPPE# 3
<20> EXP_CPPE# 9 CPUSB#
THERMAL_PAD 21
18 +3VS_MINI
RCLKEN

R5538D001-TR-F_QFN20_4X4~D JP6
1
UIM_PWR 1
2
USE TI TPS2231MRGPR R421 UIM_DATA 3
2
3
UIM_CLK 1 2 UIMCLK 4
Near to Express Card slot. 9/20 SP02000B000 +3VS_PEC 33_0402_5% UIM_RST 5
4
5
9/20 SP02000IQ00
UIM_VPP 6 8
JEXP 4.7U_0805_10V4Z 6 G1
7 9
7 G2
1 1 1 ACES_88266-07001
GND RP@ RP@
<20> USB20_N11 2 USB_D- CONN@
<20> USB20_P11 3 C677 C678
EXP_CPPE# USB_D+
4
CPUSB# 2 2
5
RSV 0.1U_0402_16V4Z
6
SMB_CK_CLK1 RSV
<20> SMB_CK_CLK1 7 R1037
SMB_CK_DAT1 SMB_CLK
<20> SMB_CK_DAT1 8
SMB_DATA +1.5VS_PEC UIM_DATA UIM_PWR 0.1U_0402_16V4Z
+1.5VS_PEC 9 +1.5V 1 2
10
MINI_PCIE_WAKE# +1.5V 4.7U_0805_10V4Z @ 10K_0402_5%
11 WAKE# 1 PA@ 1 PA@
+3V_PEC 12 1 1 C1070 C1071
PERST# +3.3VAUX RP@ RP@
13
PERST# C683 C682 4.7U_0805_10V4Z
+3VS_PEC 14 +3.3V
15 2 2
CLKREQ_NCARD# +3.3V 2 2
<15> CLKREQ_NCARD# 16
EXP_CPPE# CLKREQ#
17
CPPE# 0.1U_0402_16V4Z
<15> CLK_PCIE_NCARD# 18
REFCLK-
<15> CLK_PCIE_NCARD 19 REFCLK+
4 4
20
GND
<10> PCIE_PTX_C_IRX_N0 21 PERn0
<10> PCIE_PTX_C_IRX_P0 22 PERp0
23 +3V_PEC
GND
<10> PCIE_ITX_C_PRX_N0 24 PETn0
<10> PCIE_ITX_C_PRX_P0 25 4.7U_0805_10V4Z
PETp0
26 GND
27 GND
RP@
C684
1
RP@
C685
1 Security Classification Compal Secret Data Compal Electronics, Inc.
28 GND Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

CONN@ SANTA_130801-5_LT 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN/TV tuner/Express Card
0.1U_0402_16V4Z AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 26 of 56
A B C D E
 A B C D E

+VCC_OUT +VCC_4IN1 Card Reader Connector +VCC_4IN1

JREAD
3 21 R45 10K_0402_5% +3VS_CR
+VCC_4IN1 XD-VCC SD-VCC +VCC_4IN1
+3VS U22 XDWP#_SDWP# 2
40mil XD_SD_MS_D0 32
MS-VCC 28 1
R121 4.7K_0402_5%
XD_SD_MS_D1 XD-D0 SDCLK XD_RB# XDCD0#_SDCD#2
3 IN OUT 1 10 XD-D1 7 IN 1 CONN SD_CLK 20 2 1 1
4 5 XD_SD_MS_D2 9 14 XD_SD_MS_D0 R106 10K_0402_5%
EN OUT XD_SD_MS_D3 XD-D2 SD-DAT0 XD_SD_MS_D1 R111 4.7K_0402_5%
1 8 XD-D3 SD-DAT1 12

1
C895 2 1 XD_SD_D4 7 30 XD_SD_MS_D2 XDCD1#_MSCD# 2 1
GND XD_SD_D5 XD-D4 SD-DAT2 XD_SD_MS_D3
6 XD-D5 SD-DAT3 29
@ 0.1U_0402_16V4Z @ G5250C2T1U_SOT23-5 XD_SD_D6 5 27 XD_SD_D4
2 @ C896 XD_SD_D7 XD-D6 SD-DAT4 XD_SD_D5 D40
4 XD-D7 SD-DAT5 23
1 2 18 XD_SD_D6 2 1

2
1U_0603_10V4Z @ R123 SDCMD_MSBS_XDWE#34 SD-DAT6 XD_SD_D7 XD_CD#
XD-WE SD-DAT7 16 1
XDWP#_SDWP# 33 25 SDCMD_MSBS_XDWE# 3 1
XD_ALE XD-WP SD-CMD XDCD0#_SDCD#
35 1
150K_0402_5% XD_CD# XD-ALE SD-CD-SW DAN202U_SC70 C696
40
XD_RB# XD-CD XDWP#_SDWP# 270P_0402_50V7K
39 XD-R/B SD-WP-SW 2
XD_RE# 38 2
XDCE# XD-RE
37 XD-CE
XD_CLE 36 26 MSCLK
XD-CLE MS-SCLK XD_SD_MS_D0
17
MS-DATA0 XD_SD_MS_D1
Use 0805 type and over 20 mils 11
31
7IN1 GND MS-DATA1 15
19 XD_SD_MS_D2
7IN1 GND MS-DATA2
trace width on both side MS-DATA3 24 XD_SD_MS_D3
XDCD1#_MSCD#
Strap pin for JMicro
22
MS-INS SDCMD_MSBS_XDWE# +3VS_CR
13
+VCC_OUT +VCC_4IN1 MS-BS
41
7IN1 GND XD_CLE
42 7IN1 GND 2 1
10K_0402_5% R405
1 R383 2 CONN@ TAITW_R015-B10-LM 2 1 XD_ALE
0_0805_5% 10K_0402_5% @ R122
1 1 2 1
SDCLK MSCLK XDCE# 10K_0402_5% R1069
C689 C694

2
10U_0805_10V4Z 0.1U_0402_16V4Z
2 2
@ R413 @ R412 @ R411
100_0402_5% 100_0402_5% 100_0402_5%
2 1 XD_RE#

1
2 2 2 place near pin 5 and 200K_0402_5% R86
pin 10. +1.8VS
@ C902 @ C901 @ C900
100P_0402_25V8K 100P_0402_25V8K 100P_0402_25V8K +1.8VS_OUT
2 1 1 1 R1020 2
+3VS 20mil 0.1U_0402_16V4Z 1U_0402_6.3V4Z 2 1
1 1 1 1
Place R413,C902 close to JREAD.20; R412,C901 @ 0_0603_5%
L
1

C892 C688 C687 C893 @

R124 close to JREAD.26; R411,C900 close to JREAD.37
2 2 2 2
10K_0402_5% 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2
G

2 1
Q54 0.1U_0402_16V4Z C695
CPPE#
<20> CR_CPPE# 1 3
Power Circuit +3VS_CR +3VS
D

D3 Normal 30mA Deepest 3mA

2N7002_SOT23-3 U23 2 R1021 1
1 1 0_0603_5%
0_0402_5% 3 5 Ripple 100mV
<15> CLK_PCIE_MCARD0# APCLKN APVDD
1 2 XDCD0#_SDCD# 4 58mA 10 C691 C692
<21> CR_WAKE# <15> CLK_PCIE_MCARD0 APCLKP APV18
R369 30 Ripple 100mV
9 1mA TAV33 2 2
<10> PCIE_ITX_C_PRX_N1 APRXN
8 19 Ripple 250mV 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<10> PCIE_ITX_C_PRX_P1 APRXP 45mA DV33 20
C693 1 0.1U_0402_16V7K PCIE_PTX_IRX_N1 DV33
<10> PCIE_PTX_C_IRX_N1 2 11 44
C697 1 0.1U_0402_16V7K PCIE_PTX_IRX_P1 APTXN DV33 Ripple 250mV
<10> PCIE_PTX_C_IRX_P1 2 12 18 +1.8VS_OUT
APTXP 25mA DV18 37 1 1
APREXT DV18
2 R114 1 7 APREXT
8.2K_0402_5% 12mil 48 XD_SD_MS_D0 C686 C690
MDIO0 XD_SD_MS_D1 0.1U_0402_16V4Z 0.1U_0402_16V4Z
47
MDIO1 XD_SD_MS_D2 2 2
+3VS_CR 2 R409 1 38 46
10K_0402_5% PCIES_EN MDIO2 XD_SD_MS_D3
+5VS_LED
39
PCIES JMB385 MDIO3
MDIO4
45
43 SDCMD_MSBS_XDWE#
3 SDCLK_MSCLK_XDCE# R457 2 SDCLK 3
MDIO5 42 1 22_0402_5%
41 XDWP#_SDWP# R456 2 1 22_0402_5% MSCLK
MDIO6
1

40 XD_CLE R455 2 1 22_0402_5% XDCE#

R370 MDIO7 XD_SD_D4
MDIO8 29
1 28 XD_SD_D5 Place R455~R457 close to U23.42
470_0402_5% <11,14,19,25,26,32,33> PLT_RST#
2
XRSTN
XTEST
MDIO9
MDIO10
27 XD_SD_D6
XD_SD_D7
L
26
2

MDIO11 XD_RE#
25
CPPE# MDIO12 XD_RB#
13 23
SEEDAT MDIO13
2

PAD T45 14 22 XD_ALE

D5 SEECLK MDIO14
HT-F196BP5_WHITE 34
XDCD1#_MSCD# NC
15 CR1_CD1N NC 35
XDCD0#_SDCD# 16 36
CR1_CD0N NC
1

1 R1070 2 At least 20mils 6

+VCC_OUT
L 17
CR1_PCTLN
APGND
0_0402_5% use for PWR_EN# 24
GND
1

D @ Q53 31
CR_LED# GND
2 21 32
CR1_LEDN GND
S
G
2N7002_SOT23-3
8mA sink current GND
33
3

@ R454 J MB385-LGEZ0A_LQFP48_7X7

4.7K_0402_5% White LED: VF=3V, IF = 10mA, Res = 200 ohm

2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCI-E I/F Card Reader-JM385
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 27 of 56
A B C D E
 A B C D E

CODEC POWER
+3VDD_CODEC +3VS_HDA +3VS +VDDA_CODEC_R +VDDA_CODEC
R885 R978 R979 +5VALW +VDDA_CODEC
W=40Mil U32 (4.75V(4.56~4.94V))
+3VS 1 2 0.1U_0402_16V4Z 1 2 1 2
BLM18BD601SN1D_0603 BLM18BD601SN1D_0603 0_0603_5%
1 1 1 1 1
1
C728
2
0.1U_0402_16V4Z
1 IN
5
300mA
C734 C733 C1046 C730 C731 OUT
2 1
GND C729
0.1U_0402_16V4Z 1U_0603_10V4Z <26,33,36,38,41> SUSP# 3 4
2 2 2 2 2 SHDN BYP 2.2U_0805_16V4Z
G9191-475T1U_SOT23-5 1 2
1U_0603_10V4Z 0.1U_0402_16V4Z C732
1 1
0.1U_0402_16V4Z
2

U27

9 47 EAPD_CODEC
+3VDD_CODEC DVDD_CORE* EAPD/ SPDIF OUT 0 or 1 / GPIO 0 EAPD_CODEC <33>
1 2 DMIC_DAT <17>
DVDD_CORE VOL_UP/DMIC_0/GPIO 1
4
VOL_DN/DMIC_1/GPIO 2
+VDDA_CODEC_R 25 AVDD1*
30
GPIO 3
38 AVDD2**
HDA_BITCLK_CODEC 31
VREFOUT-E / GPIO 4
1

+3VS_HDA 3 43
R525 DVDD_IO GPIO 5
@ 47_0402_5% 32 44
MONO_OUT GPIO 6
45 SPDIF_OUT SPDIF_OUT <35>
2

HDA_BITCLK_CODEC SPDIF OUT1 / GPIO 7

1 <20> HDA_BITCLK_CODEC 6
BITCLK PAD T21
48
C745 HDA_SDOUT_CODEC SPDIF OUT0
<20> HDA_SDOUT_CODEC 5 SDO
@ 33P_0402_50V8K
2 R522 1
<20> HDA_SDIN0 2 33_0402_5% 8
SDI_CODEC VREFOUT_B
28 VREFOUT_B <29>
2 HD A_SYNC_CODEC VREFOUT-B 2
<20> HDA_SYNC_CODEC 10 SYNC
29 +VDDA_CODEC_R
HDA_RST#_CODEC VREFOUT-C
<20> HDA_RST#_CODEC 11
RESET# R548 5.1K_0402_1%
1 2
<17> DMIC_CLK R569 1 2 20K_0402_1% EXTMIC_DET# <29>
RP@ 22_0402_5% 13 SENSE R571 1 2 39.2K_0402_1%
SENSE_A JACK_DET# <29,35>
<33> EC_BEEP R563 1 2 @ 47K_0402_5% R230 1 2 46 R570 1 2 10K_0402_1% INTMIC_DET# <29>
DMIC_CLK C951 0.1U_0402_16V4Z
1 2
R524 1 2 47K_0402_5% 2 1 33 41 HP_OUTR
<20> SB_SPKR HP_OUTR <29>
C913 1U_0603_10V4Z CAP2 PORTA_R
HP Jack & Dock
R523 1 2 10K_0402_5% 1 2 MONO_INR 12 PCBEEP 39 HP_OUTL
PORTA_L HP_OUTL <29>
0.1U_0402_16V4Z
C956 1 2 0.1U_0402_16V4Z C955
22 MIC_EXTR 1 2
PORTB_R MIC_EXT_R <29>
40 C981 1U_0603_10V6K Jack MIC
R982 1 NC / OTP MIC_EXTL
+VDDA_CODEC_R 2 5.1K_0402_1% 21 1 2 PRM@ C983 0.022U_0603_25V7K MIC_EXT_L <29>
RP@R910 1 SENSEB# PORTB_L
<35> SENSE_B# 2 39.2K_0402_1% 34 C982 1U_0603_10V6K 1 2 MIC_IN_R <29>
SENSE_B / NC
1

1
RP@ C979 37 24 MIC_INR
NC PORTC_R RM@
0.1U_0402_16V4Z 18 23 MIC_INL R911 Internal MIC
2 NC PORTC_L 0_0603_5%
19 PRM@ C984 0.022U_0603_25V7K

2
NC LINE_OUT_R
36 LINE_OUT_R <29> 1 2 1 2 MIC_IN_L <29>
PORTD_R PR@R422 0_0603_5%
20
NC LINE_OUT_L
PORTD_L
35 LINE_OUT_L <29> Internal SPKR.
10U_0805_10V4Z
C744 1 2 VC_REFA 27 15 DOCK_MICR 1 2
VREFFILT PORTE_R DOCK_MIC_R <35>
RP@C985 1U_0603_10V6K DOCK MIC
26 14 DOCK_MICL 1 2
AVSS1* PORTE_L DOCK_MIC_L <35>
RP@C986 1U_0603_10V6K
3 3
42 AVSS2**
PORTF_R 17
7
DVSS**
PORTF_L 16

92HD71B7X5NLGXA1X8_QFN48_7X7

@ C746
1 2
0.1U_0402_16V4Z

@ C747
1 2
0.1U_0402_16V4Z

@ C748
SENSE A SENSE B 1 2
0.1U_0402_16V4Z

Port Resistor Port Resistor @ C749

1 2
0.1U_0402_16V4Z Use an 80mil to
4
A 39.2K E 39.2K @ R1006 connection or place 4
1
0_0402_5%
2 a 1206 resistor under
CODEC with double
B 20K F 20K @R195
1 2
vias.
0_0805_5%

C 10K G 10K R198 Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 GNDA <29> Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
0_1206_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio Codec-IDT9271B7
D 5.11K H 5.11K Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
GND GNDA DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 28 of 56
A B C D E
 A B C D E

+5VAMP +5VS
R594 SPEAKER
0.1U_0402_16V4Z 1 2
0_1206_5% JP20
GAIN0 GAIN1 Av(inv) SPKR- 1
1 1 1 1
C766 C767 C1051 SPKR+ 2
10U_0805_10V4Z SPKL- 2
3 3
0 0 6dB SPKL+ 4
2 2 2 4
+5VS 5
1 1 1 1 GND1
0.1U_0402_16V4Z 0 1 10dB 6 GND2
15.6dB C760 C761 C762 C763
CONN@ E&T_3806-F04N-02R
1 2 2 2 2 1
1 0 15.6dB
100P_0402_50V8J

16
15
6

1
U28 100P_0402_50V8J
1 1 21.6dB 100P_0402_50V8J 100P_0402_50V8J

PVDD1
PVDD2
VDD
R1000 R1001
@ 100K_0402_5% 100K_0402_5%

2
C1049 1 2 0.022U_0603_25V7K 7 2
RIN+ GAIN0
1 2
C1052 47P_0402_50V8J 3
R1002 GAIN1

1
2 1 C1050 1 2 0.022U_0603_25V7K 17
<28> LINE_OUT_R RIN- SPKR+
1 2 ROUT+ 18
0_0402_5% C1053 47P_0402_50V8J R1003 R1004
@ 100K_0402_5%
14 SPKR-

2
C1040 ROUT-
1 2 0.022U_0603_25V7K 9 LIN+
1 2 100K_0402_5%
C1054 47P_0402_50V8J 4 SPKL+
R1005 LOUT+ +VDDA_CODEC
2 1 C1041 1 2 0.022U_0603_25V7K 5 PRM@ C743
<28> LINE_OUT_L LIN- SPKL- R906 1U_0603_10V4Z
1 2 8
0_0402_5% C1055 47P_0402_50V8J LOUT-
2 1 1 2
+VDDA_CODEC INTMIC IN

1
PRM@1K_0402_5%

1
MIC_IN_L R905
PRM@R904 PR@ R951
12 MIC_IN_R 4.7K_0402_5% 4.7K_0402_5% PR@
NC 100K_0402_5%

2
THERMAL PAD
10 JP42

2
EC_MUTE# BYPASS
19 SHUTDOWN 1 1
<33> EC_MUTE#

2
1 Keep 10 mil width MIC_IN_L 2 2
<28> MIC_IN_L
MIC_IN_R 3 3
<28> MIC_IN_R

GND1
GND2
GND3
GND4
2 C1044 2
4 4
1U_0805_50V4Z PRM@ D61 2 1
2 +3VS
PSOT24C_SOT23-3 PRM@ R955 10K_0402_5% 5
GND1
<33> ANA_MIC_DET 6
20
13
11
1

21

1
GND2

1
TPA6017A2_TSSOP20 D ACES_88231-04001
PR@Q151 2 CONN@
<28> INTMIC_DET# 2N7002_SOT23-3 G

1
D
S

3
PR@Q160 2 R103
G 10K_0402_5%
2N7002_SOT23-3 S PA@ 9/20 SP02000H700/SP02000H900

2
R909 Close to CODEC U27
<28> VREFOUT_B 2 1 C742 1 2
0_0402_5%
1U_0603_10V4Z
1

R907 R908 @

4.7K_0402_5% 4.7K_0402_5% R125

2 1 GNDA_DOCK_2
GNDA_DOCK_2 <35> Audio/B & CIR
2

0_0402_5%

MIC_EXT_R
<28> MIC_EXT_R
RP@R977 0_0603_5% R126 JP43
<28> MIC_EXT_L
MIC_EXT_L EXTMIC IN 1 2 GNDA_DOCK 2 1 GNDA_DOCK_1
GNDA_DOCK_1 <35>
MIC_EXT_R 1
0_0402_5% MIC_EXT_L 1
2
2
3
HP_OUT_R 3
4
HP_OUT_L 4
5
3 Close to CODEC U27 5 3
6 6
EXTMIC_DET# 7
B+ <28> EXTMIC_DET# HP_DET# 7
<28,35> JACK_DET# 8
8
9 9
10
CIR_IN 10
<33,35> CIR_IN 11
11
1

+3VALW +3VALW RP@ 12

+5VL 12
1

D R975 13
330K_0402_5% 13
2 14
14
2

RP@ RP@ G RP@

RM@ R973 R974 S Q161 CONN@ ACES_87213-1400G
3

R414 10K_0402_5% 10K_0402_5% 2N7002_SOT23-3

0_0402_5%
3
1

6 1

RP@ 9/20 SP02000H800

2N7002DW-7-F_SOT363-6
RP@ 5
Q145B
HP_DET# 2N7002DW-7-F_SOT363-6
2
4

Q145A
1

Q147A Q148A RP@

C775 150U_Y_6.3VM RP@R968
DOCK_LOUT_R DOCK_LOUT_CR_R 2 DOCK_LOUT_C_R
+

<28> HP_OUTR 6 1 1 6 1 2 1 DOCK_LOUT_C_R <35>

60.4_0603_1%
RP@2N7002DW-7-F_SOT363-6 RP@2N7002DW-7-F_SOT363-6 RP@
C776 150U_Y_6.3VM RP@R969 HP OUT For Docking
DOCK_LOUT_L DOCK_LOUT_CR_L 2 DOCK_LOUT_C_L
+

<28> HP_OUTL 1 2 1 DOCK_LOUT_C_L <35>

5

Q147B 60.4_0603_1%
Q148B
3 4 4 3
RP@2N7002DW-7-F_SOT363-6
4 RP@ 2N7002DW-7-F_SOT363-6 C773 150U_Y_6.3VM 4
HP_OUT_R
+

1 2

C774 150U_Y_6.3VM
HP_OUT_L HP OUT For M/B
+

1 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP & Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 29 of 56
A B C D E
 A B C D E

1 1

ACCELEROMETER

+3VS RP@ +3VS_ACL RP@ +3VS_ACL_IO

D44 R959 0_0603_5%
2 1 1 2

CH751H-40PT_SOD323-2
1 1 RP@
RP@ C1030 C1031

10U_0805_6.3V6M
2 2

0.1U_0402_16V4Z

2 2

SMB_CK_CLK0
SMB_CK_CLK0 <8,9,15,20>
RP@

14
VDDIO absolute man U63
0011101b

SCL / SPC
rating is VDD+0.1
1 13 SMB_CK_DAT0
+3VS_ACL_IO Vdd_IO SDA / SDI / SDO SMB_CK_DAT0 <8,9,15,20>
RP@
R997 2 12 RP@ R998
0_0402_5% GND SDO 0_0402_5%
1 2 3 11 1 2
Reserved Reserved
4 GND GND 10

5 9 HDD_HALTLED <34>
GND INT 2

+3VS_ACL 6 8 ACCEL_INT <19>

Vdd INT 1

CS
LIS302DLTR_LGA14_3x5

7
3 RP@ 3
2 1
R999 10K_0402_5%

L Must be placed in the center of the system.

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Accelerometer
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 30 of 56
A B C D E
 A B C D E

Left side USB CONNECTOR Right side USB 0&1 Board Conn
Max 0.5A JP47
Max 2.5A D11 +USB_VCCA
+5VALW 1
+5VALW +USB_VCCA USB20_P2_R L51 JESAT 1
+USB_VCCA 4 VIN IO1 2 2 2
4 3 1 USB 3
<20> USB20_N2 4 3 VBUS 3
U40 USB20_N2_R 3 1 USB20_N2_R 2 USB_EN# 4
1 IO2 GND USB20_P2_R D- <33> USB_EN# 4 1
1 GND OUT 8 W=100mils 3 D+ <20> USB20_N0 5 5
2 7 @ PRTR5V0U2X_SOT143-4 <20> USB20_P2 1 2 4 6
IN OUT 1 2 GND <20> USB20_P0 6

1000P_0402_50V7K
150U_D_6.3VM

0.1U_0402_16V4Z

0.1U_0402_16V4Z
3 IN OUT 6 1 D12 7 7
1 4 5 1 1 1 WCM-2012-900T_4P 5 8
EN# OC# GND <20> USB20_N1 8

C789

C790

C791

C1121
C788 + 4 2 SATA_TXP2 SATA_TXP2 6 9
+USB_VCCA VIN IO1 <21> SATA_TXP2 A+ <20> USB20_P1 9
TPS2061IDGN_MSOP8~N <21> SATA_TXN2 SATA_TXN2 7 ESATA 10
4.7U_0805_10V4Z SATA_TXN2 A- 10
3 1 8
2 2 2 2 2 IO2 GND GND +5VALW
<21> SATA_RXN2_C C792 1 2 1000P_0402_50V7KSATA_RXN2 9 B-
@ PRTR5V0U2X_SOT143-4 <21> SATA_RXP2_C C793 1 2 1000P_0402_50V7KSATA_RXP2 10 B+
11 1 11
GND GND1
12 GND2
USB_EN# 12 C1109
GND 820P_0402_25V7K ACES_87213-1000G
13 GND
14 2 9/20 SP02000DX00
GND
15 CONN@
GND
CONN@ TYCO_1759576-1

JST_SM06B-XSRK-ETB(HF)
GND 8
GND 7
6 6
5 5 +3VAUX_BT
2 4 4 USB20_P6 2
3 3 USB20_N6
2 2 BT_LED
1 1
Finger printer BT Connector CONN@ JP55

CONN@ JP32
10
GND2
GND1 9
8 +3VAUX_BT
+3VALW Q31 @ SI2301BDS-T1-E3_SOT23-3 +3VS 8
7 7
R581 6 USB20_P6
6 USB20_P6 <20>
S

+3VS_FB USB20_N6
D

3 1 1 2 5 5 USB20_N6 <20>
1 0_0603_5% 4 BT_LED
4 BT_LED <34>
C832 3 @ R517 1 2 1K_0402_5%
0.1U_0402_16V4Z 3 @ R518 1 1K_0402_5% CH_DATA <26>
2 2
G

CH_CLK <26>
2

USB_EN# 2
1
2 JP39 1
D16
1 ACES 87213-0800G
USB20_N7 1 USB20_P6
<20> USB20_N7 2 2 +3VAUX_BT 4 VIN IO1 2
USB20_P7 3
<20> USB20_P7 3
4 9/20 SP02000HC00/SP02000HB00 USB20_N6 3 1
4 IO2 GND
5
5 @ PRTR5V0U2X_SOT143-4
6
@ D21 6
7
+3VS_FB USB20_P7 GND +3VS +3VAUX_BT
4 VIN 2 8
IO1 GND Q24 SI2301BDS-T1-E3_SOT23-3
USB20_N7 3 1 ACES_85201-06051
IO2 GND 0.1U_0402_16V4Z

S
CONN@

D
3 1
PRTR5V0U2X_SOT143-4 9/20 SP01000B000

G
1 1 1 1

2
3 C798 R519 C799 C800 C801 3

1U_0603_10V4Z 100K_0402_5%
2 2 2 2

2
0.01U_0402_16V7K 4.7U_0805_10V4Z
R520

<21> BT_OFF 1 2 1 2
10K_0402_5% C802 0.1U_0402_16V4Z

Check BT power consumption < 1A

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB, BT, eSATA,FPR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 31 of 56
A B C D E
 A B C D E

Ripely 2.0 will support 16Mb SPI ROM

+3VL

SPI Flash (16Mb*1) 1 20mils CONN@

SA00001IT00 C484 U29 45@ &U29
+3VL +3VAL 8 4
0.1U_0402_16V4Z VCC VSS
1 2
@ R995 0_0402_5% 2 3
+3VALW W
1 2 7
HOLD

1
R996 0_0402_5% 1 SA00001IT00
1 C803 SPI_CS# INT_SPI_CS# 1
<33> SPI_CS# 1 2 1 S
R521 R221 0_0402_5%
0.1U_0402_16V4Z 100K_0402_5% 1 2 SPI_CLK_R 6
2 <33> SPI_CLK C
U31 R227 0_0402_5%

2
8 1 <33> EC_SO_SPI_SI 2 1 EC_SO_SPI_SI_R 5 2 EC_SI_SPI_SO_R 2 1 EC_SI_SPI_SO <33>
VCC A0 R229 0_0402_5% D Q R223 0_0402_5%
7 WP A1 2
<6,33,34,37> SMB_EC_CK1 6 3 WIESON G6179 8P SPI
SCL A2
<6,33,34,37> SMB_EC_DA1 5 SDA GND 4
L Need add back R221 if no ext BIOS design U30 install.
@ AT24C16AN-10SI-2.7_SO8

1
R526
100K_0402_5%

2
2 2

3
LPC Debug Port 3

H31
+3VALW

6 5 LPC_DRQ#
LPC_DRQ# <19>

SIRQ 7 4 PLT_RST#
<19,33> SIRQ PLT_RST# <11,14,19,25,26,27,33>

LPC_AD3 8 3 LPC_AD2
<19,33> LPC_AD3 LPC_AD2 <19,33>

LPC_AD1 9 2 LPC_AD0
<19,33> LPC_AD1 LPC_AD0 <19,33>

LPC_FRAME# 10 1 CLK_PCI_SIO
<19,33> LPC_FRAME# CLK_PCI_SIO <19>
2

@ DEBUG_PAD @ R232
9/20 ?????? 22_0402_5%
1

2
@ C486
22P_0402_50V8J
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS ROM/Debug Tool
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 32 of 56
A B C D E
 A B C D E

Keyboard Connector For EMI

JP33
+3VL_EC KSO15 1 KSO15 @ C213 1 2 100P_0402_25V8K
KSO10 1 KSO10 @ C609 100P_0402_25V8K
2 1 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K KSO11 2 KSO11 @ C754 100P_0402_25V8K
3 3 1 2
+3VL KSO14 4 KSO14 @ C756 1 2 100P_0402_25V8K
1 1 1 1 1 4
1 KSO13 5 KSO13 @ C757 1 2 100P_0402_25V8K
C805 C806 C807 C808 C809 +3VL +3VL_EC +EC_AVCC KSO12 5 KSO12 @ C758 100P_0402_25V8K
6 6 1 2
+ C1105 KSO3 7 KSO3 @ C759 1 2 100P_0402_25V8K
2 2 2 2 2 R527 22U_A_4VM KSO6 7 KSO6 @ C764 100P_0402_25V8K
8 8 1 2
0.1U_0402_16V4Z 1000P_0402_50V7K 1 2 @ KSO8 9 KSO8 @ C768 1 2 100P_0402_25V8K
0_0805_5% 2 KSO7 9 KSO7 @ C769 100P_0402_25V8K
10 10 1 2
KSO4 11 KSO4 @ C822 1 2 100P_0402_25V8K
KSO2 11 KSO2 @ C823 100P_0402_25V8K
12 12 1 2

111
125
1 KSI0 KSI0 @ C824 100P_0402_25V8K 1
1/19 Change EC P/N to D3 version

22
33
96

67
13 13 1 2

9
U33 KSO1 14 KSO1 @ C825 1 2 100P_0402_25V8K
KSO5 14 KSO5 @ C826 100P_0402_25V8K
15 1 2

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
KSI3 15 KSI3 @ C875 100P_0402_25V8K
16 1 2
KSI2 16 KSI2 @ C876 100P_0402_25V8K
17 1 2
KSO0 17 KSO0 @ C877 100P_0402_25V8K
18 18 1 2
GATEA20 1 21 EC_PWM KSI5 19 KSI5 @ C878 1 2 100P_0402_25V8K
<20> GATEA20 KB_RST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F FAN_PWM EC_PWM <17> KSI4 19 KSI4
2 23 20 @ C884 1 2 100P_0402_25V8K
<20> KB_RST# SIRQ KBRST#/GPIO01 BEEP#/PWM2/GPIO10 EC_BEEP FAN_PWM <4> KSO9 20 KSO9
3 26 21 @ C885 1 2 100P_0402_25V8K
<19,32> SIRQ SERIRQ# FANPWM1/GPIO12 EC_BEEP <28> 21
LPC_LFRAME# 4 27 ACOFF KSI6 22 KSI6 @ C886 1 2 100P_0402_25V8K
<19,32> LPC_FRAME# LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <38> KSI7 22 KSI7
C810 R530 <19,32> LPC_AD3 5 0.01U_0402_16V7K 23 @ C887 1 2 100P_0402_25V8K
LPC_AD2 LAD3 ECAGND KSI1 23 KSI1
1 2 1 2 <19,32> LPC_AD2 7
LAD2 PWM Output C812 1 2 24
24
@ C888 1 2 100P_0402_25V8K
@ 33_0402_5% <19,32> LPC_AD1 LPC_AD1 8 63 BATT_TEMP
LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <37>
LPC_AD0 BATT_OVP
LAD0 LPC & MISC
@ 15P_0402_50V8J <19,32> LPC_AD0 10 64 BATT_OVP <37>
BATT_OVP/AD1/GPIO39
65 ADP_I <38>
CLK_PCI_EC ADP_I/AD2/GPIO3A
<19,23> CLK_PCI_EC 12
PCICLK AD Input AD3/GPIO3B
66 ADP_ID <37> 25
GND1
PLT_RST# 13 75 TP_BTN# 26
<11,14,19,25,26,27,32> PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 TP_BTN# <34> GND2
R533 1 2 ECRST# 37 76
+3VL_EC ECRST# SELIO2#/AD5/GPIO43 ANA_MIC_DET <29>
47K_0402_5% EC_SCI# 20 ACES_85201-24051
<20> EC_SCI# SCI#/GPIO0E
<20,23> HDARST# 38 CONN@
CLKRUN#/GPIO1D
68 DAC_BRIG <17>
C811 DAC_BRIG/DA0/GPIO3C 9/20 SP01000FF00/SP01000G300
2 1 70 VCTRL <38>
EN_DFAN1/DA1/GPIO3D IR EF +5VS_LED
0.1U_0402_16V4Z DA Output IREF/DA2/GPIO3E 71 IREF <38>
KSI0 55 72
KSI1 56
KSI0/GPIO30 DA3/GPIO3F AC_SET <38> KB Back Light Conn
KSI1/GPIO31

1
KSI2 57
KSI3 KSI2/GPIO32 R516
02/22 Add R1076, C1104 and R1077 for EMI request. KSI4
58
59
KSI3/GPIO33 PSCLK1/GPIO4A
83
84
EC_MUTE# <29>
KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# <31>
KSI5 60 85 I2C_INT <34> 150_0603_1%
+3VL_EC KSI6 KSI5/GPIO35 PSCLK2/GPIO4C
61 PS2 Interface 86 MUTE_LED <35> JP48

2
KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK
62 87 TP_CLK <34> 1
R1076 0_0402_5% KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA 1
39 88 TP_DATA <34> 2
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 2
1

2 ESB_CLK 2
<34> ESB_CLK 1 2 EC_CLK KSO1 40 KSO1/GPIO21 5 G1 3 3
R538 <34> ESB_DAT ESB_DAT 1 2 EC_DAT KSO2 41 6 4
10K_0402_5% R1077 0_0402_5% KSO3 KSO2/GPIO22 G2 4
42 97 AC_LED# <37>
KSO4 KSO3/GPIO23 SDICS#/GPXOA00 ACES_85201-04051
1 43 KSO4/GPIO24 SDICLK/GPXOA01 98 DOCK_VOL_UP# <35>
KSO5 44 KSO5/GPIO25 Int. K/B 99 DOCK_VOL_DWN# <35> CONN@
2

@ C1104 KSO6 SDIDO/GPXOA02

45 109
LID_SW# 33P_0402_50V8K KSO7 KSO6/GPIO26 Matrix SDIDI/GPXID0 VGATE <43>
9/20 SP01000KC00/SP010009O10
2
46 KSO7/GPIO27 SPI Device Interface 1 2
KSO8 47 R1044 100K_0402_5%
KSO9 KSO8/GPIO28 +3VS
48 KSO9/GPIO29 SPIDI/RD# 119 EC_SI_SPI_SO <32>
+3VL KSO10 49 120
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI <32>
Please close to EC. KSO11 50 SPI Flash ROM SPICLK/GPIO58 126 R589
4.7K_0402_5% L KSO12 51
KSO11/GPIO2B
KSO12/GPIO2C SPICS#
128
SPI_CLK <32>
SPI_CS# <32>
+5VL 10K_0402_5%
R528 2 1 SMB_EC_DA1 KSO13 52 KSO13/GPIO2D
DOCK_VOL_UP# 2 1
4.7K_0402_5% KSO14 53 R46 1 2 10K_0402_5%
+3VS KSO14/GPIO2E
R529 2 1 SMB_EC_CK1 KSO15 54 73 CIR_IN
CIR_IN <29,35>
DOCK_VOL_DWN# 2 1
4.7K_0402_5% KSO16 KSO15/GPIO2F CIR_RX/GPIO40 NB_OTP R590
81 74 NB_OTP <37>
KSO16/GPIO48 CIR_RLC_TX/GPIO41
R531 2 1 SMB_EC_DA2 KSO17 82 89 FSTCHG
FSTCHG <38>
10K_0402_5%
4.7K_0402_5% KSO17/GPIO49 FSTCHG/SELIO#/GPIO50
90 STD_ADP <38>
BATT_CHGI_LED#/GPIO52
R532 2 1 SMB_EC_CK2 91 CAPS_LED# <34>
SMB_EC_CK1 CAPS_LED#/GPIO53 BAT_LED#
10K_0402_5% <6,32,34,37> SMB_EC_CK1 77 SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 BAT_LED# <34>
R513 1 2 WL_BLUE_BTN <6,32,34,37> SMB_EC_DA1
SMB_EC_DA1 78 93 ON/OFFBTN_LED#
ON/OFFBTN_LED# <34> 2 1
SMB_EC_CK2 SDA1/GPIO45 SUSP_LED#/GPIO55 SYSON
<6> SMB_EC_CK2 79
SCL2/GPIO46 S M Bus SYSON/GPIO56
95
SYSON <26,36,40>
R541 10K_0402_5%
<6> SMB_EC_DA2 SMB_EC_DA2 80 121 VR_ON R534 +5V_TP
SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <43>
127 AC_IN_EC 2 1 10K_0402_5%
AC_IN/GPIO59 AC_IN <21,38> TP_CLK
D54 1 2
CH751H-40PT_SOD323-2 R535
SLP_S3# 6 100 EC_RSMRST# 2 1 10K_0402_5%
+3VL <20> SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <20> +3VL_EC
SLP_S5# 14 101 R1040 TP_DATA 1 2
<20> SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <20>
R514 4.7K_0402_5% EC_SMI# 15 102 150K_0402_5%
<20> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <36,39>
1 2 EC_CLK <34> LID_SW#
LID_SW# 16 103 WL_BLUE_LED# <34> 1 2
+3VL_EC EC_CLK LID_SW#/GPIO0A EC_SWI#/GPXO06 SB_PWRGD C1073
17 104
SUSP#/GPIO0B ICH_PWROK/GPXO06 SB_PWRGD <6,20,43>
2 1 EC_DAT EC_DAT 18 G PO 105 BKOFF# 100P_0402_50V8J
3 WL_BLUE_BTN PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# <17> 3
R515 4.7K_0402_5% <34> WL_BLUE_BTN 19 EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09 106
WWAN_POWER_OFF <26>
2

H_THERMTRIP#_EC 25 107 TP_LED#

<6> H_THERMTRIP#_EC EC_THERM#/GPIO11 GPXO10 TP_LED# <34>
R543 28 108 TP_LED#=L, T/P disable SUSP# SYSON
4.7K_0402_5% <36>
<35>
VLDT_EN
CONA#
E51_TXD
29
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
GPXO11 L TP_LED#=float (GPO), T/P enable
30
EC_TX/GPIO16

1
2 1 E51_RXD 31 110 VFIX_EN <43>
1

R1063 10K_0402_5% ON /OFF# EC_RX/GPIO17 PM_SLP_S4#/GPXID1 R536 R539

<34> ON/OFF# 32 112 ENBKL <11>
ON_OFF/GPIO18 ENBKL/GPXID2 100K_0402_5% 100K_0402_5%
<36> DIM_LED 34 114 EAPD_CODEC <28>
PWR_LED#/GPIO19 GPXID3
<35> DOCK_SLP_BTN# 1 2 <34> NUM_LED# 36
NUMLED#/GPIO1A GPI GPXID4
115 EC_THERM# <21>
R542 0_0402_5% 116 SUSP#
R547

2
C813 GPXID5 PWRBTN_OUT# SUSP# <26,28,36,38,41>
RP@ GPXID6 117 PWRBTN_OUT# <20>
15P_0402_50V8J 118 NMI_DBG# 1 2
C R Y2 GPXID7 PCI_SERR# <19>
1 2 122 XCLK1
123 124 2 1 0_0402_5%
XCLK0 V18R C814 4.7U_0805_10V4Z
1

AGND

Y7
GND
GND
GND
GND
GND

@
3
NC OUT
4
R545 Need 4.7uf for 926 C version +3VS
2 1 20M_0402_5% KB926QFC0_LQFP128_14X14 R1050
11
24
35
94
113

69

NC IN TP_BTN# 1 2
2

32.768KHZ_12.5PF_Q13MC30610003 10K_0402_5%

1 2 C R Y1
+3VL_EC
C815
ECAGND

15P_0402_50V8J
1

+EC_AVCC L80
0_0603_5%
R544
L81
2

LAN_POWER_OFF 1 2 E51_RXD 1 2 1 2
4 <25> LAN_POWER_OFF 4
C816 0.1U_0402_16V4Z 0_0603_5%
EC DEBUG port 0_0402_5%

02/15 Remove JP34 and

reserve R1068 for EC debug.
@ R1068

E51_TXD
Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

0_0603_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC KB926/KB conn
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 33 of 56
A B C D E
 A B C D E

ON/OFF Button Connector TP ON/OFF Max 0.5A

TP_DATA
TP_CLK
+3VALW M/B TO TP/B +5V_TP

2
1

1
+5VALW_LED
C819 D31
02/22 Reserve for EMI request.
JP1 R1038 0.1U_0402_16V4Z PSOT24C_SOT23-3
SW1 @ 10K_0402_5% 2
1

1
ON /OFF# 1 SMT1-05-A_4P JP37
<33> ON/OFF# 2

2
ON/OFFBTN_LED# 3 2 TP_BTN#
<33> ON/OFFBTN_LED# 3 G1 5 3 1 TP_BTN# <33> 1 1
4 6 2 TP_CLK TP_CLK <33>
4 G2 2 TP_DATA
4 2 5 G1 3 3 TP_DATA <33>
1 ACES_85201-04051 RP@R1074 RP@C1102 1
6 G2 4 4
CONN@ ESB_CLK1 2 1 2 1

5
6
ACES_85201-04051 0_0402_5%
CONN@ 1 1 33P_0402_50V8J
9/20
SP01000KC00/SP01E000900
9/20 SP01000J100 @ C820 @ C821 @ R1075 @ C1103
MDC 1.5 Conn. 9/20 STANDOFF (H= 5.0 mm) ES000000800 Max 0.5A 100P_0402_50V8J 2 2 100P_0402_50V8J ESB_DAT1 2 1 2 1
47_0402_5%
+5VALW R235 0_0603_5% +5V_TP 33P_0402_50V8K
1 2
L Please close to JP36

S
JP25 3 1

D
<20> HDA_SDOUT_MDC
1
3
1
3
2
4
2
4
+3VS
@ Q85 SWITCH BOARD.
5 6 SI2301BDS-T1-E3_SOT23-3

G
+3VS

2
5 6 +3VL_CAP +5VALW_LED
<20> HDA_SYNC_MDC 7 8
7 8
<20> HDA_SDIN1 1 R495 2HDA_SDIN1_MDC 9 9 10 10
<20> HDA_RST#_MDC 33_0402_5% 11 12 HDA_BITCLK_MDC <20>
11 12

1
+3VS R554 R555

GND
GND
GND
GND
GND
GND

2
ON/OFFBTN_LED# R1065 1 2 RM@ 0_0402_5% EC_CK1
<35,36,42> SYSON# ON /OFF# EC_DA1
R496 R1066 1 2 RM@ 0_0402_5% RP@ 0_0603_5% RM@ 0_0603_5%
ACES_88020-12101 13 @ 10_0402_5%
14
15
16
17
18

2
1 1 1 CONN@
+5VS_LED

1
C780 1 R1034 1 2 RM@ 0_0402_5% +3VL_R
<33> WL_BLUE_BTN

0.1U_0402_16V4Z
C778 C779 @4.7U_0805_10V4Z C777 WL_BLUE_LED# R1035 1 2 RM@ 0_0402_5%
2 2 2

4.7U_0603_6.3V6K
C256 JP36 1 1
@ 10P_0402_50V8J 0.1U_0402_16V4Z 1
2 1

C1098

C257
1000P_0402_50V7K 1 2 2
2 0.1U_0402_16V4Z R1046 1 EC_CK1 2 2
<6,32,33,37> SMB_EC_CK1 2 RP@ 0_0402_5% 3 3
R1048 1 2 RP@47_0402_5% ESB_CLK1 4 2 2
<33> ESB_CLK 4
R1049 1 2 RP@47_0402_5% ESB_DAT1 5
<33> ESB_DAT 5
<33> I2C_INT I2C_INT 6 6
7 7
<33> NUM_LED# 8
8

：
<6,32,33,37> SMB_EC_DA1 1 2 EC_DA1 9 9

0.047U_0402_16V7K
R1047 0_0402_5% 10
TouchPAD ON/OFF LED
：ESB
10

0.1U_0402_16V4Z
0.047U_0402_16V7K
ENE RP@ 1 11 GND

RP@ C1119
12
HDD/G-Sensor LED +5VS_LED CY S MB_EC GND

RP@C255
+5VS_LED +3VS

RP@C254
ACES_85201-1005N
I2C_INT 2 CONN@
+3VL 2 1

1
RM@R558 10K_0402_5% 9/20 SP01000H400
R984 R983
1

+5VS 200_0402_5% 200_0402_5%

R987 R988
RP@

2
200_0402_5% 200_0402_5% HT-297UY5/BP5_YELLOW-WHITE
1

+5VS
2

R20

2
PA@ PRM@ +3VL 1 2 +3VL_CAP
3

10K_0402_5% D17 D19

YELLOW

WHITE

YELLOW

WHITE
Q7B D18 @ R985 @ PJP605
2

PAD-OPEN 2x2m
WHITE

YELLOW

5 HT-297UY5/BP5_YELLOW-WHITE 10K_0402_5%
2

1
6

HT-297UY5/BP5_YELLOW-WHITE
4

Q7A 1 2 HDD_HALTLED# <21>

RP@R42
1

2N7002DW-7-F_SOT363-6 D 0_0402_5% D
<21> SATA_LED# 2
Q156 2 2 TP_LED#
3 HDD_HALTLED <30> TP_LED# <33> 3
2N7002DW-7-F_SOT363-6 G G
1

@ 2N7002_SOT23-3S Q153 S
3

2N7002_SOT23-3 T/P Enable (TP_LED#=L)-> White

T/P Disable (TP_LED#=X)-> Amber
11/11 Del reserved LDO for ENE cap board

Battery Charge LED WLAN and BT LED inform pin to KBC

WHITE +5VALW_LED
+3VS
R989
D6 R1041
1 2 1 R550 2 1 2 2 1 +3VS
<33> BAT_LED# 200_0402_5% @ 10K_0402_5%
HT-F196BP5_WHITE 47K_0402_5% Reed switch BOARD.
WL_BLUE_LED# 2 1 WL/WW_LED# 1 2 +3VL
CAPS LOCK LED <33> WL_BLUE_LED#
D57 R1007 0_0402_5%
WL_LED# <26>
JP40
CH751H-40PT_SOD323-2 1 1
1

+5VS_LED D
WHITE Q55 1 2 WW_LED# <26>
<33> LID_SW# 2
2
2N7002_SOT23-3 2 PA@R1008 0_0402_5% 3 5
D7 R552 G 3 G1
4 6
4 G2
1 2 1 2 S
3

<33> CAPS_LED# ACES_85201-04051

BT_LED <31>
HT-F196BP5_WHITE 470_0402_5% CONN@

POWER LED 1 1
1

WHITE +5VALW_LED R1025 C1100 C1101

4 0.1U_0402_16V4Z 10P_0402_50V8J 4
D8 100K_0402_5% 2 2
ON/OFFBTN_LED# 1 2 1 R549 2
2

200_0402_5%
HT-F196BP5_WHITE

White LED: VF=3V, IF = 10mA, Res = 200 ohm

Amber LED: VF=1.8V, IF = 8mA, Res = 390 ohm Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TP,MDC,ON/OFF,S/W,LED,Reed
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 34 of 56
A B C D E
 A B C D E

Atlas/ Saturn Dock

+DOCKVIN

JDOCK

<16> RED_L 38 CRT_Red Digital gnd 39

1 40 37 TV_LUMA_L
<16> GREEN_L CRT_Green TV Luma TV_CRMA_L PAD T51
RP@ 34 35
<16> BLUE_L D_DDCDATA CRT_Blue TV chroma TV_COMPS_L PAD T52
C831 36 33
1000P_0402_50V7K <16> D_DDCDATA DDC_DATA TV composite PAD T53
D_DDCCLK 30 31
1 2 <16> D_DDCCLK D_HSYNC DDC_Clock TV ground CIR_IN 1
<16> D_HSYNC 32 Hsync CIR input 29 CIR_IN <29,33>
D_VSYNC 26 27 DOCK_PWR_ON
<16> D_VSYNC USB20_N3 Vsync PWR_ON MUTELED
<20> USB20_N3 28 USB- Mute_LED 25 1 2 MUTE_LED <33>
USB20_P3 22 23 DOCK_SLP_BTN# RP@ R591 1K_0402_5% DOCK_SLP_BTN# <33>
<20> USB20_P3 USB+ Sleep Botton JACK_DET#
24 21 JACK_DET# <28,29>
Digital gnd Jack Detect R_VOL_UP# RP@ R567 1 DOCK_VOL_UP#
18 MDI3- VOL_up 19 2 200_0402_5% DOCK_VOL_UP# <33>
20 17 R_VOL_DWN# RP@ R568 1 2 200_0402_5% DOCK_VOL_DWN#
MDI3+ VOL_down DOCK_VOL_DWN# <33>
14 15 SPDIFO_L
MD2I- SPDIF AUDIO_OGND
DOCK_PWR_ON Spec RJ45_MIDI1-
16
10
MDI2+ Audio Output gnd 13
11 DOCK_LOUT_C_R
<25> RJ45_MIDI1- MDI1- Right headphone DOCK_LOUT_C_R <29>
0V = Notebook S4/S5, Dock off <25> RJ45_MIDI1+
RJ45_MIDI1+
RJ45_MIDI0-
12 MDI1+ Left headphone 9 DOCK_LOUT_C_L
DOCK_MIC_R_C
DOCK_LOUT_C_L <29>
<25> RJ45_MIDI0- 6 7
MDI0- Mic_Right
2.5V = Notebook S3, Dock on <25> RJ45_MIDI0+
RJ45_MIDI0+ 8 MDI0+ Mic_Left 5 DOCK_MIC_L_C
+V_BATTERY 2 3 AU DIO_IGND
4V = Notebook S0, Dock on PJP5 4
Battery out Mic gnd
1 DOCK_PRESENT
Battery out Dock_present
1 2 41 +DOCKVIN
B+ GND
42
RP@ RP@ D43 GND
45 GND GND 43
PAD-OPEN 2x2m
+5VS 1 2 2 46 44
R586 1K_0402_5% DOCK_PWR_ON GND GND
1
+3VALW 1 2 3
R585 1K_0402_5% CONN@ FOX_QL1122L-H212AR-9F
RP@ DAN202U_SC70
2
1

D R588
2 10K_0402_5%
03/03 Change JDOCK Footprint
<34,36,42> SYSON#
G RP@
S
3

Q36
2
2N7002_SOT23-3
L R976/Q149/R646 be option with R992/C945 2
RP@
R_VOL_UP# R_VOL_DWN# +1.5VS
SPDIF
1 1

2
RP@ RP@
01/23 Change NMOS type to solve Saturn docking issue C843 C844 R976 R646
1000P_0402_50V7K 1000P_0402_50V7K 1 2
+3VL_EC 2 2 @ 33_0402_5% @ 0_0402_5%

1 1
RP@ RP@
2

C C945 R647
R565 DOCK_LOUT_C_R DOCK_LOUT_C_L Q149 2 1 2 1 2 SPDIF_OUT <28>
10K_0402_5% @ MMBT3904_NL_SOT23-3 B 220_0402_5%

1
1 1 E RP@ 1 0.1U_0402_16V7K
RP@

3
RP@ RP@ R992 C944 R573
1

C942 C943 SPDIFO_L 1 2

CONA# <33>
RP@ 0_0603_5% RP@ 110_0402_5%
2 2 2

2
1

D 220P_0402_50V7K 220P_0402_50V7K 220P_0402_50V7K

DOCK_PRESENT 1 2 2 Q33
R572 22_0402_5% G 2N7002_SOT23-3
RP@ S 1 2 AUDIO_OGND
RP@
3
1

RP@R418 0_0603_5%
R566
2K_0402_5% RP@R417 0_0603_5%
RP@ GNDA_DOCKA 1 2 AU DIO_IGND
MIC_Dock Need 600 Ohm 500 mA
2

R127 R128 RP@ L94

0_0402_5% 0_0402_5% RP@ R942 10K_0402_5% FCM1608KF-601T02_2P
<28> DOCK_MIC_R 2 1 DOCK_MIC_R_R 1 2 DOCK_MIC_R_C
3 H32 H33 H34 H35 H36 @ RP@ R943 10K_0402_5% 3
2

@ H_2P8 @ H_2P8 @ H_2P8 @ H_2P8 @ H_2P8 <28> DOCK_MIC_L 2 1 DOCK_MIC_L_R 1 2 DOCK_MIC_L_C

GNDA_DOCK_1 FCM1608KF-601T02_2P
<29> GNDA_DOCK_1

1
RP@ L93 1 1

1
RP@ R980
1

GNDA_DOCK_2 RP@ R944 1.21K_0402_1%

<29> GNDA_DOCK_2
1.21K_0402_1% RP@ C921 RP@ C922
H37 H39 H40 H41 220P_0402_50V7K 2 2 220P_0402_50V7K

2
@ H_2P8 @ H_2P8 @ H_2P8 @ H_2P8

2
AU DIO_IGND
+3VS
1

H42 H43 H44 H46

2
@ H_2P8 @ H_4P2 @ H_4P2 @ H_4P2
RP@ SENSE_B# <28>
R915

2
R914 10K_0402_5%
1

1
RP@ D

1
10K_0402_5% 2 Q100
H47 H48 G

1
@ H_3P3 @ H_3P3 D 2N7002_SOT23-3
S RP@

3
RP@ Q16 2
H53 H54 H55 RP@ PMBT3904_SOT23 G GNDA_DOCKA

1
@ H_3P3X0P6N @ H_3P3X0P6N @ H_5P6N R912 C S
1

3
DOCK_MIC_L_C 1 2 2 RP@ Close to CODEC U27
10K_0402_5% B Q18

2
H52 2 E 2N7002_SOT23-3
1

2 3
@ H_1P5N
RP@R913 C978
RP@ RP@R415
4 47K_0402_5% 1 4
0_0402_5%
1

1
AU DIO_IGND 1U_0603_10V6K

1
H51 H56 H57
@ H_6P0X5P0N @ H_2P5N @ H_2P8

Security Classification Compal Secret Data Compal Electronics, Inc.

1

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DOCK CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 35 of 56
A B C D E
 A B C D E

DIM LED
+5VALW_LED

R419 0_0603_5%
+5VALW TO +5VS +3VALW TO +3VS 1 2

+3VALW +3VS @ Q32 SI2301BDS-T1-E3_SOT23-3

+5VALW PJP7
+5VS

S
4.7U_0805_10V4Z 1 2 3 1

D
+5VALW
4.7U_0805_10V4Z 1 1 1
1 1 1 Q14 C839 C838 1
PAD-OPEN 2x2m

1
1 Q35 C833 C835 C1110 @ C836 1

G
8 1

2
C1111 D S 0.1U_0603_25V7K @ R587 0.1U_0402_16V4Z
8 D S 1 7 D S 2
7 2 0.1U_0603_25V7K 6 3 2 2 2 10K_0402_5%
D S 2 2 2 D S 2
6 3 5 4
D S D G 1U_0402_6.3V4Z
5 4

2
D G 1U_0402_6.3V4Z SI4800BDY_SO8 RU NON 2 R152 1 B+

0.01U_0402_25V7K
SI4800BDY_SO8 1 1 1 330K_0402_5% DIM_LED#
1 1

1
C1112 D

1
C1113 C864 RU NON 0.1U_0603_25V7K C834 Q17 SUSP D
2
0.1U_0603_25V7K 4.7U_0805_10V4Z 2 2 C840 2 2N7002_SOT23-3
G DIM_LED @ Q51
<33> DIM_LED 2
2 2 S G 2N7002_SOT23-3

3
S

3
4.7U_0805_10V4Z +5VS_LED

@ Q166 SI2301BDS-T1-E3_SOT23-3
PJP8

S
1 2 3 1

D
+5VS

PAD-OPEN 2x2m 1
@ C1069

G
2
0.1U_0402_16V4Z

DIM_LED# 2
+1.8V TO +1.8VS +1.2VALW TO +1.2V_HT
+1.8V +1.8VS
+1.2VALW +1.2V_HT 1 2
R420 0_0603_5%
10U_0805_10V4Z 4.7U_0805_10V4Z
Q4 1 2 1 Q11 1 1 1
2 IRF8113PBF_SO8 C848 C841 IRF8113PBF_SO8 C846 C862 2
8 1 C1114 8 1 C1115
7 2 0.1U_0603_25V7K 7 2 0.1U_0603_25V7K
2 1 2 2 2 2
6 3 6 3
5 5
1U_0402_6.3V4Z 1U_0402_6.3V4Z
1 1 2 R233 1 B+
4

4
1 1 330K_0402_5%

1
C1116 C842 1

1
0.1U_0603_25V7K C1117 C847 C837 R234 D Q12 +5VL
2 2 1.8VS_ENABLE 1 R138 2 0.1U_0603_25V7K 4.7U_0805_10V4Z 2 VLDT_EN#
B+ 2 2
330K_0402_5% 750K_0402_5% G
1

1
1 0.01U_0402_25V7K 2 S 2N7002_SOT23-3

3
1

C849 R137 D R598

4.7U_0805_10V4Z 2 SUSP
750K_0402_5% G 100K_0402_5%
2 S Q13
2

2
0.01U_0402_25V7K 2N7002_SOT23-3

EC_ON#

1
D
2 Q44
<33,39> EC_ON
G 2N7002_SOT23-3
S
Discharge circuit

3
+5VS +1.8VS +1.2V_HT +1.8V +1.2VALW
2

2
3 3
R239 R279 R280 R284
470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5% R368

@ 470_0805_5%
1

1
1

1
D D D D D
SUSP 2 Q46 SUSP 2 Q48 VLDT_EN#2 Q37 SYSON# 2 Q41 EC_ON# 2 Q42
G G G G G
S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3 S @ 2N7002_SOT23-3
3

Change to +3VL(same as EC)

+5VL +5VL to avoid leakage +5VL

1
+3VS +0.9V +1.5VS +1.1VS
R595 R596 R597
2

100K_0402_5% 100K_0402_5% 100K_0402_5%

R288 R292 R293 R294

2
470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5% SYSON# SUSP
<34,35,42> SYSON# SUSP <42>
VLDT_EN#
<13> VLDT_EN#
1

1
1

1
D D D D Q38 D D Q39 D
SUSP 2 Q47 SYSON# 2 Q49 SUSP 2 Q50 SUSP 2 Q52 SYSON 2 2 VLDT_EN 2 Q40
4 <26,33,40> SYSON SUSP# <26,28,33,38,41><33> VLDT_EN 4
G G G G G G G 2N7002_SOT23-3
S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3 2N7002_SOT23-3 S S 2N7002_SOT23-3 S
3

3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuits
FM1 FM2 FM3 CF1 CF2 CF3 Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1 1 1 1 1 1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 36 of 56
A B C D E
 A B C D E

BATT1

45@ CR2032 RTC BATTERY

1 +3VALW 1

PQ3

3
TP0610K-T1-E3_SOT23-3
PR9 +3VL
1 2 BATT
100K_0402_5%

499K_0402_1% 340K_0402_1%
2 AC_LED# <33>

PR1 1
+5VALW

ADP_ID <33>

0.01U_0402_25V7K
2 1

2
PC12

1
PC1
PR8

PR4 1
2K_0402_5% PD4 @1000P_0402_50V7K
PR2

2
10K_0402_5%
PC15 0.1U_0402_16V7K VIN +DOCKVIN

2
1 2
1

2
ACES_88334-057N RLZ3.6B_LL34

8
ADP_SIGNAL 1 2 PR5
5 PR3 3 10K_0402_5%

P
5 10K_0402_5% +
4 4 0 1 2 1 BATT_OVP <33>
3 PL1 PL2 2
3 -

G
105K_0402_1%
2 SMB3025500YA_2P SMB3025500YA_2P
2

PR6 1
0.01U_0402_25V7K
1 ADPIN 1 2 2 1

4
1

1
PU1A
PJP1

PC6
LM358ADT_SO8
100P_0402_50V8J

2
1000P_0402_50V7K

390P_0402_50V7K

2
2

100P_0402_50V8J
820P_0402_50V7K

2200P_0402_50V7K
PD1
1

1
PC5

PC13
2 2
PC14

PC4

PC7
PC3
2

2
PC2

1000P_0402_50V7K
@PJSOT24C_SOT23-3
1

PH1 under CPU botten side :

CPU thermal protection at 95 +-3 degree C
PL3
VMB HCB2012KF-121T50_0805
1 2 BATT
PJP2
8 PR7
8 +5VS
7 604K_0402_1%
7 EC_SMD PD2
6
5
6
5 EC_SMC @SM05_SOT23
1
PL4
2
CPU 1 2

4 3 HCB2012KF-121T50_0805
4
1

1
3 1
3
2 2 2

1
1 PC8 PC9
2

2
1 1000P_0402_50V7K 0.01U_0402_50V4Z PH1
9
GND
10
GND
3

10KB_0603_1%_TH11-3H103FT
SUYIN_200275MR008GXOLZR ENTRIP1 <39>

2
3 PR10 3

8
200K_0402_1%
1

1
D
1 2 5

P
+
1

PD3 7 2 PQ1
1

0 G @SSM3K7002FU_SC70-3
@SM24.TC_SOT23-3 1 2 6
PR14 -

G
PR13 +5VALW PR11 PU1B S
100_0402_5%

3
1
100_0402_5% 150K_0402_1% LM358ADT_SO8
2

4
1

1
2

1
SMB_EC_DA1 PC10 PR12
SMB_EC_DA1 <6,32,33,34> 2.21K_0402_1%
0.22U_0603_10V7K PR15

2
150K_0402_1% PC11

2
SMB_EC_CK1 1000P_0402_50V7K EN0 <6,39>
SMB_EC_CK1 <6,32,33,34>

2
BAT_ID <38>

1
PR18 D
+5VS @47K_0402_1% +3VL 2 PQ2
PR16 1 2 +5VS G SSM3K7002FU_SC70-3
6.49K_0402_1% +3VL S

3
1 2 +5VALW

@100K_0402_5%
1

2
@0.01U_0402_25V7K
1

PR24
1

PR17 PH2
1
PC18

1K_0402_5%
@10KB_0603_1%_TH11-3H103FT PR23
BATT_TEMP <33>
2

@10K_0402_5%
2

PR19 NB_OTP <33>

2
5

@15K_0402_1% PU2
1

D
1 2 1
P

IN+ PQ4
4 2
O G @SSM3K7002FU_SC70-3
1 2 3
IN-
G

+5VALW PR20 S
3
1

4 4
@150K_0402_1%
2
1

PC16 PR21 @LMV331IDCKRG4_SC70-5

@2.21K_0402_1% PR22
@0.22U_0603_10V7K
2

@150K_0402_1% PC17
2

@1000P_0402_50V7K
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Connector/CPU_OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 37 of 56
A B C D E
 A B C D

P4 B+

BATT
VI N P2
PQ102
FDS6675BZ_SO8
1 8
PQ101 PQ103 PR102 PL101
1
2 7 1
SI4835BDY-T1-E3_SO8 SI4835BDY-T1-E3_SO8 0.012_2512_1% HCB2012KF-121T50_0805 3 6
8 1 1 8 1 2 1 2 CHG_B+ 5
7 2 2 7 PR103
6 3 3 6 47K_0402_5%

4
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

220P_0402_50V7K

1200P_0402_50V7K

680P_0402_50V7K
5 5 PC102 1 2
PR101 1U_0603_6.3V6M VI N

1
47P_0402_50V8J

47K_0402_5% PR104 ACD ET 1 2

1
0.1U_0603_25V7K

PC103

PC104

PC105

PC128

PC129

PC130
1 2 0_0402_5%
<33> AC_SET 1 2 AC SET

2
1

3
DTA144EUA_SC70-3 PR105
PC101

1
PQ104

0.47U_0603_16V7K

100K_0402_5%
10K_0402_5%

PC108
2

2
1

PR140
PC109

200K_0402_5%
2 PC107 AC OFF#

2
1

@0.1U_0603_25V7K

PC106

PR106
@0.01U_0402_16V7K

1
CHG_B+

2
PR107 C H GEN#

2
47K_0402_1% PR108
1 2 2 10_1206_5%
1

1
1 2 2 AC OFF <33>

LPMD

ACN

CHGEN
LPREF

ACSET

ACDET

ACP
PQ105 29
TP
1

5
6
7
8
D DTC115EUA_SC70-3 PR110 PC110
3

2 0_0402_5% 1U_0805_25V6K

3
G PR109 <26,28,33,36,41> SUSP# 1 2 8 28 1 2 PQ106
150K_0402_5% IADSLP PVCC PC111 DTC115EUA_SC70-3
S
3

PQ107 0.1U_0402_10V7K PQ108

2
SSM3K7002FU_SC70-3 9 27 BST_CHG 1 2 4 AO4466_SO8
AGND BTST
BQ24740VREF
PACIN_1 <39>
PC112 PU101
BQ24740RHDR_QFN28_5X5 D H _C HG
BATT
1 2 10 26
VREF HIDRV PL102 PR112

3
2
1
PR111 1U_0603_6.3V6M +3VL 10U_LF919AS-100M-P3_4.5A_20% 0.015_1206_1%
1

3K_0402_1% D LX_CHG
11 25 1 2 1 2
PA CIN PQ109 VDAC PH
1 2 2

2
G SSM3K7002FU_SC70-3 PD102 PR139

5
6
7
8
S PR113 VA DJ 12 24 R E GN 2 1 4.7_1206_5%
3

PD101 143K_0402_1% VADJ REGN

680P_0603_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
2 AC OFF# 1 2 PR114 1SS355_SOD323-2 2

@0_0402_5% 13 23 D L _CHG
2

1 1
EXTPWR LODRV

1
1SS355_SOD323-2
<33> VCTRL 1 2

PC113

PC114

PC115

PC116

PC132
4
1

PC131
14 22

2
ISYNSET PGND
1

DPMDET

2
1
PC117 PR115

IADAPT
1 2

SRSET

CELLS

1
1U_0603_10V6K 100K_0402_1% PC119 PQ110

SRN

SRP
2

3
2
1
BAT
PR116
2

15K_0402_1% 1U_0603_10V6K FDS6690AS_SO8 PC118

2
0.1U_0402_10V7K

15

16

17

18

19

20

21
PR117
BQ24740VREF

IAD APT
100K_0402_5%
PR118
Charge Detector 1 2

1
10K_0402_5%
1 2
<33> ADP_I 47K_0402_5%

1
D PR119
0.22U_0603_10V7K

100P_0402_50V8J
1

1
PQ111 2 BAT_ID <37>

2
PC120

PC121
SSM3K7002FU_SC70-3 G
S

BATT
2

3
VI N

0.1U_0603_25V7K

@0.1U_0603_25V7K
PR120
2 1 I R EF <33>
2

PC122
PC124
133K_0402_1%

1
PD104 PC123
1

1SS355_SOD323-2 0.1U_0402_10V7K PR122

2
PR121 681K_0402_1%
200K_0402_1% 1 2
1

PR123
2

1M_0402_5%
3
1 2 3

VIN_1 PR124
+3VL VI N 1K_0402_5%
VI N 1 2
1

+3VL AC_IN <21,33>

1
PR125
47_1206_5% PR126
1
10K_0402_5%

100K_0402_1% PR127
VI N PR130 10K_0402_1%
2

8
+3VL
PR128
10K_0402_1%

2.15K_0402_1% PU102B

2
1 2 5

P
+
1

PR129

7
2

O
1

PACIN
100K_0402_5%

PR131 6
-

G
133K_0402_1% PC125 C H GEN#
2

1
PR132

0.1U_0603_25V7K PC126 LM393DG_SO8

PR133
2

1
0.047U_0402_16V7K 10K_0603_0.1%
2

PR134
2

2
1

D PD103
3 10K_0402_5%
P

2
+ PQ112 RLZ4.3B_LL34
1 2
O
1

2 G SSM3K7002FU_SC70-3

2
-
G

PU102A S
PR135
3

LM393DG_SO8 FSTCH G#
4

10K_0603_0.1% PR136
60.4K_0402_1%
2

D
1 2 VIN_1
1.24VREF <33> FSTCHG 2 PQ113
G SSM3K7002FU_SC70-3
S
3

STD_ADP <33>
PU103

4 3 1.24VREF
ACD ET REF CATHODE
1 2

1
PC127 2
PR137 NC
22P_0402_50V8J
1

100K_0402_1%

4 4
20K_0402_1% 5 1

2
ANODE NC
PR138

APL1431LBBC-TR_SOT23-5
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3941P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 38 of 56
A B C D
 A B C D E

2VREF_51125

1
1 1
PC302
0.22U_0603_10V7K

2
PR301 PR302
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2

PR303 PR304
B+ B++
20K_0402_1% 20K_0402_1%
B++
PL301 1 2 1 2
HCB2012KF-121T50_0805
<BOM Structure>
1 2 +3VLP

ENTRIP2

ENTRIP1
2200P_0402_50V7K

@0.1U_0402_25V4K

PR305 PR306
390P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K
@0.1U_0402_25V4K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
140K_0402_1% 113K_0402_1%
1

1
PC321

PC316

1 2 1 2

1
PC322

PC301

PC303

PC317

PC304

PC305

PC313
PQ301
2

2
6

5
6
7
8
1 8
D1 1G

1
2 7 PC306

ENTRIP2

VFB2

TONSEL

VFB1

ENTRIP1
VREF
D1 1S/2D 10U_0805_6.3V6M PQ302
3 G2 1S/2D 6 25 P PAD AO4466_SO8

UG1_3V
4 5

2
S2 1S/2D
7 24 4
2 AO4932_SO8 VO2 VO1 2
8 23 PR308 PC308
PR307 VREG3 PGOOD 2.2_0402_5% 0.1U_0402_10V7K
PR309 1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2 PR310

3
2
1
0_0402_5% 0_0402_5% VBST2 VBST1 0_0402_5%
PL302 1 2 PC307 UG_3V 10 21 UG_5V 1 2 PL303
4.7UH_SIQB74B-4R7PF_4A_20% 0.1U_0402_10V7K DRVH2 DRVH1 4.7UH_PCMC063T-4R7MN_5.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP LL2 LL1

5
6
7
8
LG_3V 12 19 LG_5V
DRVL2 DRVL1
1

1
SKIPSEL

1
VREG5
1

VCLK
PC309 PR315 +3VL PR316 1 PC319

GND
B++

EN0
1

VIN
PC320 + @4.7_1206_5% PR312 4.7_1206_5% @22U_0805_6.3V6M

2
1 2 4 + PC310
1 2

1 2
150U_D_6.3VM

@22U_0805_6.3V6M 1M_0402_1% PU301 150U_D_6.3VM

2

13

14

15

16

17

18

1
2 TPS51125RGER_QFN24_4X4 PR317
PC314 100K_0402_5% PC315 2

1
@680P_0603_50V8J <6,37> EN0 680P_0603_50V8J
2

3
2
1

2
VL PQ304
PR311 SI4894BDY-T1-E3_SO8

2
191K_0402_1%
3/5V_OK <20,41>

1
PC311
10U_0805_10V6K

2
1
B++
PC312
<37> ENTRIP1

2
3 0.1U_0603_25V7K 3

2VREF_51125
ENTRIP2
1

D D
PQ305 2 2 PQ306
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
S S +3VLP +3VL
3

PJP301
PJP302 2 1
+5VALWP 1 2 +5VALW (4.5A,180mils ,Via NO.= 9)
PR313 PAD-OPEN 2x2m
100K_0402_5%
PAD-OPEN 4x4m
1 2 VL PJP303

+3VALWP
1 2 +3VALW (3A,120mils ,Via NO.= 6) VL +5VL
PQ308 PQ307
1

@SSM3K7002FU_SC70-3 D D SSM3K7002FU_SC70-3 PJP304

PAD-OPEN 4x4m
1 2 2 2 2 1
<38> PACIN_1 PR318 G G EC_ON <33,36>
@604K_0402_1% S S PAD-OPEN 2x2m
3

3
1

PC318
@0.047U_0603_16V7K PR314
2

100K_0402_5%
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3.3VALWP/5VALWP
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 39 of 56
A B C D E
 A B C D

1 1

PR401
0_0402_5%
1 2 PL401
<26,33,36> SYSON
1

HCB1608KF-121T30_0603
PC401 1.8V_B+ 1 2 B+

@0.1U_0402_25V4K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

2200P_0402_50V7K
@1000P_0402_50V7K
2

5
6
7
8

1
+5VALW

PC414

PC403

PC404

PC405
PC406
1+5VALW

BST_1.8V1 2 BST1_1.8V 1 2 470P_0402_50V7K

2
2 2

PR402 PC402
0_0402_5% 0.1U_0402_10V7K 4
PR403

15

14
1
316_0402_1% PU401
PR404

EN_PSV

TP

VBST
255K_0402_1% PQ401
PR410
2

3
2
1
1 2 2 13 DH _1.8V 1 2 DH_1.8V_1 AO4466_SO8 PL402
TON DRVH 2.2UH_PCMC063T-2R2MN_8A_20%
PR405 0_0402_5%
+1.8VP 2 1 3 12 LX_1.8V 1 2 +1.8VP
VOUT LL

220U_D2_4VY_R25M
0_0402_5%

1
4 V5FILT TRIP 11 1 2

5
6
7
8
PR406 PR407
1
5 10 +5VALW 10.7K_0402_1% @4.7_1206_5%
VFB V5DRV

PC408
+
1

1
PC409 6 9 PC415

2 2
PGOOD DRVL

PGND
1U_0603_10V6K GND 4.7U_0805_10V6K
2
4
2

2
PC412
+1.8VP TPS51117RGYR_QFN14_3.5x3.5 @680P_0603_50V7K
PR408
7

1
1 2 DL_1.8V
14.3K_0603_0.1% PQ402

3
2
1
SI4894BDY-T1-E3_SO8
1 2
PC413
@10P_0402_50V8J
1

3 3

PR409
10K_0603_0.1%
2

PJP401

+1.8VP 1 2 +1.8V (7A,280mils ,Via NO.= 14)

PAD-OPEN 4x4m

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8VP
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3941P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: Monday, March 16, 2009 Sheet 40 of 56
A B C D
 A B C D E

1 1

PR518
0_0402_5%
+1.1VS 1 2 PR501 PR502 PR503 PR504
B+++ 11.5K_0402_1% 24.9K_0402_1% 18.7K_0402_1% 11.5K_0402_1%

+1.1VSP 1 2 1 2 1 2 2 1 2 1 +1.2VALWP
PR517
10_0402_5%

B+++

2
PR505 B+++ B+
0_0402_5% PL502
2200P_0402_50V7K

@0.1U_0402_25V4K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

HCB2012KF-121T50_0805
2 1

1
1

1
+1.1VSP
PC517

PC501

PC502

PC518
2

VCCP_POK

470P_0402_50V7K

2200P_0402_50V7K

@0.1U_0402_25V4K
4.7U_0805_25V6-K
8
7
6
5

5
6
7
8
PC503 PU501

1
PC516

PC504

PC505

PC521
2 @0.022U_0603_25V7K PQ502 2

VO2

VFB2

TONSEL

VFB1

VO1
GND
25 AO4466_SO8

2
PQ501 P PAD

2
AO4466_SO8 4 7 24 4
PGOOD2 PGOOD1
PC507
PC506 PR506 8 23 PR507
EN2 EN1 0.1U_0402_10V7K
0.1U_0402_10V7K 2.2_0402_5% 2.2_0402_5%
+1.1VSP 2 1 2 1 BST_1.1V 9 22 BST_1.2V 2 1 1 2
1
2
3

3
2
1
VBST2 VBST1
+1.2VALWP
PL501 UG1_1.1V 2 1 UG_1.1V 10 21 UG_1.2V 2 1 UG1_1.2V PL503
2.2UH_PCMC063T-2R2MN_8A_20% 0_0402_5% PR508 DR VH2 DR VH1 PR509 3.3UH 30% MSCDRI-7030AB-3R3N 4.1A
+1.1VSP 2 1 LX_1.1V 11 20 LX_1.2V 0_0402_5% 1 2 +1.2VALWP
LL2 LL1
1

LG_1.1V 12 19 LG_1.2V
DR VL2 DR VL1
8
7
6
5

1
PR515

5
6
7
8
220U_D2_4VY_R25M

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K
4.7_1206_5% PR516 PR519

PGND2

PGND1
1 1

V5FILT
TRIP2

TRIP1

220U_B2_2.5VM
4.7_1206_5%

V5IN
1

2
+ +
1 2
PC508

PC509

PC510

PC511
1K_0402_5%

1 2

2
PC519 4 TPS51124RGER_QFN24_4x4
2

13

14

15

16

17

18

1
2 470P_0603_50V8J 2
4
PC520
2

PQ504 470P_0603_50V8J

2
1
PQ503 AO4468_SO8
1
2
3

FDS6690AS_NL_SO8 PR511 PR512

3
2
1
15.4K_0402_1% PR510 33K_0402_5%
1 2 10.5K_0402_1% 1 2
3/5V_OK <20,39>

2
PR513
0_0402_5%
3 3
2 1
<26,28,33,36,38> SUSP#

1
PC512
1 2 +5VALW 0.1U_0402_16V7K

2
PR514
3.3_0402_5%
1

PC513 PC514 PC515

0.1U_0402_10V7K 1U_0603_10V6K 4.7U_0805_10V6K
2

(4A,160mils ,Via NO.=8)

(6A,240mils ,Via NO.=12)

PJP501 PJP502
+1.1VSP 1 2 +1.1VS +1.2VALWP 1 2 +1.2VALW
PAD-OPEN 4x4m PAD-OPEN 4x4m

PJP503
4 4
+1.1VSP 1 2 +1.1VS
PAD-OPEN 4x4m

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.1VSP/1.2VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 41 of 56
A B C D E
 A B C D E

1 1

+1.8V
+1.8V

PU601
1 6 PU603
VIN VCNTL +5VALW

@10U_0805_10V4Z
1 VIN VCNTL 6 +5VALW

@10U_0805_10V4Z
2 5
GND NC
1

PC602
2 GND NC 5

PC609
PC601 3 7
VREF NC

1
10U_0805_10V4Z PC613 3 7
2

2
VREF NC

1
PR601 4 8 PC603 10U_0805_10V4Z

2
1K_0402_1% VOUT NC 1U_0603_16V6K PR606 PC612
4 8

2
1K_0402_1% VOUT NC 1U_0603_16V6K
9

2
TP
9

2
G2992F1U_SO8 TP
G2992F1U_SO8
1 2 VREF1.5V
<34,35,36> SYSON#

0.1U_0402_16V7K
PR602 +0.9VP
1

0.1U_0402_16V7K
0_0402_5%
+1.5VSP

1
PQ601
SSM3K7002FU_SC70-3 PR603 PQ602
1

1
2 D SSM3K7002FU_SC70-3 2
1K_0402_1% PR607

1
PC605 D
1 2 2
<36> SUSP 5.1K_0402_1%
2

PC604
G 10U_0805_6.3V6M 1 2 2 PC614
PR604 <36> SUSP

PC611
@0_0402_5% S PR608 G 10U_0805_6.3V6M
3

2
1

0_0402_5% S

3
1
PC606
2

@0.1U_0402_16V7K PC610

2
@0.1U_0402_16V7K

(500mA,40mils ,Via NO.= 1)

PU602
APL5508-25DC-TRL_SOT89-3 +2.5VSP
PJP601
+3VS
+0.9VP 1 2 +0.9V (2A,80mils ,Via NO.= 4) 2
IN OUT
3

4.7U_0805_6.3V6K
3 3

1U_0603_6.3V6M
PAD-OPEN 3x3m

1
GND

PC607

PC608
PR605
1 @150_1206_5%

2
PJP603
+1.5VSP 1 2 +1.5VS (1A,40mils ,Via NO.= 2)
PAD-OPEN 3x3m

PJP602

+2.5VSP 1 2 +2.5VS (500mA,40mils ,Via NO.= 1)

PAD-OPEN 3x3m

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.9VSP/2.5VSP/1.5VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 42 of 56
A B C D E
 A B C D E

PL201 2 1
+CPU_CORE_NB 4.7UH_PCMC063T-4R7MN_5.5A_20%

1
4.7_1206_5%
PQ202

PR245
1 PQ201
AO4466_SO8

10U_0805_6.3V6M
AO4468_SO8

1
+ PC202 1 8 1 8 CPU_B+

PC201
<6> VDD_NB_FB_H 220U_B2_2.5VM 2 7 2 7

1 2
PC251 3 6 3 6

2
2

470P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K
PC238

PC203

PC258
5 5 PC204

4.7U_0805_25V6-K
1

1
<6> VDD_NB_FB_L

4
680P_0603_50V7K

2
2
1 PR203 1

1
0_0402_5%

0_0402_5%
0_0402_5%

PR206

PR209

UGATE NB1
PHASE NB
PR204

LGATE NB
22K_0402_1%

2
ISL6265_PWROK

1 2

1 2

PC205 PR205
1000P_0402_50V7K 2_0402_5%
1 2
+5VS
1

1
D B+
CPU_B+

1
44.2K_0402_1% 1200P_0402_50V7K
2 PQ209 PC207 PL202

33P_0402_50V8K
<33> VFIX_EN G @SSM3K7002FU_SC70-3 0.1U_0402_16V7K PC206 SMB3025500YA_2P

17.4K_0402_1%
S 0.1U_0402_16V7K
3

BOOT_NB1 2
1
PC209

PC208
2 1

1000P_0402_50V7K
+5VS

PR207
1

47P_0402_50V8J
1000P_0402_50V7K
PR208 1 1

1
2200P_0402_50V7K

68U_25V_M

68U_25V_M
Connect to EC pin 110. 2_0402_5%

1
330P_0402_50V7K

3300P_0402_50V7K

1800P_0402_50V7K

390P_0402_50V7K

3300P_0402_50V7K

1800P_0402_50V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

PC211
1 2 + +
CPU_B+

47P_0402_50V8J
PC214
PC210

PC2532
5
6
7
8

1
PC243

PC239

PC234

PC235

PC212

PC213

PC248

PC254

PC255

PC249

PC250

PC215
2.2U_0603_6.3V6K

2
1

1
2 2

2
PR210
PC216 PR211

2
PC261

PC262
0.1U_0603_25V7K 1_0603_5%
2

1 2
+5VS 4

2
1 2
2 +3VS 2

PHASE NB

UGATE NB
PR212

LGATE NB
VSEN_NB

RTN_NB
0_0402_5%
1 2 PQ203

BOOT_NB

3
2
1
PR213 IRF8714TRPBF_SO8
<BOM Structure>
@0_0402_5% 2.2_0603_5% 0.22U_0603_10V7K UGATE0_1
1 2 PR214 PC217 0.36UH_PCMC104T-R36MN1R17_30A_20%
1
10K_0402_1%

1 2 1 2 2 1
48

47

46

45

44

43

42

41

40

39

38

37
+CPU_CORE_0
PR215 PU201

1
4.7_1206_5%

PC218 4.7_1206_5%

3.65K_0402_1%
PR216

@10K_0402_5% PL203
FB_NB

COMP_NB

FSET_NB

VSEN_NB

RTN_NB

OCSET_NB

PGND_NB

LGATE_NB

PHASE_NB

UGATE_NB
VIN

VCC

47P_0402_50V8J
PR220

PR242

PR221
1 2

BOOT0

1
0_0603_5%
2

PC259
1 36 PR219
OFS/VFIXEN BOOT_NB PR217

1 2

2200P_0603_50V7K 2

2
2 35 4 @4.02k_0603_1%
<33> VGATE PR246 1100K_0402_5% PGOOD BOOT0
2 1 2
<19> H_PWRGD 1 2 ISL6265_PWROK 3 34 UGATE0
<6,20,33> SB_PWRGD PR234 @100K_0402_5% PWROK UGATE0 PC219 1 2

2
PR218 1 2 SVD 4 33 PHASE0 0.1U_0603_25V7K

3
2
1
<6> CPU_SVD 0_0402_5% SVD PHASE0 PQ205 ISP 0
PR222 1 2 SVC 5 32 IRFH7932TRPBF_PQFN
<6> CPU_SVC 0_0402_5% SVC PGND0
CPU_B+
6 31 LGATE0
<33> VR_ON PR223 PR224 ENABLE LGATE0

5
6
7
8

2200P_0402_50V7K

2200P_0402_50V7K

1800P_0402_50V7K

390P_0402_50V7K
47P_0402_50V8J
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1 2 1 2 7 30
RBIAS PVCC

1
1

1
PC240

PC237

PC236

PC220

PC221

PC252

PC256

PC257
107K_0402_1% 10K_0402_1% 8 29 LGATE1
OCSET LGATE1

PC222
2

2
PR225 PC223 9 28

2
VDIFF0 ISL6265IRZ-T_QFN48_6X6 PGND1
1 2 1 2 4
10 27 PHASE1
255_0402_1% 4700P_0402_25V7K FB0 PHASE1 PR226
PR227 11 26 UGATE1 1 2 UGATE1_1 PQ206
3 COMP0 UGATE1 0_0603_5% IRF8714TRPBF_SO8 3
1 2

3
2
1
12 25 BOOT1 1 2 1 2 2 1
VW0 BOOT1 +CPU_CORE_0
1K_0402_1% PR228 PL204
COMP1
VDIFF1
VSEN0

VSEN1

1
4.7_1206_5%

4.7_1206_5%
RTN0

RTN1

2.2_0603_5% PC224 0.36UH_PCMC104T-R36MN1R17_30A_20%

ISN0

ISN1
ISP0

VW1

ISP1

1
FB1

3.65K_0402_1%
PR229

PR244
0.22U_0603_10V7K
TP

PR231
PR230 PC225
1 2 1 2
13

14

15

16

17

18

19

20

21

22

23

24

49

47P_0402_50V8J
1 2

1
54.9K_0402_1% 1200P_0402_50V7K PR232 4

2
VSEN0

PC260
+CPU_CORE_0

PR233
VSEN1

1 2 1 2
RTN0

RTN1
ISP 0

PC227 PC226 @4.02k_0603_1%

2
180P_0402_50V8J 6.81K_0402_1% +CPU_CORE_0 2200P_0603_50V7K 1 2

2
3
2
1
ISP 1 PC229
@1000P_0402_50V7K

1 2 PC230 0.1U_0603_25V7K 1 2
PC228 @1000P_0402_50V7K PQ208
1000P_0402_50V7K 2 1 IRFH7932TRPBF_PQFN

PC231
PC241 @180P_0402_50V8J ISP 1
PC244

1 2 1000P_0402_50V7K
@1000P_0402_50V7K

<6> CPU_VDD0_FB_H PR235 2 1 2 1

1

0_0402_5% PR236 PR238

1

@6.81K_0402_1% @54.9K_0402_1%
2 1 2 1
2
2

PC232
PC245

1 2 @1200P_0402_50V7K
<6> CPU_VDD0_FB_L PR237 PR240
1

@1000P_0402_50V7K

0_0402_5% @1K_0402_1%
2 1
2

4 PR243 4
@255_0402_1%
@1000P_0402_50V7K

PC242 2 1 2 1
PC246

+1.8V 1 2 @1000P_0402_50V7K
PR239 @4700P_0402_25V7K
1

0_0402_5% PC233
1

Security Classification Compal Secret Data Compal Electronics, Inc.

2

PC247
2

1 2 Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

1

PR241
@0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
Size Document Number R ev
2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 43 of 56
A B C D E
 A B C D E

V ersion C han ge L ist ( P . I. R . L ist ) for P ow er C ircuit

Item P a ge# T it le D a t e R e q u e st I s s u e D e sc rip tio n S o lu tio n D escrip tio n R ev.
O w n er
1 1
DC Connector PL3 change the value from SMB3025500YA_2P to HCB2012KF-121T50_0805
1 37 /CPU_OTP 9/29 Compal for Layout and add PL4 the same of the value.

PC508 and PC511 change the value from 220U_6.3VM_R15 to

2 41 1.1VSP/1.2VALWP 9/29 Compal HW request 220U_D24VY_R25M

3 41 1.1VSP/1.2VALWP 9/29 Compal HW request Add PJP503

4 43 CPU_CORE 9/29 Compal HW request PC202 change the value from 220U_6.3VM_R15 to 220U_D24VY_R25M

TI FAE suggested that after he review

、 、、 、
Add PC241 PC242 PC243, and the value are 1000P_0402_50V7K.
Reserve PC244 PC245 PC246 PC247, and the value are 、
5 43 CPU_CORE 9/29 Compal the layout. 1000P_0402_50V7K.

6 43 CPU_CORE 9/29 Compal

TI FAE suggested that after he review
the layout. Add PJP201 、PJP202 2

7 38 Charger 9/29 Compal the footprint is wrong Change the footprint of PR102

DC Connector
8 37 /CPU_OTP 10/08 Compal for Layout These two choke are parallel ,it's not series.

9 38 Charger 10/08 Compal the footprint is wrong Change the footprint of PR102

10 40 1.8VP 10/08 Compal PWR request Delete PC410 and PC411

3
11 41 1.1VSP/1.2VALWP 10/08 Compal PWR request Add PR517 、PR518 3

12 37
DC Connector
/CPU_OTP 11/01 Compal PWR request Add PD4 、PC12
13 37 3.3VALWP/5VALWP 11/01 Compal for Layout change PQ301, Cencel PQ303

14 43 CPU_CORE 11/02 Compal EMI request Add PC248, PC249, PC250

15 37 3.3VALWP/5VALWP 11/12 Compal for Layout Change PC310, add PC319

Add PU302, control signal changed to ACOFF

16 37 3.3VALWP/5VALWP 12/31 Compal PWR request

Change PR221 and PR231 to 16.6K_ohm

43 CPU_CORE 12/31 Compal Vendor request Change PR217 and PR233 to 4.02K_ohm
17 Change PR223 to 17.8K_ohm
4 Change PR224 to 100K_ohm 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Changed-List History-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 1.C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 44 of 56
A B C D E
 A B C D E

V ersion C han ge L ist ( P . I. R . L ist ) for P ow er C ircuit

Item P a ge# T it le D a t e R e q u e st I s s u e D e sc rip tio n S o lu tio n D escrip tio n R ev.
O w n er
1 1

18 38 Charger 01/08 Compal EMI request Add PC128 220pF

37 DC Connector 01/09 Compal AC LED change to KBC control AC_LED# connect to KBC pin 97
19 /CPU_OTP

20 37 3.3VALWP/5VALWP 01/14 Compal for layout Change PC309 to D size and add PC320

21 38 Charger 02/27 Compal EMI request CHG_B+ Add 1200pF and 330pF

22 43 CPU_CORE 02/27 Compal EMI request CPU_B+ Add 1800pF*2 2200pF*1 and 390pF*2

23 37 3.3VALWP/5VALWP 02/27 Compal EMI request B+ Add 2200pF and 390pF

2 2
24 37 DC Connector 02/27 Compal EMI request VIN Add 2200pF and 390pF, ADPIN add 820pF
/CPU_OTP

25
37 3.3VALWP/5VALWP 02/27 Compal Change OTC shun down pin. Change OTC shun down pin to PU301 pin13.

26 43 CPU_CORE 03/04 Compal Change high-side MOS for WWAN issue Change PQ203 and PQ206 to powerpak

27 43 CPU_CORE 03/04 Compal HW request add H_PWRGD control net

28 37 DC Connector 04/02 Compal AC LED issue Chaange AC_LED# pull high to +3VL
/CPU_OTP

29 43 CPU_CORE 04/24 Compal acoustic noise Add PC262

30 37 DC Connector 04/24 Compal HW CPU thermal protection Chaange PR12 to 2.21K_ohm

3
/CPU_OTP change to 95 +-3 degree C 3

31 37 1.1VSP/1.2VALWP 05/23 Compal +1.2VALW leakage Add PR519

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Changed-List History-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 1.C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 45 of 56
A B C D E
 A B C D E

V ersion C han ge L ist ( P . I. R . L ist ) for H W C ircuit

R e q u e st
Item P a ge# T it le D ate O w n er I s s u e D e sc rip tio n S o lu tio n D escrip tio n R ev.
1 25 LAN 1 0 /2 9 HW C h a n g e L A N C h ip U 2 0 fro m M a rv e ll 8 8 E 8 0 4 2 to U p d a te th e L A N D esig n p a g e a n d su p p o rt circu it 0 .2
1 1

R e a lt e k R T L 8 1 0 2 E L
2 25 LAN 1 0 /2 9 HPQ A d d P O E (P o w e r O v e r E th e rn e t) d e sig n U p d a te th e L A N D esig n p a g e a n d su p p o rt circu it 0 .2
3 16 CRT 1 0 /2 9 HW C R T c a n n o t d isp la y C h a n g e t h e C R T C o n n . sig n a ls co n n ectio n first. 0 .2
W a it c o rre c t s y m b o l f o r fix
4 29 A u d io 1 0 /3 0 HW S p e a k e r n o so u n d A d d R 9 7 3 (1 0 K _ 0 4 0 2 ) t o + 3 V A L W o n H P _ D E T # 0 .2
5 4 FAN 1 1 /0 1 HW F A N C o n n . n o t c o rre c t p a rt C h a n g e J P 2 P C B F o o t p rin t f ro m A C E S _ 8 5 2 0 4 -0 2 0 0 1 _ 2 P to 0 .2
A C E S _ 8 8 2 3 1 -0 2 0 0 1 _ 2 P
6 29 S p ea k er 1 1 /0 1 HW S p e a k e r C o n n . n o t c o rre c t p a rt C h a n g e J P 2 0 P C B F o o t p rin t f ro m A C E S _ 8 5 2 0 4 -0 4 0 0 1 _ 4 P to 0 .2
A C E S _ 8 8 2 3 1 -0 4 0 0 1 _ 4 P
7 34 MDC 1 1 /0 1 HW M D C C o n n . n o t c o rre c t p a rt C h a n g e J P 2 0 P C B F o o t p rin t f ro m A C E S _ 8 8 0 1 8 -1 2 4 G _ 1 2 P to 0 .2
A C E S _ 8 8 0 2 0 -1 2 1 0 1 _ 1 2 P
2
8 11,35 TV_OUT 1 1 /0 5 HW T V -O U T F u n c tio n n o su p p o rt D e l R 5 9 ,R 6 0 ,R 6 1 ,R 1 1 5 ,R 1 1 6 ,R 1 1 7 a n d T V -O U T re la t e d d e s ig n . 0 .2 2

9 11,21 N B /S B T h e rm a l 1 1 /0 5 HW N B T h e r m a l F u n c tio n n o su p p o rt (lo c a te to o fa r) C a n c e l N B _ T H E R M A L _ D A / D C c o n n e c t io n b e tw een N B a n d 0 .2

S B ,d e l C 5 0 0
10 21,31 SB SATA 1 1 /0 5 HW S B S A T A P o rt 5 c h a n g e to P o rt 2 fo r A T I C o m m o n C h a n g e S B S A T A p o rt 5 to p o rt 2 0 .2
D e s ig n
11 21 SB SATA 1 1 /0 5 HW S B S A T A _ A C T # P u ll H ig h b e c o m e + 3 V S C h a n g e R 3 4 3 .1 p o w e r ra il f ro m + 5 V S t o + 3 V S . In sta ll R 3 4 3 . 0 .2

12 21 S B G PIO 1 1 /0 5 HW C h a n g e S B G P I O re fe r to J B K 0 0 fo r c o m m o n 1 . C o n n e c t U 1 5 .C 6 t o G N D b y 0 _ 0 4 0 2 . 0 .2
2 . C h a n g e W L O F F # f ro m G P I O 5 0 t o G P I O 6 1 .
3 . C h a n g e B T _ C O M B O _ E N # f ro m G P I O 5 1 to G P IO 6 2 .
4 . C h a n g e W W O F F # f ro m G P I O 5 2 t o G P I O 6 3 .
13 31 SB SATA 1 1 /0 5 HW V e r t ic a l L 5 1 1 < --> 4 , 2 < --> 3 fo r la y o u t ro u tin g V e rt ic a l L 5 1 1 < --> 4 , 2 < --> 3 f o r la y o u t ro u tin g 0 .2
14 29 A u d io H P O U T 1 1 /0 5 HW A d d 1 5 0 U F C a p s fo r e a c h D O C K _ L O U T _ R / L A dd 150U F C aps for each D O C K _ L O U T _ R /L 0 .2
3 3

15 25 L A N T ra n sferm o r 1 1 /0 5 HW C o r r e c t U 1 9 L A N T ra n sfe rm o r p in d e fin itio n C o rre c t U 1 9 L A N T ra n s f e rm o r p in d e fin itio n 0 .2

16 21,24 SB SATA 1 1 /0 6 HW S B S A T A P o rt 4 c h a n g e to P o rt 3 fo r A T I O p e n I ssu e C h a n g e S B S A T A p o rt 4 to p o rt 3 0 .2
17 36 D IM LE D 1 1 /0 6 HW R e d u c e D I M L E D u n n e c e ssa ry d e sig n D e l R 1 0 2 6 a n d Q 1 6 7 , a d d N e t "D I M _ L E D # " f o r co n n ect. 0 .2
C h a n g e lo c a t io n f ro m P J P 6 0 4 to P J P 8 .
18 27 C a r d R ea d er 1 1 /0 6 HW C h a n g e C a rd R e a d e r S o c k e t fo r M / E n e w p a rt a n d C h a n g e J R E A D t o T A I T W _ R 0 1 5 -B 1 0 -L M . 0 .2
C h ip f o r J M ic ro n n e w v e rsio n R e s e rv e R 4 1 3 ,C 9 0 2 c lo s e t o J R E A D .2 0 ;
R 4 1 2 ,C 9 0 1 c lo s e t o J R E A D .2 6 ; R 4 1 1 ,C 9 0 0 c lo s e to J R E A D .3 7 .
C h a n g e R 4 5 7 c lo s e t o U 2 3 .4 2
A d d R 4 5 5 ,R 4 5 6 c lo s e t o U 2 3 .4 2
D e l Q 1 6 9 ,R 1 0 5 1 .
C h a n g e n e t C R _ L E D # b e c o m e C R _ L E D c o n n e c t U 2 3 .2 1 a n d Q 5 3 .2
A d d R 4 5 4 p u ll d o w n t o G N D
4 C h a n g e R 4 0 5 ,R 1 2 2 f ro m 2 0 0 K t o 1 0 K p u ll-h ig h 4

R e m o v e C 8 9 5 ,U 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 1.C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 46 of 56
A B C D E
 A B C D E

V ersion C han ge L ist ( P . I. R . L ist ) for H W C ircuit

R e q u e st
Item P a ge# T it le D ate O w n er I s s u e D e sc rip tio n S o lu tio n D escrip tio n R ev.
19 16 CRT 1 1 /0 7 HW N o r m a li z e C R T d e sig n fo r c o m m o n C h a n g e L 8 3 ,L 8 4 (1 0 _ 0 4 0 2 ) b e c o m e R 2 4 1 ,R 2 4 0 (0 _ 0 6 0 3 ) 0 .2
1 1

20 17 LCD 1 1 /0 7 HW N o r m a liz e L C D d e sig n fo r c o m m o n C h a n g e R 4 9 1 fro m 2 0 0 _ 0 4 0 2 to 2 0 0 _ 0 8 0 5 0 .2

21 18 LCD 1 1 /0 7 C IC C I C fe e d b a c k R M A c o n c e rn fo r com m on C h a n g e Q 4 3 fro m A O S 3 4 1 3 to S I 2 3 0 1 0 .2
22 33 KBC 1 1 /0 7 HW N o r m a liz e K B 9 2 6 C ry sta l p a rt fo r c o m m o n C h a n g e Y 7 f ro m 9 H 0 3 2 0 0 4 1 3 s m a ll t o 1 T J S 1 2 5 D J 4 A 4 2 0 P n o rm a l. 0 .2
23 17 W eb C a m 1 1 /0 9 HW C h a n g e U 5 4 W e b C a m p o w e r d e sig n a n d re la te d C h a n g e U 5 4 f ro m G 9 1 6 -3 9 0 T 1 U F t o R T 9 1 9 3 -3 9 G B . 0 .2
R e m o v e R 8 9 1 ,R 8 9 2 if n o u s e G 9 1 6 -3 9 0 T 1 U F .
A d d C 7 1 8 c lo s e t o U 5 4 .4 f o r R T 9 1 9 3 -3 9 G B .
R e m o v e R 1 0 2 7 ~ R 1 0 3 0 f o r J P 7 n o in s ta ll.
C h a n g e J P 7 f ro m 8 p in to 6 p in
24 18 HDMI 1 1 /0 9 HW R e d u c e H D M I D e sig n R e m o v e R 4 9 0 (1 0 0 K _ 0 4 0 2 ) 0 .2
25 19,32 S B -C L K -D eb u g 1 1 /0 9 HW D e b u g C a rd n o fu n c tio n issu e D e l R 1 0 3 1 ,a d d R 3 0 3 c lo s e t o R 3 0 1 a n d U 1 5 .P 2 0 .2
C o n n e c t f o r C L K _ P C I _ S I O 2 t o J P 4 1 .1 5
2
26 25 LAN 1 1 /0 9 HW R J 4 5 L E D P o w e r c o rre c t b a c k C h a n g e J R J 4 5 .1 3 , J R J 4 5 .1 1 f ro m + 3 V _ L A N _ L E D to + 3 V _ L A N 0 .2 2

27 18 HDMI 1 1 /0 9 HW R e d u c e H D M I D e sig n R e m o v e R 4 9 0 (1 0 0 K _ 0 4 0 2 ) 0 .2
28 6 CPU 1 1 /0 9 HW A d d H _ T H E R M T R I P # o n e m o re w a y A d d R 1 6 clo se to Q 3 .1 fo r H _ T H E R M T R I P # 0 .2
29 33 KBC 1 1 /0 9 HW U p d a t e K B C P in D e fin itio n fo r c o m m o n A d d H _ T H E R M T R I P # to U 3 3 .2 5 0 .2
30 35 H o les 1 1 /0 9 ME U p d a t e f o r M / E D ra w in g D el H 4 9 H 5 0 H 3 8 H 4 5 fo r M /E d ra w in g ch a n ge 0 .2
31 26 M in i -C a rd 1 1 /0 9 HW R e d u c e M in i-C a rd d e sig n , c h a n g e S I M C a rd d e sign R ep lace D 1 7 an d D 47 becom e R 52 and R 53 0 .2
D e l R 4 0 0 a n d R 4 6 , C h a n g e J P 6 p in d e f in it io n f o r c o m m o n
32 33 KBC 1 1 /0 9 HW R e s e r v e 0 _ 0 6 0 3 fo r K B B a c k L ig h t A d d R 5 1 6 (0 _ 0 6 0 3 ) b e t w e e n J P 4 8 .1 / 4 a n d + 5 V S _ L E D 0 .2
33 27 C a r d R ea d er 1 1 /1 0 HW C o rre c t C a rd R e a d e r L E D p a rt C h a n g e D 5 f ro m S C 5 0 0 0 0 4 E 0 0 (A Q U A _ W H IT E ) to 0 .2
S C 5 0 0 0 0 4 W 0 0 (W H I T E )
34 34 L E D F u n ctio n 1 1 /1 0 HW C o r r e c t L E D fu n c tio n fo r c o m m o n C h a n g e L E D f ro m D 5 0 ,D 3 0 ,D 2 7 S C 5 0 0 0 0 4 E 0 0 0 .2
(A Q U A _ W H I T E ) t o D 6 ,D 7 ,D 8 S C 5 0 0 0 0 4 W 0 0 (W H I T E )
3 C h a n g e L E D f ro m D 4 5 ,D 4 6 S C 5 0 0 0 0 4 B 0 0 3

(A Q U A _ W H I T E / A M B E R ) t o D 1 7 ,D 1 8 S C 5 0 0 0 0 5 M 0 0
(Y E L L O W / W H I T E ); A d d Q 7 ,R 2 0 a n d R 4 2 c lo s e t o D 1 8
35 21 S B -G P I O 1 1 /1 0 HW A d d o n e m o re w a y fo r G S E N S O R L E D # in fo rm p in A d d H D D _ H A L T L E D # c o n n e c t f ro m U 1 5 .P 8 0 .2
36 33 K B C-G PIO 1 1 /1 1 HW A d d C I R _ I N P H to + 5 V L A d d R 4 6 1 0 K _ 0 4 0 2 P H t o + 5 V L c lo s e t o U 3 3 0 .2
A d d E S B _ C L K / D A T P H to + 3 V L A d d R 5 1 4 ,R 5 1 5 1 0 K _ 0 4 0 2 P H t o + 3 V L c lo s e t o U 3 3
37 6,31 C P U ,F P R 1 1 /1 3 HW R e d u c e S 3 p o w e r c o n su m p tio n C h a n g e R 1 5 .2 ,R 2 1 .2 ,R 3 6 .2 ,R 3 0 .2 c o n n ectio n fro m 0 .2
+ 1 .8 V t o + 1 .8 V S ; R e m o v e R 6 2 2 , in s ta ll R 5 8 1
38 11 NB 1 1 /1 3 HW R e d u c e th e le v e l sh ift d e sig n fo r C h ip A 1 2 . D e l Q 6 ,R 8 7 ; Q 5 ,R 8 4 a n d re p la c e b y 0 o h m (a d d R 6 7 ,R 6 8 ) 0 .2
c o n n e c t d ire c t ly . I n s t a ll R 3 7 1 (1 0 K o h m )
39 17 W eb C a m 1 1 /1 3 HW U p d a te th e W e b C a m + D ig ita l M ic re se rv e r con n . C h a n g e J P 7 f ro m S P 0 2 0 0 0 H C 0 0 (8 p in )--> S P 0 2 0 0 0 I L 0 0 (6 p in ) 0 .2
40 6,33 C P U ,K B C 1 1 /1 3 HW U p d a te T H E R M T R I P # d e sig n to E C C h a n g e R 1 6 .2 c o n n e c t io n f ro m T H E R M T R I P # t o 0 .2
4
T H E R M T R I P # _ E C f o r s e p a ra t e 4

41 18 HDMI 1 1 /1 3 HW R e m o v e E M I so lu tio n b e c o m e re se rv e fo r v e rify A d d R 1 1 2 ,R 1 1 3 ,R 1 1 5 ~ R 1 2 0 c lo s e t o e a c h L 8 5 ~ L 8 8 f o r c o -la y 0 .2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 1.C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 47 of 56
A B C D E
 A B C D E

V ersion C han ge L ist ( P . I. R . L ist ) for H W C ircuit

R e q u e st
Item P a ge# T it le D ate O w n er I s s u e D e sc rip tio n S o lu tio n D escrip tio n R ev.
4 2 1 9 . 3 2 S B ,B IO S 1 1 /1 3 HW R e d u c e S B re la te d d e sig n fo r C h ip A 1 2 a n d o th e rs D e l Q 1 5 5 ,R 9 8 6 , a n d a d d R 3 1 1 c lo s e t o U 1 5 . 0 .2
1 1
D el R 1 0 1 1 becom e T 18, C ancel R 1012 and connect to H 31
a n d J P 4 1 d ire c t ly
43 21,32 S B ,B IO S 1 1 /1 3 HW B I O S D e b u g T o o l re se r v e A d d S B _ I N T _ F L A S H _ S E L a n d re la t e d 0 .2
(J P 1 2 ,U 3 0 ,R 2 2 8 ,R 2 2 6 ,C 4 8 9 c lo s e t o U 2 9 )
44 25 LAN 1 1 /1 3 HW U p d a t e L A N C h ip S y m b o l lin k to C I S se rv e r U p d a t e L A N C h ip U 2 0 S y m b o l lin k t o C I S s e rv e r 0 .2
45 13 NB 1 1 /1 3 HW A d d 0 o h m _ 0 6 0 3 t o se p a ra te V D D 1 8 _ M E M A d d R 1 0 5 1 (0 _ 0 6 0 3 ) b e t w e e n + 1 .8 V S & + 1 .8 V _ V D D _ S P 0 .2
46 18 HDMI 1 1 /1 3 HW R e d u c e H D M I re la te d d e sig n fo r c o m m o n D e l R 4 9 0 (1 0 0 K _ 0 4 0 2 ) 0 .2
47 20 SB 1 1 /1 3 HW R e d u c e S B re la te d d e sig n fo r c o m m o n a n d A 1 2 c h ip R e m o v e R 9 9 4 (0 _ 0 4 0 2 ) 0 .2
C h a n g e U 1 5 .F 1 c o n n e c t io n b e c o m e t e s t p o in t
R em ov e R 1 0 5 3 , change R 1052 becom e 0_0402
48 2 0 ,2 1 , S B ,C a rd rea d er 1 1 /1 3 HW R e se rv e C a rd re a d e r D 3 E fu n c tio n (C R _ W A K E # & A d d R 8 1 c lo s e t o U 1 5 ;Q 5 4 ,R 1 2 4 c lo s e t o U 2 3 f o r c o n n e c t U 1 5 .F 8 0 .2
27 CR_CPPE# ) t o U 2 3 .1 3 ;A d d R 3 6 9 c lo s e t o U 2 3 f o r c o n n e c t U 1 5 .M 5 t o U 2 3 . 1 6
2 2

49 21,33 S B ,K B C 1 1 /1 3 HW R e d u c e S B re la te d d e sig n fo r c o m m o n D e l D 5 1 a n d R 1 0 3 4 , C h a n g e t h e n e t A C _ I N b eco m e A C _ IN _ D 0 .2

50 28,33 C o d ec,K B C 1 1 /1 3 HPQ E C _ B E E P fu n c tio n fo r K B C a d d A d d R 5 6 3 c lo s e t o C 9 5 5 ; A d d R 5 4 4 c lo s e t o U 3 3 .3 1 0 .2
51 33 KBC 1 1 /1 3 HW R e d u c e S 5 P o w e r C o n su m p tio n C h a n g e R 1 0 4 0 .1 c o n n e c t io n f ro m + 3 V L _ E C to + 3 V A L W 0 .2
D e l R 5 4 6 P H t o + 3 V L _ E C , D e l D 2 6 re p la c e b y a d d R 5 4 7 c lo s e to
U 3 3 f o r s h o rt
52 33 KBC 1 1 /1 3 HW R e d u c e K B C D e sig n fo r c o m m o n a n d V e r:C 0 C h ip D e l R 5 3 7 b e c o m e T e s t P o in t , c h a n g e R 5 1 6 b e c o m e 1 5 0 _ 0 6 0 3 0 .2
C hange from SA 00001J530 to SA 00001J540 R e m o v e R 1 0 4 4 , c h a n g e R 1 0 4 0 f ro m 1 0 K t o 1 0 0 K
C h a n g e R 5 2 8 .2 , R 5 2 9 .2 c o n n e c t io n f ro m + 5 V A L W to + 5 V L
I n s t a ll C 8 1 4 (4 .7 U _ 0 8 0 5 )
53 34 S w i tch D esig n 1 1 /1 3 HW U p d a t e C S D f u n c tio n b o a rd d e sig n fo r c o m m o n C h a n g e J P 3 6 .1 c o n n e c t io n b e c o m e + 3 V L ;C h a n g e R 1 0 4 6 .1 0 .2
a n d R 1 0 4 7 .1 c o n n e c t io n b e c o m e S M B _ E C _ C K 1 /D A 1
C h a n g e J P 3 6 .7 c o n n e c t io n f ro m G N D to + 5 V A L W _ L E D b y
54 34 LED 1 1 /1 4 HW C o rre c t T / P O n / O ff L E D d e sig n d e f in e C h a n g e Q 1 5 3 f ro m 2 N 7 0 0 2 D W t o 2 N 7 0 0 2 0 .2
3

C o r r e c t G -S e n so r L E D d e sig n d e fin e C h a n g e R 9 8 8 .1 c o n n e c t io n f ro m + 5 V S _ L E D to + 3 V S 3

55 29 A u d io -D o ck 1 1 /1 4 HPQ F o r G S m a rk re q u ire m e n t A d d R 9 6 8 ,R 9 6 9 c lo s e t o C 7 7 5 / C 7 7 6 . 0 .2
56 29 H o les 1 1 /1 4 ME U p d a t e H o le s to m e e t M / E D ra w in g A d d back H 52 becom e H _ 1P 5N ; D el C F 4 0 .2
57 4,24 M u lti-B a y 1 1 /1 4 ME U p d a t e S y m b o l to m e e t M / E D ra w in g U p d a t e J P 2 ,J P 9 ,J P 1 0 ,J P 1 1 ,J P 2 0 ,J P 4 0 ,J H D M I ,J E S A T ,J C R T , 0 .2
JD O C K Sym bol
58 33 H o les 1 1 /1 4 ME U p d a t e H o le s to m e e t M / E D ra w in g A d d back H 52 becom e H _ 1P 5N ; D el C F 4 0 .2
59 20 SB 1 1 /1 6 A TI R e se rv e to fix th e O T S 3 2 5 0 5 5 I ssu e R e s e rv e R 8 3 P H t o + 3 V S 0 .2
60 33 KBC 1 1 /1 6 EC C h a n g e d e sig n fo r E C te a m d e b u g C h a n g e J P 3 4 .1 f ro m + 5 V A L W to + 5 V L 0 .2
61 35 DOCK 1 1 /1 6 EMC C o n n e c t D O C K g u id e p in to G N D A d d J D O C K .4 5 / 4 6 to G N D 0 .2
62 33 K /B 1 1 /1 6 HW F ix K B m a tri x issu e D e l K S I 6 a n d K S O 9 o u t o f p a g e n et co n n ect 0 .2
63 28,29 HPQ M a k e s o m e A u d io re la te d d e sig n c h a n g e C h a n g e C 9 8 3 ,C 9 8 4 f r o m 1 U F t o 0 .0 2 2 U F . C h a n g e C 1 0 4 9 ,C 1 0 5 0 ,C 1 0 4 0 ,C 1 0 4 1 0 .2
A U D IO 1 1 /1 8 f r o m 0 .4 7 U F t o 0 .0 2 2 U F . C h a n g e R 1 0 0 2 ,R 1 0 0 5 f r o m 2 0 K t o 0 o h m . C h a n g e
4 4
C 1 0 4 4 f r o m 1 0 U F t o 4 .7 U F . R e m o v e R 1 0 0 0 ,R 1 0 0 4 ; I n sta ll R 1 0 0 1 ,R 1 0 0 3 .
64 29 A U D IO 1 1 /1 9 HPQ M a k e s o m e A u d io re la te d d e sig n c h a n g e C h a n g e R 9 6 8 ,R 9 6 9 f ro m 4 0 .2 _ 0 4 0 2 t o 4 7 _ 0 6 0 3 0 .2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 1.C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 48 of 56
A B C D E
 A B C D E

V ersion C han ge L ist ( P . I. R . L ist ) for H W C ircuit

R e q u e st
Item P a ge# T it le D ate O w n er I s s u e D e sc rip tio n S o lu tio n D escrip tio n R ev.
65 13 NB 1 1 /2 0 A TI D e s ig n C h a n g e fo r N B A 1 2 V e rsio n c h ip R e m o v e U 6 4 ,C 1 0 6 4 ,C 1 0 6 5 ,C 1 0 6 6 ,C 1 0 6 7 ,R 1 0 1 5 ,R 1 0 1 6 ,Q 1 6 3 ,R 1 0 1 7 . 0 .2
1 I n s t a ll L 1 9 , r e m o v e L 9 5 1

66 22 SB 1 1 /2 0 A TI D e s ig n C h a n g e fo r S B A 1 2 V e rsio n c h ip I n s t a l l R 5 9 3 , re m o v e R 5 9 2 0 .2
67 22 SB 1 1 /2 0 HW R e d u c e S B P o w e r D e sig n -N o I D E su p p o rt R e m o v e R 1 2 ,C 5 4 3 ,C 5 4 4 ,C 5 4 7 ,C 5 3 6 0 .2
68 3 3 , 3 4 F u n ctio n B o a rd 1 1 /2 0 HW R e se rv e fo r R a c h m a n U M A se le c tiv e R e s e r v e R 5 5 5 f o r + 5 V A L W _ L E D , a d d R 5 5 4 f o r + 3 V L c lo s e t o J P 3 6 .1 0 .2
R e s e r v e R 1 0 3 4 c l o s e t o J P 3 6 .4 ,R 1 0 3 5 c lo s e J P 3 6 .5 ,R e m o v e R 1 0 3 6
A d d R 5 1 3 P H t o + 3 V S c lo s e t o U 3 3 .1 9
69 23 SB 1 1 /2 0 HW M a k e th e S B S tra p S e e tin g fo r c o m m o n I n s t a ll R 3 5 6 (1 0 K _ 0 4 0 2 ) 0 .2
70 31 B lu eT o o th 1 1 /2 0 HW U p d a t e B T d e sig n fo r c o m m o n C h a n g e R 5 2 0 f ro m 4 7 K _ 0 4 0 2 t o 1 0 K _ 0 4 0 2 0 .2
71 34 P o w er O n S w i tch 1 1 /2 2 HW C a n c e l o n e re se rv e d p o w e r o n sw itc h D el S W 3 0 .2
72 33 KBC 1 1 /2 2 HW M o d if y S M B _ E C _ D A 1 / C K 1 P H fo r c o m m o n C h a n g e R 5 2 8 ,R 5 2 9 p in 2 c o n n e c t io n f ro m + 5 V L t o + 3 V L 0 .2
73 6 CPU 1 1 /2 2 HW L in k P R O C H O T # b e tw e e n C P U a n d N B A d d R 5 9 c lo s e t o Q 2 0 .2
74 19 SB 1 1 /2 2 HW R e se rv e L P C C L K 1 fo r d e b u g c a rd fu n c tio n A d d R 3 0 8 2 2 _ 0 4 0 2 f o r U 1 5 .E 2 2 c lo s e t o R 3 6 2 .1 , re m o v e R 3 0 1 0 .2
2
75 26 E x p ress C a rd 1 1 /2 2 HW T o a v o id N e w C a rd S w itc h le a k a g e issu e A d d R 5 4 (0 _ 0 4 0 2 ) c lo s e t o U 2 1 .6 0 .2 2

76 28 A u d io C o d ec 1 1 /2 2 HW R e s e r v e S P D I F O U T 1 te st p o in t fo r v e rify A d d T 2 1 c lo s e t o U 2 7 . 4 5 0 .2
77 10~13 N B, 1 1 /2 3 HW B O M c o rre c t fo r S I -1 S M T b u ild U p d a t e U 3 ( S A 0 0 0 0 1 Z G 0 0 - - > S A 0 0 0 0 1 Z G 2 0 );U 1 0 ( S A 0 0 0 0 1 Z 3 0 0 --> 0 .2
S A 0 0 0 0 1 Z 3 1 0 );U 1 5 ( S A 0 0 0 0 1 S 5 1 0 - - > S A 0 0 0 0 1 S 5 6 0 )
78 19 SB 1 1 /2 3 HW C h a n g e C ry sta l R e s. siz e fo r la y o u t sp a c e C h a n g e R 3 8 9 f ro m 0 6 0 3 t o 0 4 0 2 0 .2
79 22 SB 1 1 /2 6 HW R e d u c e S B S A T A P o w e r C a p s (C o n firm w ith A T I F A E ) C h a n g e C 5 6 7 ,C 5 6 8 f ro m 1 0 U _ 0 8 0 5 t o 1 U _ 0 8 0 5 0 .2
80 28 C o d ec 1 1 /2 6 HW S P D I F 0 --> 1 d e sig n c h a n g e to fo llo w V a d e r C h a n g e U 2 7 .4 8 / 4 5 p in c o n n e c t io n 0 .2
81 34 T/P 1 1 /2 8 HW C h a n g e T / P P o w e r fo r re d u c e S 4 / S 5 p o w e r c o n su m p tio n R em ove R 235; A dd Q 85, R 645, Q 34 0 .2
82 14 HDMI 1 1 /2 8 A TI F i x H D M I n o fu n c tio n issu e R em ove R 102; A dd R 101 0 .2
83 15 C L K G en . 1 1 /2 8 HW C h a n g e d e sig n fo r n e w v e rsio n C L K G e n . R em ove R 1045 0 .2
84 28 C o d ec 1 1 /2 8 HW C h a n g e E C _ B E E P fu n c tio n b e c o m e re serv e R em ove R 563 0 .2
3
85 2 0 , 2 7 S B ,C a rd R ea d er 1 1 /2 8 HW D is c o n n e c t D 3 E s u p p o rt fo r A v e rsio n to a v o id risk R e m o v e R 8 1 ,R 3 6 9 0 .2 3

86 32 B IO S 1 1 /2 8 HW U se E x t. B I O S a s d efa u lt R em ove R 221 0 .2

87 34 LED 1 1 /2 8 HW C a n c e l W L A N / W W A N e x t p u ll h ig h R em ove R 1041 0 .2
88 19 SB 1 1 /3 0 HW F ix P A M / E I n te rfe re issu e fo r S I-1 c h a n g e Y 3 f ro m S J 1 0 0 0 0 1 U 0 0 t o S J 1 0 0 0 0 6 6 0 0 w it h 1 0 P P M 0 .2
89 0 6 ,1 9 , A TI A T I re c o m m e n d fo r u p d a te C h a n g e R 3 1 2 f r o m 0 _ 0 4 0 2 t o 3 3 _ 0 4 0 2 ; C h a n g e R 3 5 6 fro m 1 0 K _ 0 4 0 2 0 .2
SB 1 1 /3 0 t o 2 .2 K _ 0 4 0 2 ; I n s t a ll C 2 3 a s 0 .1 U F _ 0 4 0 2
23
90 33 KBC 1 1 /3 0 HW C h a n g e 3 2 .7 6 8 K H z M a in S o u rc e V e n d o r b e c o m e E P S O N C h a n g e Y 7 f ro m S J 1 0 0 0 0 1 V 0 0 t o S J 1 3 2 P 7 K 2 2 0 0 .2
91 32 B IO S 1 2 /0 3 HW C a n c e l E x t. B I O S re fla sh d e sig n b e c a u se of + 3 V L erroe A d d R 2 2 1 ; R e m o v e U 3 0 ,R 2 2 6 ,R 2 2 8 ,C 4 8 9 0 .2
92 34 LED 1 2 /0 3 HW C a n c e l G -S e n so r I N T 2 L E D fu n c tio n R em ove Q 156 0 .2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 1.C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 49 of 56
A B C D E
 A B C D E

V ersion C han ge L ist ( P . I. R . L ist ) for H W C ircuit

R e q u e st
Item P a ge# T it le D ate O w n er I s s u e D e sc rip tio n S o lu tio n D escrip tio n R ev.
01 19 SB 12/26 HW Remove R303 from PCICLK3 and add R301 as 0 ohm. 0.3
1 1

02 19 SB 12/26 HW Add R303 and connect to CLK_PCI_ISO2. 0.3

03 23 SB 12/26 HW Chage net name to PCI_CLK3. 0.3
04 29 Amplifier 12/26 HW Change value from 4.7uF to 1uF. 0.3
05 23 Speaker 12/26 HW Speaker right and left channel reverse. Reverse JP20 pin define. 0.3
06 31 Finger Printer 12/26 HW Delete R622 0.3
07 32 BIOS ROM 12/26 HW Reserve R221 0.3
08 32 BIOS ROM 12/26 HW Stuff U30, R228, R226, C489. Change power from +3VALW to +3VL 0.3
09 33 EC 12/26 HW Add pull down resistor R1063. 0.3
11 34 T/P ON/OFF LED 12/26 EC Common design. Reverse TP on/off LED 0.3
12 35 Docking 12/26 HW Change R572 to 22 ohm and R566 to 2K ohm 0.3
2
13 35 MDC 12/26 ME ME change stand off. Change PCB Footprint from 3P3 to 4P0 0.3 2

15 34 Switch board 01/03 HW Useless Delete R556, R557. 0.3

16 34 Switch board 01/03 HW Useless R1036 0.3
17 34 Switch board 01/03 HW Option Cypress and ENE Cap. board. Connect R1046 to JP36.3 and connect R1047 to JP36.9 0.3
18 33 EC 01/07 Power Connect VFIX_EN to EC pin 110. 0.3
19 14 SB 01/08 HW Add pull high resistor R1064. 0.3
17 Webcam and Digital MIC 01/08 HW Remove reserve circuit for Webcam and Digital MIC. 0.3
20
Change L61, L63, L66, L60, L67, L68, L69 to 0 ohm resistor.
01/08
21 22 SB HW Change C528, C543, C566, C504 to MLCC tpye.
Change C552 from 22uF to 4.7uF.
0.3
22 25 LAN 01/08 Realtek Chage part number from SA000026Q00 to SA000026Q10 0.3
23 31 USB port 01/08 Layout Swap D11, D12, L51 pin define per layout request. 0.3
24 19 SB 01/09 EMI Add reserve cap. C1085~C1087. 0.3
3 3

25 19 SB 01/09 EMI Fine-tune R302, R303, R308 from 22 ohm to 33 ohm. 0.3
26 20 SB 01/09 EMI Add reserve cap. C1088~C1091 0.3
27 21 SB 01/09 DFB Y4 Change Footprint to the same as Y2. 0.3
28 25 LAN 01/09 DFB Change Y5 Footprint to the same as Y2. 0.3
29 26 WWAN 01/09 EMI Add C738, C739, C740, C750, C751 as 39pF 0.3
30 33 EC 01/09 HW Connect AC_LED# to PQ3 0.3
31 35 M/B 01/09 ME Add screw hole. 0.3
32 36 DC-DC 01/09 HW Remove +1.2V and +3V circuit. 0.3
33 34 Switch board 01/10 HW Add R1065 and R1066 for OPP power button board 0.3
34 33 Keyboard connector 01/10 DFB Change Keyboard connector same as JBK00. 0.3
4
35 34 Lid switch connector 01/10 DFB Change Lid switch connector type. 0.3 4

36 34 Switch board 01/10 EMI Change R1048 and R1049 from 0 ohm to bead. 0.3
36 06 HDT debug port 01/14 AMD Stuff R26, R28 and R41. 0.3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 1.C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 50 of 56
A B C D E
 A B C D E

V ersion C han ge L ist ( P . I. R . L ist ) for H W C ircuit

R e q u e st
Item P a ge# T it le D ate O w n er I s s u e D e sc rip tio n S o lu tio n D escrip tio n R ev.
37 25 LAN 01/14 HW 8102E (10/100M 48 pin) can not support DSM function. Reserve Q1056, Q1057, C1077 and Q144. Change PJP605 to R1067. 0.3
1 1

38 33 EC 01/14 HW 8102E (10/100M 48 pin) can not support DSM function. Reserve R544 0.3
39 11 NB 01/15 HW No support daul channel panel. Remove LVDS signal of Channel B. 0.3
40 17 LVDS 01/15 HW No support daul channel panel. Remove LVDS signal of Channel B (remove C1061~C1063) 0.3
41 15 Clock GEN. 01/15 HW To slove noise issue. Chagne C1074~C1076 to 12pF 0.3
42 15 Clock GEN. 01/15 Vendor Clock Gen. spec. update Change R379 to 158 ohm and R380 to 90.9 ohm. 0.3

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 1.C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 51 of 56
A B C D E
 A B C D E

V ersion C han ge L ist ( P . I. R . L ist ) for H W C ircuit

R e q u e st
Item P a ge# T it le D ate O w n er I s s u e D e sc rip tio n S o lu tio n D escrip tio n R ev.
01 25 LAN 02/12 HW For ESD protect. Reserve D55. 0.4
1 1

02 34 S/W board connector 02/12 HW To avoid cap. sensor board abnormal. Reserve R558. 0.4
03 06 CPU 02/12 HW Reserve R59. 0.4
04 06 CPU 02/15 HW Follow Trinity design. Change CPU SM BUS from EC2 to EC1. 0.4
05 06 CPU 02/15 HW Reserve C16. 0.4
06 06 CPU 02/15 HW Follow Trinity design. Change R18 and R19 from 330 to 2.2K ohm. 0.4
07 07 CPU 02/15 HW Reserve C54. 0.4
08 12 NB 02/15 HW Remove L96. 0.4
09 12 NB 02/15 HW Change L12, L13 from bead to 0 ohm. 0.4
10 13 NB 02/15 HW Change L16, L18, L19, L22 from bead to 0 ohm. 0.4
11 13 NB 02/15 HW Remove L95. 0.4
2
12 24 Multibay connector 02/15 ME Change JP10 Footprint. 0.4 2

13 27 Card Reader 02/15 HW Change Card Reader LED active status. Reserve Q53 and R454, add R1070. 0.4
14 27 Card Reader 02/15 HW Change Card Reader LED active status. Reserve R112 and add pull low resistor R1069. 0.4
15 31 BT 02/15 ME Change JP32 Footprint and reverse pin define. 0.4
16 31 BT 02/15 HW Saving Power consumption. Change BT power source from +3VALW to +3VS. 0.4
17 33 EC 02/15 HW Remove JP34 and reserve R1068 for EC debug. 0.4
18 33 EC 02/15 HW To solve can't power on when first plug in AC adapter. Change R1040 from 100K to 10K ohm and connect to +3VL_EC. 0.4
19 34 Debug SW 02/15 HW Remove SW2. 0.4
20 34 TP LED 02/15 ME Add D19 for PR sku. 0.4
21 11 NB 02/18 HW Change R371 from 10K to 300 ohm. 0.4
22 11 NB 02/18 HW Add pull low resistor R1072. 0.4
3
23 19 SB 02/18 HW Reserve C1085 and R303. 0.4 3

24 21 SB 02/18 HW To solve can't power on when first plug in AC adapter. Add R1071 and D56 to connect to AC_IN. 0.4
25 32 SPI BIOS 02/18 HW Remove U30, C489, R226, and R228. Stuff R221. 0.4
26 34 WL/BT LED control 02/18 HW Modify circuit WLAN/WWAN/BT LED control. 0.4
27 33 EC 02/18 HW Follow Trinity design. Change R514 and R515 from 10K to 4.7K ohm. 0.4
28 35 Screw hole 02/19 ME To slove TP on/off button feeling no good when press. Add H57. 0.4
29 34 S/W board connector 02/19 ENE For ENE cap. board. Add LDO circuit (U65, R1073, C1097,C1099, J2). 0.4
30 34 S/W board connector 02/19 ENE For ENE cap. board. Change R554 pin 1 power plan from +3VL to +3VL_CAP. 0.4
31 34 S/W board connector 02/22 HW For cap. board. Add C1098. 0.4
32 11 NB 02/22 HW To splve CRT rising/falling fail issue. Reserve R62, R63, R64. 0.4
33 16 CRT connector 02/22 HW To splve CRT rising/falling fail issue. Change R211, R214 and R217 from 150 ohm to 75 ohm 0.4
4 4

34 16 CRT connector 02/22 HW To splve CRT rising/falling fail issue. Change C472, C476, C858 from 22pF to 6pF. 0.4
35 34 Lid switch connector 02/22 HW To solve short issue for lid switch board. Move C1100 and C1101 from lid swtich board to M/B 0.4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 1.C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 52 of 56
A B C D E
 A B C D E

V ersion C han ge L ist ( P . I. R . L ist ) for H W C ircuit

R e q u e st
Item P a ge# T it le D ate O w n er I s s u e D e sc rip tio n S o lu tio n D escrip tio n R ev.
36 25 LAN 02/22 DFB To solve kink pin to interfere with PCB. Update JRJ45 PCB Footprint. 0.4
1
37 35 Screw hole 02/22 DFB Change H53 and H54 from non PTH to PTH hole. 0.4 1

38 34 S/W board connector 02/22 EMI To solve EMI issue for ENE cap. board. Change R1048 and R1049 from bead to 0 ohm. 0.4
39 34 S/W board connector 02/22 EMI To solve EMI issue for ENE cap. board. Reserve R1074/C1102 for ESB_CLK1 and R1075/C1103 for ESB_DAT1. 0.4
40 33 EC 02/22 EMI To solve EMI issue for ENE cap. board. Add R1076, C1104 and R1077. 0.4
41 33 EC 02/22 EMI Add C1105. 0.4
42 36 DC/DC 02/25 EMI For EMI request. Add C1110~C1117. 0.4
43 31 USB connector 02/25 EMI For EMI request. Add C1109. 0.4
44 15 Clock GEN. 02/25 EMI For EMI request. Add C1106. 0.4
45 16 CRT Connector 02/25 EMI For EMI request. Add C1107. 0.4
46 17 LCD Connector 02/25 EMI For EMI request. Add C1108. 0.4
47 32 Debug connector 02/26 EMI For EMI request. Add C1118. 0.4
2 2

48 17 WEBcam LDO 02/26 HW To reduce power consumption in S3 mode. Add PJP6 to connect to +5VS. Stuff R1013 and reserve R1014. 0.4
49 34 Lid switch connector 02/26 HW Connect JP40 pin 4 to +3VALW. 0.4
50 06 CPU 02/27 POWER Change net name ENTRIP2 to EN0. 0.4
51 34 S/W board connector 03/03 EMI For EMI request. Change R558 to C1119 (0.1uF) 0.4
52 11 NB 03/03 EMI For EMI request. Change C1120 (0.1uF) 0.4
53 31 USB connector 03/03 EMI For EMI request. Change C1121 (0.1uF) 0.4
54 22 SB 03/03 HW Change L60, L61, L63, L66, L67, L68, L69 from 0 ohm to bead. 0.4
55 13 NB 03/03 HW Remove L20, L21 and use PJP604 to replace. 0.4
56 35 Docking connector 03/03 DFB Change JDOCK connector Footprint. 0.4
57 11 NB 03/03 AMD To support VariBright feature. Add D58 and connect to INV_PWM. 0.4
3
58 11 NB 03/03 AMD To support VariBright feature. Change backlight inform signal (R70, R1072) from LVDS_BLON to LVDS_ENA_BL. 0.4 3

59 33 EC 03/03 AMD To support VariBright feature. Change JDOCK connector Footprint. 0.4
60 06 CPU 03/04 AMD Reserve R175, R814, C939, Q127 and Q129. 0.4
61 19 SB 03/04 AMD To solve can not power on when use single core CPU. Change net name from H_PWRGD to H_PWRGD_SB. 0.4
62 20 SB 03/05 EMI For EMI request Add SSC circuit (U66, R1080, R1081, R1082, R1083, C1122) for HDA_BITCLK. 0.4
63 21 SB 03/06 AMD For eSATA GEN1 fail issue. Change C520 and C521 from 0.01uF to 1000pF. 0.4
64 21 SB 03/06 AMD For eSATA GEN1 fail issue. Change C520 and C521 from 0.01uF to 1000pF. 0.4
65 31 eSATA connector 03/06 AMD For eSATA GEN1 fail issue. Change C792 and C793 from 0.01uF to 1000pF. 0.4
66 17 LCDVCC circuit 03/06 HW To solve LCD power up sequence fail. Change R225 from 470 ohm to 220 ohm. 0.4
67 15 Clock GEN. 03/06 HW For IDT CLOCK GEN. Add C1123. 0.4
68 20 SB 03/06 HW To avoid CMOS data lose when shutdown suddenly. Add D58 and connect to 3/5V_OK. 0.4
4
67 15 WWAN connector 03/06 HW To support wake on WWAN feature. Add power on/off control circuit (Q167, R1087). 0.4 4

67 15 WWAN/WLAN 03/06 HW To avoid leakage power from SB. Add D59 and D60. 0.4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 1.C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 53 of 56
A B C D E
 A B C D E

V ersion C han ge L ist ( P . I. R . L ist ) for H W C ircuit

R e q u e st
Item P a ge# T it le D ate O w n er I s s u e D e sc rip tio n S o lu tio n D escrip tio n R ev.
1
68 20 SB 03/06 HW To solve can not power on if use CPU with single core Stuff R83. 0.4 1

69 11 NB 03/06 HW To support VariBright feature. Add R1085 and R1086. 0.4

70 25 LAN 03/06 HW To reduce power consumption in S3 mode. Stuff Q144, R1056, R1057, C1077 and reserve R1067. 0.4
71 33 LAN 03/06 HW To reduce power consumption in S3 mode. Stuff R544. 0.4
72 18 HDMI 03/07 HW To pass HDMI test. Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm. 0.4
73 18 HDMI 03/07 HW For EMI request. Reserve 0 ohm and stuff common choke. 0.4
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Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 1.C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 54 of 56
A B C D E
 A B C D E

V ersion C han ge L ist ( P . I. R . L ist ) for H W C ircuit

R e q u e st
Item P a ge# T it le D ate O w n er I s s u e D e sc rip tio n S o lu tio n D escrip tio n R ev.
1
68 20 SB 03/06 HW To solve can not power on if use CPU with single core Stuff R83. 0.4 1

69 11 NB 03/06 HW To support VariBright feature. Add R1085 and R1086. 0.4

70 25 LAN 03/06 HW To reduce power consumption in S3 mode. Stuff Q144, R1056, R1057, C1077 and reserve R1067. 0.4
71 33 LAN 03/06 HW To reduce power consumption in S3 mode. Stuff R544. 0.4
72 18 HDMI 03/07 HW To pass HDMI test. Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm. 0.4
0.4
0.4
0.4
0.4
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0.4
2
0.4 2

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3 3

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Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 1.C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 55 of 56
A B C D E
 A B C D E

V ersion C han ge L ist ( P . I. R . L ist ) for H W C ircuit

R e q u e st
Item P a ge# T it le D ate O w n er I s s u e D e sc rip tio n S o lu tio n D escrip tio n R ev.
1
68 20 SB 03/06 HW To solve can not power on if use CPU with single core Stuff R83. 0.4 1

69 11 NB 03/06 HW To support VariBright feature. Add R1085 and R1086. 0.4

70 25 LAN 03/06 HW To reduce power consumption in S3 mode. Stuff Q144, R1056, R1057, C1077 and reserve R1067. 0.4
71 33 LAN 03/06 HW To reduce power consumption in S3 mode. Stuff R544. 0.4
72 18 HDMI 03/07 HW To pass HDMI test. Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm. 0.4
73 33 EC 09/10 HW Avoid DOCK_VOL_UP# and DOCK_VOL_down# folating R589 R590 use 10k ohm pull high 1.0

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Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4117P 1.C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 16, 2009 Sheet 56 of 56
A B C D E