Industrial Automation Lab Date:27-02-2019

LAB#06
Objective:
Ladder Logic Programming III
 Implementation of Counter

Equipment and Components

 Fatek FBs14MA
 Winproladder

Theory:
Counters
Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known
counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock
signal applied. Counters are of two types
 Asynchronous or ripple counters.
 Synchronous counters.
Asynchronous or ripple counters
The logic diagram of a 2-bit ripple up counter is shown in figure. The toggle (T) flip-flop
are being used. But we can use the JK flip-flop also with J and K connected permanently to
logic1. External clock is applied to the clock input of flip-flop A and QA output is applied to the
clock input of the next flip-flop i.e. FF-B.
Logical Diagram

Synchronous counters
If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a
counter is called as synchronous counter.

2-bit Synchronous up counter

The JA and KA inputs of FF-A are tied to logic 1. So FF-A will work as a toggle flip-flop. The
JBand KB inputs are connected to QA.

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Industrial Automation Lab Date:27-02-2019

Logical Diagram

Classification of counters
Depending on the way in which the counting progresses, the synchronous or asynchronous
counters are classified as follows

 Up counters
 Down counters
 Up/Down counters

UP/DOWN Counter
Up counter and down counter is combined together to obtain an UP/DOWN counter. A mode
control (M) input is also provided to select either up or down mode. A combinational circuit is
required to be designed and used between each pair of flip-flop in order to achieve the up/down
operation. Type of up/down counters

 UP/DOWN ripple counters

 UP/DOWN synchronous counter

UP/DOWN Ripple Counters

In the UP/DOWN ripple counter all the FFs operate in the toggle mode. So either T flip-flops
or JK flip-flops are to be used. The LSB flip-flop receives clock directly. But the clock to every
other FF is obtained from (Q = Q bar) output of the previous FF.

 UP counting mode (M=0) − The Q output of the preceding FF is connected to the clock
of the next stage if up counting is to be achieved. For this mode, the mode select input M
is at logic 0 (M=0).

 DOWN counting mode (M=1) − If M = 1, then the Q bar output of the preceding FF is
connected to the next FF. This will operate the counter in the counting mode.

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Industrial Automation Lab Date:27-02-2019

Counter in FATEK PLC

There are total 200 16-Bit counters (C0~C199). The range of preset value is between
0~32767. C0~C139 are Retentive Counters and the CV value will be retained when the PLC
turns on or RUN again after a power failure or a PLC STOP. For Non Retentive Counters, if a
power failure or PLC STOP occurs, the CV value will be reset to 0 when the PLC turns on or
RUN again.
There are total 56 32-Bit counters (C200~C255). The range of the preset value is between
0~2147483647. C200~C239 are Retentive Counters and C240~C255 are Non Retentive Counters.

When "CLR" is at 1, all of the contact Cn, FO0 (CUP), and CV value of the counter CV are
cleared to 0 and the counter stops counting.
When "CLR" is at 0, the counter is allowed to count up. The Counter counts up every time
the clock "CK" changes from 0 to 1 (adds 1 to the CV) until the cumulative current value is
equal to or greater than the preset value (CV>=PV), the counter "Count-Up" and the contact
status of the counter Cn and FO0 (CUP) changes to 1. If the input status of clock continues to
change, even the cumulative current value is equal and greater than the preset value, the CV
value will still accumulate until it reaches the up limit at 32767 or 2147483647. The contact Cn
and FO0 (CUP) stay at 1 as long as CV>=PV unless the "CLR" input is set to 1.
In WinProladder software counter is shown by the block

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Industrial Automation Lab Date:27-02-2019

Up / Down Counter in Fatek PLCs

In WinProladder software Up / Down counter is similar to a simple counter, but U/D
terminal is added to its existing terminal. If U/D is fixed as 1, the instruction will become a
single-phase up count counter. If U/D is fixed as 0, the instruction will become a single-phase
down count counter. When the clock “PSU” is 0→1 (rising edge), the CV will increased by 1 (if
U/D=1) or decreased by 1 (if U/D=0).
When the clear control “CLR” is 1, the counter’s CV will be reset to 0 and the counter will
not be able to count. When the clear control “CLR” is 0, counting will then be allowed. The
nature of the instruction is a P instruction.
When CV=PV, FO0(“Count-Up) will change to 1”. If there are more clocks input, the
counter will continue counting which cause CV≠PV. Then, FO0 will immediately change to 0.
This means the “Count-Up” signal will only be equal to 1 if CV=PV, or else it will be equal to 0.
The upper limit of up count value is 32767 (16-bit) or 2147483647 (32-bit). After the upper
limit is reached, if another up count clock is received, the counting value will become –32768 or
-2147483648 (the lower limit of down count).
The lower limit of down count value is -32767 (16-bit) or -2147483647 (32-bit). After the
lower limit is reached, if another down count clock is received, the counting value will become
32768 or 2147483648 (the upper limit of up count).

Tasks:
Task 1
Write a program to turn on light after 6 events and to turn it off after 10 seconds. Even may
be treated as two normally open switches.

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Industrial Automation Lab Date:27-02-2019

Task 2
Design a ladder logic diagram that will use a counter elements as one UP/DOWN counter to
keep track of the cars in a certain parking plaza. If the numbers of cars exceed a certain value
(say 3), CAR LOT FULL light should be light up.

Conclusion:
In this we learn about counter, how counter count reading from Sensors.

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