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6 COMPUTER ORGANIZATION VTUNOTESAYSRE MODULE 1: BASIC STRUCTURE OF COMPUTERS BASIC CONCEPTS = Computer Architecture (CA) is concemed with the structure and beneviaur of the computer: + CA‘incluces the information formets, the instruction set and techniques for addressing memory, sin general cavers, CA covers 3 aspects of computer-design namely: 1) Computer rerdare, 2) Instruction set architecture end 3) Computer Orgarization| 1. Computer Hardware ¥ It consists of electronic circuits, splays, magnetic and optical storage media and Commrunication factties, 2. Instruction Set Architecture Fe is programmer visible machine interface such as instruction set, regsters, memory organization and excention handling > Two main approaches are 1) CISC and 2) RISC. (CISC3Cemplex Instruction Set Cernputer, RISC-Reduced Instruction Set Computer) 3. Computer Organization > Ikincludes the nigh level aspects of 2 design, such 25 + memory -system bus stricture & — design of the internal PU. » 1 refers to the operational uni’s and ther interconestions that realize the architectural speattications. > It describes the functon cf and design of the various units of digital computer that store and process in‘oration. FUNCTIONAL UNITS ‘8 computer consists of 5 functionally independent main parts: 1) Input 2) Memory 3) aw 4) Output & 5) Control units Dap w Figure 1.1 Bec hction vit a compa: 6 COMPUTER ORGANIZATION ae MAIN PARTS OF PROCESSOR + The processor contains ALU, control-crcuitry end many registers 1 The processor contains i” general-purpose registers Re through Rey 4 The IR holds the Instruction thet fs currently being executed + The controF-unit generctes the tining-signas that detesmine when 2 given action isto take place. ‘The PC contains the memory-adaress of the nex-instructon to be fetched & executed. * During the execution ef an instruction, the contents of PC are updated to point to next instruction ‘The MAR holds the address of tie memery-location to be accessed. ‘The MOR contains the deta to be written ito or read out of the addressed locaton. ‘+ MAR and MOR faciitates the communication with memory. GR > Instruction-Reaister, PC > Procram Counter) (MAR > Memory Acdress Register, MOR-> Memory Data Recister) STEPS TO EXECUTE AN INSTRUCTION 4) The address of first instruction (to be executed) gets loaded into PC. 2) The contents of PC (j.<. address) are transferred to the MAR & contral-unit issusc Read signal to mremey. 3) After certain amount of elapsed time, the first instruction is read out cf memory and placed into Mor, 4) Mex, the contents of MOR are transferred to JR. AL this point, the instruction can be decoded & executed 5) To fetch an operand, i's address Is placed into MAR & control-untt Issues Read signal. AS a result, the operand is transferred fram memery into MDR, and then its transferred fram NDR to ALU, 6) Lkewse required number of operands is fetched into processor. 7) Finally, ALU performs the desires operation 8) Ifthe result of ths operation is to be stored in the memory. then the results sent to the MOR. 98) The adcress of the location where the result is to be stored is sent to the MAR and a Write cyde is intiated 410) At some point during execution, contents of PC are incremented to point to next instruction in the procram, 2] Ls) “Figure 1.2. Connector bswoen bo promssr and he main memory 6 COMPUTER ORGANIZATION VTUNOTESAYSRE BUS STRUCTURE us is © graup of lines that se-ves as a connecting path for several devices, +A bus may be lines or wires, 1 The lines Carty data or address or contra signal ‘+ There are 2 types of Bus structures: 1) Single Bus Structure and 2) Multiple Bus Strucure, 2) Single Bus Structure * Because the Dus can be used for only one transfer at a time, only 2 units can actively use the bus at any given time. > Bus contral nes are used to arbitrate mutiple requests for use of the bus > Advantage: 1) Low cost & 2) Flexibilty for attaching peripheral devices. 2) Multiple Bus Structure 2 ‘Systems that contain multiple buses achieve more concurrency in eperstions. 2 Two or more trarefers can be carried aut at the same time. 2 Advantage: Batter performance > Disadvantage: Increased cost np Oupet Memory Procescr Fiquee 1.3 Singlebes sructore + The davices connected to a bus vary widsly in ther spaed of aparation. + To synchronize their operational-soeec, bulfer-regisiers can be used. + Buffer Registers — ere included with the devices to hod the informetion during transfers. — prevent a high-speed processor (rom being locked 10 a slow 1/0 device during data transfers. 6 COMPUTER ORGANIZATION ae PERFORMANCE + The most important measure of performance of 8 computer is how quick it con execute programs. $ The speed of computer is affected by the design of 1) scruction-set 2) Hardware & the technology in which the hardware is implemented. 53) Software including the opersting system. + Because programs are usually written in HLL, performance is also affected by the compiler that translates programs into machine language. (HLL High Level Language). + For best performance, itis necessary to design the compiler, machine instruction set and hardware in a co-ordinated way. [cate] senor {nenon] tow Figo 1.5 Te procener coca + Let us examine the flow of orogram instrucicns and data between the memery & the processor. ‘At the start of execution, all proaram instructions are stored in the main-memory. 1 As execution proceeds, instructions are fetched into the orocessor, and 2 copy is placed in the cache. | Later, f the came instruction is needed 2 second time, itis read direct fram the cacke 2 A\program willbe executed faster if mavement of instruction/data between the main-memory and the processor is minimized hich is achieved by using the cache. PROCESSOR CLOCK + Processor drauls are controlled by @ tiring signal called a Clock. he lack defines regular time intervals callec Clock Cycles. 4 To execute 3 machine instruction, tie processor divices the action to be performed into 3 sequence of basc steps such that each step can be completed in ane cock cycle. Let P = Length of one clack cycle R= Cock rate, «Relation between P and R is civen by P +R is measured in cydes per second * Cyclas per second is also called Hertz (Hz) BASIC PERFORMANCE EQUATION Let T= Processor time required to executed a program. N= Actual number of inetruction executions SS = Average number of basic steps neaded to execute ene machine instruction. R= Cock rate in cycles per second, + The program execution time is given by 4) + Gait is referrec to as the baste performance equation: + To achieve high performance, the computer designer must reduce the value of 1, which means reducing Nand, and increasing R. > The valve of Nis reduced if source program is compiled into fewer machine instructions. > The value of Sis reduced if instructons have a smaller number cf basic steps to perform. > The value of R can be increased by using a higher frequency coc ‘Care has to be taken vhile modifying values since changes in one parameter may affect the other. COMPUTER ORGANIZATION ae Problem 1: Represent the decimal values 5, -2, 14, -10, 26, -19, St and -43 as signed 7-bit numbers in the following binary formats (@) sign-and-rreanitude (b) 1's complement (©) 2s-compement Solution: “The three binary representations are given 2s Decimal | Signand-magnitude | 1'scomplement | 7+-complement values presentation | representation | repreeutation 5 ooo nono nono 2 1000010 nani0L m0 4 001110 ooniti0 oooiti0 0 1001010, nuwoio1 mDLI0 2% oori010 onni010 onni010 0 o10ont 10110 no1ior st onion, ouo011 onto a ni010n 01010 ro10101 Problem 2: (@) Convert the fllowing pairs of decimal numbers to S-bit 2's-complement numbers, then edd then, Slate whether or net overflow occurs in each case. 2) 5.21019 by? and 13 cj-14ancu. =)“ ane7 6) -3and-8 (b) Repeat Problem 1.7 for the subtract operation, where the second number cf each pairis to be subtracted fram the first number. State whether or nct overflow accurs in each case. Solution: @) (a) oot) emt (e) 10010 100 1101 oon oun 10100 uo moorerfon ——werflae no ovetlow 4 uo) Gy) tH + ont 1000 10011 cnn0 0101 001 soon mo orton ono (b) To subsract the secenc number, form its 2's-complement and add itto the first number. *) 0101 (%) OMNI fe) 10010 + 10110 + 10011 10101 no 11010 oon 1 overt ett avert @ won (er) 010 + 1001 1000 onto! 1100 oor! 011 vo ovetom wo cmatlow mo ometiow COMPUTER ORGANIZATION Problem 3: vrunoresayser Perform following operations on the 6-bit signed numbers using 2's complement representation system. Also indicate whether overfiow has cccurred. Solution: oot nunnt0 100101 100001 oniot un oon 00111 111000 100 se101r -+pig01, 100101 ortoot sont +0100 =:1H10n 100 111110 OL 100101 mint owt nou +1001 T0600 10110 + 100001 on nite soure11 100001 + 100011 waTK overt nimi + 111001 Tn ‘00111 001000 Trier oom mint umn 10101 mun 00011 worn 10101 01011 OT D +2) 7 6 COMPUTER ORGANIZATION VTUNOTESAYSRE MODULE 1 (CONT.): MACHINE INSTRUCTIONS & PROGRAMS MEMORY-LOCATIONS & ADDRESSES Memory consists of rary milions of storage cells (fip-flops). + Esch call can store 2 bt af information i.e. 0 or 1 (Figure 21) 1 Each group of n bits is rarred to-ae a word of irformaton, and n iz called the word length. 1 The word length ean vary from 8 to 64 bits, + A unit of 8 bits is called & byte. + Accessing the memory to store or retieve @ single item of informetion (word/byte) requires distinct Gddresses for ech item location. (It is customery to use numbers from 0 through 2-1 35 the addresses of successive-localians in the memory). sir2"=no, of adaressaole locations} ‘then 2" addresses consttute the adress-space cf the computer. For example, 2 24-bit address generates an address-space of 2* locations (16 MB). _——| for poe mambo lor ecpine mio (a Aig ger (38 eT oe Figure 2.2 Examples enmaded information no SLb# word 6 COMPUTER ORGANIZATION ae BYTE-ADDRESSAGILITY inbyte-aderessable memory, successive addresses refer to successive byte locations in the memary. + yte locations have addresses 0, 1,2. Ifthe word-length is 32 bits successive words are located at addresses 0, 4, 8. . with each word having 4 bytes. BIG-ENDIAN & LITTLE-ENDIAN ASSIGNMENTS «There are two nays in which byte-addresses are arranged (Figure 23). 11) Big-Endian: Lower byte-addresses are used for the more sicnicant bytes of the word, 2) Little-Endian: Lower byte-addresses are used for the less significant bytes of the word +n both cases, byte-addresses 0, 4, 8... .. are taken as the addresses of successive words in the memory. wide Bye dies Ryteados (2) Big onan seegnmant (2) Lmie-ondanassignrt Figure 2.3 byteond werd adening + Consider a 32-bit integer (in nex): 0x12345678 which consists of 4 bytes: 12, 34, $6, and 78. > Harice this irteger will o=cupy 4 bytes in memory. > Assume, we store it at memory adcress starting 1000. > Oniittle-endian, memory wil look ike ‘Agdress | Value 3000 | 78 001 56 3002 | 34 (003 42} » On big-endian, memory wil 'ook ike ‘Aadross | Value 1000 [43 soos a 003 se. 003 178 WORD ALIGNMENT. + Words are said to be Aligned in memory if they begin at a byée-address that is a multiple of the rhumber of bytes in 2 word For exainple, > I the word length is 16(2 bytes), aligned words begin at byte-acuresses 0, 2, 4 > the word length is 64(2 ytes), allgned words begin at byte-acdresses 0, 8, 16 |. + Words are said to have Unaligned Addresses, ithey begin at an artitrary pyte-address. 6 COMPUTER ORGANIZATION VTUNOTESAYSRE [ACCESSING NUMBERS, CHARACTERS & CHARACTERS STRINGS + A number usually occupies one ward. Tt can be accessed in the memory by specifying its word address. Similarly, individual charaders can be accessed by their byte-address, = There are to nays indicate the length of the sering 11) A special Control character with the meaning "end of sting" can be used as the last character inthe sting 2) A separate merrory word location or register can contain a number indcating the length of the string in bytes, MEMORY OPERATIONS ‘Two memory operations are: 1) Load (Read/Fetch) & 2) Store (Wrte) «+ The Load operation transfere a copy of the contents of 2 specific memory-location ta the processor. ‘The memery contents remain unchanged. + Steps for Load operation 1) Freceszor-sends the address ofthe desired location ta the memory. 2) Processor issues ‘read’ sighel to memory to feich the data. 5) Nemory reads the data Stored at that adress 4) Memory sends the read data to the processor. + The store operation trarsrers the informaton from che register to the specifies memary-location. “This will destroy the original contents of that memory-location, + Steps for Store operation are 1) Processor sends the address of the memory-lacation where it wants to store cata. 2) Processor issues ‘write signal to memory to store the cata. 3) Content of regster(MDR) s written into the specified memory-lacation INSTRUCTIONS & INSTRUCTION SEQUENCING ‘= computer must have instructions capable of parforming 4 typas of operations: 1) Data transfers betwean the memory ard the ragisters (MOv, PUSH, POP, XCHG). 2) Arithmetic anc logis operations on data (ADD, SUB, NUL, DIV, AND, OR, NCT). 5) Program sequencing and control (CALLRET, LOOP, INT) 4) votrarsfers (IN, GUT). 6 COMPUTER ORGANIZATION ae REGISTER TRANSFER NOTATION (RIN) + The pessbie locations in which transfer of infermation occurs are: 1) Memery-location 2) Processor Feyister & 3) Registers in YO device Location | Hardware Binary Acdress | Example Description marory LOC, PLACE, RU [Rete ‘Gnients of memor-tocation LOC] ‘are transferred Into register Ru Processor | RO, RI FZ TEST © TRITFIRAY | Ada the contents of register x GAZ ‘apd places thelr sum into RS. tents of YO ‘eater DATALIY a Uansferred int register 2. [70 Reaiszers | ASSEMBLY LANGUAGE NOTATION ‘To represent machine instructions and programs, assembly language format is used ‘Assembly Language Format Description. Move LOC, Ri ‘Trasfer data from marmory location LOC to register Ri. The cortents of LOC are unchanged bythe execution 0! this instruction, 9ut the ol corerts of Fegister Rare cverwriten. REGRI, FE, RS ‘Add the contents of reqisterS RZ and RZ, and places thelr Sum rto register BASIC INSTRUCTION TYPES Instruction | Syntax Example | Description Instructions ‘Type for ‘Operation cx{al+16} | Thre ‘Opeade Spircel Souree2,Desthation | AGZABC Add the contents a aearess ‘memory-beations 4 8B. ‘Then, place the resut into location “Two AGGTESS | OpCoGe SHU, Destination ‘GERB—[ Rag the — contents —a| Nove B,C memory-beatons ABB. © | AdaA,C ‘Then, place the resut into location By replacing the frighal contents of ths focatton. ‘Operand 8 's both 2 source ‘anda destination ‘One Address | Opcode Souce/Deaination Toad | Copy contents of memory | Load A focalon Aino scumulawr, | Add ‘de® [Add contents of memory. | Store focation to ‘contents of ‘accumulavor register ploce cum ‘back nt Secular, Stare | Copy the contante af the Secumlatr inte location ©. Bare ‘peed [he Sourea/Bezinaton) Pach Leeations ef all operanas | Nat poceble edocs are dofined imply ‘The operands are stored In ‘a pushdown stack ‘= Access to data in the registers if much faster than fo data stored in memory locations Let Ri represent a general-purpose register. The instructions: Load Ai ‘Store Ria are generalizations of the Lead, Store and /idd Instructions for the singla-accumulator case, in which register Ri performs the function of the accumulator. ‘In processors, where arithmetic operations as allowed only on operands that are in registers, the task C="{A}+1B] con be performed by the instruction sequence: ‘Nowe 48 ‘Noe 5,8) 2a 8 owe 8.2 6 COMPUTER ORGANIZATION VTUNOTESAYSRE INSTRUCTION EXECUTION & STRAIGHT LINE SEQUENCING + The program's excaited as follows 4) hilialy, the address of the first instruction is loeded into PC (Figure 2.8). 2) Then, the processor control circuits use the Information In the PC to fetch and execute insvuctions, one at 2 time, In the erder of increasing addresses. This Is called Straight-Line sequencing. 3) During the execution of each instructon, PC is incremented by 4 to point to next instruction. ‘There are 2 phases for Instruction Execution: 11) Fetch Phase: The instruction is fetched from the merrary-iocation and placed in the IR 2) Execute Phase: The contents of IR is examined to determine which cperation is to be Performed. The specified-operation is then per‘ormed by the processor. ’ Moe NOMI «(Tana egncaemtin ee = 4 ct ‘ve| ae) pe |__| tes ton aE — feta] nat - iste [ie asi oo j | sm , => so Tm we Cd Fett Apmgamtoc AB Sent? handabe ares angen Program Explanation + Consider the program for adding e lst of n nurmbers (Figure 2.8). The Address of the memery-locetions containing the n numbers are symbolically given 2s NUML, uz... NUM. + Seperate Add instruction is used to add each number to the contents of register RO. ‘After all the numbers have been adcec, the result is placed in menory-location SUN. 6 COMPUTER ORGANIZATION ae BRANCHING ensider the task of adding a list of 'n’ numbers (Figure 2.10). {Number of entries in the ist nfs stored in mermery-locetien Nv. + Register RA is Used as @ counter to determine the humber of times the loop Is executed. + Content-iocation Ns loaded into reaister RL atthe beginning of tie progrem. ‘The Loop is streight line sequerce of instructions executed as many times as needed. “The lcop starts at location LOOP and ends at the instruction Branch> 0. ‘During each pass, = adress ofthe next list ertry is determined ard = that entry is fetched and added to 80. ‘The instruction Decrement Ri reduces the contents of R1 by 1 eachttime through the foop, + Then Branch Instruction loads a new value into the progam counter. As a result, the processor fetches and executes the instnicton 2 this new address called the Branch T + A Conditional Branch Instruction causes a branch only if 2 s3ecihed condition is satisfied. f the Condition is net satisfied, the PC is incremented in the normal way, and the next instruction in Sequential address order is fetched and executed. a I swe ate ages 2.10 Wang oop ald nba, ‘CONDITION coDt The processor Keeps track of Information about the resus of verlous operations. This ‘cccrmplishes by recording the requrred information in Individual ois, called Condition Code Flags. * These flags are grouped together in a spacial processar-register called the condition coce register (or statue register). ‘Four commonly used flacs are: 1) N (negative) set to 1 if the result is necative, otherwise cleared to 0. 2) Z (zero) set to 1 if the result is 0; otherwise, cleared to 0. 3) V (overflow) set to 1 if arithmetic overflow occurs; otherwise, cleared to 0. 4) C (camry) set to 1 if a carry-out results from the aparstion; otherwise cleared ta 0. 6 COMPUTER ORGANIZATION VTUNOTESAYSRE ‘ADDRESSING MODES * The different ways in which the location of an cperand is specified in an instruction are referred to as Addressing Modes (Table 2.1) able 2.1 Genceadsng moter — Tatiergaas Aden co ae Roper u canes Ate ie) LOC eam toc a wy) tae 109) eA=BOG Inder oy Baw mile time win R)) PAu ue wi nd RL) Ee Bu BUY X tethe ete x9 taaraet Aucinnen BE emt Tet 8 Aware) a Ao [asain Vee ep ter IMPLEMENTATION OF VARIABLE AND CONSTANTS + Variable is represented by allocating a meory-location to hold its value. ‘Thus, the value can be changed as needed using appropriate instructions. ‘There are 2 accessing modes to access the variables: 1) Register Mode 2) Absolute Mode Rogistor Mode + The operand is the contents of regster. + The name (or address) of the register is given in the instruction. + Registers ave used es temporary storage locations where the dats in a register are accessed + For exemple, the instruction Move Rl, R2 Copy content of register RA Into register R2. Absolute (Direct) Mode ‘The operand is na memory-location. ‘The address of memory-location is civen explicitly inthe instruction. ‘The absolute mode can represent global varizbles in the program. + For example, the instruction ‘Move LOC. R2 ‘Copy content of memery-location LOC into reaister 82. Immediate Mode + Tre operand is given explictly in the instruction. + For example, the instruction ‘Move #200, RO _;Place the value 200 in register RO. + Clearly, the immediate mode is orly used to specify the value of a source-operand. 6 COMPUTER ORGANIZATION ae INDIRECTION AND POINTERS + Instruction dees not give the operand orits adcress explicitly + trotead, the instruction provides infermation from which the new address of the operand can be determines. = THs address is called Effective Address (EA) of the operand. Indirect Mode + The BA of the operand isthe contents of a register(or merrory-locaton). ‘The resister (or memory-locaticn) that contains the address of an opeand is called a Pointer. + We denote the indirection by = rame of the register or — rew address aven inthe instruction. Eg: Add (R1).RO The operand is in memory. Revister R1 gives the efective-address (8) of the operand. The data is read fram location B and adéed to contents of resister PO a KD a0 ie entry | 5 Onna } a * ” . Regie » Opa (@) Though general pups ier (0) Mreugnamencr ceo Figun 2.11 lndvct orang, + To execute the Add instruction in ig 2.11 (a), the processor uses the value which isin register Ri, as the EA of the operand. 4 Terequests 3 read cperation from the memcry to read the contents of location B. The value read is the desired cperand, uhich the processor adds to the contents of register RO. * Indirect addressing through 2 memory-location is alse possible az chown in fig 2.11(b). Tn this case, the processor first reads the contants of memory-location A, then requests 2 second read operation Using the value B ac an address to ebtain the operand. oy ext { totatce " (rate a ut oo asm Figen 12 Un del ening he woyon sie? 0 Fypeerey Program Explanation ‘In above pregram, Register R2 is used as a pointer to the numbers mn the Ist, and the operands are accessed Inairecty trough Fo. ‘The inibalzation-setion ofthe program loads the courter-value from memory-lecation N Inte RL and uses the iinmedate adcressing-move 10 place the address value NUMA, whieh Is the adoress of Ue frst number nthe Uist, Into R2. Then le dears RO to G ‘The firs vo Instructions in the loop implement the unspecied instruction block startng at LOCP. ‘The frst ume tirough the oop the instruction Add (R2), RO fetches the operand at location NUM and adds to 1 The second Ads instructon adds 4 to the contents of the pointer R2; so that It will contain the addiess value FNUMG when the above instruction & executed in the second pass ty ough tre lon. 6 COMPUTER ORGANIZATION ae INDEXING AND ARRAYS + A different kind of flexibility for accessing operancs is useful in dealing with lists end rays. Index mode + The operation is indicated as X(RI) where X=the constart value which defines an offset(also called a displacement) Risthe name of the index register which contains address oF @ new location, 1 The effective-acdress of the operand is civen by EA=X+[Ri] The contents of the index-register are not changed in the process of generating the effective- ‘address. ‘The constant X may be given either ~as.an expict number o- as. symbolic-neme representing a numerical value. Tas aR Ta Ton ccs + = Lee Ll (aoe yr asco (0) Ot taper Fipre 23 bd ag += Fig(a) illustrates two ways of using the Index mode. In fig(a), the Index register, RL, contains the adaress of a memory-location, and the value X cefnes an offset(also called a asplacement) ‘rom this ‘daress to the location where the operand is Found. To fing EA of operand: Eg: Add 20(R1), 82 FA=>1000+20=1020 + An alternative use is ilustrated in flab). Here, the constart X corresponds to a memory address, and the contents of the index register define the offset to the operand. In either case, the effective-edaress is the sum of two values; one is civen explicitly in the instruction, enc the other is stored in 2 register. = ‘ z = © = oa = 5 rs we ust+# heat? secon! oor Aa ae oe unten as vn ‘amas Sone s = = a 5 Ta? ‘Sede? Bentod LOOP. = he bcd Move RESUME = oo Tel banacideg doce Rose LM Aki sade’ mas Jos sens iain ae? 1 6 COMPUTER ORGANIZATION ae Base with Index Node + Another version of the Index mode uses 2 registers which can be denoted as (Bi, Ri) + Here, a Second regtster may be used to contain the offset. 1 The Second register 's usualy called the Dase register 4 The etfecive-acaress of the operand Is clven by EA=[8i)+(R] + Thisfarm oF indexed addressing provides more flexibility in accessing operands because bath comporents ofthe effective-address can be changed. Base with Index & Offset Mode « Another version of the Index mode uses 2 reaisters plus @ XR, Ri) «The effective-address ofthe operand is civen by FA=X+(Ri]+CRi] * This added flexbilty is useful in accessing multiple corrpenents inside aach item in a record, where the beginning of an item i specified by the (Ri, Rj) part of the addressing-mode. In other words, this ‘mode implements 3 3-dimensional array. stant, which can be denated as RELATIVE MODE + This is similar to index-mmode with one diference: “The effective-adress Is determined using the PC In place of the general purpose register Rl + The operation is indicated as X(PC), + X(PC) denctes an eifective-adéress of the operand which Is X locations above oF below the current Contents of PC. + Since the adaressed-location is identified ‘reative" to the PC, the name Relative mode is associated with this type of addressing. ‘This mod= is used commaniy in conditional branch instructions An instruction such as Branch > OLOOP —_; Causes program execution to go to the branch target location identified by name LOCP if branch cencition is satisfied ADDITIONAL ADDRESSING MODES 41) Auto Increment Mode > Cifective~adcress of operand is contents of a register specified in the instruction (Fig: 2.16) > after accessing the cperanc, the contents of this register are aucomatically incremented to point to the next item in 2 ist. » Implictly, the increment amount Is 1. > This mode is denoted as (R)+ where Ri-pointer-register. 2) Auto Decrement Mode > The comtents of 2 reqister specified in the instruction are first automatically decremented and are then used as the effeciive-address of the operand. This made is denoted as (Fi) where Ri=painter-register > Thee 2 modes can be Used together to implament an important data structure called a stade Tw NET Move NUMLRZ nice Ce a Davenen Rl eco LO? eres Te Arar odvina mode wed te wovon lane 212 COMPUTER ORGANIZATION ‘ASSEMBLY LANGUAGE + We generally use symbolc-names te write 3 program. +A complete set of symbotcnemes and rules for their use constitute an Assembly Language. 2 The set ef ules for using the mnernonics in the spedtication of complete inst Giled the Syntax of tie language 6 vrunoresaysar fons and programs is = Programs written in an assembly language can be sutomatically translated into a sequence of rrachine instructions by a program called an Assembler. = The user pregram in its original alphanumeric text formal is called 2 Source Program, anc the assembled machine language program is called an Object Program. For example: ‘MOVE RO,SUM ;The term MOVE represents OP code for operation performed by instruction. ADD 5,83, ASSEMBLER DIRECTIVES ‘Adds number 5 to cortents of register R3 & puts the result back into registerR3. * Directives are the assembler commands te the assembler concerning the program being assembled. 1 Theee commands are not translated into machine opcede in tre object-program. Meno ‘aren ie de Intel Cpentin eestor Keele decivs SOM 2QU 2 fonuome a NDATAWORD am NIM RSE m onion Staenese that START. MOVE RL — Move gv factine aR fo feted LOOP ADD (RRO apd alt be | wom = Loop MOVE ISU Amc deste RETURN IND sTART Te bit_Aeby mem roromrtn fr pono P= ‘+ EQU informs the assembler about the value of an identifier (Figure: 2.18). Be: SUM £QU 200 “Informe assembler that the name SUN should be replaced by the value 200, + ORIGIN tals the accombler abaut the starting-address of memory-araa to piace the data block. Ex: ORIGIN 204 instructs assembler to intiste data-black at memory-locations starting fram 204. + DATAWORD directive tells the assembler toload 2 value into the lecation, Ex: NDATAVORD 100 jinforms the assembler te lead data £00 into the memory-location N(204). {RESERVE directive fs used to reserve a beck of memory. Ex: NUM RESERVE 490 ;dedares 2 memoty-Ulo:k of 400 bytes 's to be reserved for date. {END directive tells the asserrbler that this 's the end of the source-prograin text. + RETURN difective identifies tne point at which execution of the program should te terminated, ‘ Any statement that makes instructions or data being placed in a memory-\ocation may be civen 2 label. The labe\(say N or NUM1) is assioned 3 value equal to the acdress of that location. GENERAL FORMAT OF A STATEMENT ‘# Most assembly languages requite statements in a scurce program ta be written in the form: Label | Operation | Operands | Comment 41) Label ic an optional name ascociated vith the memory-aderess where the machine language instruction produced from the statement vill be loaded. 2) Operation Field cortains the OP-code mnemoric ofthe desired instruction or assembler. 3) Operand Field contains addressing information fer accessing ans or more cpersnés, depending on the type ef instruction 4) Comment Field is used for documentation purposes to make progrem easier te understand fr COMPUTER ORGANIZATION Ea BASIC INPUT/OUTPUT OPERATIONS * Consider the problem of moving a character-code from the keyboard to the processor (Figure: 2.19). For this transfer, buffer-register DATAIN & a status control fags(SIN) are used + When 2 key is pressed, the corresponding ASCII code is stored in a DATAIN register associated with the keyboard. [> SIN=1 > When a character is typed in the keyboard. This informs the processor that 2 valid character is in DATAIN. SIN=0 > When the characteris transferred to the processor. + An analogous process takes place when characters are transferred from the processor to the cisplay. For this transfer, buffer-register DATAOUT & a status control flag SOUT are used. SOUT=1 5 When the display is ready to receive a character. 7 SOUT=0 > When the character Is being Lansferred to DATAOUT. + The buffer registers DATAIN and DATAOUT and the status flags SIN and SOUT are part of circuitry commonly known as a device interface. Fagen 219 bs comecton a proce, kno’ on dp Program to rend a line of tharnoters and daplay Te Move LOCO niilie pointer register RO to post tthe drs ofthe is ation fo emery trhece the characters are tobe stored READ TestBt #SINSTATUS Wilt fo a character tobe entered Branch-0 READ in the leyboned bller DATAIN MoveByte DATATN(R) Transfer the eharactr from DATAIN ito the memory (this dears SIN to 0) ECHO TentBit 43,0UTSTATUS Wal forthe dspay to became ready Braschi=0 ECHO MoweByte (RO).DATAOUT — Move the character jut rend to the day ler register (this leas SOUT to 0). Compare #CR,RO}+ Chef the arc just read CR (carageretara) Mit aot CR then Bronehyo READ ‘wane bake aod ed anoer character ‘Avo increment the pointer to toe the est cara, Tipe 20 Apogen het wads ole d Gwrocen ond delat MEMORY-MAPPED I/O + Some address values are used to refer to peripheral device buffer-registers such as DATAIN & DATAOUT. ‘No special instructions are needed to access the contents of the registers; data can be transferred between these registers and the processor using instructions such as Move, Load ar Store. * For example, contents of the keyboard character buffer DATAIN can be transferred to register R1 in the processor by the instruction MoveByte DATAIN,R1 + The MoveByte operation code signifies that the operand size is a byte. ‘+ The Testbit instruction tests the state of one bit in the destination, where the bit position to be tested fs indicated by the first operand. 6 COMPUTER ORGANIZATION. Ee ‘STACKS * A stack is a special type of data structure where elements are inserted from one end and elerments re deleted from the same and. This end iz called the top of the stacc (Figure: 2-14). * The various operations performed on stack 41) Insert: An element is inserted from top end. Insertion operation is called push operation. 2) Delate: An clement is deloted from top end. Deletion operation ia called pop operation. + A processor-register is used to keep track of the address of the element of the stack that is atthe top at any given time. This register is called the Stack Pointer (SP). # If we essume a byte-eddresseble memory with @ 32-Wit word length, 41) The push operation can be implemented as ‘Subtract #4, SP Hove NEWITEM, (5?) 2) The pop operation can be implemented as ‘Move (SP), ITEM Aad #4, 52 + Routine fora safe pop and push operation as follows: 'SAPEPOP Compare 4200057 Chwch to meri the wach pointer conten Braodiod EMPTYERROR as addres vale reer than 200, It oe, te ack empty. Base to the ‘wutne EMPTYERBOR fo appropiate Move (SP}LITEM Otherwise, pop thet ofthe stack ato semery lotion FFEM (a) Rios rae pop opeaon SAFEPOSH Compare #O0SP ‘Chk tse tbe wack paar Branco FULLERROR —centais an address value equal {oe a than 50. IES he stack fall. Brick to the routine PULLERROR fe apron act Mocs NEWTTEM.(8P) Others, ph th len in mamory ocation NEWITEM onto the tack 1B Retna bras ph cpr Figen 223 Chachi fer ep nd hil eres ia op ond ph opens. eto norrom, ae Figure 2.14 Asta of wards in he memory é COMPUTER ORGANIZATION. ———— LOGIC INSTRUCTIONS + Logic operations such as AND, OR, and NOT applied to individual bits. + These are the besic building blocks of digital-circuits. * This is also useful to be able to perform logic operations is sotware, which is done using instructions that apply these operations to all bits of 8 word or byte independently and in parallel + For example, the instruction ‘Not det SHIFT AND ROTATE INSTRUCTIONS ‘There are many applications that require the bits of an operand to be shifted right or left seme specified number of bit positions. ‘The details of how the shits are performed depend on whether the operand is a signed number or some more general binary-coded information. ‘For general operands, we use a logical shit. For a number, we use an arithmetic shift, which preserves the sign of the number. LOGICAL SHIFTS ‘Two lagical shift instructions are 41) Shifting left (LShiftL) & 2) Shifting right (LShifiR). + These instructions shift a operanc over @ number of bit positions specitied in a count operand contained in the instruction. (9) Artamets stright TASHA. Ra, 2 Figure 2.23 Logi ond orihmetic hit insrutions Mow fLOGRO RO poms w dan Moveyte (RO)K,RI Lan fet byte nto RU Ushi 4. Shit elt by 4 bit pions Moweiyte (RO\R2 Land seco byte into R2. Aad WSPR2 ——Blisinatehighorder tite. Or RLR2 ——Comeatenate the BCD digits Mowivte _R2PACKED Store the eeu Fore 231 A ule Fa pod wo CO Og 6 COMPUTER ORGANIZATION ae ROTATE OPERATIONS + In shift operstions, the bits shifted out of the operanc are lost, except for the last tt shifted cut Wwiich is retained in the Certy-feg C. = To preseive al bits, 2 set of rotate instructions can be used. + They move the bits thet are shited out of one end of the operand back into the other end. ‘+ Two versions of both the let and nght rotate instructions are usually provided. 1n one version, the bits of the operand is simply rotated. In the cther version, the rotation includes the C fag. we [Doers 7 o (6) Rotate right wthout carry Rotter 2, #2 wos [oo 7] f (2) Peta ght wth cary omienc Ao, #2 Figure 2.25 Reto iesiocion,