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precedence-constrained tasks DOI: 10.1177/1063293X16679001

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on heterogeneous clusters

Nirmal Kaur1,2, Savina Bansal3,4 and Rakesh Kumar Bansal3,4

Abstract
Efficient task scheduling of concurrent tasks is one of the primary requirements for high-performance computing plat-
forms. Recent advances in high-performance computing have resulted in widespread performance improvement though
at the cost of increased energy consumption and other system resources. In this article, an energy conscious scheduling
algorithm with controlled threshold has been developed for precedence-constrained tasks on heterogeneous cluster,
which aims at lower makespan along with reduced energy consumption. Energy conscious scheduling with controlled
threshold algorithm combines the benefits of dynamic voltage scaling with controlled threshold-based duplication strat-
egy to achieve its objectives. Effectiveness of the proposed algorithm is analyzed in comparison with available duplication-
and non-duplication-based scheduling algorithms (with and without dynamic voltage scaling approach) to ascertain its
performance and energy consumption. Exhaustive simulation results on random and real-world graphs demonstrate that
energy conscious scheduling algorithm with controlled threshold has the potential to reduce energy consumption and
makespan.

Keywords
heterogeneous computing, energy conscious scheduling, dynamic voltage scaling, duplication-based scheduling, power
consumption

Introduction about 50%, and it is predicted to rise to 70%–80% in

Traditionally, the focus and main priority of high-
performance computing (HPC) systems has been
toward enhancing system’s computational speed.
However, in recent times, huge power consumption of
multiprocessors, storage disks, interconnection net-
works, and memory devices has prompted researchers
to design energy-aware solutions to reduce energy con-
sumption. Current consumption—around 0.5% of
world’s total power usage—is expected to increase four
times by 2020 (Forrest, 2008). The power requirements
of clusters typically ranges from 75 to 150–200 W/ft2
and it will probably increase to 200–300 W/ft2 in near
future. Furthermore, the integration of nearly billion of
transistors onto contemporary processors (e.g. Intel
Itanium) shall lead toward raising temperature level
which may affect system reliability as well (Koch,
2005). The current dynamic energy consumption is
coming years (Rahaman and Chowdhury, 2009). Apart
from processor energy, network energy consumption is
also quite significant and can be severe for communica-
tion intensive applications (Rahaman and Chowdhury,
2009; Zong et al., 2011). Excessive energy consumption
results in increased green house gas emissions and cool-
ing costs to ensure system reliability, besides increasing
the electricity bills. Task scheduling on parallel
1
I.K.Gujral Punjab Technical University, Kapurthala, India
2
Department of CSE–UIET, Panjab University, Chandigarh, India
3
Department of ECE, Giani Zail Singh Campus College of Engineering &
Technology, Bathinda, India
4
Maharaja Ranjit Singh Punjab Technical University, Bathinda, India
Corresponding author:
Nirmal Kaur, Department of CSE–UIET, Panjab University, Chandigarh
160014, India.
Email: nirmaljul19@gmail.com

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2 Concurrent Engineering: Research and Applications
computing system relates to mapping the tasks of an
application on available processors to reduce overall
completion time (makespan or schedule length). A non-
judicious mapping heuristic may lead to redundant
energy consumption. Duplication-based scheduling, as
proposed by many researchers, is a viable solution for
reducing the communication overhead by replicating
predecessors to reduce makespan of an application
(Bansal et al., 2003, 2005; Lai and Yang, 2008; Shin
et al., 2008) and hence could be useful to reduce commu-
nication energy in interconnects. However, reduction in
makespan is achieved at the cost of increased computa-
tion energy (due to duplication of predecessors).
This article attempts an energy conscious duplication
scheduling under flexible threshold to conserve energy
and improve performance in heterogeneous cluster
(HC) system. Threshold is dynamic and is gradually
adapted to next best level till desired makespan and
energy reduction are achieved. The strength of the algo-
rithm lies in duplicating immediate predecessors under
a controlled threshold keeping an eye on reducing
makespan and energy consumption. Energy conscious
scheduling algorithm with controlled threshold
(ECSCT) uses energy control (EC) as a decisive para-
meter; if it is within the limits of a threshold, duplica-
tion is carried out, otherwise discarded. As a result,
ECSCT can strike a good balance between performance
(makespan) and energy consumption. Next, dynamic
voltage scaling (DVS) is exploited for the idle time slots
to reduce more processor energy consumption.
The article is organized as follows: section ‘‘Related
work’’ presents the related work that underlies the
existing energy-aware scheduling techniques. Section
‘‘Models’’ formulates the cluster, task, and energy
model. Section ‘‘Proposed ECSCT algorithm’’ presents
the proposed ECSCT algorithm. The performance
metrics and task graph generation are discussed in sec-
tion ‘‘Performance Metrics and Task Graph
Generation.’’ Subsequent section ‘‘Simulation setup
and performance comparison’’ gives the simulation
setup and comparison of ECSCT with other related
work. Section ‘‘Conclusion’’ summarizes the conclu-
sions and future scope of work.
Related work
Scheduling is an NP-complete problem, and as a conse-
quence, scheduling heuristics are applied to get sub-
optimal but practical schedules (Bala and Chana, 2015;
Bansal et al., 2003, 2005; Lai and Yang, 2008; Shin
et al., 2008; Topcuoglu et al., 2002). Duplication-based
scheduling helps in reducing makespan of communica-
tion intensive applications but with increased computa-
tion energy. DVS has been primarily used to conserve
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energy of independent tasks on uniprocessor systems
(Manzak and Chakrabarti, 2001; Yao et al., 1995) and
later it became popular in homogeneous and heteroge-
neous multiprocessor systems too. This technique has
also been exploited for conserving energy of dependent
tasks on homogeneous and heterogeneous multiproces-
sors (Baskiyar and Abdel-Kader, 2010; Baskiyar and
Palli, 2006; Kaur et al., 2015, 2016; Lee and Zomaya,
2009; Mori et al., 2009; Wang et al., 2013). Comito
et al. (2013) proposed an energy-aware task allocation
strategy to prolong battery life of mobiles. However,
only little energy-aware duplication strategies have
been proposed so far and that too for homogeneous
clusters (Liu et al., 2014; Zong et al., 2011). These algo-
rithms create groups of heavily communicating tasks
and then allocate each group of tasks on a different
processor to conserve energy. But these techniques are
not always adaptable to schedule multiple task groups
for a bounded number of heterogeneous processors. If
available processors are less than as required to sched-
ule multiple task groups, then some dummy processors
are assumed to assign leftover groups. Inclusion of
dummy processors in HC raises concern about the
competitiveness of the algorithm owing to different
capacities of processors.
As collected from the available works, most of the
energy-aware scheduling techniques have focused on
independent tasks, or on uniprocessor systems, or on
homogeneous multiprocessors. Furthermore, energy
reduction is handled mainly through managing proces-
sor energy for active states, overlooking processor idle
energy. In addition, the communication energy of inter-
connect has also been largely neglected in most of the
prior works. Therefore, in this article, an energy con-
scious controlled duplication-based scheduling has been
developed for precedence-constrained tasks on HC to
improve performance and reduce total energy con-
sumption considering computation energy of processor
in active and idle states and communication energy of
the interconnects as well.
Models
HC model
A cluster model is a set P{pk:k = 0, 1, 2 .p2 1} of
‘‘p’’ DVS-enabled processors/nodes connected in a fully
connected topology. In DVS cluster, each pk has dis-
crete states, and each state has a voltage and frequency
set. Voltage–frequency of all states is sorted in non-
increasing order, such that (v1, f1) and (vn, fn) corre-
sponds to highest and lowest voltage–frequency set
among the discrete states. For each pk, the set
fp(v
k
d , fd )
, pkactive(vd , fd ) , pkidle(vd , fd ) g represents the operating
voltage–frequency, active and idle power consumption,
Kaur et al. 3

!
for 1 !d!n. Communication links among processors X
u
1 , f1 )
are assumed to be without any contention, and compu- ep k
idle = makespan % pidle(v
k " xik " w(ti , pk ) ð3Þ
tation and communication can take place concurrently. i=1

This assumption is justifiable as each processor in the xik is 1 if ti is scheduled on pk, else 0. Total idle
modern cluster has a separate coprocessor that can be energy consumed on all processors is given as follows
utilized to relieve processor from communication
chores. The processors are heterogeneous, so each task X
p
has different execution time on each pk. EPidle = epkidle
k =1
!
X p X
u
Task model = makespan % pidle(v
k
1 , f1 )
" xik " w(ti , pk )
A parallel application is assumed to be decomposed k =1 i=1

into multiple tasks with precedence constraints and is ð4Þ

modeled by a directed acyclic graph (DAG), G (T, E)
where vertices T{ti:i = 0, 1, 2, .u2 1} is a set of tasks Therefore, total processor energy dissipation of a
with precedence relation such that tj cannot start until parallel application is given as follows
ti finishes its execution, and E, the set of edges is a mes-
EP = EPactive + EPidle ð5Þ
sage set. Each task ti2T has computation cost, w(ti, pk),
which represents its execution time on pk. Task execu- This energy model is compatible with DVS tech-
tions are assumed to be non-preemptive. cij is the com- nique. In DVS system, it is possible to reduce processor
munication cost to transfer data between tasks ti and tj power consumption by lowering down its maximum
scheduled on different processors. Local communica- operating voltage–frequency p(v 1 , f1 )
to best fit scaled
k
tion cost is assumed to be negligible in comparison with down level pk (vd , fd )
, for 2 !d!n, without affecting make-
inter-processor communication cost. A task without span of the application. In that case, we can replace
any predecessor and successor is taken as an entry and pkactive(v1 , f1 ) and pkidle(v1 , f1 ) with pkactive(vd , fd ) and pkidle(vd , fd ) .
exit task in the DAG. The new execution time wnew (ti , pk ) of ti on pk at scaled
down voltage level vd is given as follows
Energy model
v21 " w(ti , pk )
The energy model of homogeneous cluster (Zong et al., wnew (ti , pk ) = for 2 ! d ! n ð6Þ
v2d
2011) has been extended to cope up with different pro-
cessing capabilities of processors in HC system.
Communication energy model. The network interconnect
Computation energy model. Let pkactive(v1 , f1 )
be the active is assumed to be homogeneous, so the bandwidth to
power consumption on pk for highest voltage and fre- transfer data over the links interconnecting any pair of
quency (v1, f1). Processor active energy consumed to processors is same with same consumption of commu-
execute ti on pk, denoted as epactive (ti , pk ) is given as nication power. Let PL be the power consumption of a
follows link interconnecting two processors. Communication
energy elij consumed to transfer data over the link from
epactive (ti , pk ) = pkactive(v1 , f1 ) " w(ti , pk ) ð1Þ ti to tj scheduled on different nodes is given as follows

Processor active energy consumed to execute all elij = PL " cij ð7Þ
tasks in T on P is given by equation (2)
Communication energy consumption of whole net-
jT j X
X jPj work interconnect is given by equation (8)
EPactive = epactive (ti , pk )
i=1 k =1
ð2Þ
u X
X u X
p X
p
! "
Xu X p EL = xik " xjm " PL " cij ð8Þ
1 , f1 )
= (pactive(v
k " xik " w(ti , pk )) i=1 j=1 k =1 m=1
k6¼m
j6¼i
i=1 k =1

Let pkidle(v1 , f1 ) be the idle power consumption on pk Consequently, total energy consumption (computa-
under highest voltage and frequency (v1, f1). Idle energy tion and communication) of a cluster is given as follows
consumed on pk corresponding to its idle state is given
by equation (3) ET = EP + EL ð9Þ

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4 Concurrent Engineering: Research and Applications

Table 1. Notations used in ECSCT algorithm.

T, E Number of tasks and edges in the DAG

ti , pk ith task ti2T and kth node/processor pk2P
cij Communication cost to transfer message from ti to tj scheduled on different processors
w(ti , pk ) Execution time of ith task on kth processor
(v1 , f1 ), (vn , fn ) Highest and lowest voltage–frequency among discrete states
pkactive(vd , fd ) , pkidle(vd , fd ) Active and idle power consumption on pk for voltage–frequency (vd , fd ), for 1 ! d ! n
PL Power consumption of interconnect
ST(ti , pk ), FT(ti , pk ) Start and finish time of ith task on kth processor without duplication
ST d(ti , pk ), FT d(ti , pk ) Start and finish time of ith task on kth processor with duplication of its immediate predecessors
AST(ti , pk ), AFT(ti , pk ) Actual start and finish time of ith task on kth processor
EC(ti , pk ) Energy control to be computed if duplication of predecessors of ti on pk reduces schedule length
epactive (ti , pk ), EPactive Active energy consumed to execute ith task on kth processor, total active energy consumed to execute
all tasks
epkidle , EPidle Idle energy consumed on kth processor, total idle energy consumed on all processors
elij Communication energy consumed over a link to transfer data from ith to jth task running on different
processors
EP, EL Total energy consumption of processor (active and idle) and interconnect

ECSCT: energy conscious scheduling algorithm with controlled threshold; DAG: directed acyclic graph.

Proposed ECSCT algorithm
In this article, an energy conscious duplication schedul-
ing exploited under controlled threshold is proposed to
reduce energy and makespan in HC system. The algo-
rithm comprises of two major phases. In first phase,
priority-based task sequence is generated, while in the
second phase, energy conscious duplication scheduling
is done within threshold, and this phase terminates
once feasible threshold is reached. ECSCT adopts the
limited duplication strategy as done in heterogeneous
limited duplication (HLD) (Bansal et al., 2005). HLD
reduces the inter-task communication by replicating
the immediate predecessors on multiple processors to
reduce makespan. However, accommodating a dupli-
cated task may increase processor’s active energy con-
sumption that has not been considered in (Bansal et al.,
2005). ECSCT includes an additional EC parameter
which takes into account the impact of duplication on
makespan and energy consumption and thus balances
trade-off of makespan–energy. Threshold is upgraded
dynamically to next level till a feasible threshold is
reached that corresponds to desired makespan and
energy reduction. Table 1 enlists the notations used in
ECSCT and its pseudocode is shown ahead.
Generation of priority-based task sequence
In the first phase, priorities are assigned to each and
every task of a DAG based on their bottom level b(t)
(Bansal et al., 2005), which is calculated recursively
based on the mean costs, as given in equation (10)
! i + maxfb(tj ) + !cij g8tj esucc(ti )
b(ti ) = w
where w! i and !cij are mean computation and mean com-
munication cost, respectively. Tasks are then arranged
in decreasing order of their bottom level generating a
task sequence satisfying precedence constraints.
Energy conscious duplication scheduling
In the second phase, energy conscious duplication sche-
duling is employed under a controlled threshold till fea-
sible threshold is reached. Initially, temp_threshold and
upper_threshold is set to 5,000,000 and 0. ECSCT
selects an unscheduled task ti from the ordered task
sequence and computes its start and finish time on each
pk2P with and without duplication of its immediate
predecessors (step 4). If duplication is useful (step 5),
then EC (ti, pk) is computed to analyze whether the
impact of duplication on makespan and energy con-
sumption is within the limits of temp_threshold. If yes,
duplication is allowed, else discarded on pk. Task ti is
scheduled on a processor pk that gives minimum earlier
finish time, and EC value (due to duplication of prede-
cessors) on scheduled pk is maintained in a threshold
array (i.e. Th-list). The min_sch_len is temp_sch_len
generated under initial temp_threshold. After all tasks
are scheduled, temp and upper thresholds are revised
from threshold array (step 7). If computed upper
threshold is zero, ECSCT returns upper threshold as
feasible threshold and terminates. Otherwise, an addi-
tional step r2 is used to compute feasible threshold. In
this step, temp_sch_len is computed (steps 2–6) under
revised temp_threshold and compared if generated
temp_sch_len is less than or equal to min_sch_len and
total energy consumption at temp_sch_len, that is,
ð10Þ E_temp_sch_len is less than or equal to total energy

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Kaur et al.
consumption of HLD_DVS, that is, E_hld_dvs. If yes,
feasible threshold is attained. If no, temp_threshold is
updated with next_threshold and temp_sch_len is com-
puted under updated temp_threshold until desired
objective is met. Furthermore, DVS is applied to the
scheduled tasks as well as to the task replicas created
on different processors to further reduce processor
energy consumption while maintaining temp_sch_len.
Algorithm 1. Pseudocode of ECSCT algorithm
Input: G (T, E), processor and network power, temp_-
threshold = 5000000, upper_threshold = 0, x = 0,
Th-list [x] = {0}, y = 0,
temp_Th-list [y] = {0};
Output: feasible_threshold
Step 1: Priority based task sequence generation
Step 2: ti = first unscheduled task from ordered task
sequence;
Step 3: for all pk2P
Step 4: find ST (ti, pk), FT (ti, pk) and ST_d (ti, pk),
FT_d (ti, pk)//start and finish time of ti on pk
with and without duplication
Step 5: if (FT_d (ti, pk) \ FT (ti, pk))//duplication
reduces schedule length
{ Performance metrics and task graph
reduced_sch_len (ti, pk) = FT (ti, pk) 2 FT_d
(ti, pk)
EC (ti, pk) = (epactive (tn, pk) 2elni)/reduced_s-
ch_len (ti, pk) where tn = immediate predeces-
sors of ti duplicated on pk
temp_Th-list [y + + ] = EC (ti, pk)
if (EC(ti, pk) ! temp_threshold)//duplica-
tion allowed on pk
AST (ti, pk) = ST_d (ti, pk) & AFT (ti,
pk) = FT_d (ti, pk)
else//ignore duplications on pk
AST (ti, pk) = ST (ti, pk) & AFT (ti, pk)
= FT (ti, pk)
} ES =
else//duplication does not reduce schedule
length
AST (ti, pk) = ST (ti, pk) & AFT (ti, pk) = FT
(ti, pk)
Step 6: schedule ti on pk with minimum actual finish
time and undo duplications (if any) on any
other pk. Record Th-list [x + + ] = EC (ti, pk)
while (unscheduled tasks exist in task sequence)
record temp_sch_len
Step 7: revise temp_threshold and upper_threshold with
minimum and maximum threshold value from
Th-list[x] respectively
Step 8: Call Get_feasible_threshold (temp_threshold,
upper_threshold)
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5
return feasible_threshold
Get_feasible_threshold (temp_threshold, upper_thres-
hold)
Step r1: if (upper_threshold = = 0)
return feasible_threshold = upper_threshold;
Step r2: else
while (temp_threshold ! upper_threshold)
{y = 0; temp_Th-list [y] = {0};
repeat steps 2 to 6 to get temp_sch_len under
temp_threshold
if (temp_sch_len ! min_sch_len &&
E_temp_sch_len ! E_hld_dvs)
return feasible_threshold = temp_threshold
break
else
{//compute next threshold
next_threshold = 5000000
for (z = 0; z \ y; z + + )
if (temp_Th-list [z] \ next _threshold &&
temp_Th-list [z] . temp_threshold)
next_threshold = temp_Th-list [z];
temp_threshold = next_threshold
}
}//end while
generation
The performance of the algorithm is analyzed in terms
of makespan and energy consumption comprising com-
putation (active and idle) energy and communication
energy of interconnect. As a large set of random and
real-world task graphs are simulated, so makespan is
normalized with respect to absolute lower bound value
termed as normalized schedule length (NSL). The
energy reduction effectiveness of ECSCT over others is
ascertained based on parameter energy saving (ES)
given as follows
EREF % EECSCT
ð11Þ
EREF
where EREF represents the energy consumption of any
reference algorithm under consideration, and EECSCT is
the energy consumption of the proposed algorithm.
The algorithms used for comparison are Heterogeneous
Earliest Finish Time (HEFT) (Topcuoglu et al., 2002),
HLD (Bansal et al., 2005), Low Power Heterogeneous
Makespan (LPHM) (Baskiyar and Palli, 2006), and
HLD_DVS (Kaur et al., 2016). HEFT is a list schedul-
ing algorithm, and HLD is a duplication-based schedul-
ing algorithm that exploits the available scheduling
holes to duplicate the immediate predecessors to gener-
ate shorter makespan than non-duplication algorithms.
HLD is an effective algorithm as it avoids redundant
6 Concurrent Engineering: Research and Applications

Table 2. Configuration detail of AMD Athlon 64 3000þ processor.

S-state Frequency (GHz) Voltage Active power (W) Idle power (W)

1 2.0 1.50 100 87

2 1.8 1.40 87 78
3 1.0 1.10 61 59

duplications and incorporates only limited duplications
as against other duplication scheduling algorithms in
literature. LPHM is a list-based energy-aware schedul-
ing algorithm that blends DVS with well-known HEFT
algorithm. HLD_DVS is energy-aware duplication
algorithm, in which the scheduled tasks (original and
duplicated) on multiple processors exploit DVS in their
slack times. All algorithms are coded in cross-platform
integrated development environment (IDE): Code
Blocks 13.12. For an unbiased evaluation, random and
real-world task graphs are generated by modifying
benchmark task graph suite (Kwok and Ahmad, 1999)
to be used for heterogeneous system. Task graphs are
generated by varying five communication to computa-
tion cost ratios (CCRs) {0.1, 0.5, 1.0, 2.0, 10.0}, four
high-speed interconnects {Ethernet, QsNetII,
Infiniband, Myrinet}, 10 task graph sizes (v) {50 to 500
with an increment of 50}, five different average paralle-
lism (nOv){1 !n! 5}, and five computation ranges (b)
{0.1, 0.25, 0.5, 0.75, 1.0}. CCR is the ratio of average
communication cost to average computation cost of a
graph. High and low CCRs imply a communication
and computation intensive graph. Average parallelism
(nOv) is the maximum number of non-precedence tasks
in a graph that indicates the parallelism available in an
application. Computation range (b) is the processor
heterogeneity for variation in the computation costs on
processors. A high b (1.0) causes significant difference
in computation cost of a task among processors, and a
low b (0.1) means that the execution time of a task on
any processor is almost equal. The expected execution
time w(ti, pk) of ti on pk is calculated as follows
# $ # $
b b
!i 3 1 %
w(ti , pk ) = w !i 3 1 +
! w(ti , pk )\ w
2 2
ð12Þ
where w ! i is mean computation cost of task ti taken
from the computation cost of homogeneous benchmark
suite (Kwok and Ahmad, 1999). Real-world parallel
numerical applications are simulated: mean value anal-
ysis (MVA) and Gaussian elimination (Gauss). Task
graph size of these applications is roughly O(N2); N is
{19, 22, 25, 28, 31, 34, 37, 40} for MVA and {19, 24,
29, 34, 39, 44, 49} for Gauss.
Table 3. Configuration profile of networks.
Network type Power (W) Bandwidth Message
(MB/s) delay
Ethernet 80 50 13
QsNetII 54 340 1.73
Infiniband 35.6 822 0.9
Myrinet 64.5 243 1
Simulation setup and performance
comparison
Configuration details
The performance comparisons on random and real-
world graphs are simulated with AMD Athlon 64
3000 + processor (Mori et al., 2009) and four high-
speed interconnection networks (Zong et al., 2011)
widely used in cluster. Tables 2 and 3 give the config-
uration details of processor and network types used for
simulation.
Performance comparison for random task graphs
Impact of varying CCRs. Based on parameters (5 CCRs, 5
nOv, 5 b, 10 v, and one network = QsNetII), 1250 ran-
dom task graphs were generated and simulated on clus-
ter. Figure 1 shows performance (average NSL) and
total energy (CPU + communication) consumption.
From average NSL (Figure 1(a)), it is seen that for
communication intensive graphs (high CCRs), HLD
gives significant improved performance over HEFT as
it exploits the available scheduling holes to duplicate
the immediate predecessors to reduce makespan,
whereas for computation intensive graphs (low CCRs),
performance of HLD is more or less comparable to
HEFT as duplication may not be desirable under such
cases. Performance of ECSCT is comparable or better
than HLD at high CCRs because ECSCT employs
duplication scheduling under a threshold to balance
makespan and energy consumption. Therefore, proces-
sor’s available scheduling holes left unexploited due to
discarded duplication can be utilized in future to
accommodate the unscheduled and duplicated tasks,

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Kaur et al.
Figure 1. (a) Average performance and (b) energy consumption for varying CCRs.
Figure 2. (a) Average performance and (b) energy consumption for varying interconnects.
and as a result, ECSCT gives reduction in makespan
than remaining algorithms. At CCR 0.1, average NSL
of ECSCT is good over HEFT and HLD by 0.1% and
0.2%, but at CCR 10, it is improved by 24.7% and
1%, respectively. For total energy (Figure 1(b)), we
can find that for compute intensive graphs, HLD is
slightly less energy efficient than HEFT because some-
times duplication tends to increase processor active
energy without boosting up performance. But for high
CCRs, HLD yields significant energy saving over
HEFT as duplication solution on such graphs tends to
reduce communication delay, which reduces substantial
communication and processor idle energy consump-
tion. In contrary, ECSCT performs better than other
algorithms as it retains the strengths of duplication
under controlled threshold to satisfy desired makespan
and energy reduction. Total energy saving in LPHM is
better than HLD and HLD_DVS for compute inten-
sive graphs, thus it is better suited for these graphs.
But for large CCR, HLD_DVS performs better than
LPHM because combined effect of duplication and
DVS causes communication and processor idle energy
saving to dominate total energy. The superiority of the
ECSCT algorithm gets reflected from these results. At
low CCR, ECSCT yields reduced makespan and better
energy savings than other duplication algorithms and is
quite comparable to list-based algorithms. While at
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7
large CCRs, ECSCT exhibits both reduced energy con-
sumption and makespan than other algorithms. At
CCR 10, average total energy saving of ECSCT is
improved by 27.2%, 6.8%, 12%, and 2.3% over
HEFT, HLD, LPHM, and HLD_DVS, respectively.
Impact of varying network interconnects. Here, 1000 ran-
dom graphs were generated with four interconnects
({Ethernet, QsNetII, Infiniband, Myrinet}, 5 nOv, 5 b,
10 v, and one CCR = 10) to reflect the effect of vary-
ing interconnects. It is seen that Ethernet results in
higher total energy consumption than Infiniband for
all scheduling algorithms. Ethernet has more latency,
and Infiniband has less latency; therefore, communi-
cation time in Ethernet is more resulting in increased
makespan and energy consumption over Infiniband.
Myrinet and QsNetII observe almost comparable per-
formance, but QsNetII gives somewhat more energy
savings than Myrinet because power of QsNetII is
lower than that of Myrinet. However, the strengths
of ECSCT get exhibited as compared to other algo-
rithms regardless of interconnect type. Energy saving
of ECSCT over HEFT, HLD, LPHM, and
HLD_DVS is 36.8%, 3.4%, 31.2%, and 0.8% when
Ethernet interconnect is deployed in cluster and for
Infiniband it is 25.9%, 7.8%, 8.8%, and 3.2%,
8 Concurrent Engineering: Research and Applications

Figure 3. (a) Average performance and (b) energy consumption for varying task sizes.

Figure 4. (a) Average performance and (b) energy consumption for varying heterogeneities.

respectively. Therefore, average performance and
energy results (Figure 2) of scheduling algorithms
vary for different interconnects, and difference
among their latency and power affects overall make-
span and energy. Scheduling algorithms can benefit
from low latency and high bandwidth interconnects
that can reduce communication times and yield
improved performance and energy.
communication intensive graphs. From average NSL of 50
size graphs, ECSCT noticeably perform well than HEFT
and HLD by 38.3% and 2.2%, whereas, for 500 tasks, per-
formance reduces to 20.3% and 0.9%. For total energy
consumption of 50 tasks, ECSCT is better than HEFT,
HLD, LPHM, and HLD_DVS by 40.5%, 12%, 22%, and
3.8%, respectively.

Impact of heterogeneity. Unlike homogeneous systems, in

Impact of varying number of tasks. In this section, we gen-
erated 250 random graphs based on (10 v, 5 nOv, 5 b,
one CCR = 10, and one network = Infiniband).
From results (Figure 3), it is gathered that makespan
deteriorates and energy consumption increases as num-
ber of task size increases for all algorithms because
data dependencies among tasks increases and paralle-
lism needs to be taken care of in the presence of high
inter process communication. Here, it may be observed that
duplication scheduling algorithms (HLD, HLD_DVS, and
ECSCT) are quite effective to preserve parallelism despite
of high communication costs and thus perform well for
heterogeneous computing system, the capacities of pro-
cessors are different. For the 250 random task graphs
as generated in section ‘‘Impact of varying number of
tasks,’’ performance and energy reduction (Figure 4)
improve as heterogeneity increases regardless of sche-
duling algorithm. At each heterogeneity parameter b,
energy saving of HLD is found to be more effective
than HEFT because duplication scenario better adapts
to HC platform and thus brings more benefit of
heterogeneity. Furthermore, it is seen that DVS tech-
nique gives better energy savings as heterogeneity
increases because different processors execute similar

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Kaur et al. 9

Figure 5. (a) Average performance and (b) energy consumption of MVA for varying CCRs.

Figure 6. (a) Average performance and (b) energy consumption of GE for varying CCRs.
Gauss: Gaussian elimination.

tasks at different speeds resulting in more idle time
to be exploited by DVS. For instance, at heterogene-
ity 1, HLD_DVS saves 24%, 5.2%, and 6.4% energy
than HEFT, HLD, and LPHM. For total energy, at
b = 0.1, ECSCT is better than HEFT, HLD, LPHM,
and HLD_DVS by 25.3%, 7.5%, 8.3%, and 3%,
respectively, and for b = 1, it is increased to 27%,
8.5%, 9.7%, and 3.5%. From results, ECSCT is found
to be quite energy efficient over other algorithms
regardless of heterogeneity.
Performance comparison for regular task graphs for
varying CCRs
Two parallel applications were simulated: MVA and
Gaussian elimination (Gauss). For MVA, 200 graphs
are generated based on (5 CCRs, 5 b, 8 N, and one net-
work = Myrinet). For Gauss application, 175 graphs
were created based on (5 CCRs, 5 b, 7 N, and one net-
work = Myrinet). ECSCT yields highest performance
and energy saving as compared to other algorithms for
both the real applications. For small CCR, average per-
formance of ECSCT is more or less comparable to
HEFT, but for large CCR, ECSCT is significantly
improved over HEFT and HLD. For example, at CCR
10, ECSCT provides better performance than HEFT
and HLD by 18.6% and 3.4% for MVA and it is 8.1%
and 4.8% for Gauss. In terms of total energy, for small
CCR, ECSCT gives good energy gain against HEFT,
HLD, and HLD_DVS, and it is only marginally energy
efficient than LPHM. For large CCR, performance
and energy improvement of ECSCT are significantly
improved than all other algorithms. Justification of
these results is consistent with random task graphs
results. Compared with HEFT, HLD, LPHM, and
HLD_DVS at CCR 10, energy saving of ECSCT is
10.7%, 9.9%, 3.3%, and 7.5% for Gauss and it
increases to 33.2%, 14.8%, 15.8%, and 6.8% when
MVA is simulated on same cluster. Thus, from results
of Figures 5 and 6, it is clear that communication inten-
sive graphs can take more benefit from ECSCT to
improve performance and reduce energy consumption.

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10
Conclusion
Judicious scheduling of concurrent tasks is crucial for
exploiting full potential of parallel computing plat-
forms. However, for solving increasingly complex
engineering and scientific applications, the excessive
power consumption of underlying computing archi-
tectures is becoming a major concern. In this work,
an energy conscious duplication-based scheduling
algorithm with controlled threshold (ECSCT) is pro-
posed to address makespan and energy consumption
issues concurrently for scheduling DAG on heteroge-
neous computing platforms. Threshold is selected
based on the computation, communication energy,
and makespan and it is updated dynamically till a fea-
sible threshold is reached. After attaining feasible
threshold, DVS is applied to further conserve the
computation energy, wherever feasible. The exhaus-
tive simulation-based analysis on random and real-
world graphs justifies the logic behind the strategy
proposed. Although, for compute intensive applica-
tions (with CCR ! 1), average makespan of ECSCT
is slightly reduced (within 1%) with marginal energy
reduction (within 20.3% and + 2.6%) in comparison
with other prominent list and duplication-based sche-
duling algorithms with and without DVS. However,
for communication intensive applications (with CCR
. 1), the average makespan reduction generated by
ECSCT is appreciable (minimum 3.4% and maximum
10%) and that too with significant reduced energy
consumption (minimum 5.7% and maximum 15%) in
comparison with other algorithms. Implication of
results state that ECSCT is a potential substitute to
contemporary algorithms to reduce energy consump-
tion while still retaining or improving makespan on
HC. The present research focused on energy con-
scious duplication scheduling under classical model to
survive makespan and reduce total energy consump-
tion. The future work is being extended toward realis-
tic model taking into account the contention for
communication resources. Energy-aware duplication
scheduling under contention model has a scope to
reduce communication delay and thus communication
energy consumption.
Declaration of conflicting interests
The author(s) declared no potential conflicts of interest with
respect to the research, authorship, and/or publication of this
article.
Funding
The author(s) received no financial support for the research,
authorship, and/or publication of this article.
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Concurrent Engineering: Research and Applications
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Author biography
Nirmal Kaur received her Masters in CSE (2009) from IK-Gujral Punjab Technical University,
Kapurthala and Bachelors in CSE (2003) from Punjabi University, Patiala. She is pursuing PhD
in CSE from IK-Gujral Punjab Technical University, Kapurthala. She is an assistant professor in
UIET, Panjab University, Chandigarh, India. Her areas of interest include energy aware multi-
processor scheduling, and digital Image watermarking techniques.

Savina Bansal earned PhD from IIT, Roorkee (2004), Masters in CSE (1994) from Thapar
University, Patiala, and Bachelors in ECE (1988) from Punjab Engg College Chandigarh, India.
She is a Professor at GZS Campus College of Engg & Tech, Bathinda (A Punjab Govt
Established Institute) and Dean (R&D), Maharaja Ranjit Singh Punjab Technical University,
Bathinda, India. Her current areas of interest include energy efficient and fault tolerant schedul-
ing on parallel computing systems, wireless sensor networks, image processing and wireless com-
munication systems. Six PhD scholars, including the first author, are working under her
supervision. She is available at savina.bansal@gmail.com.

Rakesh Kumar Bansal earned PhD (2009) from Pbi University and Masters in Computer
Engineering (1992) and Bachelors in EIC (1986) both from Thapar University, Patiala- India. He
is a professor at GZS Campus College of Engg & Tech, Bathinda (A Punjab Govt Established
Institute) and Dean (Students), Maharaja Ranjit Singh Punjab Technical University, Bathinda,
India. His areas of interest include real time and energy aware fault tolerant scheduling and wire-
less sensor networks. Five PhD scholars, including the first author, are working under his supervi-
sion. He is available at drrakeshkbansal@gmail.com.

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