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Abstract— Unlike existing single-stage AC/DC converters with IEC 61000-3-2 requirement [11]. However, the bus voltage still
uncontrolled intermediate bus voltage, a new single-stage AC/DC varies largely with the input voltage. Therefore the capacitance
converter achieving power factor correction (PFC), intermediate has to be large enough for hold-up time requirement at low-
bus voltage output regulation and output voltage regulation is
proposed. The single power stage circuit is formed by integrating line condition. Load current feedback technique is introduced
a boost PFC converter with a two-switch-clamped forward con- [12] in which the load information is brought forward to the
verter. The current stress of the main power switches is reduced input stage, controlling the input current directly. At any time
due to separated conduction period of the two source currents the switch handles current from either the line input voltage
flowing through the power switch. A dual-loop peak current mode or the storage capacitor. However, the high input current
controller is proposed to achieve PFC, and ensure independent
bus voltage and output voltage regulations. Experimental results harmonics problem and large variation of bus voltage against
on a 24V/100W hardware prototype are given to confirm the line voltage still exist. Operating both stages in DCM may
theoretical analysis and performance of the proposed converter. reduce the voltage stress but it may not favour high output
The converter ranges 86%–92% of conversion efficiency at full current/power applications [9], [13]-[14]. Direct power transfer
load condition. is introduced [9]-[19] to place an auxiliary coupled winding
in series with the charging path of boost inductor, “stealing”
I. I NTRODUCTION
energy to output directly after the first power process. The
Single-stage power-factor-corrected (S2 PFC) AC/DC con- voltage stress is reduced ripidly while maintaining high power
verters, which combine a power factor correction (PFC) circuit factor. Conversion efficiency is also improved. But there is no
and a DC/DC regulator circuit, and share a common set of control of bus voltage against the line voltage. The authors in
active power switch(es), have been introduced [1]-[5]. The [3] and [20] attempted to control the bus voltage and output
aims are to reduce the converter size, control circuitry and thus voltage in S2 PFC converters but due to the integrated structure,
cost. Three critical problems are found in S2 PFC converters: the currents from both input sources (AC mains and storage
1) Extra current stress on the switch as it has to handle currents capacitor) cannot be separated. Hence the current stress issue
from the line input voltage and the bus voltage simultaneously, remains. Moreover, since the duty cycle varies largely for
hence lowering conversion efficiency; 2) High voltage stress on universal input applications, an extra range switch is needed.
power semiconductor devices due to uncontrolled intermediate
In this paper, a new S2 PFC converter derived from novel
bus voltage; 3) Voltage spike on main switch caused by the
integration of boost converter and two-transistor-clamped for-
leakage energy for transformer-isolated rear DC/DC stage.
ward converter is proposed. In summary, the proposed con-
Therefore the S2 PFC approach is only attractive for low power
verter has the following advantages:
applications.
Various approaches have been introduced to solve partly
the aforementioned problems [6]-[20]. Variable switching fre- • The proposed S2 PFC converter gives simultaneous PFC,
quency [6]-[7] limits the input power pumping to the bus bus voltage regulation and fast output regulation which
capacitor by increasing the switching frequency at decreasing are not possible in existing S2 PFC converters.
load, and vice versa. Bulk capacitor voltage feedback [8]- • No additional switches, such as range switch, are needed
[10] can effectively reduce the voltage stress by reducing to implement universal input range applications.
the charging current in the boost inductor when the load • The current stress of the two power switches is lower
is decreasing. However, dead angle of input current occurs, than that of the single-switch (or multiple-switch) S2 PFC
resulting in poor power factor and reduced available power converter circuits.
from the line. By adding a parallel PFC converter with the • High power factor as there is no deadband of input current
diode-capacitor filter, the bus voltage is clamped at the peak around the zero crossing of the line input voltage.
input voltage and input current can be designed to comply with • Stand-by mode is possible that saves power.
vDS2 6
iD2
D4 Io
S2 D2 N :1 - z1
”1”-D Q S2
Lo
E/A 1 vc1
iL1 Vref 1 PWM 1 R FF1
- -
ip Lp D5 Co Ro Vo
”0”- S
X A
L1
6 6
iD1
CB VB 6
iin vDS1 T1 CLK
|vin | D1 VB z4
?
”1”-D
B
S1 A Q S1
R2 R1
z3 PWM 2 R FF2
”0”- S
B E/A 2 vc2
Vref 2
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Low input |vin,L | High input |vin,H |
z }| { z }| {
T -..
.
S1
Gate ... .. -
..
S2 ... ..
.. ..
Gate .. ..
-
-.... D1a T ......
.. .. .. .. .. ..
..-.. ..
.. .. .. D2a T ..
.. .. .. ..
iL1 .. . . .. .. .. ..
..
-.... .... ... ...-...
.. .. ..
...
..
..
. . . -
D1b T D2b T t
Fig. 4. Switching waveforms of iL1 (upper) and iD1 (lower). Scale: 4A/Div,
vc2 is generated. vc2 is summed with the inductor L1 current 4A/Div.
and compared to ground by comparator PWM 2 to produce
desired off duty cycle for S1 through the D-type flip-flop As |vin,H | > |vin,L |, comparing (6) and (7) we can conclude
(FF2). Duration of S1 is longer than that of S2 (Fig. 3). When that iin,H > iin,L . As the instantenous average input current
current flowing through R2 (in Fig. 1), which represents peak follows the input line voltage, the converter achieves PFC
inductor current iL1 , is reached, point B is pull to negative automatically under peak current mode control.
and S1 is turned off. The converter then enters Mode 3.
In the design of the controller, on one hand, the compen- V. E XPERIMENTAL V ERIFICATION
sation network by E/A2 is of slow response, which has the To verify the feasibility of the proposed boost-forward
cut-off frequency of around 10-20Hz, to avoid the 100Hz ac S2 PFC AC/DC converter, a laboratory prototype with the
ripple from bus capacitor being amplified and cause input following specifications has been implemented and tested:
current distortion eventually. On the other hand, E/A1 is of |vin | = 100 - 240Vac; Vo = 24Vdc; Po = 100W; fs =1/T
fast response to provide tight output regulation. = 50kHz. The key circuit parameters are listed as follows:
IV. P OWER FACTOR C ORRECTION C APABILITY L1 =400µH, Lp =750µH, N =4, Lo =800µH, CB =470µF/450V,
Co =4700µF/35V, S1-IRF830, S2-IRF840, D1 =D2 -UF5407,
Let the input line voltage near zero-crossing and near peak
D3 =D4 -BYW29, R1 =R22/2W and R2 =R47/2W.
value be |vin,L | and |vin,H | respectively. The instantaneous
Fig. 4 shows the switching waveforms of inductor current
average input currents, as shown in Fig. 3, at low and high
iL1 (upper) and diode D1 current iD1 (lower). The input
line voltages are given respectively by
voltage and filtered input current of the converter at 240V
|vin,L | and 100V line voltages and at full load condition are shown in
iin,L = D1a T (D1a + D1b ), (1) Figs. 5 and 6 respectively. The measured power factor is above
2L1
0.96 and efficiency of the converter is above 86% at full load
|vin,H | condition, with maximum efficiency of 92%, as shown in Fig.
iin,H = D2a T (D2a + D2b ). (2)
2L1 7. The converter regulates at VB =400V (through Mode 2) and
Because of peak current mode control, the peak input currents Vo =24V (through Mode 1) for entire line and load conditions.
at different input voltages are the same, therefore Finally, Fig. 8 shows that the stand-by mode feature is made
|vin,L | |vin,H | possible in the proposed converter by keeping S2 closed and
D1a = D2a . (3) allowing current from CB to regulate Vo through switching of
2L1 2L1
S1. Once VB is below 350V, S2 is open to allow input current
Applying voltage-second on L1 in both conditions, we get to supply energy to CB .
|vin,L | L1 + Lp
D1b = D1a × , (4) VI. C ONCLUSION
VB − |vin,L | L1
This paper presents with verifications of experimental re-
|vin,H | L1 + Lp sults the single stage PFC (S2 PFC) converter concept - PFC,
D2b = D2a × . (5)
VB − |vin,H | L1 regulation of bus and output voltages at the same time. The
Substituting (4) and (3) into (1), we have key idea is to construct the power circuit so that current
Lp from two input sources (AC main and bus capacitor) can
|vin,H | VB + |vin,L | L1 be separately controlled. Therefore, although the two power
iin,L = D2a T [ ]. (6)
2L1 VB − |vin,L | processing stages share the same power switches, only one of
Similarly, we have the input current for higher line voltage the two currents passes the switches at a time within each
Lp
switching period. Current stress on power switches is also
|vin,H | VB + |vin,H | L1 reduced as a result. Moreover, by deliberatly restricting the
iin,H = D2a T [ ]. (7)
2L1 VB − |vin,H | current from AC main, the converter can work at stand-by
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Fig. 7. Measured power factor and conversion efficiency of the proposed
converter at full load.
Fig. 5. Input voltage vin and filtered input current iin at 240V(rms) and
full load. Scale: 190V/Div; 0.25A/Div.
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