www.vedic-vlsi.

com
IEEE Titles and Research & Development Projects for students of
Network Security & Encryption Standards
1. FPGA implementation of SHA-224/256 algorithm oriented Digital Signature (IEEE 2010)
2. A Design and Implementation of High-Speed 3DES Algorithm System (IEEE 2010)
3. Design of SHA-1 Algorithm based on FPGA (IEEE 2010)
4. Enhancing RC4 algorithm for WLAN WEP protocol (IEEE 2010)
5. An RC4-based hash function for ultra-low power devices (IEEE 2010)
6. A Simplified FPGA Implementation Based on an Improved DES Algorithm (IEEE 2010)
7. An improved RC6 algorithm with the same structure of encryption and decryption (IEEE 2009)
8. A Compact AES Encryption Core on Xilinx FPGA (IEEE 2009)
9. FPGA Implementation(s) of a Scalable Encryption Algorithm (IEEE 2008)
Effective Uses of FPGAs for Brute-Force Attack on RC4 Ciphers (IEEE 2008)
10. Cost-Efficient SHA Hardware Accelerators (IEEE 2008)
11. Hardware Implementation Analysis of the MD5 Hash Algorithm (IEEE 2005)
12. Low-Cost Advanced Encryption Standard (AES) VLSI Architecture: A Minimalist Bit-Serial Approach (IEEE 2005)
13. Hard ware implementation of the SAFER+ Encryption algorithm for the Bluetooth algorithm (IEEE 2002)
14. FPGA Implementation of MD5 Secure Hash Algorithm (IEEE 2001)
Design for Testability (DFT) Techniques
15. Built-in Self-Detection/Correction Architecture for Motion Estimation Computing Arrays
(IEEE 2010)
16. Power optimization of linear feedback shift Register (LFSR) for low power BIST (IEEE 2009)
17. A VHDL Implementation of UART Design with BIST Capability
An Accumulator-Based Compaction Scheme for Online BIST of RAMs (IEEE 2008)
18. An Area efficient Design for programmable Memory Built in Self Test (MBIST) (IEEE 2008)
Digital Signal Processing
19. New Approach to Look-Up- Table Design and Memory- Based Realization of FIR Digital Filter (IEEE 2010)
20. High speed parallel architecture for cyclic convolution based on FNT (IEEE 2009)
21. Design and implementation of 16-bit fixed point digital signal processor (IEEE 2009)
22. High Speed and Low Power FPGA Implementation of FIR Filter for DSP Applications
(Euro Journal 2009)
23. A Reusable Distributed Arithmetic Architecture for FIR Filtering (IEEE 2008)
24. Flexible-Length Fast Fourier Transform (FFT) for COFDM (IEEE 2008)
25. Distributed Arithmetic for FIR filter Design on FPGA (IEEE 2007)
26. A High Performance VLSI FFT Architecture (IEEE 2006)
Image Processing & Compression Techniques
27. Low Cost and Memory less CAVLD Architecture for H.264/AVC Decoder (IEEE 2009)
28. An Efficient Hardware Architecture for Multimedia Encryption and Authentication using the Discrete Wavelet Transform
(IEEE 2009)
29. Low-Power H.264 Video Compression Architectures for Mobile Communication (IEEE 2009)
30. Mixed-radix Algorithm for the Computation of Forward and Inverse MDCT (IEEE 2008)
Bus Protocols
31. Implementation of a Multi-channel UART Controller Based on FIFO Technique and FPGA (IEEE 2007)
Digital Electronics & ALU Architectures
32. Improving FPGA Performance for Carry-Save Arithmetic (IEEE 2010)
33. A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm (IEEE 2010)
34. Field programmable gate array prototyping of end around carry parallel prefix tree architectures (IEEE 2010)
35. An Optimized Design for Serial-Parallel Finite Field Multiplication over GF (2m) Based on All-One Polynomials (IEEE
2009)
36. A Novel carry-look-ahead approach to a unified BCD and Binary adder/Subtractor
(IEEE 2008)
37. Arithmetic Unit for Finite Field GF (2^ {m}) (IEEE 2008)
38. Minimization of Switching Activities of Partial Products for Designing Low-Power Multipliers (IEEE 2003)
Digital Communications
39. Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation (IEEE 2010)
40. An Energy Efficient Layered Decoding Architecture for LDPC Decoder (IEEE 2010)
41. High-Throughput Layered LDPC Decoding Architecture (IEEE 2009)
42. Multi-Gb/s LDPC Code Design and Implementation (IEEE 2009)
43. An FPGA Implementation of 30Gbps Security Module for GPON Systems (IEEE 2008)
44. A High-Speed Viterbi Decoder (IEEE 2008)
45. GSM-Based Remote Sensing and Control System Using FPGA (IEEE 2008)
46. A Low-Complexity Reed-Solomon Decoder (IEEE 2008)
47. Applying CDMA Technique to Network-on-Chip (IEEE 2007)
48. VLSI Architecture for Layered Decoding for irregular LDPC codes (IEEE 2007)
49. High Speed CRC implementation using Pipelining, Unfolding and Retiming (IEEE 2006)
50. Implementation of Digital Binary Phase Shift Keying (BPSK) Modulator & Demodulator (R&D)
General Purpose Processors
51. AXI Compliant DDR3 Controller (IEEE 2010)
52. DDR3 based lookup circuit for high-performance network processing (IEEE 2009)
53. Design and Implementation of a 64-bit RISC Processor using VHDL (IEEE 2009)
54. A Small, Low Power, and Configurable 32-bit RISC Processor (IEEE 2008)
55. An Interrupt Controller for FPGA-based Multiprocessors (IEEE 2007)