32nd Annual International Conference of the IEEE EMBS

Buenos Aires, Argentina, August 31 - September 4, 2010

A Digital Driven Right Leg Circuit

Marcelo Haberman and Enrique Spinelli, Senior Member, IEEE

Abstract— A novel scheme and a digital approach to the are depicted in Fig.2, are due to the potential divider effect
Driven Right Leg Circuit (DRL) are presented. It presents an [1, 2] and to the differences between channel gains when
ultra high common mode (CM) reduction of power line biopotentials at each electrode are independently amplified
interference (higher than 80dB) without endangering stability. [4, 5]. These transformations of VCM into differential mode
This improves by 40-50dB the CM reduction provided by a voltages can be considered, respectively, by their equivalent
classical analog DRL, retaining the same stability criterion. The
improvement comes from the inclusion of a high Q resonator in common mode rejection ratios CMRRPD and CMRRG given
parallel with the common mode amplifier. It provides a large by [3, 5]:
gain at power line frequency (50/60 Hz) whereas it does not
significantly affect the open loop gain for high frequencies. The ZC (1)
CMRRPD = ; ∆Z E = Z E1 − Z E2
proposed scheme can be thought as an analog circuit, but the ∆Z E
accuracy required, mainly in the resonator frequency response,
leads to a digital implementation. In this way, component
ageing and thermal fluctuation problems are avoided, as well as G
CMRRG = ; ∆G = G − G′ (2)
the need for manual adjusting. A prototype of the proposed ∆G
DRL circuit was built and tested in laboratory conditions
showing an open-loop gain of 74dB at 50Hz. It was also tested Considering typical values, these CMRRs could be as low
by acquiring real EEG signals. as 30-40dB then its effects are dominant compared with the
amplifier CMRR. A VCM voltage of 10mV could result in
I. INTRODUCTION differential mode voltages of up to 100µV at amplifier input.
This is a high interference level for ECG measurements and
P OWER line interference affects biopotential acquisition
systems by many ways. The technique to reject it unacceptable for EEG applications.
depends on the coupling mechanism. For instance, capacitive
coupling interference to electrode’s leads can be avoided by Power Line
CP
using shielded cables [1], whereas magnetically coupled iP
interference can be reduced by twisting them, thus reducing
the exposed area [2]. Another gateway for power line
interference is by imposing a Common Mode Voltage (VCM)
between the patient (considered equipotential) and the
amplifier common (GND). As it is depicted in Fig.1, this ZRL GND
voltage is produced by the displacement current iISO flowing iISO
through the electrode-skin impedance ZRL associated to the VCM
CISO
ground electrode.
CB
The value of VCM depends on relationships between stray iB iISO
capacitances (CP, CB, CISO) and, in general, it is about tens of
mV [1]. This common mode (CM) voltage should be easily
Fig.1. Simple interference model to illustrate how power line works as
rejected by a differential biopotential amplifier and a common mode generator.
common mode rejection ratio (CMRR) of 80dB should be
enough to reduce these undesirable voltages below amplifier ZE1
G
noise level [1]; but VCM can become a differential mode ∆ZE
signal before it reaches the amplifier, then it will not be
VoD≈ VCM. VOD= VCM. ∆G
ZE2 ZC
rejected [3]. The main ways of mode transformation, which G’
VCM ZC ZC VCM
Manuscript received March 20, 2010. This work was supported in part GND GND
by the Universidad Nacional de La Plata (UNLP) under Grant I-127,
ANPCyT by project PICT 2007-00535 and by Consejo Nacional de
Investigaciones Científicas y Tecnológicas (CONICET) through project Fig.2. Two common transformations of common mode voltage into
PIP-0253. M. Haberman is with CONICET and UNLP, Dto. Electrotecnia, differential mode voltages: (a) “Potential divider effect”, due to electrode
CC 91 (1900) La Plata, Argentina; email: impedance imbalances and (b) “Gain mismatch”, due to differences
marcelo.haberman@ing.unlp.edu.ar. between gain channels when each electrode potential is independently
E. Spinelli is with CONICET and UNLP (e-mail: spinelli@ieee.org) amplified.

978-1-4244-4124-2/10/$25.00 ©2010 IEEE 6559

 A simple way to lower VCM is reducing the ground
electrode impedance by abrading the skin; but there are other
techniques less awkward for the patient. Some of them work
on the already power line polluted signals and reject the
interference by subtraction, as proposed in [4] for pre-
amplified active electrodes. This method consists on
adapting the balance of a difference amplifier by varying one
of its resistors, in order to compensate the gain mismatch
between active electrodes. Another approach to deal with
common mode interference can be found in [6]. This
technique locks VCM with a PLL to detect its contribution to
the differential signal and subtracts it.
The above mentioned solutions are useful for single
channel systems or for a reduced number of electrodes, but
they are impractical for multichannel applications, because a
complete compensation system is required for each channel,
thus increasing systems complexity.
A method to reject CM interference for all the channels at
the same time is acting directly on VCM as the well known
DRL circuit does. This circuit performs a negative feedback
of the CM patient voltage through the ground electrode as
indicated in Fig.3 (a). This closed-loop technique, widely
used in biopotential acquisition systems, allows reducing
VCM (i.e. the “effective” impedance of the ground electrode)
by the open-loop gain factor [1, 7]. On the other hand, being
a feedback system, it is potentially instable and it must be
designed to ensure its stability. The usual criterion, given
that many of the involved parameters, as electrode
impedances and stray capacitances are widely variable, is
adopting a pessimistic case [7]. Figure 3(b) shows a
simplified scheme of the DRL system including the main
elements that affect its stability: electrode impedances (R0,
RDRL), stray capacitances (CP, CB, CISO) and the capacitor
CSH, which represents the shield capacitance (if shielded
cables are used) and includes input capacitances associated
to the amplifier, protections and RF filters. In order to reduce
analysis complexity, resistors are used to model electrode-
skin interfaces as usual in DRL analysis [1, 7, 8, 10].
Power Line
CP
R0
GDRL(s) GDRL(s)
CSH
GND VCM GND
RDRL
CISO
(a) CB
(b)
Fig.3 (a) General scheme of a DRL system and (b) including the main
parameters that affect its stability.
The DRL circuit can be analyzed as a control loop where a
CM amplifier GDRL acts as a compensation block that feeds
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back to the body the error signal between a desired CM
reference (the amplifier common [7] or a proper dc voltage
[9]) and VCM. In this context, the CM voltage produced by
the power line is viewed as a perturbation that must be
rejected. The open loop gain GH(s) is given by [7, 8]:
GDRL ( s )
GH (s) = (3)
2
s τ 0τ 1 + (τ 0 + τ 1 + τ 2 )s + 1
where
C N = CISO ( CP + CB ) ( CISO + CP + CB ) ; τ 0 = R0CSH ;
τ 1 = RDRLCN and τ 2 = RDRLCSH
Adopting a pessimistic case: R0=RDRL=200kΩ; CP=2pF
and CISO=CB=CSH=200pF, (2) becomes:
GDRL ( s )
GH (s) = (4)
(1 + s ( 2π1.5kHz ) ) (1 + s ( 2π10.4kHz ) )
As shown in (4) GH(s) presents a low frequency pole at
fC=1.5kHz and a second pole nearly a decade higher [7]. For
frequencies below fC, the open-loop gain is approximately
given by the CM amplifier gain (i.e. GH≈GDRL) and the CM
rejection at power line frequency is given by the gain that
GDRL provides. The usual compensation approach consists in
using an integrator as GDRL with a time constant τi such that
its gain is unity (0dB) at the lowest pole frequency (fC) [7, 8],
thus ensuring a phase margin of 45 degrees. Therefore, for fC
=1.5kHz; τi=100µs and the GDRL of (5) result. This is the
usually τi adopted value, but lower time constants (e.g. 10µs)
can be used for better stability conditions, as when CSH is
reduced by shield-driver circuits and protections and RF
filters at the input stage are avoided [1].
1 1 (5)
GDRL,CLASSIC (s) = =
τ is (100µs ) s
As it was depicted, in the classical design approach, the
DRL gain given by (5) is designed accounting for stability
and an open loop gain at 50Hz of about 30dB results. This
implies a CM reduction of 30 times.
In this work, we propose a novel scheme for GDRL,
intended to achieve an ultra high gain at 50Hz to improve
interference rejection but without jeopardizing circuit
stability.
II. PROPOSED SCHEME
The main interference in biopotential measurements is due
to power line, so the ideal DRL should have a gain as high as
possible at power line frequency (fPL=50/60Hz). Usually, the
DRL is designed for stability, and a limited interference
rejection results. As it was previously stated, classical DRL
approach implements the DRL amplifier GDRL as an
integrator (5) that provides approximately 30dB gain at fPL.
In order to achieve a higher gain at power line frequency, we
propose to introduce a high Q resonator at fPL in parallel with
the classical integrator (Fig.4), thus resulting the following
GDRL transfer function: 80

GDRL ( s ) =
1
+K 2
( 2πf PL ) (6)
60
2
τ is s + ( 2πf PL Q ) s + ( 2πf PL )

|GDRL| (dB)
40

20
2

R (s ) = K
( 2πf PL ) 0
2 2
s + ( 2πf PL Q ) s + ( 2πf PL ) -20

-40
1 10
0 1
10 10
2
10
3

τ is
Fig. 4: Proposed structure for the CM amplifier GDRL.
The resonator transfer function R(s) must provide a high
gain at power line frequency, while its contribution close to
the cutoff frequency fC must be negligible when compared to
the integrator gain at this point (0dB). In this way, GDRL
presents a high gain at fPL whereas it behaves as the classic
integrator for high frequencies (see Fig. 5). This is the key
issue to keep the stability conditions of the classical
approach: a phase margin of 45 degrees. In summary, the
design conditions for R(s) are a huge gain at fPL and a
reduced gain (lower than unity) at fC:
R ( j 2πf PL ) = KQ
(7)
2
R(2πf C ) ≈ K ( f PL f C ) ≪ 1
Power line common mode voltage will be reduced by the
open loop gain at this frequency, i.e. by KQ. Then, selecting
a high enough Q factor and an appropriate dc gain K, it is
possible to choose the peak gain and the bandwidth
BW=2πfPL/Q.
The implementation of the proposed scheme requires a
high Q circuit with a very precise central frequency f0. This
is difficult to achieve by analog circuits having in mind
aging, tolerance and temperature sensibility of the electronics
devices. Therefore, a fully digital implementation of the
DRL was adopted, which provides a precise and time stable
transfer function.
III. SYSTEM DESIGN & IMPLEMENTATION
A general scheme of the proposed digital DRL (DDRL)
circuit is shown in Fig.6, which was supported by a low-cost
Digital Signal Controller (DSC) DSPIC33FJ128GP802 of
Microchip Technology. Digital processing was made in 16
bits fixed-point arithmetic at a sampling rate of 40kHz. The
common mode voltage VCM was sampled using a 12 bit ADC
embedded in the DSC. A CM voltage amplifier (with a gain
of 10) was included prior to the ADC in order to make a
good use of ADC dynamic range.
Frequency (Hz)
Fig.5. Common mode amplifier gain GDRL for the classic approach (in
black dashed line) and for the proposed scheme (solid line). It is also
indicated (in gray dashed line) the gain of the high Q resonator.
The transfer function GDRL was implemented using a
space-state approach in order to achieve the best pole
location placement resolution for the limited coefficient
precision (16 bits) [11]. The DSC performs all the digital
signal processing and transfers the output through its SPI
channel to a 16 bit digital-to-analog-converter (DAC8830 of
Texas Instruments), which finally converts the digital signal
to the analog world.
Fixed point arithmetic introduces restrictions in the pole
locations [11, 12], then only a discrete number of pole places
are possible. A pole location set which produces a central
frequency of 49.93 Hz and a Q factor of 130 (BW=0.4Hz)
was selected. Adopting K=127, the conditions in (7) are
fulfilled, providing a GDRL gain of 84dB at 50Hz. Using a
floating-point DSP it is possible to achieve a better pole
placement resolution, but it implies increasing cost,
complexity and power consumption: a reduced resource in
battery powered equipments. Anyway, a reduction of 70-
80dB is enough. An unusual high CM patient voltage, let say
100 mVp-p, will be reduced to 30 µVp-p. Even regarding a
CMRR as low as 30 dB, the differential mode signal
produced by VCM will be below the electrode/amplifier noise,
which is typically higher than 2-3 µV p-p.
DDRL
DSPIC33FJ128
10 ADC
VCM(t)
DAC8830
y(t) y[n] e[n]
DAC GDRL(z)
Fig. 6: Simplified scheme of the implemented DDRL.

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 IV. EXPERIMENTAL RESULTS
The proposed DDRL was implemented and its transfer
function was verified in laboratory conditions. The resulting
experimental data are shown in Fig.7. The circuit shows a
remarkable gain of 74dB at power line frequency. The
difference between the experimental gain of 74 dB and the
theoretical 84 dB are due to the limited arithmetic and ADC
resolution.
In order to test the proposed DRL scheme with real EEG
signals, one channel of occipital visual alpha rhythm was
acquired. The front end was performed by two single-ended
non-inverter preamplifiers as used in [4], with unbalanced
gains of 10.873 V/V and 10.804 V/V respectively (this
implies a CMRR of about 44dB). The non-inverter
preamplifiers were built with a low noise TLC2274 op-amp..
The result is the signal shown in Fig.8, where no power line
interference is observed, thus verifying the feasibility of the
proposed scheme. When DRL was not used, and the
reference electrode was connected to amplifier’s common,
the EEG signal acquired was corrupted completely by a
power line interference level of about 100µV. A future work
will be to compare the rejection of the proposed circuit to the
classical DRL case for different EMI situations.
80
60
40
|GDRL| (dB)
20
0 1
10 10
2 3
10
Frequency (Hz)
Fig. 7. Open loop DDRL frequency response. The designed frequency
response is indicated in solid line and the experimental data with markers.
The dashed line curve represents classical DRL frequency response.
EEG amplitude (µV)
20
10
0 [6]
-10
-20
1 1.5 2 2.5 3 3.5 4 4.5
Time (s)
Fig. 8. EEG signal (alpha rhythm) acquired as subtraction of two single
ended channels while common mode is reduced by the proposed DDRL.
No power line interference is present.
V. CONCLUSIONS AND FUTURE WORK
A novel digital DRL circuit, which provides a high
common mode voltage reduction, was proposed. Typically, it
reduces CM voltages by more than 70dB, providing an
improvement of around 50dB respect to classical DRL. Its
digital implementation avoids the effects of ageing and
temperature sensibility of analog circuits. Also, it constitutes
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a flexible and versatile platform to develop and test other
strategies to reject power line interference.
The system is intended having in mind multichannel
monopolar acquisition applications, where independent
amplification at each electrode is performed. Also, it is
advantageous to be used with recently proposed capacitive
coupled electrodes [13]. In these last cases, the common
mode potential is the main interference source, because of
small differences between gain channels transform common
mode voltages to differential mode ones.
A fully digital DRL prototype, using a low-cost DSC with
16 bit arithmetic, allowed achieving a power line CM
reduction higher than 70dB. This relaxes CMRR
requirements, making techniques as single-ended amplifiers,
preamplified active electrodes and capacitive electrodes
feasible. In this implementation the DDRL demanded just the
31% of CPU time (at 40MIPS) allowing to use the same
DSC for other tasks as biopotential acquisition.
Works oriented to compare the features of the proposed
scheme to the classical DRL are underway. The application
of the proposed scheme in EEG multichannel acquisition
systems and its adaptation for capacitive coupled electrodes,
are also scheduled.
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