6 — Designing the Memory System

Objectives

The aim of this LAB experiment is to design the third phase of our microcomputer system
by interfacing the 8086 to a small memory system using SRAM and EPROM memory
chips. 

6.1 8086 Memory Mapping

The 8086 microprocessor has 20-bit address lines (A19 − A0) capable of addressing 1MB.
This memory space can be accessed through 16-bit data lines (D15 − D0) during memory
read/write cycles.
Basically, ROM and RAM memory chips are byte organized. Therefore, the 8086 micro-
processor requires a memory module to be organized as two banks (each 8-bit wide) called
the even and odd banks. The ROM memory is used to store resident programs that must
run when the microprocessor system is powered on. The RAM memory is used to store
application programs that are ready to run as well as to provide some reserved locations
for the proper operations of interrupts. The designer must be careful with bank selection
especially when dealing with read/write memories. In this case, byte operations with one
bank must be done while enabling one of the memory banks and disabling the other.

6.2 Designing the Memory System

In this experiment, we will design a memory system consisting of two memory modules as
shown in Figure 6.1. The first module is a 16KB SRAM starting at address 00000H, whereas
58 Designing the Memory System

the second is a 16KB EPROM ending at address FFFFH. The EPROM module is mapped
specifically to this range in the memory space because, on reset, the 8086 microprocessor
begins executing instructions at location FFFF0H. This location is called the boot-strap
and typically contains a jump instruction that transfers execution to a location of the
ROM where a start-up program is stored. In our design, we will use two 6264 (8KB) SRAM
memory chips and two 2764 (8KB) EPROM memory chips. You can refer to the data sheets
of these two chips to familiarize yourself of their pin functions.

FFFFFH
ROM
16KB
FC000H

1MB

03FFFH
RAM
16KB
00000H

Figure 6.1 – Mapping of the ROM and RAM modules into the 8086 memory
space.

Exercise 6.1 Based on the design requirements of the memory system discussed above, answer the
following questions :
1. How to decode the RD, W R and M/IO signals to generate the following memory and I/O read
and write control signals : M EM R, M EM W , IOR and IOW ?
2. How to design the 32KB memory system using full address decoding ?
3. How to design the same memory system using partial address decoding ?
4. Which address decoding approach should we use for our design ? Why ?
5. Which of 8086 address lines are required to address the two modules ?
6. How to distinguish the even and odd banks of the SRAM module ?
7. Is it necessary to distinguish the even and odd banks of the EPROM module ? Why ? 

Memory and IO Control Signals (Control Bus Decoder)

The 8086 microprocessor provides three control signals RD, W R and M/IO signals which
can be decoded as shown in Figure 6.2 to generate the required memory and I/O control
signals (i.e. M EM R, M EM W , IOR and IOW ).

Exercise 6.2 Open the bus system design built in Experiment 5 and create a new design sheet with
title "Control Bus Decoder". In the newly created design sheet, draw the schematic of the control bus
decoder shown in Figure 6.3. 
6.2 Designing the Memory System 59

RD
IOR

MEMR

M/IO

MEMW

IOW
WR

Figure 6.2 – Decoding memory and I/O read and write signals.

Figure 6.3 – Schematic of the control bus decoder.

60 Designing the Memory System

Address Decoding
In this project, we will consider partial address decoding because our 8086-based micro-
computer system uses only a small part of the 1MB memory space. It is only necessary to
distinguish two memory modules (i.e. RAM and ROM), and hence, only one address line
is needed for address decoding. Figure 6.4 shows that the two modules differ in the 6 most
significant address lines A19 − A14. Thus, we can use any one of these address lines to build
the address decoder (say A19). This decoder, as shown in Figure 6.5, is simply just a single
inverter.
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RAM
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ROM
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Address Address
Decoding Lines

Figure 6.4 – Address decoding of the RAM and ROM memory modules.

RAM_SELECT

A19 ROM_SELECT

Figure 6.5 – Partial address decoder.

Memory Bank Selection

As you know the RAM module allows write operations that change content of the memory.
Thus, we need to make sure that a write operation will modify the correct memory location.
A proper selection of even and odd banks of the RAM module is an essential requirement
of the memory system design. The 8086 provides a special signal (BHE) that can be used
together with the address line A0 to enable the proper memory bank as shown in Table 6.1.
The logic necessary to select even and odd banks of the RAM module is shown in Figure 6.6.
Table 6.1 – Memory bank(s) selection in 8086

BHE A0 Bank(s) Selected

0 0 Both banks (D15 − D8 and D7 − D0
0 1 Odd bank (D15 − D8)
1 0 Even bank (D7 − D0)
1 1 None

The ROM module, on the other hand, does not require any logic to select the even/odd
banks. This is because the ROM module allows only read operations which are considered as
safe operations. Therefore, both the even and odd banks are enabled during a read operation
6.2 Designing the Memory System 61

A0
RAM_EVEN

A19

RAM_ODD
BHE

Figure 6.6 – Logic to select even/odd banks of the RAM module.

and 8086 will select the required byte(s) from the data bus. An unneeded byte on the data
bus is simply ignored by the processor.

Connecting Address and Data Lines

The complete memory system design is shown in Figure 6.7. As indicated in our design
specifications, each one of memory modules (i.e. RAM and ROM) consists of two 8KB
memory chips. So, each memory chip requires 13 address lines (note that 8K = 23 × 210 =
213 ). As shown in Figure 6.4, the address lines A13 − A1 are used to address each individual
memory bank and A0 is used together with BHE to select even/odd banks. The even bank
chips are connected to the even byte of the processor (D7 − D0), while odd bank chips are
connected to the odd byte (D15 − D8).

D7-D0 D15-D8 D7-D0 D15-D8

IO7-IO0 IO7-IO0 IO7-IO0 IO7-IO0

A12-A0

A12-A0

A12-A0

A12-A0

A13-A1
8KB 8KB 8KB 8KB
RAM RAM ROM ROM
MEMR OE OE OE OE
MEMW WE WE
CS CS CS CS

A0
RAM_EVEN
A19 A19
ROM_SELECT

BHE RAM_ODD

Figure 6.7 – The complete memory system design.

Exercise 6.3 Create a new design sheet with title "Memory System" and draw the schematic of the
memory system as shown in Figure 6.8. 
62 Designing the Memory System

Figure 6.8 – Schematic of the complete memory system design.

 6.2 Designing the Memory System 63

6.2.1 Testing the Memory System

In this part of the experiment, we will test our memory system using digital analysis while
the 8086 model is running very simple memory read and write operations. For this purpose,
we will write two assembly programs and add few connections to our schematic in order to
test memory read and write cycles. For simplicity, the RAM and ROM modules will be test
separately as will be explained in the two next subsections. However, testing both modules
require the same digital analysis configurations shown in Figure 6.9.

Figure 6.9 – Digital analysis configurations required for testing the memory
system.

Testing the RAM Module

Testing the RAM module involves the following steps :

1. Write an assembly code (see Program 6.1) to write one word to memory location at
address 0000 :0120 and read it back.
2. Compile and link the assembly code to generate the executable file.
3. Load the executable file into the internal memory of the 8086 simulation model.
4. Run the digital analysis simulation.
64 Designing the Memory System

Program 6.1 A Simple Memory Read/Write Program

01 ; assembly code to write one word to memory location at address 0000:0120

02 ; and read it back.
03 .MODEL SMALL
04 .8086
05 .STACK
06 .CODE
07 .STARTUP
08 MOV AX, 0
09 MOV DS, AX
10 MOV BX, 0120H
11 MOV AX, 3B7CH
12 MOV [BX], AX
13 MOV AX, [BX]
14 ENDLESS_LOOP:
15 JMP ENDLESS_LOOP
16 .DATA
17 END

After completing your design according to the previous procedure, you should obtain
a timing diagram similar to the one shown in Figure 6.10. This timing diagram shows a
memory write cycle to the RAM module followed by a memory read cycle from the RAM
module. The behavior of each monitored signals in this diagram is explained as follows :
– The ALE signal is active in T 1 in the memory write cycle as well as in the memory
read cycle.
– The M/IO signal is active HIGH in both bus cycles which indicates a memory access.
– The W R signal is active LOW in the first bus cycle which indicates a memory write
cycle.
– The RD signal is active LOW in the second bus cycle which indicates a memory read
cycle.
– The address 00120H is latched on the address lines A19 − A0 at the end of T 1 of each
bus cycle.
– The data lines D15 − D0 carry the correct data word 3B7CH in both bus cycles.

Testing the ROM Module

Before starting the test procedure, we need to load some data into the EPROM chips.
This can be done easily using a text file formatted according to Intel HEX format. The
details of this hex format is out of the scope of this LAB manual. An interested reader can
refer to the following Wikipedia website (http ://en.wikipedia.org/wiki/Intel_HEX). In this
experiment, we will load data into the EPROM chips according to Table 6.2.

Data
Offset Address Even EPROM Odd EPROM
1710H ACH 7DH
1712H 36H EBH

Table 6.2 – Sample data to be loaded into EPROM chips.

6.2 Designing the Memory System 65

Figure 6.10 – Result of the digital analysis of an 8086 a RAM read and write
cycles.
66 Designing the Memory System

The following procedure can be used to load data into the EPROM chips :
1. Using any text editor, type the data shown below in Intel HEX format and save the
file as "rom_data.hex" in the same directory as your design file.

:04171000AC7D36EB8B
:00000001FF

2. Double click the even EPROM chip to open its properties window and edit the follo-
wing properties as shown in Figure 6.11 :
– In Image File text box type the name of the data file "rom_data.hex".
– In File Base Address text box type the value 0. Note that this property is used to
re-map the addresses in the file in order to achieve byte splitting between even and
odd chips. Setting this property to 0 assigns even bytes (i.e. bytes 0, 2, . . . , etc.) to
this chip.
– In File Address Shift text box type the value 1. Note that this property is used
to shift the addresses in the file by a certain number of bits. In the case of 8086
microprocessor, the address is shifted by 1 bit because A0 is used to distinguish
even and odd banks and not used as part of the address lines connected to the
memory chip.
– Click OK button to save these setting.
3. Double click the odd EPROM chip to open its properties window and edit the following
properties :
– In Image File text box type the name of the data file "rom_data.hex".
– In File Base Address text box type the value 1. Setting this property to 1 assigns
odd bytes (i.e. bytes 1, 3, . . . , etc.) to this chip.
– In File Address Shift text box type the value 1.
– Click OK button to save these setting.
Testing the ROM module involves the following steps :
1. Write an assembly code (see Program 6.2) to read two words from the following me-
mory addresses : FC00 :1710 and FC00 :1712.
2. Compile and link the assembly code to generate the executable file.
3. Load the executable file into the internal memory of the 8086 simulation model.
4. Run the digital analysis simulation.
After completing your design according to the previous procedure, you should obtain a
timing diagram similar to the one shown in Figure 6.12. This timing diagram shows two
memory read cycles from the ROM module. The behavior of each monitored signals in this
diagram is explained as follows :
– The ALE signal is active in T 1 in both memory read cycles.
– The M/IO signal is active HIGH in both bus cycles which indicates a memory access.
– The RD signal is active LOW in both bus cycle which indicates two memory read
cycles.
6.2 Designing the Memory System 67

Figure 6.11 – Editing the properties of the even EPROM chip

– The address FD710H (F C00 :1710)is latched on the address lines A19 − A0 at the end
of T 1 of first bus cycle.
– The address FD712H (F C00 :1712)is latched on the address lines A19 − A0 at the end
of T 1 of second bus cycle.
– The data lines D15 − D0 carry the correct data words 7DACH and textEB36H res-
pectively.

Program 6.2 A Simple Memory Read Program

01 ; assembly code to read two words from the following memory addresses:
02 ; FC00:1710 and FC00:1712.
03 .MODEL SMALL
04 .8086
05 .STACK
06 .CODE
07 .STARTUP
08 MOV AX, 0FC00H
09 MOV DS, AX
10 MOV BX, 1710H
11 MOV AX, [BX+0]
12 MOV AX, [BX+2]
13 ENDLESS_LOOP:
14 JMP ENDLESS_LOOP
15 .DATA
16 END
68 Designing the Memory System

Figure 6.12 – Result of the digital analysis of an 8086 a ROM read cycles.