VLSI LAB MANUAL

B.Tech ECE Vth SEMESTER

 EXP:1 DESIGN AND IMPLEMENTATION OF CMOS INVERTER

AIM: To design and simulate the CMOS Invertor.

TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave and Calibre tools in Mentor
Graphics..
Introduction:
This document gives an overview of CMOS design using Mentor Graphics Tools.
There are five basic steps:

1. Design the schematic in Pyxis schematic.

2. Simulate the schematic using ELDO / AMS.
3. Physical design using Pyxis Layout.
4. Perform Physical Verification using Calibre which includes DRC, LVS and PEX.
5. Back annotation of parasitics into the schematic for post layout simulation.

Invoking Mentor tools:

• Click on the Xmanager Enterprise3 on desktop.
• Clock on Xstart and RUN.
• Type csh and press enter.
• Type source /home/software/cshrc/ams_2009.cshrc which will invoke the mentor tools
environment.
We get “Welcome to Mentor Graphics” statement
• Type dmgr_ic & to invoke the Pyxis manager tool shown below.
•

Creating a Project:

To create a new project click on “File  new  project “which invokes the new project
window as shown
Browse on the folder and specify the “project path” by creating a new folder in present
working directory in user as shown below

Next Technology Libraries have to be added to the project.

In order to add the technology files browse on the folder as shown
LibraryhomesoftwareFoundryGDKPyxis_SPT_HEPic_reflibstech_libs
generic13 click on OK.
Again click on OK then manage external / logic libraries window will pop up as shown

 Then the libraries will be added up as shown below

Click on the “Add Standard Libraries”
Click on OK
• Then the pyxis project manager window will be shown where the technology
libraries are added to the project and are placed below the project name

Creating a Library:
• To create a library right click on the project name and select new library or
click on the icon on the icon bar

• Then a new library window will pop up asking for the library name.
Give library name (cmos-inv) and OK

Next name the library and click on OK.

Creating a Schematic cell view:
• To create a schematic cell view, a new cell has to be created in which new schematic
has to be defined.
• In order to create new cell right click on the manual library (cmos-inv) below the
project name and select new cell or

• Select the library and click on icon in the icon bar.

• Then a “New cell” window will pop up asking for the cell name in which give the
cell name (inv) and click OK.

• To create a schematic in the cell, right click on the cell name (inv) and select new
schematic or click on the new cell and select the icon in the icon bar
• A window will pop up asking for the schematic name

Now name the schematic (invschematic) and click on OK which in turn leads to the pyxis
schematic editor window as shown

Creating a Schematic:
In this section you will become familiar with placing primitive analog devices for an
inverter.
You’ll learn how to:
• place primitives on the schematic
• select and manipulate devices
• customizing hotkeys for placing devices
• route devices
• edit device parameter values
• name instances
• check and save the schematic
• create upper hierarchical symbols
• create test bench
• simulate using Eldo
• view results

Creating an Inverter:

Placing devices:
 • From the left icon bar press on add instance icon

or press “ctrl+I”

• Then a file browser which contains entire libraries will pop up as shown

• Next click on the double click on “generic13” in the library list

And then follow the path to select pmos from $generic13/symbols/pmos as shown

• Select the pmos and click on OK to place the pmos on the workspace as shown
Changing device properties
In order to change the properties of the devices on the workspace select the device in
workspace and click ‘Q’ then the corresponding device properties will be shown in the
object editor as shown.

Now enter the prescribed value in the field provided and press enter .Then the value will be
changed .Here the width has been set to 0.13u and length to 0.13u.

• Similarly select the nmos and change the W=0.15u, L=0.13u and the schematic
would look as follows

Adding the ports and connecting the devices

In the similar way select the VDD and ground from the generic lib or click on the library in
the layer palatte window then layer palatte will be shown as ic library window. Then select
generic library and place VDD and ground
• Place in IN and OUT ports in a similar way as above from the generic library or click on
the add ports icon in the left icon bar and connect the circuit
Then the schematic would look as follows
For changing the port names click on the port and change the net name in the object editor
to the required name which is shown below.
To change the name, enter the name in the field given for the net name and press enter. Then
the schematic will be as shown

• Next click on check/save icon in the icon bar

This will result to a window which shows the error report where the errors and
warnings in the schematic can be seen
Generating a symbol:
To generate a symbol select “Add” in the menu bar and then select “generate symbol”
from pull down menu bar
Add --> generate symbol

• A generate symbol will pop up as shown

• Here check activate symbol as shown above. If you want set shape of the symbol
select it from choose shape. Then click on OK which leads to the pyxis symbol window.
Make sure to check “Replace existing”, “Activate Symbol” and “Edit Symbol” and click on
“Choose Shape” as shown below
Select Buffer then click OK and OK in symbol setting window
Now add circle to buffer as shown below by selecting circle symbol from left menu bar
 • Next click on check/save icon in the icon bar

Creating a Test bench

• To create a test bench close the pyxis schematic and symbol windows and go back to
pyxis project manager window. In the project manager window to create new cell
right click on the manual library (cmos_inv) below the project name and select new
cell or select the library and click on the icon in the icon bar

• Then a new cell window will pop up asking for the cell name in which give the
cell name and click OK

Here the test bench cell name has been specified as inv_tb
• Right click on the test bench cell and select new schematic which in turn opens
pyxis schematic editor window

• Now instantiate the new inverter symbol by selecting Add  Instance  Choose
symbol Select the Symbol view of the inverter cell from the inv cell of the manual
library
Place the symbol on the work space as shown

. Add the IN and OUT net as before by selecting the hot key i. Name the nets with hot key
“q”.
. Defining input pattern from Palette area: Sources library PATTERN and place in work
space.
• Now edit Pattern using object editor ( by click on hotkey ‘q’).
 • Add and define VDD and Ground ports from Palette area.

Add a DC voltage source dc_v_source, from Palette area (Sources library Dc (V)). And
place the DC source on work space. Change the value of the DC Mag to be 3.3 V. Add
PULSE voltage source pulse_v_source and change the value of the pulse_value property to
be 3.3 V also change the delay to be 0S.
Finally the circuit looks like the following

• Next click on check/save icon in the icon bar

This will result to a window which shows the error report where the errors and
warnings in the symbol can be seen.
Simulating the schematic:
Simulating test bench

When you have no errors select the Simulation icon from the left icon palette and go to
simulation or “context” and “Enter simulation mode” in the menu bar and run
simulation.

In the design context from menu bar select Simulation-> setup simulation or click on
setup simulation icon in the left icon palatte.
Click “New design configuration”

Click on OK and OK

Click on Analysis in palette area

A set up simulation window will pop up as shown
Select TRAN in “Analysis Selector”.

To set up analysis select analysis in the simulation panel and in the analysis setup select
the required analysis and set the values of the analysis in the beside window as shown above
Here I have selected the transient analysis with the start time as 0ns,
stoptime=100ns
and print timestep=5ns as shown.

After specifying the values click on apply

• To probe the waveforms, click on the outputs in the selection panel (Palette area) ,
then select the input and output ports of the schematic in the pyxis schematic window
as shown.

• Click on “Selection from Schematic” click on input and output terminals of design and go back to
outputs window (In the setup simulation window , click Add button then the port will
be added to the waveform as shown)
Click on APPLY
Click on the outputs in the selection panel (Palette area) , then select the Device in the
pyxis schematic window as shown

Similarly add all the waveforms required to see in the ezwave.

• To add the power plot select the symbol in simulation schematic, click on outputs
it opens simulation setup. Here we have to select
Analysis -> TRAN
Task -> Plot
Type -> Power

Click Add button then the Device will be added to the objects window
Click on “APPLY” then “OK & RUN”

Now it enters into simulation mode

In palette area Results view waves

View the simulation results by selecting the plot results from latest run icon from the left
icon palatte. This will open EZWave for you with the output waveforms. This is how the
waveforms look like after zooming

Click on Measurement tool in the icon bar which opens up the measurement tool window
where we can measure the different properties of your waveforms
Delay measurement :

In order to measure delay select the Measurement tool in Ezwave window and select the
Below options

Measurement -> Delay

Waveform(#1) -> select V(A) and add selected waveform

Waveform(#2) -> select V(Y) and add selected waveform

In Measurement setup select

Waveform(#2) Edge Relationship : Inverting

Enable the Find Closest reference edge option. And click ok.
This process shows you how to measure the delay between input and output.

DC Analysis:

• For adding DC analysis click on Analysis button in palette pane of simulation

environment, enable the DC option as displayed below, click apply and ok.

• Now select the input and output nets in simulation schematic and click on
outputs button and select the following options for DC analysis outputs
Analysis  DC Task Plot Type  Voltage
then click on add button and click ok.
After adding the outputs click on Run ELDO (the log should display netlist completed
successfully and Simulation completed successfully). Then click on View waves to
visualise the DC analysis results.

Now use Add Cursor option to visualise the switching voltage of the design.
 EXP:2 DESIGN AND IMPLEMENTATION OF NMOS INVERTER

AIM: To design and simulate the NMOS INVERTER.

TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.

CIRCUIT DIAGRAM:

SIMULATION CIRCUIT:
PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Pyxis schematic.
2. Create a simulation schematic for simulation.
3. Add necessary nets in outputs to view waveforms.
4. Run the Simulation and observe results in EZwave.
5. Draw the Layout for the circuit using Pyxis Layout.
7. Run the physical verification (DRC, LVS, PEX) using Calibre tool.
8. Run the post layout simulation by adding the .dspf file generated in PEX.
9. Observe the post layout results.
LAYOUT: Use auto Layout in tool to get LAYOUT.

RESULT:
 EXP:3 DESIGN AND IMPLEMENTATION NMOS AND GATE using PASS
Transistor

AIM: To design and simulate the NMOS AND GATE using PASS Transistor.

TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.

CIRCUIT DIAGRAM:

SIMULATION CIRCUIT:
PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Pyxis schematic.
2. Create a simulation schematic for simulation.
3. Add necessary nets in outputs to view waveforms.
4. Run the Simulation and observe results in EZwave.
5. Draw the Layout for the circuit using Pyxis Layout.
6. Run the physical verification (DRC, LVS, PEX) using Calibre tool .
7. Run the post layout simulation by adding the .dspf file generated in PEX.
8. Observe the post layout results.

LAYOUT: Use auto Layout in tool to get LAYOUT

RESULT:
 EXP:4 DESIGN AND IMPLEMENTATION OF CMOS NOR Gate

AIM: To design and simulate the CMOS NOR gate

TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.

CIRCUIT DIAGRAM:

SIMULATION CIRCUIT:

PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Pyxis schematic.
2. Create a simulation schematic for simulation.
3. Add necessary nets in outputs to view waveforms.
4. Run the Simulation and observe results in EZwave.
5. Draw the Layout for the circuit using Pyxis Layout.
6. Run the physical verification (DRC, LVS, PEX) using Calibre tool .
7. Run the post layout simulation by adding the .dspf file generated in PEX.
8. Observe the post layout results.
LAYOUT:

RESULTS:
 EXP:5 DESIGN AND IMPLEMENTATION OF CMOS NAND Gate

AIM: To design and simulate the CMOS NAND gate.

TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.

CIRCUIT DIAGRAM:

SIMULATION CIRCUIT:

PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Pyxis schematic.
2. Create a simulation schematic for simulation.
3. Add necessary nets in outputs to view waveforms.
4. Run the Simulation and observe results in EZwave.
5. Draw the Layout for the circuit using Pyxis Layout.
6. Run the physical verification (DRC, LVS, PEX) using Calibre tool .
7. Run the post layout simulation by adding the .dspf file generated in PEX.
8. Observe the post layout results.
LAYOUT:

RESULT:
 EXP:6 DESIGN AND IMPLEMENTATION OF XOR Gate using Transmission
Gates

AIM: To design and simulate the XOR Gate using Transmission Gates.

TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.

CIRCUIT DIAGRAM:

SIMULATION CIRCUIT:
PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Pyxis schematic.
2. Create a simulation schematic for simulation.
3. Add necessary nets in outputs to view waveforms.
4. Run the Simulation and observe results in EZwave.
5. Draw the Layout for the circuit using Pyxis Layout.
6. Run the physical verification (DRC, LVS, PEX) using Calibre tool .
7. Run the post layout simulation by adding the .dspf file generated in PEX.
8. Observe the post layout results

LAYOUT: Use auto Layout in tool to get LAYOUT

RESULTS:
EXP:7 DESIGN AND IMPLEMENTATION OF FULL ADDER

AIM: To design and simulate the CMOS 1 Bit Full Adder.

TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.

CIRCUIT DIAGRAM:

SIMULATION CIRCUIT:

PROCEDURE:
1. Connect the Circuit as shown in the circuit diagram using Pyxis schematic.
2. Create a simulation schematic for simulation.
3. Add necessary nets in outputs to view waveforms.
4. Run the Simulation and observe results in EZ wave.
5. Draw the Layout for the circuit using Pyxis Layout.
7. Run the physical verification (DRC, LVS, PEX) using Calibre tool .
8. Run the post layout simulation by adding the .dspf file generated in PEX.
9. Observe the post layout results.
LAYOUT:

RESULTS:
 Aditional Experiment: DESIGN AND IMPLEMENTATION OF RS LATCH

AIM: To design and simulate the CMOS RS Latch

TOOLS: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.

CIRCUIT DIAGRAM:

SIMULATION CIRCUIT:

PROCEDURE:
1. Connect the Circuit as shown in the circuit diagram using Pyxis schematic.
2. Create a simulation schematic for simulation.
3. Add necessary nets in outputs to view waveforms.
4. Run the Simulation and observe results in EZwave.
5. Draw the Layout for the circuit using Pyxis Layout.
7. Run the physical verification (DRC, LVS, PEX) using Calibre tool .
8. Run the post layout simulation by adding the .dspf file generated in PEX.
9. Observe the post layout results.
LAYOUT:

RESULTS:
 Viva questions

1. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
2. What are set up time & hold time constraints? What do they signify?
3. explain Clock Skew?
4. Why is NAND gate preferred over NOR gate for fabrication?
5. What is Body Effect?
6. Why is the substrate in NMOS connected to Ground and in PMOS to VDD?
7. What is the fundamental difference between a MOSFET and BJT ?
8. Why PMOS and NMOS are sized equally in a Transmission Gates?
9. What happens when the PMOS and NMOS are interchanged with one another in an inverter?
10. Why are pMOS transistor networks generally used to produce high signals, while nMOS
networks are used to product low signals?
11. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you
avoid Latch Up?
12. Difference between Synchronous and Asynchronous reset.
13. What is DRC ?
14. What is LVS ?
15. What is RCX ?
16. What are the differences between SIMULATION and SYNTHESIS?
17. What is a counter?
18. What are the differences between flipflop and latch?
19. How can you convert JK flipflop into Jk?
20. What are different types of adders?
21. Give the excitation table for JK flipflop?
22. Give the excitation table for SR flipflop?
23. Give the excitation table for D flipflop?
24. Give the excitation table for T flipflop?
25. What is the race around condition?
26. What is an amplifier?
27. What is an op-amp?
28. What is differential amplifier?
29. What is elaboration?
30. What is transient analysis?
31. What is DC analysis?
32. What is AC analysis?