Compal Confidential: Q5WV1 M/B Schematics Document

A B C D E
Compal Confidential
Model Name :Q5WV1/Q5WS1
Compal Project Name :
1 1
File Name : LA-7912P
Compal Confidential
2 2
Q5WV1 M/B Schematics Document

Intel Sandy/Ivy Bridge Processor with DDRIII + Panther Point PCH
Nvidia N13P GS/GL
3
2012-02-03b 3
REV:0.3
ZZZ2 1G@ ZZZ3 2G@

MB PCB
4 4
Part Number Description
DA60000SV00 PCB 0N4 LA-7912P REV0 M/B
X76344BOL01 X76344BOL02
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A7912
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019ID
Date: Friday, February 10, 2012 Sheet 1 of 63
A B C D E
A B C D E
Fan Control
page 42
1 1
x16 Gen3(N13P-GS) Intel Memory BUS(DDRIII)

Nvidia
x16 Gen2(N13P-GL)
Dual Channel 204pin DDRIII-SO-DIMM X2
100MHz x8 Gen2(N13M-GS) PER LANE
PEG(DIS) Sandy/Ivy Bridge BANK 0, 1, 2, 3 page 11,12
N13P GS/GL 133MHz
1.5V DDRIII 1066/1333
N13M-GS Processor
page22~30
eDP rPGA989
page31
page 4~10
FDI x8 DMI x4 USB 2.0 conn x2 Bluetooth CMOS Camera

Conn
USB port 1,2 on USB port 11 USB port 10
HDMI Conn. CRT Conn. LVDS Conn. 100MHz 100MHz USB/B page 38 page 38 page 31
page 33 page 32 page 31 2.7GT/s 1GB/s x4
2 USBx14 3.3V 48MHz 2
LVDS(UMA/OPTIMUS)
Intel
CRT(UMA/OPTIMUS) HD Audio 3.3V 24MHz
TMDS(UMA/OPTIMUS) Panther Point-M

USB3.0 PCH
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) 100MHz HDA Codec
989pin BGA ALC271X/281X
port 1 port 5 port 1 SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz page 41
page 13~21 SPI
USB 3.0 LAN(GbE) & port 1 port 0
page 17 USB 3.0 port 2
Card Reader SATA HDD
Fresco FL1009 BCM57785 Conn. page 34
page 38 page 35,36 port 2 SPI ROM (4M)x1 Int. Speaker Phone Jack x 2
SPI ROM (1M)x1
USB3.0 Conn. WLAN page 13 page 41 page 41
mSATA(reserve) SATA CDROM
page 39
Card Reader RJ45 USB port 8 Conn. page 34 LPC BUS
3
page 34 3
Conn. page 35,36 page 36

33MHz
ENE KB930/KB9012
page 39
RTC CKT.
page 13
Touch Pad Int.KBD
page 40 page 40
Power On/Off CKT. Sub-board

page 40
LS-7911P
USB 2.0/B 2Port BIOS ROM
USB Port1,2
page 39 page 40
DC/DC Interface CKT.
4
page 43,44 4
LS-7912P
Power Circuit DC/DC PWR/B
page 41
page 46~59 Security Classification Compal Secret Data Compal Electronics, Inc.
SCHEMATIC,MB A7912
Custom C
4019ID
A B C D E
A B C D E
Voltage Rails
Power Plane Description S1 S3 S5
SIGNAL
VIN Adapter power supply (19V) N/A N/A N/A STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
BATT+ Battery power supply (12.6V) N/A N/A N/A
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
B+ AC or battery power rail for power circuit. N/A N/A N/A
+CPU_CORE Core voltage for CPU ON OFF OFF S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1
+VGA_CORE Core voltage for GPU ON OFF OFF 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+1.05VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU ON OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS_VTT +1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF
+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH ON OFF OFF
+1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF
Board ID / SKU ID Table for AD channel
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF
Vcc 3.3V +/- 5%
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF
Ra/Rc/Re 100K +/- 5%
Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8VSDGPU +1.8VS to +1.8VSDGPU switched power rail for GPU ON OFF OFF
+3VALW +3VALW always on power rail ON ON ON*
0 0 0 V 0 V 0 V
+3VALW_EC +3VALW always to KBC ON ON ON*
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON*
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Jumper) ON ON ON*
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VS +3VALW to +3VS power rail ON OFF OFF
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VALW +5VALWP to +5VALW power rail ON ON ON*
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
2
+5VALW_PCH +5VALW to +5VALW_PCH power rail for PCH (Short resister) ON ON ON*
6 200K +/- 5% 1.935 V 2.200 V 2.341 V 2
+5VS +5VALW to +5VS switched power rail ON OFF OFF

7 NC 2.500 V 3.300 V 3.300 V
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON*
+RTCVCC RTC power ON ON ON BOARD ID Table BTO Option Table
BTO Item BOM Structure
Board ID PCB Revision
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. UMA Only UMAO@
0
EC SM Bus1 address EC SM Bus2 address Dis with OPTIMUS DIS@
1
Blue Tooth BT@
2
Device Address Device Address Internal USB 3.0 PUSB3@
3 0.1
Smart Battery 0001 011X b Internal USB 2.0 PUSB@
4 0.2
PCH SM Bus address USB 2.0 flag PUSB2@
5 0.3
eDP eDP@
6 0.4
Device Address VRAM X76@
7
Clock Generator (9LVS3199AKLFT,
RTM890N-631-VB-GRT)
1101 0010b Connector CONN@
DDR DIMM0 1001 000Xb
Unpop @
3 DDR DIMM2 1001 010Xb
N13P-GS GS@ 3
USB Port Table N13P-GL GL@

4319IDBOL01SMT MB A7912 Q5WV1 HM77 QC UMA 3
Win8 Win8@
3 External
4319IDBOL02SMT MB A7912 Q5WV1 HM77 QC 13PGL1G 3 USB 2.0 USB 1.1 Port Audio ALC271X 271X@
USB Port
Audio ALC281X 281X@
4319IDBOL03SMT MB A7912 Q5WV1 HM77 QC 13PGL2G 3 0 USB3.0 colay USB2.0 Conn
UHCI0 PCH HM65 HM65@
1 USB/B (Right Side)
4319IDBOL04SMT MB A7912 Q5WV1 HM77 QC 13PGS1G 3 PCH HM76 HM76@
2 USB/B (Right Side)
UHCI1 N13P-GS & GL GSGL@
4319IDBOL05SMT MB A7912 Q5WV1 HM77 QC 13PGS2G 3 3
EHCI1 N13M-GS GM@
4
4319IDBOL06SMT MB A7912 Q5WV1 HM77 DC UMA 2 UHCI2 support AC function AC@
5
no AC function NOAC@
6
4319IDBOL07SMT MB A7912 Q5WV1 HM77 DC UMA 3 UHCI3
7
4319IDBOL08SMT MB A7912 Q5WV1 HM77 DC 13PGL1G 2 8 Mini Card 1(WLAN)
UHCI4
9
4319IDBOL09SMT MB A7912 Q5WV1 HM77 DC 13PGL1G 3
10 Camera
EHCI2 UHCI5
4319IDBOL10SMT MB A7912 Q5WV1 HM77 DC 13PGL2G 2 11 BlueTooth
4
12 4
4319IDBOL11SMT MB A7912 Q5WV1 HM77 DC 13PGL2G 3 UHCI6

13
4319IDBOL12SMT MB A7912 Q5WV1 HM77 DC 13MGS1G 2
4319IDBOL13SMT MB A7912 Q5WV1 HM77 DC 13MGS1G 3

SCHEMATIC,MB A7912
4319IDBOL14SMT MB A7912 Q5WV1 HM77 DC 13PGS2G 3 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Custom C
4019ID
A B C D E
5 4 3 2 1
D +1.05VS_VTT D
PEG_ICOMPI and PEG_RCOMPO signals should be
shorted and routed,
1
R517
max length = 500 mils,trace width=4mils
24.9_0402_1% PEG_ICOMPO signals should be routed with - max
JCPU1A
length = 500 mils,trace width=12mils
2
PEG_ICOMPI J22 PEG_COMP spacing =15mils
PEG_ICOMPO J21
<15> DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22
<15> DMI_CRX_PTX_N1 B25 DMI_RX#[1]
<15> DMI_CRX_PTX_N2 A25 DMI_RX#[2]
<15> DMI_CRX_PTX_N3 B24 K33 PEG_GTX_C_HRX_N15 C46 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_N15
DMI_RX#[3] PEG_RX#[0] PEG_GTX_C_HRX_N14 C49 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_N14
PEG_RX#[1] M35 1 2
<15> DMI_CRX_PTX_P0 B28 L34 PEG_GTX_C_HRX_N13 C51 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_N13
DMI_RX[0] PEG_RX#[2] PEG_GTX_C_HRX_N12 C53 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_N12
<15> DMI_CRX_PTX_P1 B26 DMI_RX[1] PEG_RX#[3] J35 1 2
<15> DMI_CRX_PTX_P2 A24 J32 PEG_GTX_C_HRX_N11 C60 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_N11
DMI
DMI_RX[2] PEG_RX#[4] PEG_GTX_HRX_N[0..15] <22>
<15> DMI_CRX_PTX_P3 B23 H34 PEG_GTX_C_HRX_N10 C71 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_N10
DMI_RX[3] PEG_RX#[5] PEG_GTX_HRX_P[0..15] <22>
H31 PEG_GTX_C_HRX_N9 C75 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_N9
PEG_RX#[6] PEG_GTX_C_HRX_N8 C82 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_N8
<15> DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33 1 2 PEG_HTX_C_GRX_N[0..15] <22>
E22 G30 PEG_GTX_C_HRX_N7 C92 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N7
<15> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] PEG_HTX_C_GRX_P[0..15] <22>
F21 F35 PEG_GTX_C_HRX_N6 C93 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N6
<15> DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
D21 E34 PEG_GTX_C_HRX_N5 C102 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N5
<15> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10]
E32 PEG_GTX_C_HRX_N4 C111 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N4
PEG_RX#[11] PEG_GTX_C_HRX_N3 C113 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N3
<15> DMI_CTX_PRX_P0 G22 DMI_TX[0] PEG_RX#[12] D33 1 2
D22 D31 PEG_GTX_C_HRX_N2 C125 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N2
<15> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
F20 B33 PEG_GTX_C_HRX_N1 C129 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N1
PCI EXPRESS* - GRAPHICS

C21 C32 PEG_GTX_C_HRX_N0 C144 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_N0
J33 PEG_GTX_C_HRX_P15 C47 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_P15
PEG_RX[0] PEG_GTX_C_HRX_P14 C50 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_P14
PEG_RX[1] L35 1 2
C PEG_GTX_C_HRX_P13 C52 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_P13 C
PEG_RX[2] K34 1 2
A21 H35 PEG_GTX_C_HRX_P12 C56 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_P12
<15> FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3]
H19 H32 PEG_GTX_C_HRX_P11 C66 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_P11
E19 G34 PEG_GTX_C_HRX_P10 C68 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_P10
F18 G31 PEG_GTX_C_HRX_P9 C81 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_P9
Intel(R) FDI
B21 F33 PEG_GTX_C_HRX_P8 C86 1 2 GSGL@ 0.22U_0402_10V6K PEG_GTX_HRX_P8
C20 F30 PEG_GTX_C_HRX_P7 C89 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P7
D18 E35 PEG_GTX_C_HRX_P6 C100 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P6
E17 E33 PEG_GTX_C_HRX_P5 C105 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P5
F32 PEG_GTX_C_HRX_P4 C106 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P4
PEG_RX[11] PEG_GTX_C_HRX_P3 C117 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P3
PEG_RX[12] D34 1 2
A22 E31 PEG_GTX_C_HRX_P2 C119 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P2
<15> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
G19 C33 PEG_GTX_C_HRX_P1 C135 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P1
E20 B32 PEG_GTX_C_HRX_P0 C138 1 2 DIS@ 0.22U_0402_10V6K PEG_GTX_HRX_P0
<15> FDI_CTX_PRX_P3 G18 FDI0_TX[3]
B20 M29 PEG_HTX_GRX_N15 C516 1 2 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N15
<15> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32 PEG_HTX_GRX_N14 C520 1 2 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N14
D19 M31 PEG_HTX_GRX_N13 C529 1 2 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N13
F17 L32 PEG_HTX_GRX_N12 C534 1 2 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N12
L29 PEG_HTX_GRX_N11 C538 1 2 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N11
+1.05VS_VTT PEG_TX#[4]
eDP_COMPIO and ICOMPO signals should <15> FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 PEG_HTX_GRX_N10 C540 1 2 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_N10
J17 K28 PEG_HTX_GRX_N9 C542 1 2 GSGL@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N9
be shorted near balls, <15> FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6]
J30 PEG_HTX_GRX_N8 C544 1 2 GSGL@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N8
PEG_TX#[7]
Trace Width for EDP_COMPIO=4mils, <15> FDI_INT H20 FDI_INT PEG_TX#[8] J28 PEG_HTX_GRX_N7 C546 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N7
H29 PEG_HTX_GRX_N6 C548 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N6
EDP_ICOMPO=12mils, PEG_TX#[9]
1
<15> FDI_LSYNC0 J19 G27 PEG_HTX_GRX_N5 C550 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N5

FDI0_LSYNC PEG_TX#[10]
and both length less than 500 mils... R145 <15> FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29 PEG_HTX_GRX_N4 C552 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N4
F27 PEG_HTX_GRX_N3 C554 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N3
should not be left floating 24.9_0402_1% PEG_TX#[12]
D28 PEG_HTX_GRX_N2 C556 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N2
PEG_TX#[13]
,even if disable eDP function... F26 PEG_HTX_GRX_N1 C558 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N1
2
PEG_TX#[14] PEG_HTX_GRX_N0 C560 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N0

PEG_TX#[15] E25 1 2
EDP_COMP A18
B eDP_COMPIO PEG_HTX_GRX_P15 C515 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P15 B
A17 eDP_ICOMPO PEG_TX[0] M28 1 2
EDP_HPD# B16 M33 PEG_HTX_GRX_P14 C528 1 2 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P14
eDP_HPD# PEG_TX[1] PEG_HTX_GRX_P13 C533 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P13
PEG_TX[2] M30 1 2
L31 PEG_HTX_GRX_P12 C536 1 2 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P12
PEG_TX[3] PEG_HTX_GRX_P11 C539 GSGL@ 0.22U_0402_10V6KPEG_HTX_C_GRX_P11
<31> EDP_AUXP C15 eDP_AUX PEG_TX[4] L28 1 2
Add eDP circuit <31> EDP_AUXN D15 eDP_AUX# PEG_TX[5] K30
K27
PEG_HTX_GRX_P10
PEG_HTX_GRX_P9
C541
C543
1
1
2
2
GSGL@
GSGL@
0.22U_0402_10V6KPEG_HTX_C_GRX_P10
0.22U_0402_10V6K PEG_HTX_C_GRX_P9
eDP
PEG_TX[6] PEG_HTX_GRX_P8 C545 GSGL@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P8

PEG_TX[7] J29 1 2
C17 J27 PEG_HTX_GRX_P7 C547 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P7
<31> EDP_TXP0 eDP_TX[0] PEG_TX[8]
F16 H28 PEG_HTX_GRX_P6 C549 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P6
<31> EDP_TXP1 eDP_TX[1] PEG_TX[9]
C16 G28 PEG_HTX_GRX_P5 C551 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P5
eDP_TX[2] PEG_TX[10] PEG_HTX_GRX_P4 C553 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P4
G15 eDP_TX[3] PEG_TX[11] E28 1 2
+1.05VS_VTT F28 PEG_HTX_GRX_P3 C555 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P3
PEG_TX[12] PEG_HTX_GRX_P2 C557 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P2
<31> EDP_TXN0 C18 eDP_TX#[0] PEG_TX[13] D27 1 2
E16 E26 PEG_HTX_GRX_P1 C559 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P1
<31> EDP_TXN1 eDP_TX#[1] PEG_TX[14]
1
D16 D25 PEG_HTX_GRX_P0 C561 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P0

R809 eDP_TX#[2] PEG_TX[15]
F15 eDP_TX#[3]
EDP@ 1K_0402_5%
TYCO_2013620-2_IVY BRIDGE
2
CONN@
<31> EDP_HPD# Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)
A A

SCHEMATIC,MB A7912
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019ID C
5 4 3 2 1
5 4 3 2 1
D D
SNB_IVB# had changed the name to JCPU1B

PROC_SELCT#,function for future platform,
connect to the DF_TVS strap on the PCH
A28 CLK_CPU_DMI
BCLK CLK_CPU_DMI <14>
C26 A27 CLK_CPU_DMI#
MISC
CLOCKS
<17> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <14>
AN34 SKTOCC# For LVDS

A16 CLK_CPU_DPLL
DPLL_REF_CLK CLK_CPU_DPLL <14>
DPLL_REF_CLK# A15 CLK_CPU_DPLL# For
CLK_CPU_DPLL# <14> eDP CLK_CPU_DPLL R516 2 LVDS@ 1 1K_0402_5%
CLK_CPU_DPLL# R518 2 LVDS@ 1 1K_0402_5% +1.05VS_VTT
T6 PAD H_CATERR# AL33 CATERR# If use External Graphic or
@
use integrated without eDP
DPLL_REF_SSCLK PD 1K_5% to GND
THERMAL
Processor Pullups <18,40> H_PECI
H_PECI AN33 PECI SM_DRAMRST# R8 SM_DRAMRST#
SM_DRAMRST# <6> DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT
R91 2 1 62_0402_5% R92
DDR3
MISC
+1.05VS_VTT
56_0402_5%
<40,46> H_PROCHOT# H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 R231 2 1 140_0402_1%
C PROCHOT# SM_RCOMP[0] SM_RCOMP1 R566 C
SM_RCOMP[1] A5 2 1 25.5_0402_1%
A4 SM_RCOMP2 R571 2 1 200_0402_1%
SM_RCOMP[2]
<18> H_THRMTRIP#
H_THRMTRIP# AN32 THERMTRIP# DDR3 Compensation Signals
PRDY# AP29
PREQ# AP27
AR26 TCK @ +3VS

TCK PAD T66
AR27 TMS @
PWR MANAGEMENT
TMS PAD T67
JTAG & BPM

H_PM_SYNC AM34 AP30 TRST# PAD @
<15> H_PM_SYNC PM_SYNC TRST# T68
1
R84 2 1 10K_0402_5% AR28 TDI PAD @
TDI T69
AP26 TDO PAD @ R40
TDO T70
<18> H_CPUPWRGD H_CPUPWRGD AP33 1K_0402_5%
UNCOREPWRGOOD
UNCOREPWRGOOD:非CORE外的電OK
2
AL35 XDP_DBRESET# XDP_DBRESET# <15>
PM_DRAM_PWRGD_R DBR#
V8 SM_DRAMPWROK
BPM#[0] AT28
SM_DRAMPWROK:DRAM power ok BPM#[1] AR29
BPM#[2] AR30
BUF_CPU_RST# AR33 AT30
RESET# BPM#[3]
BPM#[4] AP32
BPM#[5] AR31
BPM#[6] AT31
BPM#[7] AR32
B B
CONN@
Buffered reset to CPU

+3VALW
+3VS +1.5VS
1
C307
1
+1.05VS_VTT 0.1U_0402_16V4Z
1
C162 R205
0.1U_0402_16V4Z 2
1
U11 200_0402_1%
2 R90 74AHC1G09GW_TSSOP5
2
5
75_0402_1%
1
P
<15> SYS_PWROK B
5
U7 R87 4 PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_R

2
43_0402_1% O R204 130_0402_5%

1 2
P
NC <15> PM_DRAM_PWRGD A
1
4 BUFO_CPU_RST# 1 2 BUF_CPU_RST#
PLT_RST# Y R203
<17> PLT_RST# 2
3
A
G
SN74LVC1G07DCKR_SC70-5 2 39_0402_1%
@
3
R88 C2090 @
2
0_0402_5% 0.1U_0402_16V4Z
1
2
RESET#:都ok後請CPU做reset
A A
R04 modify

SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1
JCPU1C JCPU1D
<11> DDR_A_D[0..63] SA_CLK[0] AB6 SA_CLK_DDR0 <11> <12> DDR_B_D[0..63] SB_CLK[0] AE2 SB_CLK_DDR0 <12>
SA_CLK#[0] AA6 SA_CLK_DDR#0 <11> SB_CLK#[0] AD2 SB_CLK_DDR#0 <12>
DDR_A_D0 C5 V9 DDR_B_D0 C9 R9
SA_DQ[0] SA_CKE[0] DDRA_CKE0_DIMMA <11> SB_DQ[0] SB_CKE[0] DDRB_CKE0_DIMMB <12>
DDR_A_D1 D5 DDR_B_D1 A7
DDR_A_D2 SA_DQ[1] DDR_B_D2 SB_DQ[1]
D3 SA_DQ[2] D10 SB_DQ[2]
DDR_A_D3 D2 DDR_B_D3 C8
D6 SA_DQ[4] SA_CLK[1] AA5 SA_CLK_DDR1 <11> A9 SB_DQ[4] SB_CLK[1] AE1 SB_CLK_DDR1 <12>
D DDR_A_D5 DDR_B_D5 D
C6 SA_DQ[5] SA_CLK#[1] AB5 SA_CLK_DDR#1 <11> A8 SB_DQ[5] SB_CLK#[1] AD1 SB_CLK_DDR#1 <12>
DDR_A_D6 C2 V10 DDR_B_D6 D9 R10
SA_DQ[6] SA_CKE[1] DDRA_CKE1_DIMMA <11> SB_DQ[6] SB_CKE[1] DDRB_CKE1_DIMMB <12>
DDR_A_D7 C3 DDR_B_D7 D8
F10 SA_DQ[8] G4 SB_DQ[8]
DDR_A_D9 F8 DDR_B_D9 F4
G10 SA_DQ[10] RSVD_TP[1] AB4 F1 SB_DQ[10] RSVD_TP[11] AB2
DDR_A_D11 G9 AA4 DDR_B_D11 G1 AA2
DDR_A_D12 SA_DQ[11] RSVD_TP[2] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
F9 SA_DQ[12] RSVD_TP[3] W9 G5 SB_DQ[12] RSVD_TP[13] T9
DDR_A_D13 F7 DDR_B_D13 F5
G8 SA_DQ[14] F2 SB_DQ[14]
DDR_A_D15 G7 DDR_B_D15 G2
K4 SA_DQ[16] RSVD_TP[4] AB3 J7 SB_DQ[16] RSVD_TP[14] AA1
DDR_A_D17 K5 AA3 DDR_B_D17 J8 AB1
K1 SA_DQ[18] RSVD_TP[6] W10 K10 SB_DQ[18] RSVD_TP[16] T10
DDR_A_D19 J1 DDR_B_D19 K9
J5 SA_DQ[20] J9 SB_DQ[20]
DDR_A_D21 J4 DDR_B_D21 J10
J2 SA_DQ[22] SA_CS#[0] AK3 DDRA_CS0_DIMMA# <11> K8 SB_DQ[22] SB_CS#[0] AD3 DDRB_CS0_DIMMB# <12>
DDR_A_D23 K2 AL3 DDR_B_D23 K7 AE3
SA_DQ[23] SA_CS#[1] DDRA_CS1_DIMMA# <11> SB_DQ[23] SB_CS#[1] DDRB_CS1_DIMMB# <12>
DDR_A_D24 M8 AG1 DDR_B_D24 M5 AD6
N10 SA_DQ[25] RSVD_TP[8] AH1 N4 SB_DQ[25] RSVD_TP[18] AE6
DDR_A_D26 N8 DDR_B_D26 N2
N7 SA_DQ[27] N1 SB_DQ[27]
DDR_A_D28 M10 DDR_B_D28 M4
M9 SA_DQ[29] SA_ODT[0] AH3 SA_ODT0 <11> N5 SB_DQ[29] SB_ODT[0] AE4 SB_ODT0 <12>
DDR_A_D30 N9 AG3 DDR_B_D30 M2 AD4
DDR SYSTEM MEMORY B

SA_DQ[30] SA_ODT[1] SA_ODT1 <11> SB_DQ[30] SB_ODT[1] SB_ODT1 <12>
DDR SYSTEM MEMORY A

DDR_A_D31 M7 AG2 DDR_B_D31 M1 AD5
AG6 SA_DQ[32] RSVD_TP[10] AH2 AM5 SB_DQ[32] RSVD_TP[20] AE5
DDR_A_D33 AG5 DDR_B_D33 AM6
AK6 SA_DQ[34] AR3 SB_DQ[34]
DDR_A_D35 AK5 DDR_B_D35 AP3
AH5 SA_DQ[36] DDR_A_DQS#[0..7] <11> AN3 SB_DQ[36] DDR_B_DQS#[0..7] <12>
C DDR_A_D37 DDR_A_DQS#0 DDR_B_D37 DDR_B_DQS#0 C
AH6 SA_DQ[37] SA_DQS#[0] C4 AN2 SB_DQ[37] SB_DQS#[0] D7
DDR_A_D38 AJ5 G6 DDR_A_DQS#1 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ6 SA_DQ[39] SA_DQS#[2] J3 AP2 SB_DQ[39] SB_DQS#[2] K6
DDR_A_D40 AJ8 M6 DDR_A_DQS#3 DDR_B_D40 AP5 N3 DDR_B_DQS#3
AK8 SA_DQ[41] SA_DQS#[4] AL6 AN9 SB_DQ[41] SB_DQS#[4] AN5
DDR_A_D42 AJ9 AM8 DDR_A_DQS#5 DDR_B_D42 AT5 AP9 DDR_B_DQS#5
AK9 SA_DQ[43] SA_DQS#[6] AR12 AT6 SB_DQ[43] SB_DQS#[6] AK12
DDR_A_D44 AH8 AM15 DDR_A_DQS#7 DDR_B_D44 AP6 AP15 DDR_B_DQS#7
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH9 SA_DQ[45] AN8 SB_DQ[45]
DDR_A_D46 AL9 DDR_B_D46 AR6
AL8 SA_DQ[47] AR5 SB_DQ[47]
DDR_A_D48 AP11 DDR_B_D48 AR9
SA_DQ[48] DDR_A_DQS[0..7] <11> SB_DQ[48] DDR_B_DQS[0..7] <12>
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D49 AJ11 C7 DDR_B_DQS0
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AL12 SA_DQ[50] SA_DQS[1] F6 AT8 SB_DQ[50] SB_DQS[1] G3
DDR_A_D51 AM12 K3 DDR_A_DQS2 DDR_B_D51 AT9 J6 DDR_B_DQS2
AM11 SA_DQ[52] SA_DQS[3] N6 AH11 SB_DQ[52] SB_DQS[3] M3
DDR_A_D53 AL11 AL5 DDR_A_DQS4 DDR_B_D53 AR8 AN6 DDR_B_DQS4
AP12 SA_DQ[54] SA_DQS[5] AM9 AJ12 SB_DQ[54] SB_DQS[5] AP8
DDR_A_D55 AN12 AR11 DDR_A_DQS6 DDR_B_D55 AH12 AK11 DDR_B_DQS6
AJ14 SA_DQ[56] SA_DQS[7] AM14 AT11 SB_DQ[56] SB_DQS[7] AP14
DDR_A_D57 AH14 DDR_B_D57 AN14
AL15 SA_DQ[58] AR14 SB_DQ[58]
DDR_A_D59 AK15 DDR_B_D59 AT14
AL14 SA_DQ[60] DDR_A_MA[0..15] <11> AT12 SB_DQ[60] DDR_B_MA[0..15] <12>
DDR_A_D61 AK14 AD10 DDR_A_MA0 DDR_B_D61 AN15 AA8 DDR_B_MA0
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AJ15 SA_DQ[62] SA_MA[1] W1 AR15 SB_DQ[62] SB_MA[1] T7
DDR_A_D63 AH15 W2 DDR_A_MA2 DDR_B_D63 AT15 R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_DQ[63] SB_MA[2] DDR_B_MA3
SA_MA[3] W7 SB_MA[3] T6
V3 DDR_A_MA4 T2 DDR_B_MA4
SA_MA[4] DDR_A_MA5 SB_MA[4] DDR_B_MA5
SA_MA[5] V2 SB_MA[5] T4
W3 DDR_A_MA6 T3 DDR_B_MA6
<11> DDR_A_BS0 AE10 SA_BS[0] SA_MA[7] W6 <12> DDR_B_BS0 AA9 SB_BS[0] SB_MA[7] R2
B DDR_A_MA8 DDR_B_MA8 B
<11> DDR_A_BS1 AF10 SA_BS[1] SA_MA[8] V1 <12> DDR_B_BS1 AA7 SB_BS[1] SB_MA[8] T5
V6 W5 DDR_A_MA9 R6 R3 DDR_B_MA9
<11> DDR_A_BS2 SA_BS[2] SA_MA[9] <12> DDR_B_BS2 SB_BS[2] SB_MA[9]
AD8 DDR_A_MA10 AB7 DDR_B_MA10
SA_MA[11] V4 SB_MA[11] R1
W4 DDR_A_MA12 T1 DDR_B_MA12
<11> DDR_A_CAS# AE8 SA_CAS# SA_MA[13] AF8 <12> DDR_B_CAS# AA10 SB_CAS# SB_MA[13] AB10
AD9 V5 DDR_A_MA14 AB8 R5 DDR_B_MA14
<11> DDR_A_RAS# SA_RAS# SA_MA[14] <12> DDR_B_RAS# SB_RAS# SB_MA[14]
AF9 V7 DDR_A_MA15 AB9 R4 DDR_B_MA15
<11> DDR_A_WE# SA_WE# SA_MA[15] <12> DDR_B_WE# SB_WE# SB_MA[15]
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

CONN@ CONN@
Follow CRB1.0 +1.5V

1
@R184
@ R184
0_0402_5% R217
CPU通知DIMM做reset 1 2 1K_0402_5%
R155
2
1K_0402_5%
S
<5> SM_DRAMRST# SM_DRAMRST# 3 1 DIMM_DRAMRST#_R 1 2 DIMM_DRAMRST# <11,12>

2 Q12
2
R02 modify for ESD S TR SSM3K7002F 1N SC59-3

C2065 R186 S0
G
2
0.1U_0402_16V4Z 4.99K_0402_1% RST_GATE hgih ,MOS ON

1
A SM_DRAMRST# HIGH,DIMM_DRAMRST# HIGH A
Dimm not reset
1
S3
<11,12,14> RST_GATE RST_GATE Low ,MOS OFF
SM_DRAMRST# lo,DIMM_DRAMRST# HIGH
Dimm not reset
1
C293
S4,5
RST_GATE Low ,MOS OFF
0.047U_0402_16V7K SM_DRAMRST# lo,DIMM_DRAMRST# low
2
Dimm reset THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor
CFG2
1
Sandy Ivy R112
D
AH26 1K_0402_5% D
2
GND VSS_DIE_SENSE
JCPU1E
AH27 change to VCC_DIE_SENSE PEG Static Lane Reversal - CFG2 is for the 16x
1: Normal Operation; Lane # definition matches

VCC_DIE_SENSE AH27 @ PAD T7 CFG2 socket pin map definition
T8 PAD CFG0 AK28 AH26 @ PAD T74
@ CFG[0] VSS_DIE_SENSE
AK29 CFG[1]
CFG2 AL26 0:Lane Reversed
CFG4
AL27
AK26
CFG[2]
CFG[3]
CFG[4] RSVD28 L7
*
CFG5 AL29 AG7 CFG4
CFG6 CFG[5] RSVD29
AL30 CFG[6] RSVD30 AE7
1
CFG7 AM31 AK2 EDP@
CFG[7] RSVD31
AM32 CFG[8]
AM30 W8 R109
CFG
CFG[9] RSVD32 1K_0402_5%
AM28 CFG[10]
AM26
2
CFG[11]
AN28 CFG[12] RSVD33 AT26
+CPU_CORE +VGFX_CORE
AN31 CFG[13] RSVD34 AM33
AN26 CFG[14] RSVD35 AJ27
AM27 CFG[15]
AK31 CFG[16]
2
AN29 CFG[17]
R810 R811 Display Port Presence Strap
C @ @ C
49.9_0402_1% 49.9_0402_1% T8
RSVD37
J16 1 : Disabled; No Physical Display Port
*
1
RSVD38
VAXG_VAL_SENSE AJ31 VAXG_VAL_SENSE RSVD39 H16 CFG4 attached to Embedded Display Port
VSSAXG_VAL_SENSE AH31 G16
VCC_VAL_SENSE VSSAXG_VAL_SENSE RSVD40
AJ33 VCC_VAL_SENSE
VSS_VAL_SENSE AH33 VSS_VAL_SENSE 0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
2
AJ26 RSVD5 RSVD_NCTF1 AR35

R812 R813 AT34
RESERVED
@ @ RSVD_NCTF2
RSVD_NCTF3 AT33
49.9_0402_1% 49.9_0402_1% AP35 CFG6
RSVD_NCTF4
AR34
1
RSVD_NCTF5 CFG5
1
F25 GM@
RSVD8 R107 R108
F24 RSVD9
F23 1K_0402_5% @ 1K_0402_5%
RSVD10
D24 RSVD11 RSVD_NCTF6 B34
G25 A33
2
RSVD12 RSVD_NCTF7
G24 RSVD13 RSVD_NCTF8 A34
E23 RSVD14 RSVD_NCTF9 B35
D23 RSVD15 RSVD_NCTF10 C35
C30 RSVD16
A31 RSVD17
B30 RSVD18 PCIE Port Bifurcation Straps
B29 RSVD19
D30 RSVD20 RSVD51 AJ32
B31 AK32 11: (Default) x16 - Device 1 functions 1 and 2 disabled
B
A30
C29
RSVD21
RSVD22
RSVD23
RSVD52
CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2 B
AN35
disabled
BCLK_ITP
J20 RSVD24 BCLK_ITP# AM35 01: Reserved - (Device 1 function 1 disabled ; function
B18 RSVD25 RSVD54 and RSVD55 had changed to 2 enabled)
BCLK_ITP and BCLK_ITP#
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
J15 RSVD27 RSVD_NCTF11 AT2
RSVD_NCTF12 AT1
RSVD_NCTF13 AR1
B1 CFG7
KEY
1
R102
@ 1K_0402_5%
2
CONN@
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB

CFG7 de assertion
A A
0: PEG Wait for BIOS for training
Security Classification Compal Secret Data

SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1
SV type CPU JCPU1F POWER

+CPU_CORE
QC 53A
DC 53A +1.05VS_VTT
AG35
8.5A
VCC1
AG34 VCC2 VCCIO1 AH13
AG33 VCC3 VCCIO2 AH10
AG32 VCC4 VCCIO3 AG10
AG31 VCC5 VCCIO4 AC10
D D
AG30 VCC6 VCCIO5 Y10
AG29 VCC7 VCCIO6 U10
AG28 VCC8 VCCIO7 P10
AG27 VCC9 VCCIO8 L10
AG26 VCC10 VCCIO9 J14
AF35 VCC11 VCCIO10 J13
AF32 VCC14 VCCIO13 H14
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13
AF27 G12
PEG AND DDR

VCC19 VCCIO18
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20 F13
AD32 VCC24 VCCIO23 E14
AD30 VCC26
AD28 VCC28 VCCIO26 D14
AC35 VCC31 VCCIO29 D11
AC34 VCC32 VCCIO30 C14
AC30 VCC36 VCCIO34 B14
AC29 VCC37 VCCIO35 B12
C C
AC28 VCC38 VCCIO36 A14
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23
AA32 VCC44
AA31 VCC45
AA30 VCC46
AA29 VCC47
AA28 VCC48 +1.05VS_VTT
AA27 VCC49 +1.05VS_VTT
AA26 VCC50
Y35
CORE SUPPLY
VCC51
Y34 VCC52
Y33 VCC53
Y32 VCC54
1
Y31 VCC55
Y30 R450 R447
VCC56 130_0402_1%
Y29 VCC57 75_0402_5%
Y28 VCC58
Y27
2
VCC59 R448
Y26 VCC60
V35 43_0402_1%
VCC61 H_CPU_SVIDALRT#
V34 AJ29 1 2
SVID
VCC62 VIDALERT# VR_SVID_ALRT# <52>

V33 AJ30 H_CPU_SVIDCLK R446 1 2 0_0402_5%
VCC63 VIDSCLK VR_SVID_CLK <52>
V32 AJ28 H_CPU_SVIDDAT R449 1 2 0_0402_5%
VCC64 VIDSOUT VR_SVID_DAT <52>
V31 VCC65
V30 VCC66
V29 VCC67
V28 VCC68
V27 VCC69
B B
V26 VCC70
U35 VCC71
U34 VCC72
U33 VCC73 Place the PU
U32
U31
VCC74 resistors close to CPU
VCC75
U30 VCC76
U29 VCC77
U28 VCC78
U27 VCC79
U26 +CPU_CORE
VCC80
R35 VCC81
R34 VCC82
1
R33 VCC83
R32 R445
VCC84
R31 VCC85 100_0402_1%
R30 VCC86
R29
2
VCC87
R28
SENSE LINES
VCC88
R27 VCC89 VCC_SENSE AJ35 VCCSENSE_R R444 1 2 0_0402_5%
VCCSENSE <52>
R26 VCC90 VSS_SENSE AJ34 VSSSENSE_R R443 1 2 0_0402_5%
VSSSENSE <52>
P35 VCC91
P34 VCC92 1 2 +1.05VS_VTT
1
P33 R910 10_0402_5%
VCC93 R442
P32 VCC94 VCCIO_SENSE B10 VCCIO_SENSE <50>
P31 A10 VSSIO_SENSE 100_0402_1%
VCC95 VSS_SENSE_VCCIO VSSIO_SENSE <50>
P30 VCC96 VSSIO_SENSE
1
P29 change to
2
VCC97
P28
P27
VCC98 VSS_SENSE_VCCIO R163
VCC99 10_0402_5%
P26 VCC100
Should change to connect form
2
A A
power cirucit & layout differential
with VCCIO_SENSE.
TYCO_2013620-2_IVY BRIDGE CONN@

SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1
+VGFX_CORE
1
POWER
D D
R903
+VGFX_CORE QC 46A JCPU1G 10_0402_5%
DC 33A
2
AT24 AK35
SENSE
LINES
VAXG1 VAXG_SENSE VCC_AXG_SENSE <52>
AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE <52> +1.5VS
AT21 VAXG3
1
AT20 VAXG4
AT18 R904
VAXG5
1
AT17 VAXG6
AR24 10_0402_5% R582
VAXG7 1K_0402_1%
AR23 +V_SM_VREF should
2
VAXG8
AR21 VAXG9
AR20 have 20 mil trace width
2
VAXG10 +V_SM_VREF
AR18 VAXG11 SM_VREF AL1
AR17 VAXG12
1
AP24
VREF
VAXG13 1
AP23 C688 R575
VAXG14 0.1U_0402_16V4Z 1K_0402_1%
AP21 VAXG15
AP20 B4 SA_DIMM_VREFDQ
VAXG16 SA_DIMM_VREFDQ SA_DIMM_VREFDQ <11> 2
AP18 D1 SB_DIMM_VREFDQ
SB_DIMM_VREFDQ <12>
2
VAXG17 SB_DIMM_VREFDQ
AP17 VAXG18
AN24 VAXG19
AN23 VAXG20
AN21 VAXG21
AN20
AN18
VAXG22 INTEL Recommend
DDR3 -1.5V RAILS

VAXG23 +1.5VS
AN17 5A
AM24
VAXG24
AF7 1*330uF,6*10uF
GRAPHICS
VAXG25 VDDQ1
AM23 VAXG26 VDDQ2 AF4
C
AM21 VAXG27 VDDQ3 AF1 from CR PDDG 0.8 C
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
AM20 VAXG28 VDDQ4 AC7 1 1 1 1 1 1 1
330U_D2_2V_Y
AM18 VAXG29 VDDQ5 AC4
+
C363
C364
C362
C341
C365
C361
C355
AM17 VAXG30 VDDQ6 AC1
AL24 VAXG31 VDDQ7 Y7
2 2 2 2 2 2
2
AL20 VAXG34 VDDQ10 U7
AK24 VAXG37 VDDQ13 P7
AK20 VAXG40
AK18
AK17
VAXG41
VAXG42
INTEL Recommend
AJ24
AJ23
VAXG43
VAXG44 1*330uF,3*10uF
AJ21 VAXG45
AJ20
AJ18
VAXG46 6A +VCCSA
from CR PDDG 0.8
VAXG47 +VCCSA R137 1 @
AJ17 VAXG48 VCCSA1 M27 2 0_0402_5% +VCCSA_SENSE
SA RAIL
AH24 VAXG49 VCCSA2 M26
AH23 VAXG50 VCCSA3 L26 1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
AH21 VAXG51 VCCSA4 J26 1 1 1 1 1 1
AH20 J25 + C221 VCCSA
VAXG52 VCCSA5
C214
C605
C219
C213
C828
C829
AH18 J24 @
VAXG53 VCCSA6
AH17 H26 330U_D2_2V_Y VID0 VID1 Vout Sandy Ivy
VAXG54 VCCSA7 2 2 2 2 2 2 2
VCCSA8 H25
0 0 0.9V V V
INTEL Recommend
0 1 0.8V V V
B
1*330uF,1*10uF and 2*1uF(0402) 1 0 0.725V X V
B
1.8V RAIL
+1.8VS from CR PDDG 0.8 1.2A VCCSA_SENSE H23 +VCCSA_SENSE <51>

1 1 0.675V X V
1 2 +VCCPLL B6
R528 0_0805_5% VCCPLL1 H_VCCSA_VID0
A6 C22
MISC
1 VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <51>

330U_D2_2V_Y
C664
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
C654
1U_0402_6.3V6K
C653
1 1 1 1 1 A2 C24 H_VCCSA_VID1
+ VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 <51>
C831
C830
C655
1
2 2 2 2 2 2 VCCIO_SEL R138
VCCIO_SEL A19
0_0402_5%
@
2
CONN@
+3VALW
1
VCCIO_SEL For 2012 CPU support R909
10K_0402_5%
1/NC : (Default) +1.05VS_VTT

*
2
A19
0: +1.0VS_VTT VCCIO_SEL
1
RSVD26 had changed the name to VCCIO_SEL
R913 @
A Need PH +3VALW 10K at +1.05VS_VTT source A
10K_0402_5%
for 2012 processor +1.05V and +1.0V select
2
SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1
JCPU1H JCPU1I
D D
AT35 VSS1 VSS81 AJ22
AT32 VSS2 VSS82 AJ19
AT29 VSS3 VSS83 AJ16 T35 VSS161 VSS234 F22
AT27 VSS4 VSS84 AJ13 T34 VSS162 VSS235 F19
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13
AT4 VSS12 VSS92 AH34 T26 VSS170 VSS243 E10
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9
AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8
AR10 VSS19 VSS100 AH19 N35 VSS177 VSS250 E3
AR2 VSS22 VSS103 AH4 N32 VSS180 VSS253 D35
AP34 VSS23 VSS104 AG9 N31 VSS181 VSS254 D32
AP25 VSS26 VSS107 AF6 N28 VSS184 VSS257 D20
AP22 VSS27 VSS108 AF5 N27 VSS185 VSS258 D17
AP19 VSS28 VSS109 AF3 N26 VSS186 VSS259 C34
AP16 VSS29 VSS110 AF2 M34 VSS187 VSS260 C31
AP13 VSS30 VSS111 AE35 L33 VSS188 VSS261 C28
C C
AN30 VSS35 VSS116 AE30 L6 VSS193 VSS266 C1
AN27 VSS36 VSS117 AE29 L5 VSS194 VSS267 B22
AN25
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE28
AE27
AE26
L4
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B19
B17
B15
AN16 VSS40 VSS121 AE9 L1 VSS198 VSS271 B13
AN13 VSS41 VSS122 AD7 K35 VSS199 VSS272 B11
AN10 VSS42 VSS123 AC9 K32 VSS200 VSS273 B9
AM29 VSS45 VSS126 AC5 J34 VSS203 VSS276 B5
AM25 VSS46 VSS127 AC3 J31 VSS204 VSS277 B3
AM22 VSS47 VSS128 AC2 H33 VSS205 VSS278 B2
AM19 VSS48 VSS129 AB35 H30 VSS206 VSS279 A35
AM2 VSS55 VSS136 AB28 H10 VSS213
AM1 VSS56 VSS137 AB27 H9 VSS214
AL34 VSS57 VSS138 AB26 H8 VSS215
AL31 VSS58 VSS139 Y9 H7 VSS216
AL13 VSS64 VSS145 W35 H1 VSS222
B B
AL10 VSS65 VSS146 W34 G35 VSS223
AK33 VSS69 VSS150 W30 G23 VSS227
AK22 VSS73 VSS154 W26 F34 VSS231
AK19 VSS74 VSS155 U9 F31 VSS232
AK16 VSS75 VSS156 U8 F29 VSS233
AK13 VSS76 VSS157 U6
AK10 VSS77 VSS158 U5
AK7 VSS78 VSS159 U3
AK4 VSS79 VSS160 U2
AJ25 VSS80
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

CONN@ CONN@
A A

SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1
+1.5V
1
R320
DDR_A_DQS#[0..7] <6>
1K_0402_5%
@ R133 +1.5V +1.5V
M3 support 0_0402_5% JDIMM1
DDR_A_DQS[0..7] <6>
2
<9> SA_DIMM_VREFDQ 1 2 +V_DDR_REFA 1 2
VREF_DQ VSS1 DDR_A_D[0..63] <6>
3 4 DDR_A_D4
VSS2 DQ4
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5 DDR_A_MA[0..15] <6>
C408
C411
DDR_A_D1 7 8
DQ1 VSS3
D
3 1 R319 1 1 9 10 DDR_A_DQS#0
Q46 1K_0402_5% DDR_A0_DM0 VSS4 DQS#0 DDR_A_DQS0
11 DM0 DQS0 12
S TR SSM3K7002F 1N SC59-3 @ 13 14
2
D DDR_A_D2 VSS5 VSS6 DDR_A_D6 D
G
15 16
2
2 2 DDR_A_D3 DQ2 DQ6 DDR_A_D7
<6,12,14> RST_GATE 17 DQ3 DQ7 18
19 VSS7 VSS8 20 Layout Note:
DDR_A_D9 23
DQ8 DQ12
24 DDR_A_D13 Place near JDIMM1
DQ9 DQ13 +1.5V
25 VSS9 VSS10 26
DDR_A_DQS#1 27 28 DDR_A0_DM1
DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DIMM_DRAMRST# <6,12>
All VREF traces should 31 VSS11 VSS12 32
0.1U_0402_16V4Z
C2066
1U_0402_6.3V6K
C371
1U_0402_6.3V6K
C385
1U_0402_6.3V6K
C410
1U_0402_6.3V6K
C409
have 10 mil trace width DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36 1 1 1 1 1
37 VSS13 VSS14 38
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
2 2 2 2 2
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A0_DM2
DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23 R02 modify for ESD
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3 +1.5V
DDR_A0_DM3 VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DQ26 DQ30
10U_0603_6.3V6M
C384
10U_0603_6.3V6M
C378
10U_0603_6.3V6M
C415
10U_0603_6.3V6M
C414
DQ27 DQ31
71 VSS25 VSS26 72 1 1 1 1
C DDRA_CKE0_DIMMA DDRA_CKE1_DIMMA 2 2 2 2 C
<6> DDRA_CKE0_DIMMA 73 CKE0 CKE1 74 DDRA_CKE1_DIMMA <6>
75 VDD1 VDD2 76
77 78 DDR_A_MA15
DDR_A_BS2 NC1 A15 DDR_A_MA14
<6> DDR_A_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6 +1.5V
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
DDR_A_MA3
93 VDD7 VDD8 94
DDR_A_MA2
CHG C407 to oscon
95 A3 A2 96
10U_0603_6.3V6M
C413
10U_0603_6.3V6M
C412
10U_0603_6.3V6M
DDR_A_MA1 97 98 DDR_A_MA0 1
A1 A0
330U_D2_2V_Y
99 100 1 1 1 @
VDD9 VDD10 +
C383
C407
<6> SA_CLK_DDR0 SA_CLK_DDR0 101 102 SA_CLK_DDR1 SA_CLK_DDR1 <6>
SA_CLK_DDR#0 CK0 CK1 SA_CLK_DDR#1
<6> SA_CLK_DDR#0 103 CK0# CK1# 104 SA_CLK_DDR#1 <6> +1.5V @
105 VDD11 VDD12 106
DDR_A_MA10 DDR_A_BS1 2 2 2 2
107 A10/AP BA1 108 DDR_A_BS1 <6>
<6> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS# DDR_A_RAS# <6>
BA0 RAS#
111 VDD13 VDD14 112
1
<6> DDR_A_WE# DDR_A_WE# 113 114 DDRA_CS0_DIMMA# DDRA_CS0_DIMMA# <6>
DDR_A_CAS# WE# S0# SA_ODT0 R267
<6> DDR_A_CAS# 115 CAS# ODT0 116 SA_ODT0 <6>
117 118 1K_0402_5%
DDR_A_MA13 VDD15 VDD16 SA_ODT1
119 A13 ODT1 120 SA_ODT1 <6>
<6> DDRA_CS1_DIMMA# DDRA_CS1_DIMMA# 121 122
2
S1# NC2
123 VDD17 VDD18 124
125 126 +VREF_CA
NCTEST VREF_CA
127 VSS27 VSS28 128
2.2U_0603_6.3V6K
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36
1
C372
0.1U_0402_16V4Z
C373
DDR_A_D33 131 132 DDR_A_D37 +0.75VS
DQ33 DQ37 R266
133 VSS29 VSS30 134 1 1
DDR_A_DQS#4 135 136 DDR_A0_DM4 1K_0402_5%
B DDR_A_DQS4 DQS#4 DM4 B
137 DQS4 VSS31 138
1U_0402_6.3V6K
C393
1U_0402_6.3V6K
C395
1U_0402_6.3V6K
C394
1U_0402_6.3V6K
C388
139 140 DDR_A_D38
2
DDR_A_D34 VSS32 DQ38 DDR_A_D39 2 2
141 DQ34 DQ39 142 1 1 1 1
DDR_A_D35 143 144
DQ35 VSS33 DDR_A_D44
145 VSS34 DQ44 146
DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 DQ40 DQ45 2 2 2 2
149 DQ41 VSS35 150
151 152 DDR_A_DQS#5
DDR_A0_DM5 VSS36 DQS#5 DDR_A_DQS5
153 DM5 DQS5 154
155 VSS37 VSS38 156
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_A_D48 163 DQ48 DQ52 164 DDR_A_D52 Layout Note:
DDR_A_D49 165 166 DDR_A_D53
167
DQ49 DQ53
168 Place near JDIMM1.203,204
DDR_A_DQS#6 VSS41 VSS42 DDR_A0_DM6
169 DQS#6 DM6 170
DDR_A_DQS6 171 172
DQS6 VSS43 DDR_A_D54
173 VSS44 DQ54 174
DDR_A_D50 175 176 DDR_A_D55
DDR_A_D51 DQ50 DQ55
177 DQ51 VSS45 178
179 180 DDR_A_D60
DDR_A_D56 VSS46 DQ60 DDR_A_D61 DDR_A0_DM0
181 DQ56 DQ61 182
DDR_A_D57 183 184 DDR_A0_DM1
DQ57 VSS47 DDR_A_DQS#7 DDR_A0_DM2
185 VSS48 DQS#7 186
DDR_A0_DM7 187 188 DDR_A_DQS7 DDR_A0_DM3
DM7 DQS7 DDR_A0_DM4
189 VSS49 VSS50 190
DDR_A_D58 191 192 DDR_A_D62 DDR_A0_DM5
DDR_A_D59 DQ58 DQ62 DDR_A_D63 DDR_A0_DM6
193 DQ59 DQ63 194
195 196 DDR_A0_DM7
VSS51 VSS52
197 SA0 EVENT# 198
+3VS 199 200 D_CK_SDATA
A VDDSPD SDA D_CK_SDATA <12,14,41> A
201 202 D_CK_SCLK
SA1 SCL D_CK_SCLK <12,14,41>
+0.75VS 203 VTT1 VTT2 204 +0.75VS
0.1U_0402_16V4Z
C404
2.2U_0603_6.3V6K
C416
10K_0402_5%
R301
205 G1 G2 206
1
2
10K_0402_5%
R302
<Address(SA1,SA0): 00> 1 1
FOX_AS0A626-U8SN-7F
CONN@
DIMM_1 Reserve H:8mm 2 2 Security Classification Compal Secret Data

2
SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1
+1.5V
1
+1.5V +1.5V
R341 JDIMM2
1K_0402_5% +V_DDR_REFC 1 2
@R346
@ R346 VREF_DQ VSS1 DDR_B_D4
M3 support 3 VSS2 DQ4 4
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
0_0402_5% DDR_B_D0 5 6 DDR_B_D5
2
DQ0 DQ5
C438
C437
<9> SB_DIMM_VREFDQ 1 2 DDR_B_D1 7 8
DQ1 VSS3 DDR_B_DQS#0
1 1 9 VSS4 DQS#0 10 DDR_B_DQS#[0..7] <6>
1
DDR_B0_DM0 11 12 DDR_B_DQS0
DM0 DQS0
13 VSS5 VSS6 14 DDR_B_DQS[0..7] <6>
D
3 1 R340 DDR_B_D2 15 16 DDR_B_D6
Q47 1K_0402_5% 2 2 DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18 DDR_B_D[0..63] <6>
D S TR SSM3K7002F 1N SC59-3 @ D
19 20
2
DDR_B_D8 VSS7 VSS8 DDR_B_D12
G
21 22 DDR_B_MA[0..15] <6>
2
DDR_B_D9 DQ8 DQ12 DDR_B_D13
<6,11,14> RST_GATE 23 DQ9 DQ13 24
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28 DDR_B0_DM1
DDR_B_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DIMM_DRAMRST# <6,11>
All VREF traces should 31 VSS11 VSS12 32 Layout Note:
DDR_B_D10 33 34 DDR_B_D14
have 10 mil trace width DDR_B_D11 35
DQ10 DQ14
36 DDR_B_D15 Place near JDIMM2
DQ11 DQ15 +1.5V
37 VSS13 VSS14 38
41 DQ17 DQ21 42
43 VSS15 VSS16 44
1U_0402_6.3V6K
C445
1U_0402_6.3V6K
C444
1U_0402_6.3V6K
C430
1U_0402_6.3V6K
C429
DDR_B_DQS2 DQS#2 DM2
47 DQS2 VSS17 48 1 1 1 1
49 50 DDR_B_D22
DDR_B_D18 VSS18 DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS19 DDR_B_D28 2 2 2 2
55 VSS20 DQ28 56
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_B_DQS#3
DDR_B0_DM3 VSS22 DQS#3 DDR_B_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_B_D27 DQ26 DQ30 DDR_B_D31 +1.5V
69 DQ27 DQ31 70
71 VSS25 VSS26 72
10U_0603_6.3V6M
C424
10U_0603_6.3V6M
C425
10U_0603_6.3V6M
C450
10U_0603_6.3V6M
C449
<6> DDRB_CKE0_DIMMB DDRB_CKE0_DIMMB 73 74 DDRB_CKE1_DIMMB DDRB_CKE1_DIMMB <6> 1 1 1 1
CKE0 CKE1
75 VDD1 VDD2 76
C DDR_B_MA15 C
77 NC1 A15 78
<6> DDR_B_BS2 DDR_B_BS2 79 80 DDR_B_MA14
BA2 A14 2 2 2 2
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA1 A3 A2 DDR_B_MA0 +1.5V
97 A1 A0 98
99 VDD9 VDD10 100
<6> SB_CLK_DDR0 SB_CLK_DDR0 101 102 SB_CLK_DDR1 SB_CLK_DDR1 <6> CHG C359 to oscon
SB_CLK_DDR#0 CK0 CK1 SB_CLK_DDR#1
<6> SB_CLK_DDR#0 103 CK0# CK1# 104 SB_CLK_DDR#1 <6> +1.5V
10U_0603_6.3V6M
C448
10U_0603_6.3V6M
C447
10U_0603_6.3V6M
105 VDD11 VDD12 106 1
330U_2.5V_M
DDR_B_MA10 107 108 DDR_B_BS1 DDR_B_BS1 <6> 1 1 1 @
A10/AP BA1 +
C426
C359
<6> DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS# DDR_B_RAS# <6>
BA0 RAS#
111 VDD13 VDD14 112
1
<6> DDR_B_WE# DDR_B_WE# 113 114 DDRB_CS0_DIMMB# DDRB_CS0_DIMMB# <6>
DDR_B_CAS# WE# S0# SB_ODT0 R351 2 2 2 2
<6> DDR_B_CAS# 115 CAS# ODT0 116 SB_ODT0 <6>
117 118 1K_0402_5%
DDR_B_MA13 VDD15 VDD16 SB_ODT1
119 A13 ODT1 120 SB_ODT1 <6>
<6> DDRB_CS1_DIMMB# DDRB_CS1_DIMMB# 121 122
2
S1# NC2
123 VDD17 VDD18 124
125 126 +VREF_CC
NCTEST VREF_CA
127 VSS27 VSS28 128
2.2U_0603_6.3V6K
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36
1
C451
0.1U_0402_16V4Z
C446
DDR_B_D33 131 132 DDR_B_D37
DQ33 DQ37 R350
133 VSS29 VSS30 134 1 1
DDR_B_DQS#4 135 136 DDR_B0_DM4 1K_0402_5% +0.75VS
DDR_B_DQS4 DQS#4 DM4
137 DQS4 VSS31 138
139 140 DDR_B_D38
2
B DDR_B_D34 VSS32 DQ38 DDR_B_D39 2 2 B
141 DQ34 DQ39 142
1U_0402_6.3V6K
C440
1U_0402_6.3V6K
C427
1U_0402_6.3V6K
C439
1U_0402_6.3V6K
C428
DDR_B_D35 143 144
DQ35 VSS33 DDR_B_D44
145 VSS34 DQ44 146 1 1 1 1
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDR_B_DQS#5
DDR_B0_DM5 VSS36 DQS#5 DDR_B_DQS5 2 2 2 2
153 DM5 DQS5 154
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_B_D48 163 164 DDR_B_D52
165 DQ49 DQ53 166
167 VSS41 VSS42 168 Layout Note:
DDR_B_DQS6 171
DQS#6 DM6
172 Place near JDIMM2.203,204
DQS6 VSS43 DDR_B_D54
173 VSS44 DQ54 174
DDR_B_D50 175 176 DDR_B_D55
DDR_B_D51 DQ50 DQ55
177 DQ51 VSS45 178
179 180 DDR_B_D60 DDR_B0_DM0
DDR_B_D56 VSS46 DQ60 DDR_B_D61 DDR_B0_DM1
181 DQ56 DQ61 182
+3VS DDR_B_D57 183 184 DDR_B0_DM2
DQ57 VSS47 DDR_B_DQS#7 DDR_B0_DM3
185 VSS48 DQS#7 186
DDR_B0_DM7 187 188 DDR_B_DQS7 DDR_B0_DM4
DM7 DQS7
10K_0402_5%
R344
189 190 DDR_B0_DM5

VSS49 VSS50
2
DDR_B_D58 191 192 DDR_B_D62 DDR_B0_DM6

DDR_B_D59 DQ58 DQ62 DDR_B_D63 DDR_B0_DM7
193 DQ59 DQ63 194
195 VSS51 VSS52 196
197 SA0 EVENT# 198
+3VS 199 200 D_CK_SDATA
D_CK_SDATA <11,14,41>
1
VDDSPD SDA D_CK_SCLK

201 SA1 SCL 202 D_CK_SCLK <11,14,41>
+0.75VS 203 VTT1 VTT2 204 +0.75VS
A A
0.1U_0402_16V4Z
C435
2.2U_0603_6.3V6K
C436
205 G1 G2 206
1
10K_0402_5%
R345
1 1
FOX_AS0A626-U4RN-7F
CONN@
<Address(SA1,SA0): 10> 2 2
2

DIMM_2 Reserve H:4mm Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title
SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1
+RTCVCC PCH_RTCX1 +RTCBATT +3VS

+RTCBATT
R567 1 2 1M_0402_5% SM_INTRUDER# 1 2 PCH_RTCX2 SERIRQ R275 2 1 10K_0402_5%
R568 10M_0402_5% +CHGRTC
1
R585 1 2 330K_0402_5% PCH_INTVRMEN PCH_SATALED# R640 2 1 10K_0402_5%
R375 JBATT1
+
Y3
INTVRMEN 1K_0402_5%
PCH_GPIO19 R624 1 2 4.7K_0402_5%
* H：Integrated VRM enable 1 2
3 1
15P_0402_50V8J
L：Integrated VRM disable +RTCBATT_R
2
32.768KHZ_12.5PF_FC-135 D13 20mil
(INTVRMEN should always be pull high.) 1 1
C686
D C682 15P_0402_50V8J D
+3VS +RTCVCC This part had been re-modified
2 2
20mil be careful,if link symbol!!+3VS
1
R294 1 @ 2 1K_0402_5% PCH_SPKR R04 modify
-
1 CHN202UPT_SC70-3 CONN@ SUYIN_060003HA002G202ZL U36
2
HIGH= Enable ( No Reboot ) C471 PCH_SPI_CS0#_1 1 8
CS# VCC
* LOW= Disable (Default)
2
0.1U_0402_16V4Z
SPI_WP1#
SPI_HOLD1#
3
7
WP#
HOLD#
SCLK
SI/SIO0
6
5
PCH_SPI_CLK_1
PCH_SPI_MOSI_1
4 2 PCH_SPI_MISO_1
+3VALW_PCH R556 GND SO/SIO1
1K_0402_5% 32M W25Q32BVSSIG_SO8
2 @ 1 HDA_SDOUT_PCH
R557 SPI ROM FOR ME (4MB)
R02 Modify 0_0402_5%
<40> ME_EN 2 1 Footprint 200mil
HDA_SDO as Capella ME override (GPIO33) +3VS R654 1

R667 1
2 3.3K_0402_5% SPI_WP1#
2 3.3K_0402_5% SPI_HOLD1#
ME debug mode,this signal has a weak internal PD RTCRST close RAM door R866 C893
* Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide] PCH_SPI_CLK_1 1 2
@ @
SHORT PADS
JCMOS1
U33A 22_0402_5% 33P_0402_50V8K
1
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 <40>
+3VALW_PCH A38 LPC_AD1
LPC
FWH1 / LAD1 LPC_AD1 <40>
C360 @ PCH_RTCX2 C20 B37 LPC_AD2 Rserve the 2M ROM for Win8
LPC_AD2 <40>
2
RTCX2 FWH2 / LAD2
R539 2 1 1K_0402_5% HDA_SYNC_PCH 1U_0603_10V6K
FWH3 / LAD3 C37 LPC_AD3
LPC_AD3 <40>
2 PCH_RTCRST# +3VS
1 2 D20 RTCRST#
This signal has a weak internal pull-down R248 20K_0402_1% D36 LPC_FRAME# U42 WIN8@
FWH4 / LFRAME# LPC_FRAME# <40>
1 2 PCH_SRTCRST# G22 PCH_SPI_CS0#_2 1 8 PCH_SPI_VCC
R243 20K_0402_1% 1 SRTCRST# SPI_WP2# CS# VCC PCH_SPI_CLK_2
E36 3 6
RTC
LDRQ0# WP# SCLK
On Die PLL VR Select is supplied by 1
SHORT PADS
JME1
C SM_INTRUDER# PCH_GPIO23 SPI_HOLD2# PCH_SPI_MOSI_2 C
K22 INTRUDER# LDRQ1# / GPIO23 K36 7 HOLD# SI 5
* 1.5V when smapled high
1.8V when sampled low
C356
1U_0603_10V6K PCH_INTVRMEN C17 V5 SERIRQ SERIRQ <40>
Modify R02
4 GND SO 2 PCH_SPI_MISO_2
2
2 @ INTVRMEN SERIRQ MX25L1606EM2I-12G_SO8

Needs to be pulled High for Huron River platfrom
SATA0RXN AM3 SATA_PRX_DTX_N0 <34>
HDA_BITCLK_PCH N34 AM1 SATA_PRX_DTX_P0 <34>
HDA_BCLK SATA0RXP
SATA 6G
SATA0TXN AP7 SATA_PTX_DRX_N0 <34> HDD
R544 SRTCRST close RAM door HDA_SYNC_PCH L34 AP5 R703 1 WIN8@ 2 SPI_HOLD2#
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 <34>
33_0402_5% +3VS 3.3K_0402_5%
<42> HDA_BITCLK_AUDIO 1 2 HDA_BITCLK_PCH <42> PCH_SPKR
PCH_SPKR T10 SPKR SATA1RXN AM10 SATA_PRX_DTX_N1 <37> R704 1 WIN8@2 SPI_WP2#
R542 AM8 SATA_PRX_DTX_P1 <37> 3.3K_0402_5%
SATA1RXP
33_0402_5% HDA_RST_PCH# K34 HDA_RST# SATA1TXN AP11 SATA_PTX_DRX_N1 <37> MSATA
<42> HDA_SYNC_AUDIO 1 2 HDA_SYNC_PCH_R SATA1TXP AP10 SATA_PTX_DRX_P1 <37>
PCH_SPI_CLK_2 @1 R2048 2 @ C2049
R545 22_0402_5%
33_0402_5% <42> HDA_SDIN0 HDA_SDIN0 E34 AD7 SATA_PRX_DTX_N2 <34> 33P_0402_50V8K
HDA_SDIN0 SATA2RXN Modify R03
<42> HDA_RST_AUDIO# 1 2 HDA_RST_PCH# SATA2RXP AD5 SATA_PRX_DTX_P2 <34>
R555 G34 AH5 ODD Co-lay NPCE885N
HDA_SDIN1 SATA2TXN SATA_PTX_DRX_N2 <34>
33_0402_5% AH4
SATA2TXP SATA_PTX_DRX_P2 <34>
<42> HDA_SDOUT_AUDIO 1 2 HDA_SDOUT_PCH C34
IHDA
HDA_SDIN2 Modify R04
SATA3RXN AB8
A34 AB10 Delete Co-lay NPCE885N
HDA_SDIN3 SATA3RXP
SATA3TXN AF3
SATA3TXP AF1
HDA_SDOUT_PCH A36
SATA
HDA_SDO
SATA4RXN Y7
SATA4RXP Y5
Prevent back drive issue. C36 HDA_DOCK_EN# / GPIO33 SATA4TXN AD3
AD1
SATA4TXP
N32 HDA_DOCK_RST# / GPIO13
+3VS Y3
@ R674 SATA5RXN +3VS
SATA5RXP Y1
2
G
B Q36 51_0402_5% B
SATA5TXN AB3
1
S TR SSM3K7002F 1N SC59-3 2 1 PCH_JTAG_TCK J3 AB1
HDA_SYNC_PCH_R JTAG_TCK SATA5TXP
3 1HDA_SYNC_PCH R259
PCH_JTAG_TMS R260 +1.05VS_VTT
S
H7 Y11 10K_0402_5%
JTAG
PAD T75 @ JTAG_TMS SATAICOMPO 37.4_0402_1%
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
T76 @
2
PAD JTAG_TDI SATAICOMPI
1 2
@ PCH_JTAG_TDO H1 SGEN#
R540 PAD T77 @ JTAG_TDO R241 +1.05VS_VTT
SATA3RCOMPO AB12
1
0_0402_5% 49.9_0402_1%
1
AB13 SATA3_COMP1 2 R258

R792 PCH_SPI_CLK_2 SATA3COMPI
2 WIN8@ 1 R625 10K_0402_5%
1M_0402_5% R734 33_0402_5% 750_0402_1% @
PCH_SPI_CLK_1 1 2 PCH_SPI_CLK T3 AH1 RBIAS_SATA3 1 2
2
R681 33_0402_5% SPI_CLK SATA3RBIAS
2
PCH_SPI_CS0#_1 Y14
R04 modify SPI_CS0#
PCH_SPI_CS0#_2 T1 GPIO21
SPI
SPI_CS1# PCH_SATALED#
SATALED# P3 PCH_SATALED# <41>
PCH_SPI_MOSI_2 2 WIN8@ 1 SGEN#
R733 33_0402_5% V4 V14 SGEN#
SPI_MOSI SATA0GP / GPIO21
PCH_SPI_MOSI_1 1
R684
2 PCH_SPI_MOSI
33_0402_5% U3 P1 PCH_GPIO19
Switchable GPU 0
SPI_MISO SATA1GP / GPIO19
+3VS
PCH_SPI_MISO_1 1
R652
2 PCH_SPI_MISO
33_0402_5%
* Non-Switchable 1
PCH_SPI_MISO_2 1 WIN8@ 2 COUGARPOINT_FCBGA989~D
R2050 33_0402_5% HM65@
Boot BIOS Strap
2
SA00004EEY0 U33
PUSB3@
R2128
Boot BIOS GPIO51 GPIO19
20K_0402_1%
LPC 0 0
1
A
PCH_GPIO23 BD82HM77 QPRG C1 BGA 989P
Reserved 0 1 A
HM77@
- 1 0
2
SA00005AG00
PUSB2@
R2092
GPIO23
USB_config
* SPI 1 1
20K_0402_1%
1
USB2.0 0 2011/06/02 2012/06/02 Title

Issued Date Deciphered Date
USB3.0 1 SCHEMATIC,MB A7912
modify on 7912 V0.3 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
5 4 3 2 1
5 4 3 2 1
U33B +3VALW_PCH
<35> PCIE_PRX_DTX_N1 PCIE_PRX_DTX_N1 BG34 PCH_GPIO11 R240 1 2 10K_0402_5%

PCIE_PRX_DTX_P1 PERN1 PCH_GPIO11
<35> PCIE_PRX_DTX_P1 BJ34 PERP1 SMBALERT# / GPIO11 E12
PCIE LAN <35> PCIE_PTX_C_DRX_N1
C672 1 2 .1U_0402_16V7K PCIE_PTX_DRX_N1 AV32 PETN1
RST_GATE R608 2 1 1K_0402_5%
C669 1 2 .1U_0402_16V7K PCIE_PTX_DRX_P1 AU32 H14 PCH_SMBCLK
<35> PCIE_PTX_C_DRX_P1 PETP1 SMBCLK PCH_SMBCLK <37>
<37> PCIE_PRX_DTX_N2 PCIE_PRX_DTX_N2 BE34 C9 PCH_SMBDATA PCH_SMBDATA <37> PCH_SMBCLK R677 1 2 2.2K_0402_5%
PCIE_PRX_DTX_P2 PERN2 SMBDATA
<37> PCIE_PRX_DTX_P2 BF34 PERP2
Mini Card 1 (WLAN) <37> PCIE_PTX_C_DRX_N2
C675 1 2 .1U_0402_16V7K PCIE_PTX_DRX_N2 BB32 PETN2
PCH_SMBDATA R662 1 2 2.2K_0402_5%
C677 1 2 .1U_0402_16V7K PCIE_PTX_DRX_P2 AY32
SMBUS
<37> PCIE_PTX_C_DRX_P2 PETP2
A12 RST_GATE
SML0ALERT# / GPIO60 RST_GATE <6,11,12>
BG36 PCH_GPIO74 R647 1 2 10K_0402_5%
PERN3
BJ36 PERP3 SML0CLK C8
D
R02 Modify AV34 PETN3
D
AU34 G12 PCH_SML1CLK R642 1 2 2.2K_0402_5%
PETP3 SML0DATA
BF36 PCH_SML1DATA R643 1 2 2.2K_0402_5%
PERN4
BE36 PERP4
AY34 C13 PCH_GPIO74
PETN4 SML1ALERT# / PCHHOT# / GPIO74 PCH_GPIO47 R280 10K_0402_5%
BB34 PETP4 1 2
E14 PCH_SML1CLK
PCI-E*
SML1CLK / GPIO58
BG37 PERN5
BH37 M16 PCH_SML1DATA
PERP5 SML1DATA / GPIO75
AY36 PETN5
BB36 PETP5 +3VS For DDR
BJ38 PERN6
+3VS BG38 R669
Controller
PERP6 4.7K_0402_5%
AU36 PETN6 CL_CLK1 M7
2
R638 2 1 10K_0402_5% MINI1_CLKREQ# AV36 1 2 +3VS
PETP6
Link
R273 2 1 10K_0402_5% USB30_CLKREQ# BG40 T11 PCH_SMBDATA 6 1 D_CK_SDATA D_CK_SDATA <11,12,41>
PERN7 CL_DATA1
BJ40 PERP7
+3VALW_PCH AY40 Q40A
PETN7 DMN66D0LDW-7_SOT363-6 R670
BB40 PETP7 CL_RST1# P10
R618 2 1 10K_0402_5% PCH_GPIO73 4.7K_0402_5%
5
BE38 PERN8 1 2 +3VS
R630 2 @ 1 10K_0402_5% LAN_CLKREQ# BC38 PERP8 PCH_SMBCLK D_CK_SCLK
AW38 PETN8 3 4 D_CK_SCLK <11,12,41>
R653 2 1 10K_0402_5% MINI2_CLKREQ# AY38 PETP8 Q40B
R238 2 1 10K_0402_5% PCH_GPIO44 M10 PCH_GPIO47 DMN66D0LDW-7_SOT363-6
PEG_A_CLKRQ# / GPIO47
Y40 CLKOUT_PCIE0N
R293 2 1 10K_0402_5% PCH_GPIO45 Y39 CLKOUT_PCIE0P
CLKOUT_PEG_A_N AB37
CLOCKS
C R295 PCH_GPIO46 PCH_GPIO73 C
2 1 10K_0402_5% J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38
+3VS Pull up at EC side.
<37> CLK_PCIE_MINI1#
CLK_PCIE_MINI1# AB49 AV22 CLK_CPU_DMI#
CLK_CPU_DMI# <5>
For VGA,EC
CLK_PCIE_MINI1 CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI
<37> CLK_PCIE_MINI1 AB47 CLKOUT_PCIE1P CLKOUT_DMI_P AU22 CLK_CPU_DMI <5>
Mini Card 1(WLAN)
2
<37> MINI1_CLKREQ# MINI1_CLKREQ# M1 PCIECLKRQ1# / GPIO18 CLK_CPU_DPLL#
CLKOUT_DP_N / CLKOUT_BCLK1_N AM12 CLK_CPU_DPLL# <5>
CLK_CPU_DPLL <5>120 MHz for eDP
AM13 CLK_CPU_DPLL PCH_SML1DATA 6 1 EC_SMB_DA2 EC_SMB_DA2 <22,40>
CLKOUT_DP_P / CLKOUT_BCLK1_P
AA48 CLKOUT_PCIE2N
AA47 Q38A
CLKOUT_PCIE2P CLK_BUF_CPU_DMI# R233 1
CLKIN_DMI_N BF18 2 10K_0402_5% DMN66D0LDW-7_SOT363-6
5
USB30_CLKREQ# V10 BE18 CLK_BUF_CPU_DMI R234 1 2 10K_0402_5%
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
PCH_SML1CLK 3 4 EC_SMB_CK2 EC_SMB_CK2 <22,40>
CLK_PCIE_LAN# Y37 BJ30 CLKIN_GND1# R563 1 2 10K_0402_5%
<35> CLK_PCIE_LAN# CLKOUT_PCIE3N CLKIN_DMI2_N
PCIE LAN <35> CLK_PCIE_LAN
CLK_PCIE_LAN Y36 CLKOUT_PCIE3P CLKIN_DMI2_P BG30 CLKIN_GND1 R561 1 2 10K_0402_5% Q38B
Pull down 10K ohm DMN66D0LDW-7_SOT363-6
LAN_CLKREQ# A8
<35> LAN_CLKREQ# PCIECLKRQ3# / GPIO25 CLK_BUF_DREF_96M# R220 1
for using internal Clock
CLKIN_DOT_96N G24 2 10K_0402_5%
E24 CLK_BUF_DREF_96M R221 1 2 10K_0402_5%
CLKIN_DOT_96P
Y43 CLKOUT_PCIE4N
Y45 CLKOUT_PCIE4P
AK7 CLK_BUF_PCIE_SATA# R264 1 2 10K_0402_5% XTAL25_IN
MINI2_CLKREQ# CLKIN_SATA_N / CKSSCD_N CLK_BUF_PCIE_SATA R265 1
L12 PCIECLKRQ4# / GPIO26 CLKIN_SATA_P / CKSSCD_P AK5 2 10K_0402_5%
XTAL25_OUT R527 1 2 1M_0402_5%
V45 K45 CLK_BUF_ICH_14M R175 1 2 10K_0402_5% Y2 25MHZ 10PF 7V25000014

CLKOUT_PCIE5N REFCLK14IN
V46 CLKOUT_PCIE5P
3 3 1 1
PCH_GPIO44 L14 H45 CLK_PCI_LPBACK
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <17> GND GND
1 1
B B
CLK_PEG_VGA# XTAL25_IN C630 4 2 C631
<22> CLK_PEG_VGA# AB42 CLKOUT_PEG_B_N XTAL25_IN V47
CLK_PEG_VGA AB40 V49 XTAL25_OUT 10P_0402_50V8J 10P_0402_50V8J
<22> CLK_PEG_VGA CLKOUT_PEG_B_P XTAL25_OUT 2 2
PEG_CLKREQ#_R E6 R526 +1.05VS_VTT R02 modify
PEG_B_CLKRQ# / GPIO56 90.9_0402_1%
Y47 XCLK_RCOMP 1 2
XCLK_RCOMP
V40 CLKOUT_PCIE6N
V42 CLKOUT_PCIE6P @R530
@ R530 @C642
@ C642
PCH_GPIO45 T13 33_0402_5% 22P_0402_50V8J
PCIECLKRQ6# / GPIO45 CLK_PCI_LPBACK 2 1 1 2
V38 K43 CLK_FLEX0 @ PAD
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 T9
FLEX CLOCKS
V37 CLKOUT_PCIE7P
CLKOUTFLEX1 / GPIO65 F47 CLK_FLEX1 @
T73 PAD Reserve for EMI please close to U33
PCH_GPIO46 K12 PCIECLKRQ7# / GPIO46
CLKOUTFLEX2 / GPIO66 H47 CLK_FLEX2 @
T29 PAD
AK14 CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AK13 K49 DGPU_PRSNT#
CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX3 / GPIO67 +3VS
COUGARPOINT_FCBGA989~D
1
HM65@
UMAO@
R159
<17,25,44,51,53> VGA_ON +3VALW_PCH
GPIO67 10K_0402_5%
2
1
DGPU_PRSNT# DGPU_PRSNT#
1
DIS@
2
R632
10K_0402_5%
R663
10K_0402_5%
DIS,OPTIMUS 0 DIS@
UMA 1 R160
2
A DIS@ 10K_0402_5% A
2
Q39
1
2
G
2N7002H_SOT23-3
2 DIS@ 1 3 1 PEG_CLKREQ#_R
<22> PEG_CLKREQ#
R631
S
D
1
Pull high @ VGA side 0_0402_5%

@ @
R644
2.2K_0402_5%
R668
2.2K_0402_5%
for safe
SCHEMATIC,MB A7912
2
5 4 3 2 1
5 4 3 2 1
D U33C D
+3VALW_PCH DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

<4> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <4>
<4> DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1 FDI_CTX_PRX_N1 <4>
DMI_CTX_PRX_N2 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N2
<4> DMI_CTX_PRX_N2 BG18 DMI2RXN FDI_RXN2 BE14 FDI_CTX_PRX_N2 <4>
<4> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3 FDI_CTX_PRX_N3 <4>
R607 DMI3RXN FDI_RXN3
2 1 10K_0402_5% SUSWARN#
FDI_RXN4 BC12 FDI_CTX_PRX_N4 FDI_CTX_PRX_N4 <4>
<4> DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 FDI_CTX_PRX_N5 <4>
R218 DMI0RXP FDI_RXN5
2 1 200K_0402_5% PCH_ACIN <4> DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 DMI1RXP FDI_RXN6 BG10 FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 <4>
<4> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 FDI_CTX_PRX_N7 <4>
R247 PCH_GPIO72 DMI_CTX_PRX_P3 DMI2RXP FDI_RXN7
2 1 10K_0402_5% <4> DMI_CTX_PRX_P3 BJ20 DMI3RXP
BG14 FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 <4>
R610 RI# DMI_CRX_PTX_N0 FDI_RXP0 FDI_CTX_PRX_P1
2 1 10K_0402_5% <4> DMI_CRX_PTX_N0 AW24 DMI0TXN FDI_RXP1 BB14 FDI_CTX_PRX_P1 <4>
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 FDI_CTX_PRX_P2 <4>
<4> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 <4>
<4> DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3
R597 2 1 200_0402_1% PM_DRAM_PWRGD DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4
DMI
FDI
<4> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <4>
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 <4>
DMI_CRX_PTX_P0 FDI_RXP5 FDI_CTX_PRX_P6
<4> DMI_CRX_PTX_P0 AY24 DMI0TXP FDI_RXP6 BJ10 FDI_CTX_PRX_P6 <4>
R559 2 1 10K_0402_5% PCH_RSMRST# DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 <4>
<4> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7
DMI_CRX_PTX_P2 AY18
<4> DMI_CRX_PTX_P2 DMI2TXP
DMI_CRX_PTX_P3 AU18
<4> DMI_CRX_PTX_P3 DMI3TXP
AW16 FDI_INT
FDI_INT FDI_INT <4> +RTCVCC
+1.05VS_VTT BJ24 AV12 FDI_FSYNC0
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <4>
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1 DSWODVREN R577 2 1 330K_0402_5%
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <4>
R223 49.9_0402_1%
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 R581 2 1 330K_0402_5%
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <4>
R578 750_0402_1% @
4mil width and place BB10 FDI_LSYNC1
FDI_LSYNC1 <4> DSWODVREN - On Die DSW VR Enable
FDI_LSYNC1
C
within 500mil of the PCH * H：Enable
L：Disable C
A18 DSWODVREN
DSWVRMEN
System Power Management

not support Deep S4,S5 DPWROK mux with PWROK
@ PAD T78 SUSACK#_R C12 SUSACK# DPWROK E22 PCH_RSMRST# check list1.0 P.42
<5> XDP_DBRESET# 1 2 XDP_DBRESET#_R K3 SYS_RESET# WAKE# B9 PCH_PCIE_WAKE# PCH_PCIE_WAKE# <35,37>

R678 0_0402_5%
SYS_PWROK P12 N3 PCH_GPIO32

SYS_PWROK CLKRUN# / GPIO32
not support AMT APWROK can mux
+3VALW_PCH
with PWROK (check list1.0 P.40) PCH_PWROK PCH_PWROK_R SUS_STAT# T22 PAD @
1 2 L22 PWROK SUS_STAT# / GPIO61 G8
R635 0_0402_5% PCH_PCIE_WAKE# R613 1 2 10K_0402_5%
L10 N14 SUSCLK PCH_GPIO29 R235 1 @ 2 10K_0402_5%

APWROK SUSCLK / GPIO62 SUSCLK <40>
T23 PAD @ +3VS
PM_DRAM_PWRGD B13 D10 PM_SLP_S5#
<5> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <40>
PCH_GPIO32 R622 1 2 10K_0402_5%
T21 PAD @
<40> PCH_RSMRST# PCH_RSMRST# C21 H4 PM_SLP_S4#
RSMRST# SLP_S4# PM_SLP_S4# <40>
T20 PAD @
SUSWARN# K16 SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# F4 PM_SLP_S3#
PM_SLP_S3# <40> Can be left NC
when IAMT is not
support on the
PBTN_OUT# E20 G10 PAD T47
<40> PBTN_OUT# PWRBTN# SLP_A# @
platfrom
<40,44,47,48> ACIN 1 2 PCH_ACIN H20 G16 not support

ACPRESENT / GPIO31 SLP_SUS#
B D9 CH751H-40PT_SOD323-2 Deep S4,S5 can NC B
T16 PAD PCH EDS1.2 P.74
PCH_GPIO72 E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <5>
@
RI# A10 K14 PCH_GPIO29
RI# SLP_LAN# / GPIO29
Ring Indicator CRB1.0 PH 10K +3VALW
HM65@
tell PCH all power ok +3VS

but cpu core
ALL power OK
5
U35
2 B
P
<40> PCH_PWROK
4 SYS_PWROK
Y SYS_PWROK <5>
<40,52> VGATE 1 A
G
MC74VHC1G08DFT2G_SC70-5
3
R629
10K_0402_5%
2
A A

SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1
D D
Pull high at LVDS conn side.

U33D
IGPU_BKLT_EN J47 AP43
L_BKLTEN SDVO_TVCLKINN
<31> PCH_ENVDD M45 L_VDD_EN SDVO_TVCLKINP AP45
<31> DPST_PWM P45 L_BKLTCTL SDVO_STALLN AM42

SDVO_STALLP AM40
<31> PCH_LCD_CLK T40 L_DDC_CLK
ENBKL R532 2 1 0_0402_5% IGPU_BKLT_EN K47 AP39
<40> ENBKL <31> PCH_LCD_DATA L_DDC_DATA SDVO_INTN
CTRL_CLK SDVO_INTP AP40 SDVO_CTRLDATA strap pull high
T45 L_CTRL_CLK
1 1 CTRL_DATA P39 at level shift page
@ @ L_CTRL_DATA
C2043 C2044 2 1 LVDS_IBG AF37 P38 SDVO_SCLK
LVD_IBG SDVO_CTRLCLK SDVO_SCLK <33>
10P_0402_50V8J 10P_0402_50V8J R189 AF36 M39 SDVO_SDATA
2 2 LVD_VBG SDVO_CTRLDATA SDVO_SDATA <33>
2.37K_0402_1%
C LVD_VREF C
AE48 LVD_VREFH
2 1 AE47 LVD_VREFL DDPB_AUXN AT49
R177 AT47
0_0402_5% DDPB_AUXP PCH_DPB_HPD
DDPB_HPD AT40 PCH_DPB_HPD <33>
RF request PCH_TXCLK- AK39
LVDS
<31> PCH_TXCLK- LVDSA_CLK#
+3VS PCH_TXCLK+ AK40 AV42 PCH_DPB_N0 PCH_DPB_N0 <33>
<31> PCH_TXCLK+ LVDSA_CLK DDPB_0N
AV40 PCH_DPB_P0 PCH_DPB_P0 <33> HDMI D2
R174 DDPB_0P
1 2 2.2K_0402_5% CTRL_CLK
<31> PCH_TXOUT0-
PCH_TXOUT0- AN48 LVDSA_DATA#0 DDPB_1N AV45 PCH_DPB_N1 PCH_DPB_N1 <33>
PCH_TXOUT1- PCH_DPB_P1
Digital Display Interface

<31> PCH_TXOUT1- AM47 LVDSA_DATA#1 DDPB_1P AV46 PCH_DPB_P1 <33> HDMI D1
R158 1 2 2.2K_0402_5% CTRL_DATA PCH_TXOUT2- AK47 AU48 PCH_DPB_N2 PCH_DPB_N2 <33>
<31> PCH_TXOUT2- LVDSA_DATA#2 DDPB_2N
AJ48 AU47 PCH_DPB_P2 PCH_DPB_P2 <33> HDMI D0
LVDSA_DATA#3 DDPB_2P PCH_DPB_N3
DDPB_3N AV47 PCH_DPB_N3 <33>
R156 1 2 2.2K_0402_5% PCH_LCD_CLK PCH_TXOUT0+ AN47 AV49 PCH_DPB_P3 PCH_DPB_P3 <33> HDMI CLK
<31> PCH_TXOUT0+ LVDSA_DATA0 DDPB_3P
PCH_TXOUT1+ AM49
<31> PCH_TXOUT1+ LVDSA_DATA1
R157 1 2 2.2K_0402_5% PCH_LCD_DATA PCH_TXOUT2+ AK49
<31> PCH_TXOUT2+ LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
DDPC_CTRLDATA P42
AF40 LVDSB_CLK#
AF39 LVDSB_CLK DDPC_AUXN AP47
DDPC_AUXP AP49
AH45 LVDSB_DATA#0 DDPC_HPD AT38
AH47 LVDSB_DATA#1
AF49 LVDSB_DATA#2 DDPC_0N AY47
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
+3VS AH43 AY45
LVDSB_DATA0 DDPC_1P
AH49 LVDSB_DATA1 DDPC_2N BA47
R521 1 2 2.2K_0402_5% PCH_CRT_CLK AF47 BA48
LVDSB_DATA2 DDPC_2P
AF43 LVDSB_DATA3 DDPC_3N BB47
R522 1 2 2.2K_0402_5% PCH_CRT_DATA BB49
DDPC_3P
B B
PCH_CRT_B N48 M43
<32> PCH_CRT_B CRT_BLUE DDPD_CTRLCLK
R534 1 2 150_0402_1% PCH_CRT_B PCH_CRT_G P49 M36
<32> PCH_CRT_G CRT_GREEN DDPD_CTRLDATA
PCH_CRT_R T49
<32> PCH_CRT_R CRT_RED
R533 1 2 150_0402_1% PCH_CRT_G
AT45
CRT
R535 PCH_CRT_R PCH_CRT_CLK DDPD_AUXN
1 2 150_0402_1% <32> PCH_CRT_CLK T39 CRT_DDC_CLK DDPD_AUXP AT43
PCH_CRT_DATA M40 BH41
<32> PCH_CRT_DATA CRT_DDC_DATA DDPD_HPD
DDPD_0N BB43
<32> PCH_CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
<32> PCH_CRT_VSYNC M49 CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
DDPD_2N BF42
CRT_IREF T43 BE42
DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
DDPD_3P BG42
1
R02 Modify
R178 HM65@
C2076 1 2 1U_0402_6.3V6K PCH_DPB_HPD 1K_0402_0.5%
2
A A

SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1
U33E
+3VS AY7
NV_CE#0
NV_CE#1 AV7
BG26 TP1 NV_CE#2 AU3
R173 1 2 10K_0402_5% PCI_PIRQA# BJ26 BG4
R180 10K_0402_5% PCI_PIRQD# TP2 NV_CE#3
1 2 BH25 TP3
R181 1 2 10K_0402_5% PCI_PIRQC# BJ16 AT10
R183 10K_0402_5% PCI_PIRQB# TP4 NV_DQS0
1 2 BG16 TP5 NV_DQS1 BC8
AH38 TP6
AH37 TP7 NV_DQ0 / NV_IO0 AU2
AK43 TP8 NV_DQ1 / NV_IO1 AT4
D D
AK45 TP9 NV_DQ2 / NV_IO2 AT3
R152 1 2 10K_0402_5% PCH_GPIO55 C18 AT1
R153 10K_0402_5% PCH_GPIO51 TP10 NV_DQ3 / NV_IO3
1 2 N30 TP11 NV_DQ4 / NV_IO4 AY3
R161 1 2 10K_0402_5% PCH_GPIO5 H3 AT5
1 2 AH12 AV3
NVRAM
TP13 NV_DQ6 / NV_IO6
AM4 TP14 NV_DQ7 / NV_IO7 AV1
AM5 TP15 NV_DQ8 / NV_IO8 BB1
Y13 TP16 NV_DQ9 / NV_IO9 BA3
K24 TP17 NV_DQ10 / NV_IO10 BB5
R166 1 2 10K_0402_5% PCH_GPIO2 L24 BB3
R169 10K_0402_5% VGA_ON TP18 NV_DQ11 / NV_IO11
1 2 AB46 TP19 NV_DQ12 / NV_IO12 BB7
R170 1 2 10K_0402_5% PCH_GPIO4 AB45 BE8
RSVD
1 2 NV_DQ14 / NV_IO14 BD4
NV_DQ15 / NV_IO15 BF6
B21 TP21 NV_ALE AV5

M20 AY1 DF_TVS
TP22 NV_CLE
AY16 TP23 DMI Termination Voltage
R165 1 2 8.2K_0402_5% PCH_GPIO53 BG46 AV10
TP24 NV_RCOMP
Set to Vcc when HIGH
NV_RB# AT8 DF_TVS
Set to Vss when LOW
<39> PCH_USB3_RX1_N PCH_USB3_RX1_N BE28 AY5
TP25 NV_RE#_WRB0
BC30 TP26 NV_RE#_WRB1 BA2
R188 1 DIS@ 2 8.2K_0402_5% DGPU_HOLD_RST# BE32 TP27
BJ32 TP28 NV_WE#_CK0 AT12 DG 1.2 CRB1.0 PH 2.2K series 1K
<39> PCH_USB3_RX1_P PCH_USB3_RX1_P BC28 BF3
R2137 1 @ USB20_P8 TP29 NV_WE#_CK1
2 10K_0402_5% BE30 TP30
BF32 R05 Modify +1.8VS
TP31
for IOAC PCH leakage issue BG32 TP32 USBP0N C24 USB20_N0
USB20_N0 <39>
PCH_USB3_TX1_N USB20_P0
LA-7912PR03 <39> PCH_USB3_TX1_N AV26 TP33 USBP0P A24 USB20_P0 <39>USB Conn. Colay USB3.0
1
BB26 C25 USB20_N1
C TP34 USBP1N USB20_N1 <39> C
USB20_P1 R633
AU28 TP35 USBP1P B25 USB20_P1 <39>USB/B (Right side)
AY30 C26 USB20_N2 2.2K_0402_5%
TP36 USBP2N USB20_N2 <39>
PCH_USB3_TX1_P USB20_P2
<39> PCH_USB3_TX1_P AU26 TP37 USBP2P A26 USB20_P2 <39>USB/B (Right side)
AY26 K28
2
TP38 USBP3N DF_TVS
AV28 TP39 USBP3P H28 2 1 H_SNB_IVB# <5>
AW30 E28 R626 1K_0402_5%
TP40 USBP4N
USBP4P D28
USBP5N C28 CLOSE TO THE BRANCHING POINT
USBP5P A28
USBP6N C29
USBP6P B29
PCI_PIRQA# K40 N28 Some PCH config not support USB port 6 & 7.
PCI_PIRQB# PIRQA# USBP7N
K38 M28
PCI
PCI_PIRQC# PIRQB# USBP7P USB20_N8
PCI_PIRQD#
H38 PIRQC# USBP8N L30
USB20_P8
USB20_N8 <37> Mini Card 1 (WLAN)
G38 PIRQD# USBP8P K30 USB20_P8 <37>
USBP9N G30
GPIO51 Internal pull high DGPU_HOLD_RST# C46 E30 +3VALW_PCH
USB
PCH_GPIO52 REQ1# / GPIO50 USBP9P USB20_N10
C44 REQ2# / GPIO52 USBP10N C30 USB20_N10 <31>
VGA_ON E40 A30 USB20_P10 CMOS Camera (LVDS)
<14,25,44,51,53> VGA_ON REQ3# / GPIO54 USBP10P USB20_P10 <31>
Boot BIOS Strap bit1 BBS1 USBP11N L32 USB20_N11
USB20_N11 <39>
USB_OC0# R596 1 2 10K_0402_5%
PCH_GPIO51 D47 K32 USB20_P11 BlueTooth USB_OC2# R588 1 2 10K_0402_5%
GNT1# / GPIO51 USBP11P USB20_P11 <39>
Boot BIOS PCH_GPIO53 E42 GNT2# / GPIO53 USBP12N G32 USB_OC7# R595 1 2 10K_0402_5%
PCH_GPIO55 F46 E32 R05 Modify USB_OC5# R590 1 2 10K_0402_5%
Bit11 Bit10 Destination GNT3# / GPIO55 USBP12P
USBP13N C32
USBP13P A32
0 1 Reserved PCH_GPIO2 G42 PIRQE# / GPIO2
GNT1#/ PCH_GPIO3 G40 PIRQF# / GPIO3 Within 500 mils
GPIO51 1 0 PCI PCH_GPIO4 C42 PIRQG# / GPIO4 USBRBIAS# C33 USBRBIAS 1 2
PCH_GPIO5 D44 R558 22.6_0402_1%
PIRQH# / GPIO5
1 1 SPI USB_OC1# R773 1 2 10K_0402_5%
B33 USB_OC4# R612 1 2 10K_0402_5%
USBRBIAS
B
0 0 LPC PAD T18 @ K10 PME# R05 Modify USB_OC3# R592 1 2 10K_0402_5%
B
SMIB R616 1 PUSB@ 2 10K_0402_5%
PLT_RST# C6 A14 USB_OC0# USB_OC0# <39>
<5> PLT_RST# PLTRST# OC0# / GPIO59
K20 USB_OC1#
OC1# / GPIO40 USB_OC2#
OC2# / GPIO41 B17
CLK_PCI_LPBACK R531 2 1 22_0402_5% CLK_PCI0 H49 C16 USB_OC3#
<14> CLK_PCI_LPBACK CLKOUT_PCI0 OC3# / GPIO42
CLK_PCI_LPC R529 1 2 22_0402_5% CLK_PCI1 H43 L16 USB_OC4#
<40> CLK_PCI_LPC CLKOUT_PCI1 OC4# / GPIO43
PAD T30 @ CLK_PCI2 J48 A16 USB_OC5#
PAD T10 @ CLK_PCI3 CLKOUT_PCI2 OC5# / GPIO9 SMIB
K42 CLKOUT_PCI3 OC6# / GPIO10 D14 SMIB
1 1 PAD T12 @ CLK_PCI4 H40 C14 USB_OC7#
CLKOUT_PCI4 OC7# / GPIO14
C633 C632
22P_0402_50V8J @ @ 22P_0402_50V8J COUGARPOINT_FCBGA989~D
2 2 HM65@
For RF request
+3VS +3VALW
5
5
DIS@ R296
VCC
VCC
PLT_RST# 1 100_0402_1% PLT_RST# 1
IN1 IN1
OUT 4 1 2 PLTRST_VGA# <22> OUT 4 PLT_RST_BUF# <35,37,40>
DGPU_HOLD_RST# 2 2
GND
GND
IN2 IN2
1
1
R02 modify for ESD R297

DIS@ R281 U15 100K_0402_5%
3
3
DIS@ U14 100K_0402_5% MC74VHC1G08DFT2G_SC70-5
MC74VHC1G08DFT2G_SC70-5
2
2
A
1 2 PLT_RST# R02 modify A
C2067 0.1U_0402_16V4Z
1 2 PLTRST_VGA#
C2068 0.1U_0402_16V4Z
1 2 PLTRST_VGA#
C2075 0.1U_0402_16V4Z
SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1
HDA_SYNC PH(PLL =+1.5VS)

GPIO28
On-Die PLL Voltage Regulator
This signal has a weak internal pull up
H：On-Die voltage regulator enable
* L：On-Die PLL Voltage Regulator disable
+3VALW_PCH +3VS
1 2
R768 PCH_GPIO68 R771 1 2 10K_0402_5%
D 4.7K_0402_5% D
EC_KBRST# R279 1 2 10K_0402_5%
1 2 PCH_GPIO28
@
R272
1K_0402_5% U33F
PCH_GPIO0 T7 C40 PCH_GPIO68

BMBUSY# / GPIO0 TACH4 / GPIO68
WL_EN# A42 B41 PCH_GPIO69
<39> WL_EN# TACH1 / GPIO1 TACH5 / GPIO69
Deep S4,S5 wake event signal +3VS
PCH_GPIO6 H36 C41 PCH_GPIO70
RTC alarm,Power BTN,GPIO27 TACH2 / GPIO6 TACH6 / GPIO70
PCH_GPIO27 (Have internal Pull-High) <40> EC_SCI# EC_SCI# E38 TACH3 / GPIO7 TACH7 / GPIO71 A40 PCH_GPIO71 PCH_GPIO71 <31>
2
Deep S4,S5 wake event signal EC_SMI# C10 R278
<40> EC_SMI# GPIO8
No use PD to GND Check list1.0 P.70 10K_0402_5%
PCH_GPIO12 C4 LAN_PHY_PWR_CTRL / GPIO12
1
<40> EC_LID_OUT# EC_LID_OUT# G2 P4
GPIO15 A20GATE GATEA20 <40>
R661 1 2 10K_0402_5% PCH_GPIO27
AU16 PCH_PECI_R 1 2 PECI CPU-EC
CPU/MISC
PECI H_PECI <5,40>
<37> MSATA_DET# MSATA_DET# U2 0_0402_5% @ R239
SATA4GP / GPIO16 EC_KBRST# CTRL+ALT+DEL
RCIN# P5 EC_KBRST# <40>
GPIO
DGPU_PWROK D40 TACH0 / GPIO17 PROCPWRGD AY11 H_CPUPWRGD <5> non CPU power ok
PCH_GPIO22 T5 SCLOCK / GPIO22 THRMTRIP# AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP# H_THRMTRIP# <5> 130 degree
+3VS R627 390_0402_5% shut sown
PCH_GPIO24 E8 T14
GPIO24 / MEM_LED INIT3_3V#
R623 1 @ 2 10K_0402_5% OPTIMUS_EN# PCH_GPIO27 E16 INIT3_3V Checklist1.0 P.59
C GPIO27 C
PCH_GPIO28 P8 GPIO28
This signal has weak internal
R639 1 DIS@ 2 10K_0402_5%
BT_ON# 2 @ NC_1 AH8 PU, can't pull low,leave NC
<37,39,40> BT_ON# 1 K1 STP_PCI# / GPIO34
R2122 0_0402_5% AK11
NC_2
K4 GPIO35
NC_3 AH10
PCH_GPIO36 V8 SATA2GP / GPIO36
TS_VSS1~4
GPIO38 WWAN_OFF# M5
NC_4 AK10 PD to GND
WWAN_OFF# SATA3GP / GPIO37
OPTIMUS_EN# NC_5 P37
OPTIMUS_EN# N2 SLOAD / GPIO38
* OPTIMUS 0 PCH_GPIO39 M3 SDATAOUT0 / GPIO39
DIS Only 1 PCH_GPIO48 V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15 +3VS +3VS
<37,40> WL_OFF# WL_OFF# 2 R2123 1@ V3 BG48
0_0402_5% SATA5GP / GPIO49 VSS_NCTF_16
1
PCH_GPIO57 D6 BH3
GPIO57 VSS_NCTF_17 R554 R548
+3VS +3VS BH47 10K_0402_5% 10K_0402_5%
VSS_NCTF_18 @
R277 1 @ 2 200K_0402_5%WWAN_OFF# A4 BJ4
2
VSS_NCTF_1 VSS_NCTF_19
1
PCH_GPIO69 PCH_GPIO70
R276 1 2 10K_0402_5% PCH_GPIO0 +3VS R2053 A44 BJ44
2
10K_0402_5%
R546 1 2 10K_0402_5% WL_EN# A45 BJ45 R553 R549
2
DIS@ 10K_0402_5% 10K_0402_5%
NCTF
2
10K_0402_5%
R2054
R191 1 2 10K_0402_5% PCH_GPIO6 DGPU_PWROK A46 BJ46 @

+3VSDGPU VSS_NCTF_4 VSS_NCTF_22
1
6
R641 1 2 10K_0402_5% MSATA_DET# 1 DIS@ A5 BJ5

B DIS@ Q2001A C2050 VSS_NCTF_5 VSS_NCTF_23 B
1
2
100K_0402_5%
R2055
DMN66D0LDW-7_SOT363-6
DIS@
R290 1 2 10K_0402_5% PCH_GPIO22 0.1U_0402_16V4Z A6 BJ6

2
2
R649 1 2 10K_0402_5% PCH_GPIO39 B3 VSS_NCTF_7 VSS_NCTF_25 C2 Project ID GPIO69 GPIO70
3
R291 1 @ 2 200K_0402_5% PCH_GPIO36 DIS@ B47 C48 Q5WE0 0 0

1
Q2001B
R619 1 NOAC@ 2 10K_0402_5% BT_ON#

1
5 BD1 VSS_NCTF_9 VSS_NCTF_27 D1 Q7YE0 0 0
R292 1 2 10K_0402_5% PCH_GPIO48 DIS@ BD49 D49 *Q5Wxx-QC 1 0
4
1U_0402_6.3V6K
C2051
R274 1 NOAC@ 2 10K_0402_5% WL_OFF#

2
BE1 VSS_NCTF_11 VSS_NCTF_29 E1 x 1 1
BE49 VSS_NCTF_12 VSS_NCTF_30 E49
BF1 VSS_NCTF_13 VSS_NCTF_31 F1
BF49 VSS_NCTF_14 VSS_NCTF_32 F49
+3VALW_PCH HM65@
GPIO24 Unmultiplexed
NOTE: GPIO24 configuration
R262 1 2 10K_0402_5% PCH_GPIO24 register bits are not cleared by
R620
CF9h reset event.
1 2 10K_0402_5% PCH_GPIO12
R672 1 2 1K_0402_5% EC_LID_OUT# CRB1.0 PH10K to +3VALW

R263 1 2 10K_0402_5% PCH_GPIO57
A A
GPIO36/GPIO37 is Strap functionality

that requires internal pull down to be sampled at rising PWROK.
When uses as SATA2GP/SATA3GP for mechanical presence detect
R911 PCH_GPIO36
-use a external pull up 150K-200K ohm to Vcc3_3
1 2 10K_0402_5%
When used as GP input
R912 1 2 10K_0402_5% WWAN_OFF# -ensure GPI is not driven high during strap sampling window
When Unused as GPIO or SATA*GP Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title
-use 8.2K-10K pull-down THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A7912
check list page 47 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom C
4019ID
5 4 3 2 1
5 4 3 2 1
+VCCADAC should be powered up during S0

system state.Note that Thermal Sensor +3VS
shares the same power supply rail with DAC L31
4.7UH_LQM18FN4R7M00D_20%
U33G POWER +VCCADAC

1 1 1 1 1
2 1
0.01U_0402_16V7K
C2063
0.01U_0402_16V7K
C640
.1U_0402_16V7K
C644
10U_0603_6.3V6M
C629
+1.05VS_VTT C2064
1700mA 22U_0805_6.3V6M
+1.05VS_VTT AA23 U48
VCCCORE[1] VCCADAC 2 2 2 2 2
AC23 VCCCORE[2] 1mA
10U_0603_6.3V6M
C334
1U_0402_6.3V6K
C346
1U_0402_6.3V6K
C319
1U_0402_6.3V6K
C320
CRT
1 1 1 1 AD21 VCCCORE[3]
AD23 VCCCORE[4] VSSADAC U47 R02 Modify
VCC CORE
AF21 VCCCORE[5]
AF23 VCCCORE[6]
D 2 2 2 2 R149 +3VS D
AG21 VCCCORE[7]
AG23 0_0603_5%
VCCCORE[8] +VCCA_LVDS 1
AG24 VCCCORE[9] VCCALVDS AK36 2
AG26 VCCCORE[10] 1mA
AG27 VCCCORE[11] VSSALVDS AK37
AG29 VCCCORE[12]
AJ23
LVDS
VCCCORE[13]
AJ26 VCCCORE[14] VCCTX_LVDS[1] AM37
AJ27 +1.8VS
VCCCORE[15] L16
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38
AJ31 0.1UH_MLF1608DR10KT_10%_1608
+1.05VS_VTT VCCCORE[17] +VCCTX_LVDS
40mA VCCTX_LVDS[3] AP36 2 1
1 1 1 0.1uH inductor, 200mA
AP37 C300
VCCTX_LVDS[4] C305 C310 22U_0805_6.3V6M
AN19 VCCIO[28] 0.01U_0402_16V7K 0.01U_0402_16V7K
2 2 2
PAD T48 @ +VCCAPLLEXP BJ22 VCCAPLLEXP 228mA +3VS
PCH Power Rail Table
On-Die PLL Voltage Regulator V33
HVCMOS
VCC3_3[6]
H：On-Die PLL voltage regulator enable AN16 VCCIO[15] I/O Buffer Voltage S0 Iccmax
1 Voltage Rail Voltage Current(A)
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 AN17 VCCIO[16]
V34 C313
,VCCAPLLSATA VCC3_3[7]
.1U_0402_16V7K V_PROC_IO 1.05 0.001 Processor I/F
AN21
3711mA 2
R02 Modify
VCCIO[17]
AN26 VCCIO[18]
V5REF 5 0.001 PCH Core Well Reference Voltage
Internal PLL and VRM(+1.5VS)
AN27 AT16 +VCCAFDI_VRM
VCCIO[19] VCCVRM[3]
V5REF_Sus 5 0.001 Suspend Well Reference Voltag
+1.05VS_VTT AP21 +1.05VS_VTT
C VCCIO[20] C
AP23 VCCIO[21] VCCDMI[1] AT20 Vcc3_3 3.3 0.266 I/O Buffer Voltage
1 DMI buffer logic
DMI
Display DAC Analog Power. This power is
10U_0603_6.3V6M
C314
1U_0402_6.3V6K
C353
1U_0402_6.3V6K
C325
1U_0402_6.3V6K
C342
1U_0402_6.3V6K
C332
1 1 1 1 1 AP24
VCCIO
VCCIO[22]
47mA C344 VccADAC 3.3 0.001 supplied by the core well.
AP26 AB36 1U_0402_6.3V6K
VCCIO[23] VCCIO[1] 2
2 2 2 2 2 1 place near AT20
AT24 VCCIO[24]
VccADPLLA 1.05 0.08 Display PLL A power
C308
2
1U_0402_6.3V6K Core Well I/O Buffer
AN33 VCCIO[25] 190mA place near AB36 VccADPLLB 1.05 0.08 Display PLL B power
AN34 VCCIO[26] VCCPNAND[1] AG16
+3VS +1.8VS VccCore 1.05 1.3 Internal Logic Voltage
NAND / SPI
BH29 VCC3_3[3] VCCPNAND[2] AG17
1 1 VccDFTERM should PH +1.8VS or +3VS VccDMI 1.05 0.042 DMI Buffer Voltage
C322 C349
R02 Modify .1U_0402_16V7K
VCCPNAND[3] AJ16 .1U_0402_16V7K
VccIO 1.05 2.925 Core Well I/O buffers
2 +VCCAFDI_VRM 2 R02 Modify
AP16 VCCVRM[2]
AJ17 1.05 V Supply for Intel R Management
VCCPNAND[4]
VccASW 1.05 1.01 Engine and Integrated LAN
PAD T19 @ +1.05VS_VCCAPLL_FDI BG6 VCCFDIPLL
+1.05VS_VTT +3VS VccSPI 3.3 0.02 3.3 V Supply for SPI Controller Logic
AP17 VCCIO[27]
FDI
VCCSPI V1
Trace 20mil 10mA 1 VccDSW 3.3 0.003 3.3v supply for Deep S4/S5 well
1 AU20 VCCDMI[2]
For SPI control logi
C703
C347 1U_0402_6.3V6K VccpNAND 1.8 0.19 1.8V power supply for DF_TVS
B COUGARPOINT_FCBGA989~D 2 B
2 1U_0402_6.3V6K HM65@
VccRTC 3.3 6 uA Battery Voltage
GPIO28 VccSus3_3 3.3 0.266 Suspend Well I/O Buffer Voltage

H：On-Die PLL voltage regulator enable High Definition Audio Controller Suspend
VccSusHDA 3.3 / 1.5 0.01 Voltage
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 +VCCAFDI_VRM
+1.5VS 1.8 V Internal PLL and VRMs (1.8 V for
VccVRM 1.8 / 1.5 0.16 Desktop)
R257 2 1 0_0603_5% +VCCAFDI_VRM
VccCLKDMI 1.05 0.02 DMI Clock Buffer Voltage
VCCVRM==>1.5V FOR MOBILE
VCCVRM==>1.8V FOR DESKTOP VccSSC 1.05 0.095 Spread Modulators Power Supply
VCCVRM = 160mA detal waiting for newest spec
配HDA_SYNC PH(PLL =+1.5VS) VccDIFFCLKN 1.05 0.055 Differential Clock Buffers Power Supply
Analog power supply for LVDS (Mobile
VccALVDS 3.3 0.001 Only)
Analog power supply for LVDS (Mobile
VccTX_LVDS 1.8 0.06 Only)
A A

SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1
+3VS
L14 VCC3_3 = 266mA detal waiting for newest spec

10UH_LB2012T100MR_20%
1 2
1
+3VS_VCC_CLKF33
1
+3VALW_PCH Have internal VRM U33J POWER +1.05VS_VTT VCCDMI = 42mA detal waiting for newest spec
10U_0603_6.3V6M
C277
1U_0402_6.3V6K
C304
1 AD49 VCCACLK VCCIO[29] N26
Not support Deep S4,S5 1
2 2
connect to +3VALW C340
VCCIO[30] P26
.1U_0402_16V7K T16 C321
D 2 R02 Modify VCCDSW3_3
VCCIO[31] P28
2
1U_0402_6.3V6K +5VALW TO +5VALW_PCH(PCH AUX Power) D
PAD T17 @ +PCH_VCCDSW V12

1mA T27
DCPSUSBYP VCCIO[32]
+5VALW +5VALW_PCH
VCCIO[33] T29
suppied by internal +3VS_VCC_CLKF33 T38 VCC3_3[5]
+3VALW_PCH
1.05V VR must NC @
T23 1 R197 2
PAD T11 @ +VCCAPLL_CPY_PCH VCCSUS3_3[7] 0_0603_5%
BH23 VCCAPLLDMI2 95mA
20K_0402_1%
0.1U_0402_16V4Z
VCCSUS3_3[8] T24 1 1
2
GPIO28 +1.05VS_VTT AL29 VCCIO[14]
C330 C333
R2090
V23 .1U_0402_16V7K .1U_0402_16V7K 3 1 1
D
USB
VCCSUS3_3[9]
H：On-Die PLL voltage regulator enable Place near Place near
C2062
Q2006
2 2
PAD T13 @ +VCCSUS1 AL24 V24 P24 P24 AO3413L_SOT23-3
G
DCPSUS[3] VCCSUS3_3[10]
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
1
2
P24
,VCCAPLLSATA VCCSUS3_3[6]
AA19 +1.05VS_VTT R02 Modify
VCCASW[1]
903mA VCCIO[34] T26
+1.05VS_VTT AA21 PCH_PWR_EN#
VCCASW[2] <35,44> PCH_PWR_EN#
AA24 M26 +PCH_V5REF_SUS
1 1
VCCASW[3] 1mA V5REF_SUS
R03 Modify
22U_0805_6.3V6M
C336
22U_0805_6.3V6M
C335
Clock and Miscellaneous

AA26 VCCASW[4]
AN23 +VCCA_USBSUS @ T14 PAD
DCPSUS[4] +3VALW_PCH suppied by internal
AA27 VCCASW[5]
+1.05VS_VTT 2 2
L12
VCCSUS3_3[1] AN24 1.05V VR Must NC
10UH_LB2012T100MR_20% AA29
+1.05VS_VCCA_A_DPL VCCASW[6]
1 2
AA31 VCCASW[7] +5VALW_PCH +3VALW_PCH
1U_0402_6.3V6K
C296
1
AC26 P34 +PCH_V5REF_RUN
1 VCCASW[8] 1mA V5REF
2
+ +3VALW_PCH
330U_D2_2V_Y
C278
C C
1 1 1
2
1U_0402_6.3V6K
C326
1U_0402_6.3V6K
C327
1U_0402_6.3V6K
C316
R808 AC27
0_0603_5% VCCASW[9] +3V_VCCPSUS R202 D8
N20 1
PCI/GPIO/LPC
2 2 VCCSUS3_3[2] C352 100_0402_1% CH751H-40PT_SOD323-2
AC29 VCCASW[10]
@ 2 2 2 1U_0402_6.3V6K
N22
1
VCCSUS3_3[3]
AC31
1
VCCASW[11] 2 +PCH_V5REF_SUS
VCCSUS3_3[4] P20
1 2 +1.05VS_VCCA_B_DPL AD29 1
L11 VCCASW[12] +3VS
VCCSUS3_3[5] P22
1U_0402_6.3V6K
C295
10UH_LB2012T100MR_20% AD31 C318

VCCASW[13] 0.1U_0603_25V7K
1 2
W21 VCCASW[14] VCC3_3[1] AA16
SGA00001700 1 1 1
C704 C343 C309
220U 2.5V M B2 2
W23 VCCASW[15] VCC3_3[8] W16
.1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K
ESR 35mohm@100Khz W24 T34 Place near Place near Place near
VCCASW[16] VCC3_3[4] 2 2 2
AJ2 AA16,W16 T34 +5VS +3VS
W26 VCCASW[17]
W29 R02 Modify
VCCASW[18]
2
W31 AJ2 +1.05VS_VTT R148 D7
VCCASW[19] VCC3_3[2] 100_0402_1% CH751H-40PT_SOD323-2
W33 VCCASW[20]
AF13
1
VCCIO[5] +PCH_V5REF_RUN
1
+VCCRTCEXT N16 1
DCPRTC C350
1 VCCIO[12] AH13
C348 1U_0402_6.3V6K C244
.1U_0402_16V7K +VCCAFDI_VRM 2 1U_0603_10V6K
Y49 VCCVRM[4] VCCIO[13] AH14
2
R02 Modify 2
B
AF14 GPIO28 B
VCCIO[6]
+1.05VS_VCCA_A_DPL BD47 80mA On-Die PLL Voltage Regulator
SATA
VCCADPLLA +VCCSATAPLL @ T62 PAD H：On-Die PLL voltage regulator enable
VCCAPLLSATA AK1
+1.05VS_VCCA_B_DPL BF47 +VCCAFDI_VRM
+1.05VS_VTT VCCADPLLB 80mA VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
AF11 +VCCAFDI_VRM
AF17
VCCVRM[1] ,VCCAPLLSATA
VCCIO[7] +1.05VS_VTT
AF33 VCCIO[8]
AF34 VCCIO[9] 55mA VCCIO[2] AC16
1 C311 1 C312 1 C317 AG34 VCCIO[11]
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K AC17 1
VCCIO[3] C351
Place Place Place AG33 AD17 1U_0402_6.3V6K
2 2 2 VCCIO[10] VCCIO[4]
near AF17 near AG33 near AF33, 130mA 2
AF34,AG34 +1.05VS_VTT
1 2 C354 +VCCSST V16 DCPSST
.1U_0402_16V7K
R02 Modify
PAD T15 @ +1.05VM_VCCSUS T17 T21
DCPSUS[1] VCCASW[22]
suppied by internal V19
MISC
DCPSUS[2]
1.05V VR Must NC
+1.05VS_VTT V21
VCCASW[23]
1mA
CPU
BJ8 V_PROC_IO
VCCASW[21] T19
1 1 1
+RTCVCC +3VALW_PCH
4.7U_0603_6.3V6K
C700
.1U_0402_16V7K
C694
.1U_0402_16V7K
C693
RTC
A22 10mAVCCSUSHDA P32

HDA
2 2 2 VCCRTC
Need +3VALW and 0.1U close PCH
1U_0402_6.3V6K
C331
.1U_0402_16V7K
C685
.1U_0402_16V7K
C687
1 1 1 1
COUGARPOINT_FCBGA989~D C315
A HM65@ 0.1U_0402_16V4Z A
2 2 2 2
Close P32
Place R02 Modify
near BJ8
R02 Modify
2011/06/02 2012/06/02 Title
Issued Date Deciphered Date SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1
U33I
AY4 VSS[159] VSS[259] H46

AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46
D U33H D
B15 VSS[164] VSS[264] K7
H5 VSS[0] B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
AA17 VSS[1] VSS[80] AK38 B27 VSS[167] VSS[267] L20
AB11 VSS[6] VSS[85] AL16 F45 VSS[172] VSS[272] M12
AB14 VSS[7] VSS[86] AL17 BB12 VSS[173] VSS[273] P16
AB39 VSS[8] VSS[87] AL19 BB16 VSS[174] VSS[274] M18
AC19 VSS[13] VSS[92] AL27 BB30 VSS[179] VSS[279] M34
AC33 VSS[17] VSS[96] AL48 BC14 VSS[183] VSS[283] M46
AC34 VSS[18] VSS[97] AM11 BC18 VSS[184] VSS[284] M8
AC48 VSS[19] VSS[98] AM14 BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD19 VSS[24] VSS[103] AM46 BC36 VSS[190] VSS[290] T33
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
AD33 VSS[28] VSS[107] AN3 BD46 VSS[194] VSS[294] P7
AD34 VSS[29] VSS[108] AN31 BD5 VSS[195] VSS[295] R2
C C
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 VSS[31] VSS[110] AP19 BE26 VSS[197] VSS[297] T12
AD38 VSS[32] VSS[111] AP28 BE40 VSS[198] VSS[298] T31
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
AD46 VSS[39] VSS[118] AP8 BF26 VSS[205] VSS[305] V11
AD8 VSS[40] VSS[119] AR2 BF28 VSS[206] VSS[306] V17
AE2 VSS[41] VSS[120] AR48 BD3 VSS[207] VSS[307] V26
AE3 VSS[42] VSS[121] AT11 BF30 VSS[208] VSS[308] V27
AF10 VSS[43] VSS[122] AT13 BF38 VSS[209] VSS[309] V29
AF12 VSS[44] VSS[123] AT18 BF40 VSS[210] VSS[310] V31
AD14 VSS[45] VSS[124] AT22 BF8 VSS[211] VSS[311] V36
AD16 VSS[46] VSS[125] AT26 BG17 VSS[212] VSS[312] V39
AF16 VSS[47] VSS[126] AT28 BG21 VSS[213] VSS[313] V43
AF19 VSS[48] VSS[127] AT30 BG33 VSS[214] VSS[314] V7
AF24 VSS[49] VSS[128] AT32 BG44 VSS[215] VSS[315] W17
AF26 VSS[50] VSS[129] AT34 BG8 VSS[216] VSS[316] W19
AF27 VSS[51] VSS[130] AT39 BH11 VSS[217] VSS[317] W2
AF38 VSS[54] VSS[133] AT7 BH19 VSS[220] VSS[320] Y12
AF4 VSS[55] VSS[134] AU24 H10 VSS[221] VSS[321] Y38
AF42 VSS[56] VSS[135] AU30 BH27 VSS[222] VSS[322] Y4
AF46 VSS[57] VSS[136] AV16 BH31 VSS[223] VSS[323] Y42
AF8 VSS[60] VSS[139] AV30 BH39 VSS[226] VSS[328] BG29
AG19 VSS[61] VSS[140] AV38 BH43 VSS[227] VSS[329] N24
B B
AG2 VSS[62] VSS[141] AV4 BH7 VSS[228] VSS[330] AJ3
AG31 VSS[63] VSS[142] AV43 D3 VSS[229] VSS[331] AD47
AG48 VSS[64] VSS[143] AV8 D12 VSS[230] VSS[333] B43
AH11 VSS[65] VSS[144] AW14 D16 VSS[231] VSS[334] BE10
AH3 VSS[66] VSS[145] AW18 D18 VSS[232] VSS[335] BG41
AH36 VSS[67] VSS[146] AW2 D22 VSS[233] VSS[337] G14
AH39 VSS[68] VSS[147] AW22 D24 VSS[234] VSS[338] H16
AH40 VSS[69] VSS[148] AW26 D26 VSS[235] VSS[340] T36
AH7 VSS[72] VSS[151] AW34 D34 VSS[238] VSS[344] C22
AJ19 VSS[73] VSS[152] AW36 D38 VSS[239] VSS[345] AP13
AJ21 VSS[74] VSS[153] AW40 D42 VSS[240] VSS[346] M14
AJ24 VSS[75] VSS[154] AW48 D8 VSS[241] VSS[347] AP3
AJ33 VSS[76] VSS[155] AV11 E18 VSS[242] VSS[348] AP1
AJ34 VSS[77] VSS[156] AY12 E26 VSS[243] VSS[349] BE16
AK12 VSS[78] VSS[157] AY22 G18 VSS[244] VSS[350] BC16
AK3 VSS[79] VSS[158] AY28 G20 VSS[245] VSS[351] BG28
G26 VSS[246] VSS[352] BJ28
COUGARPOINT_FCBGA989~D G28
HM65@ VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
H30 VSS[255]
H32 VSS[256]
H34 VSS[257]
F3 VSS[258]
A A
HM65@

SCHEMATIC,MB A7912
5 4 3 2 1
A B C D E
04/06 : Add 6bit VID Function.

U1001A for GS4, the boot voltage is 0.975V +3VSDGPU
GPIO I/O USAGE
AN12 Part 1 of 7 for GV4, the boot voltage is 0.85V
<4> PEG_HTX_C_GRX_P0 PEX_RX0
<4> PEG_HTX_C_GRX_N0 AM12 P6 VID_4 GPIO0 O GPU_VID4
PEX_RX0_N GPIO0
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
<4> PEG_HTX_C_GRX_P1 AN14 M3 VID_3
PEX_RX1 GPIO1
<4> PEG_HTX_C_GRX_N1 AM14 PEX_RX1_N GPIO2 L6
<4> PEG_HTX_C_GRX_P2 AP14 PEX_RX2 GPIO3 P5 GPIO1 O GPU_VID3
<4> PEG_HTX_C_GRX_N2 AP15 PEX_RX2_N GPIO4 P7
@ 1
GM@ 1
GL@ 1
GL@ 1
GS@ 1
2 DIS@ 1
<4> PEG_HTX_C_GRX_P3 AN15 L7 VID_1
PEX_RX3 GPIO5 VID_2 +3VSDGPU
<4> PEG_HTX_C_GRX_N3 AM15 PEX_RX3_N GPIO6 M7 GPIO2 O LCD_BL_PWM
<4> PEG_HTX_C_GRX_P4 AN17 PEX_RX4 GPIO7 N8
<4> PEG_HTX_C_GRX_N4 AM17 M1 GPIO8 R1000 2 DIS@ 1 10K_0402_5%
PEX_RX4_N GPIO8
R1017
R1018
R1019
R1020
R1021
R1022
<4> PEG_HTX_C_GRX_P5 AP17 M2 GPIO9 R1001 2 DIS@ 1 10K_0402_5% GPU_GPIO16 R1025 1 @ 2 0_0402_5% GPIO3 O LCD_VCC
2
1 PEX_RX5 GPIO9 1
<4> PEG_HTX_C_GRX_N5 AP18 PEX_RX5_N GPIO10 L1
<4> PEG_HTX_C_GRX_P6 AN18 M5 VID_0
GPIO
PEX_RX6 GPIO11 GPU_ACIN VID_0 R1026 DIS@ 0_0402_5%
<4> PEG_HTX_C_GRX_N6 AM18 PEX_RX6_N GPIO12 N3
VID_5
GPU_ACIN <40>
VID_1 R1027
1
DIS@
2
0_0402_5%
GPU_VID0 <53> GPIO4 O LCD_BLEN
<4> PEG_HTX_C_GRX_P7 AN20 PEX_RX7 GPIO13 M4 1 2 GPU_VID1 <53>
<4> PEG_HTX_C_GRX_N7 AM20 N4 VID_2 R1028 1 DIS@ 2 0_0402_5%
PEX_RX7_N GPIO14 GPU_VID2 <53>
<4> PEG_HTX_C_GRX_P8 AP20 P2 VID_3 R1030 1 DIS@ 2 0_0402_5% GPIO5 O GPU_VID1
PEX_RX8 GPIO15 GPU_VID3 <53>
<4> PEG_HTX_C_GRX_N8 AP21 R8 GPU_GPIO16 VID_4 R1031 1 DIS@ 2 0_0402_5%
PEX_RX8_N GPIO16 GPU_VID4 <53>
<4> PEG_HTX_C_GRX_P9 AN21 M6 VID_5 R1032 1 DIS@ 2 0_0402_5%
PEX_RX9 GPIO17 GPU_VID5 <53>
<4> PEG_HTX_C_GRX_N9 AM21 PEX_RX9_N GPIO18 R1 GPIO6 O GPU_VID2
R1033
R1034
R1035
R1036
R1037
R1038
<4> PEG_HTX_C_GRX_P10 AN23 PEX_RX10 GPIO19 P3
2 DIS@ 1
2 GSGL@ 1
GS@ 1
GS@ 1
GL@ 1
@ 1
<4> PEG_HTX_C_GRX_N10 AM23 PEX_RX10_N GPIO20 P4
<4> PEG_HTX_C_GRX_P11 AP23 PEX_RX11 GPIO21 P1 GPIO7 O 3D Vision
<4> PEG_HTX_C_GRX_N11 AP24 PEX_RX11_N
AN24 GPIO20,21
<4> PEG_HTX_C_GRX_P12 PEX_RX12 N13P/M = NC;
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
<4> PEG_HTX_C_GRX_N12 AM24 GPIO8 I/O OVERT
2
PEX_RX12_N N13P-PES = GPIO20,21
<4> PEG_HTX_C_GRX_P13 AN26 PEX_RX13
<4> PEG_HTX_C_GRX_N13 AM26 PEX_RX13_N
<4> PEG_HTX_C_GRX_P14 AP26 PEX_RX14 GPIO9 I/O ALERT
<4> PEG_HTX_C_GRX_N14 AP27 PEX_RX14_N
<4> PEG_HTX_C_GRX_P15 AN27 PEX_RX15 DACA_RED AK9
<4> PEG_HTX_C_GRX_N15 AM27 PEX_RX15_N DACA_GREEN AL10 GPIO10 O MEM_VREF_CTL
DACA_BLUE AL9
DACs
<4> PEG_GTX_HRX_P0 AK14 PEX_TX0 MEM_VDD_CTL(PES)
<4> PEG_GTX_HRX_N0 AJ14 PEX_TX0_N DACA_HSYNC AM9 GPIO11 O
<4> PEG_GTX_HRX_P1 AH14 PEX_TX1 DACA_VSYNC AN9
R1019 R1020 R1037
GPU_VID0(Real N13P)
<4> PEG_GTX_HRX_N1 AG14 PEX_TX1_N
<4> PEG_GTX_HRX_P2 AK15 PEX_TX2
AJ15 AG10 R1003 2 DIS@ 1 10K_0402_5% GPIO12 I PWR_LEVEL
<4> PEG_GTX_HRX_N2 PEX_TX2_N DACA_VDD
PCI EXPRESS
<4> PEG_GTX_HRX_P3 AL16 PEX_TX3 DACA_VREF AP9
<4> PEG_GTX_HRX_N3 AK16 PEX_TX3_N DACA_RSET AP8
<4> PEG_GTX_HRX_P4 AK17 PEX_TX4 GPIO13 O THERM_LOAD_STEP_DOWN
2 10K_0402_5% 10K_0402_5% 10K_0402_5% 2
<4> PEG_GTX_HRX_N4 AJ17 PEX_TX4_N
AH17 GM@ GM@ GM@
<4> PEG_GTX_HRX_P5 PEX_TX5
<4> PEG_GTX_HRX_N5 AG17 PEX_TX5_N SD028100280 SD028100280 SD028100280 GPIO14 I HPD_AB
<4> PEG_GTX_HRX_N6 AJ18 PEX_TX6_N
<4> PEG_GTX_HRX_P7 AL19 PEX_TX7 VGA_DDC_CLK
GPIO15 I HPD_C
<4> PEG_GTX_HRX_N7 AK19 PEX_TX7_N I2CA_SCL R4
AK20 R5 VGA_DDC_DATA
<4> PEG_GTX_HRX_P8 PEX_TX8 I2CA_SDA
<4> PEG_GTX_HRX_N8 AJ20 PEX_TX8_N GPIO16 O THERM_LOAD_STEP_UP
AH20 R7 I2CB_SCL
<4> PEG_GTX_HRX_P9 PEX_TX9 I2CB_SCL
AG20 R6 I2CB_SDA
<4> PEG_GTX_HRX_N9 PEX_TX9_N I2CB_SDA
GPIO17 I HPD_D
I2C
AJ21 R2 VGA_LCD_CLK
<4> PEG_GTX_HRX_N10 PEX_TX10_N I2CC_SCL
AL22 R3 VGA_LCD_DATA
<4> PEG_GTX_HRX_P11 PEX_TX11 I2CC_SDA
<4> PEG_GTX_HRX_N11 AK22 PEX_TX11_N +3VSDGPU
add ADPS function GPIO18 I HPD_E
AK23 T4 I2CS_SCL
<4> PEG_GTX_HRX_P12
AJ23
PEX_TX12 I2CS_SCL
T3 I2CS_SDA under GPU follow Acer Request
<4> PEG_GTX_HRX_N12 PEX_TX12_N I2CS_SDA
<4> PEG_GTX_HRX_P13 AH23 PEX_TX13 close to ball : AD8 GPIO19 I HPD_F
2
<4> PEG_GTX_HRX_N13 AG23 PEX_TX13_N
AJ24 GPIO8 1 6 GPIO20 Reserved
<4> PEG_GTX_HRX_N14 PEX_TX14_N GPU_OVERT <40>
AL25 C1000 1 2
<4> PEG_GTX_HRX_P15 PEX_TX15
AK25 DIS@ 0.1U_0402_16V4Z DMN66D0LDW-7_SOT363-6
<4> PEG_GTX_HRX_N15 PEX_TX15_N DIS@ Q2005A GPIO21 Reserved
PLLVDD AD8 +PLLVDD
AJ11 PEX_WAKE_N
AE8 +GPU_PLLVDD +3VSDGPU SLI_RASTER_SYNC
SP_PLLVDD GPIO22 I/O
+3VSDGPU 1 DIS@ 2 <14> CLK_PEG_VGA AL13 PEX_REFCLK
R1014 10K_0402_5% AK13 AD7
<14> CLK_PEG_VGA# PEX_REFCLK_N VID_PLLVDD
5
0.1U_0402_16V4Z
0.1U_0402_16V4Z
GPIO23 O SLI_SWAPRDY
CLK
<14> PEG_CLKREQ# AK12 PEX_CLKREQ_N
DIS@ C1001
DIS@ C1002
1 1
PEX_TSTCLK_OUT+ AJ26 H3 XTALIN GPIO9 4 3
3 PEX_TSTCLK_OUT XTAL_IN GPU_THERMAL_ALERT# <40> 3
2 1 PEX_TSTCLK_OUT- AK26 H2 XTALOUT GPIO24
R1015 DIS@ 200_0402_1% PEX_TSTCLK_OUT_N XTAL_OUT DMN66D0LDW-7_SOT363-6
2 2
<17> PLTRST_VGA# AJ12 PEX_RST_N XTAL_OUTBUFF J4 XTAL_OUTBUFF Q2005B DIS@ R02 Modify
2 1 PEX_TREMP AP29 H1 XTAL_SSIN
R1016 DIS@ 2.49K_0402_1% PEX_TERMP XTAL_SSIN
U1001
under GPU
N13P-PES-A1_FCBGA908 close to ball : AE8,AD7
GF108@
N13P-GS-A2 FCBGA 908P

GS@
SA000051880
U1001
XTALOUT @ XTALIN +3VSDGPU
R1024 1M_0402_5%
L1003 +1.05VSDGPU +3VSDGPU
2
BLM18PG330SN1_2P 27MHZ 10PF 7V27000050

+PLLVDD 1 2 3 1 VGA_DDC_CLK R1004 1 DIS@ 2 2.2K_0402_5%
3 1
22U_0805_6.3V6M
DIS@ I2CS_SCL 1 6 VGA_DDC_DATA R1005 1 DIS@ 2 2.2K_0402_5% N13P-GL-A1 FCBGA 908P

GND GND EC_SMB_CK2 <14,40>
DIS@ C1061
1 1 1 GL@
Y1000 DMN66D0LDW-7_SOT363-6 I2CB_SCL R1006 1 DIS@ 2 2.2K_0402_5% SA000051A00
DIS@ C1008 DIS@ 4 2 DIS@ C1009
Q1000ADIS@ I2CB_SDA R1007 1 DIS@ 2 2.2K_0402_5%
10P_0402_50V8J 10P_0402_50V8J U1001
2 2 2 +3VSDGPU VGA_LCD_CLK R1008 1 DIS@ 2 2.2K_0402_5%
VGA_LCD_DATA R1009 1 DIS@ 2 2.2K_0402_5%
5
R02 modify
33ohm (ESR:0.05) I2CS_SCL R1010 1 DIS@ 2 2.2K_0402_5%
I2CS_SDA 4 3 I2CS_SDA R1011 1 DIS@ 2 2.2K_0402_5%
EC_SMB_DA2 <14,40>
L1001 N13M-GS FCBGA 908P GPU
4 BLM18PG181SN1D_2P DMN66D0LDW-7_SOT363-6 GM@ 4
+GPU_PLLVDD
150mA
1 2 Q1000BDIS@ SA000057F20
22U_0805_6.3V6M
22U_0805_6.3V6M
4.7U_0603_6.3V6K
DIS@ XTAL_OUTBUFF XTAL_SSIN

DIS@ C1005
DIS@ C1006
DIS@ C1007
1 1 1
1
N13X Design Guide page173

= 180R@100MHz(ESR=0.2) R1023
10K_0402_5% R1029
2 2 2 DIS@ 10K_0402_5%
DIS@ Security Classification Compal Secret Data Compal Electronics, Inc.
2
SCHEMATIC,MB A7912
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019ID
A B C D E
A
VRAM Interface <27> MDA[15..0]
<27> MDA[31..16]
MDA[15..0]
MDA[31..16] <29> MDC[15..0]

MDC[15..0]
MDC[31..16]
MDA[47..32] <29> MDC[31..16]
<28> MDA[47..32] MDC[47..32]
MDA[63..48] <30> MDC[47..32]
<28> MDA[63..48] MDC[63..48]
<30> MDC[63..48]
U1001B U1001C
CMDA[30..0] <27,28> CMDC[30..0] <29,30>
Part 2 of 7 Part 3 of 7
MDA0 L28 U30 CMDA0 MDC0 G9 D13 CMDC0
MDA1 FBA_D0 FBA_CMD0 CMDA1 MDC1 FBB_D0 FBB_CMD0 CMDC1
M29 FBA_D1 FBA_CMD1 T31 E9 FBB_D1 FBB_CMD1 E14
MDA2 L29 U29 CMDA2 MDC2 G8 F14 CMDC2
M28 FBA_D3 FBA_CMD3 R34 F9 FBB_D3 FBB_CMD3 A12
MDA4 N31 R33 CMDA4 MDC4 F11 B12 CMDC4
P29 FBA_D5 FBA_CMD5 U32 G11 FBB_D5 FBB_CMD5 C14
MDA6 R29 U33 CMDA6 MDC6 F12 B14 CMDC6
P28 FBA_D7 FBA_CMD7 U28 G12 FBB_D7 FBB_CMD7 G15
MDA8 J28 V28 CMDA8 MDC8 G6 F15 CMDC8
H29 FBA_D9 FBA_CMD9 V29 F5 FBB_D9 FBB_CMD9 E15
MDA10 J29 V30 CMDA10 MDC10 E6 D15 CMDC10
H28 FBA_D11 FBA_CMD11 U34 F6 FBB_D11 FBB_CMD11 A14
MDA12 G29 U31 CMDA12 MDC12 F4 D14 CMDC12
E31 FBA_D13 FBA_CMD13 V34 G4 FBB_D13 FBB_CMD13 A15
MDA14 E32 V33 CMDA14 MDC14 E2 B15 CMDC14
F30 FBA_D15 FBA_CMD15 Y32 F3 FBB_D15 FBB_CMD15 C17
MDA16 C34 AA31 CMDA16 MDC16 C2 D18 CMDC16
D32 FBA_D17 FBA_CMD17 AA29 D4 FBB_D17 FBB_CMD17 E18
MDA18 B33 AA28 CMDA18 MDC18 D3 F18 CMDC18
C33 FBA_D19 FBA_CMD19 AC34 C1 FBB_D19 FBB_CMD19 A20
MDA20 F33 AC33 CMDA20 MDC20 B3 B20 CMDC20
F32 FBA_D21 FBA_CMD21 AA32 C4 FBB_D21 FBB_CMD21 C18
MDA22 H33 AA33 CMDA22 MDC22 B5 B18 CMDC22
H32 FBA_D23 FBA_CMD23 Y28 C5 FBB_D23 FBB_CMD23 G18
MEMORY INTERFACE
MDA24 P34 Y29 CMDA24 MDC24 A11 G17 CMDC24
P32 W31 C11 F17
MEMORY INTERFACE B
P31 FBA_D26 FBA_CMD26 Y30 D11 FBB_D26 FBB_CMD26 D16
MDA27 P33 AA34 CMDA27 MDC27 B11 A18 CMDC27
L31 FBA_D28 FBA_CMD28 Y31 D8 FBB_D28 FBB_CMD28 D17
MDA29 L34 Y34 CMDA29 MDC29 A8 A17 CMDC29
L32 FBA_D30 FBA_CMD30 Y33 C8 FBB_D30 FBB_CMD30 B17
MDA31 L33 V31 MDC31 B8 E17
MDA32 FBA_D31 FBA_CMD31 MDC32 FBB_D31 FBB_CMD31
AG28 FBA_D32 F24 FBB_D32
MDA33 AF29 MDC33 G23
MDA34 FBA_D33 MDC34 FBB_D33
AG29 FBA_D34 E24 FBB_D34
MDA35 AF28 R32 MDC35 G24 C12
MDA36 FBA_D35 FBA_CMD_RFU0 MDC36 FBB_D35 FBB_CMD_RFU0
AD30 FBA_D36 FBA_CMD_RFU1 AC32 D21 FBB_D36 FBB_CMD_RFU1 C20
MDA37 AD29 MDC37 E21
MDA38 FBA_D37 +1.5VSDGPU MDC38 FBB_D37 +1.5VSDGPU
AC29 FBA_D38 G21 FBB_D38
MDA39 AD28 MDC39 F21
FBA_D39 FBB_D39
A
MDA40 AJ29 R28 FBA_DEBUG0 R1039 2 DIS@ 1 60.4_0402_1% MDC40 G27 G14 FBB_DEBUG0 R1040 2 DIS@ 1 60.4_0402_1%
MDA41 FBA_D40 FBA_DEBUG0 FBB_D40 FBB_DEBUG0
AK29 FBA_D41 FBA_DEBUG1 AC28 FBA_DEBUG1 R1041 2 DIS@ 1 60.4_0402_1% MDC41 D27 FBB_D41 FBB_DEBUG1 G20 FBB_DEBUG1 R1042 2 DIS@ 1 60.4_0402_1%
MDA42 AJ30 MDC42 G26
AK28 FBA_D43 E27 FBB_D43
1 MDA44 AM29 MDC44 E29 1

AM31 FBA_D45 FBA_CLK0 R30 CLKA0 <27> F29 FBB_D45 FBB_CLK0 D12 CLKC0 <29>
MDA46 AN29 R31 CLKA0# <27> MDC46 E30 E12 CLKC0# <29>
MDA47 FBA_D46 FBA_CLK0_N MDC47 FBB_D46 FBB_CLK0_N
AM30 FBA_D47 FBA_CLK1 AB31 CLKA1 <28> D30 FBB_D47 FBB_CLK1 E20 CLKC1 <30>
MDA48 AN31 AC31 CLKA1# <28> MDC48 A32 F20 CLKC1# <30>
MDA49 FBA_D48 FBA_CLK1_N MDC49 FBB_D48 FBB_CLK1_N
AN32 FBA_D49 C31 FBB_D49
MDA50 AP30 MDC50 C32
AP32 FBA_D51 B32 FBB_D51
MDA52 AM33 K31 MDC52 D29 F8
MDA53 FBA_D52 FBA_WCK01 MDC53 FBB_D52 FBB_WCK01
AL31 FBA_D53 FBA_WCK01_N L30 A29 FBB_D53 FBB_WCK01_N E8
MDA54 AK33 H34 MDC54 C29 A5
AK32 FBA_D55 FBA_WCK23_N J34 B29 FBB_D55 FBB_WCK23_N A6
MDA56 AD34 AG30 MDC56 B21 D24
AD32 FBA_D57 FBA_WCK45_N AG31 C23 FBB_D57 FBB_WCK45_N D25
MDA58 AC30 AJ34 MDC58 A21 B27
AD33 FBA_D59 FBA_WCK67_N AK34 C21 FBB_D59 FBB_WCK67_N C27
MDA60 AF31 MDC60 B24
AG34 FBA_D61 C24 FBB_D61
MDA62 AG32 MDC62 B26
AG33 FBA_D63 FBA_WCKB01 J30 C26 FBB_D63 FBB_WCKB01 D6
<27> DQMA[3..0] FBA_WCKB01_N J31 <29> DQMC[3..0] FBB_WCKB01_N D7
DQMA0 P30 J32 DQMC0 E11 C6
DQMA1 FBA_DQM0 FBA_WCKB23 DQMC1 FBB_DQM0 FBB_WCKB23
F31 FBA_DQM1 FBA_WCKB23_N J33 E3 FBB_DQM1 FBB_WCKB23_N B6
DQMA2 F34 AH31 DQMC2 A3 F26
<28> DQMA[7..4] M32 FBA_DQM3 FBA_WCKB45_N AJ31 <30> DQMC[7..4] C9 FBB_DQM3 FBB_WCKB45_N E26
DQMA4 AD31 AJ32 DQMC4 F23 A26
AL29 FBA_DQM5 FBA_WCKB67_N AJ33 F27 FBB_DQM5 FBB_WCKB67_N A27
DQMA6 AM32 DQMC6 C30
DQMA7 FBA_DQM6 DQMC7 FBB_DQM6
AF34 FBA_DQM7 A24 FBB_DQM7
<27> DQSA[3..0] <29> DQSC[3..0]
DQSA0 M31 E1 DQSC0 D10
DQSA1 FBA_DQS_WP0 FB_CLAMP DQSC1 FBB_DQS_WP0
G31 FBA_DQS_WP1 D5 FBB_DQS_WP1
DQSA2 E33 Under GPU +FB_PLLAVDD DQSC2 C3
DQSA3 FBA_DQS_WP2 DQSC3 FBB_DQS_WP2
M33 B9
<28> DQSA[7..4]
DQSA4 AE31
FBA_DQS_WP3
K27
close to ball : K27 <30> DQSC[7..4]
DQSC4 E23
FBB_DQS_WP3
H17 +FB_PLLAVDD
DQSA5 FBA_DQS_WP4 FB_DLL_AVDD C1010 DIS@ DQSC5 FBB_DQS_WP4 FBB_PLL_AVDD
AK30 FBA_DQS_WP5 100mA E28 FBB_DQS_WP5 100mA
DQSA6 AN33 1 2 DQSC6 B30
FBA_DQS_WP6 FBB_DQS_WP6
0.1U_0402_16V4Z
DQSA7 AF33 0.1U_0402_16V4Z DQSC7 A23
FBA_DQS_WP7 FBB_DQS_WP7
N13P-PES=1.05V
DIS@ C1012
U27 +FB_PLLAVDD 1
<27> DQSA#[3..0] FBA_PLL_AVDD <29> DQSC#[3..0]
DQSA#0 M30 DQSC#0 D9
DQSA#1 H30
FBA_DQS_RN0
1 2 DQSC#1 E4
FBB_DQS_RN0 N13P/M=1.0V
DQSA#2 FBA_DQS_RN1 C1011 0.1U_0402_16V4Z DQSC#2 FBB_DQS_RN1
E34 FBA_DQS_RN2 B2 FBB_DQS_RN2
DQSA#3 DIS@ DQSC#3 2 +1.05VSDGPU DIS@ +FB_PLLAVDD
<28> DQSA#[7..4] M34 FBA_DQS_RN3 FB_VREF H26 <30> DQSC#[7..4] A9 FBB_DQS_RN3
DQSA#4 AF30 DQSC#4 D22 L1000 300mA
FBA_DQS_RN4 FBB_DQS_RN4
DQSA#5 AK31 FBA_DQS_RN5 Under GPU DQSC#5 D28 FBB_DQS_RN5 2 1 +FB_PLLAVDD
CV48 Under GPU
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
DQSA#6 AM34 DQSC#6 A30 BLM18PG330SN1_2P
FBA_DQS_RN6 close to ball : U27 FBB_DQS_RN6 33ohm (ESR:0.05)
DIS@ C1015
DIS@ C1014
DIS@ C1013
DQSA#7 AF32 DQSC#7 B23
FBA_DQS_RN7 FBB_DQS_RN7 close to ball : H17 1 1 1
2 2 2
N13P-PES-A1_FCBGA908 N13P-PES-A1_FCBGA908
GF108@ GF108@

SCHEMATIC,MB A7912
A
5 4 3 2 1
STRAP2 STRAP1 R1057

R1045
MULTI LEVEL STRAPS

+3VSDGPU +3VSDGPU
Straps
45.3K_0402_1%
D U1001D 10K_0402_1% GL@ D
GM@ SD034453280
2 GSGL@ 1
GM@ 1
GL@ 1
@ 1
GS@ 1
GS@ 1
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
45.3K_0402_1%
34.8K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
Part 4 of 7 SD034100280
@
AM6 IFPA_TXC
AN6 IFPA_TXC_N NC P8 ROM_SO
AP3 IFPA_TXD0 NC AC6 R1049 STRAP3 R1059
R1043
R1044
R1045
R1046
R1047
R1048
R1049
R1050
AN3 AJ28
2
IFPA_TXD0_N NC
AN5 IFPA_TXD1 NC AJ4
AM5 AJ5 STRAP0 ROM_SI
IFPA_TXD1_N NC STRAP1 STRAP3 ROM_SO
AL6 IFPA_TXD2 NC AL11
AK6 C15 STRAP2 STRAP4 ROM_SCLK
IFPA_TXD2_N NC
NC
AJ6 D19 10K_0402_1% 10K_0402_1%
IFPA_TXD3 NC GM@ GM@
AH6 IFPA_TXD3_N NC D20
GM@ 1
GS@ 1
GS@ 1
2 X76@ 1
GL@ 1
10K_0402_1%
15K_0402_5%
10K_0402_5%
15K_0402_5%
4.99K_0402_1%
4.99K_0402_1%
45.3K_0402_1%
34.8K_0402_1%
NC D23 SD034100280 SD034100280
R04 modify
R1057 GS@
R1059 GS@
R1054 GL@
NC D26
AJ9 IFPB_TXC NC H31 ROM_SCLK STRAP4
AH9 T8 R1055 R1052
IFPB_TXC_N NC
R1051
R1058
R1052
R1053
R1055
AP6 V32
2
IFPB_TXD4 NC
AP5 IFPB_TXD4_N
AM7 IFPB_TXD5
AL7 IFPB_TXD5_N
AN8 R04 modify
IFPB_TXD6 10K_0402_1% 10K_0402_1%
AM8 IFPB_TXD6_N
AK8 GM@ GM@
IFPB_TXD7
AL8 IFPB_TXD7_N SD034100280 SD034100280
L4 VCCSENSE_VGA_R 1 DIS@ 2
VDD_SENSE R1056 0_0402_5% VCCSENSE_VGA <53>
AK1 IFPC_L0
AJ1 IFPC_L0_N
AJ3 L5 VSSSENSE_VGA_R 1 DIS@ 2
IFPC_L1 GND_SENSE VSSSENSE_VGA <53>
AJ2 R1060 0_0402_5%
IFPC_L1_N
AH3 IFPC_L2
C C
AH4 IFPC_L2_N
AG5 IFPC_L3
AG4 IFPC_L3_N
TEST DIS@
AM1 AK11 R1061 1 2 10K_0402_5%
IFPD_L0 TESTMODE
AM2 IFPD_L0_N DIS@
AM3 AM10 JTAG_TCK R1062 1 2 10K_0402_5%
IFPD_L1 JTAG_TCK JTAG_TDI @
AM4 IFPD_L1_N JTAG_TDI AM11 PAD T2
AL3 AP12 JTAG_TDO PAD T3 @
IFPD_L2 JTAG_TDO JTAG_TMS @
AL4 IFPD_L2_N JTAG_TMS AP11 PAD T4
AK4 AN11 JTAG_TRST PAD T5 @
IFPD_L3 JTAG_TRST_N
AK5 IFPD_L3_N
LVDS/TMDS
1 DIS@ 2
AD2
R1063 10K_0402_5%
For N13P-GS(QS) strap table (PN:SA000051880)
IFPE_L0
AD3 IFPE_L0_N GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
AD1
AC1
IFPE_L1 SERIAL +3VSDGPU
IFPE_L1_N ROM_CS# R1064 1 DIS@
AC2 IFPE_L2 ROM_CS_N H6 2 10K_0402_5%
AC3 H4 ROM_SCLK 128M* 16* 8 Hynix R R R R R R R R
IFPE_L2_N ROM_SCLK ROM_SI N13P-GS 900 MHz 2GB SA00003YO20 PU 45K PD 5K PD 15K PD 5K PD 45K PD 35K PU 10K PU 5K
AC4 IFPE_L3 ROM_SI H5
AC5 H7 ROM_SO
IFPE_L3_N ROM_SO
N13P-GS 900 MHz 64M* 16* 8 Hynix R R R R R R R R
AE3 1GB SA000041S40 PU 45K PD 5K PD 15K PD 5K PD 45K PD 15K PU 10K PU 5K
IFPF_L0
AE4 IFPF_L0_N
AF4 IFPF_L1
AF5
AD4
IFPF_L1_N GENERAL For N13P-GL(QS) strap table (PN:SA000051A00)
IFPF_L2 R1065
AD5 IFPF_L2_N BUFRST_N L2 1 @ 2 10K_0402_5%
AG1 GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
B IFPF_L3 R1066 1 DIS@ B
AF1 IFPF_L3_N CEC L3 2 10K_0402_5% +3VSDGPU
J1 MULTI_STRAP_REF0_GND 1 GSGL@ 2 N13P-GS 900 MHz 128M* 16* 8 Hynix R R R R R R
MULTI_STRAP_REF0_GND R1067 40.2K_0402_1% 2GB SA00003YO20 PU 45K PD 45K PU 10K n/a n/a PD 35K PD 10K PD 15K
AG3 IFPC_AUX_I2CW_SCL
AG2 IFPC_AUX_I2CW_SDA_N
J2 STRAP0
R04 modify N13P-GS 900 MHz 64M* 16* 8 Hynix R R R R R R
STRAP0 STRAP1 1GB SA000041S40 PU 45K PD 45K PU 10K n/a n/a PD 15K PD 10K PD 15K
STRAP1 J7
AK3 J6 STRAP2
IFPD_AUX_I2CX_SCL STRAP2 STRAP3
AK2 IFPD_AUX_I2CX_SDA_N STRAP3 J5
STRAP4 J3 STRAP4
For N13M-GS(QS) strap table (PN:SA000051A00)
AB3 IFPE_AUX_I2CY_SCL
AB4 GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
IFPE_AUX_I2CY_SDA_N
THERMDP K3
THERMDN K4
AF3 N13M-GS 900 MHz 128M* 16* 8 Hynix R R R R R R R R
IFPF_AUX_I2CZ_SCL 2GB SA00003YO20 PD 10K PU 10K PU 10K PD 10K PD 10K PD 10K PU 10K PD 10K
AF2 IFPF_AUX_I2CZ_SDA_N
N13P-PES-A1_FCBGA908
GF108@
A A

SCHEMATIC,MB A7912
Custom C
5 4 3 2 1
5 4 3 2 1
+3VS to +3VSDGPU for GPU

+3VS +3VSDGPU
3 1
Q33
2 DIS@
DIS@
4.7U_0603_6.3V6K
C602
AP2301GN-HF_SOT23-3
2
+3VALW
D 1 D
3VSdelay_gate
DIS@ 100mil(1.5A)
R515
100K_0402_5% Modify R03
2
2
2
DIS@ DIS@
4.7U_0603_6.3V6K
C590
1 DIS@ 2 R511
R519 470_0603_5%
4.7K_0402_5% 1
6 1
3
DIS@
DIS@ R514 DIS@ Q35A
1K_0402_5%
DMN66D0LDW-7_SOT363-6 1 DIS@ DMN66D0LDW-7_SOT363-6
<14,17,44,51,53> VGA_ON 1 2 5 C612
Q35B 0.1U_0603_25V7K 23VSdelay_gate
1
4
DIS@ 2
1
C603
0.1U_0603_25V7K 2
Near GPU Under GPU +1.05VSDGPU
Design guide no define
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
DIS@ C1016
DIS@ C1017
DIS@ C1018
DIS@ C1019
DIS@ C1020
C1021
C1022
U1001E 1 1 1 1 1 1 1
Under GPU
DIS@
DIS@
+1.5VSDGPU Part 5 of 7
7200mA 2 2 2 2 2 2 2
AA27 FBVDDQ_0 PEX_IOVDD_0 AG19
1U_0402_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AA30 FBVDDQ_1 PEX_IOVDD_1 AG21

DIS@ C1023
DIS@ C1024
DIS@ C1025
DIS@ C1026
DIS@ C1027
DIS@ C1037
C C
1 1 1 1 1 1 AB27 FBVDDQ_2 PEX_IOVDD_2 AG22
AB33 FBVDDQ_3 PEX_IOVDD_3 AG24
AC27 FBVDDQ_4 PEX_IOVDD_4 AH21 2700 mA
AD27 FBVDDQ_5 PEX_IOVDD_5 AH25
2 2 2 2 2 2 Near GPU Under GPU +1.05VSDGPU
AE27 FBVDDQ_6 total 2700mA
AF27
AG27
FBVDDQ_7
AG13
Design guide page.68
FBVDDQ_8 PEX_IOVDDQ_0
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
B13 FBVDDQ_9 PEX_IOVDDQ_1 AG15
Under GPU
DIS@ C1028
DIS@ C1034
DIS@ C1029
DIS@ C1035
DIS@ C1030
DIS@ C1031
DIS@ C1036
B16 FBVDDQ_10 PEX_IOVDDQ_2 AG16 1 1 1 1 1 1 1
B19 FBVDDQ_11 PEX_IOVDDQ_3 AG18
E13 FBVDDQ_12 PEX_IOVDDQ_4 AG25
1U_0402_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
E16 FBVDDQ_13 PEX_IOVDDQ_5 AH15

2 2 2 2 2 2 2
DIS@ C1038
DIS@ C1039
DIS@ C1032
DIS@ C1033
DIS@ C1040
DIS@ C1041
1 1 1 1 1 1 E19 FBVDDQ_14 PEX_IOVDDQ_6 AH18

H10 FBVDDQ_15 PEX_IOVDDQ_7 AH26
H11 FBVDDQ_16 PEX_IOVDDQ_8 AH27
H12 FBVDDQ_17 PEX_IOVDDQ_9 AJ27
2 2 2 2 2 2 +3VSDGPU
H13 FBVDDQ_18 PEX_IOVDDQ_10 AK27
H14 AL27 Near GPU
POWER
FBVDDQ_19 PEX_IOVDDQ_11
H15 FBVDDQ_20 PEX_IOVDDQ_12 AM28
1U_0402_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
H16 FBVDDQ_21 PEX_IOVDDQ_13 AN28
Near GPU
DIS@ C1042
DIS@ C1043
DIS@ C1044
H18 FBVDDQ_22 1 1 1
H19 FBVDDQ_23
H20 FBVDDQ_24 150mA 370mA
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
H21 AH12 +PEX_PLL_HVDD

FBVDDQ_25 PEX_PLL_HVDD 2 2 2
DIS@ C1045
DIS@ C1046
DIS@ C1047
DIS@ C1048
1 1 1 1 H22 FBVDDQ_26
H23 DIS@ 1 2
FBVDDQ_27 C1049 0.1U_0402_16V4Z
H24 FBVDDQ_28
H8 FBVDDQ_29 PEX_SVDD_3V3 AG12
2 2 2 2
H9 FBVDDQ_30
L27 DIS@ 1 2 +1.05VSDGPU L1002 L1002
FBVDDQ_31
M27 FBVDDQ_32
C1050 0.1U_0402_16V4Z 150mA Under GPU Near GPU
N27 AG26 +PEX_PLLVDD 2 1
FBVDDQ_33 PEX_PLLVDD
1U_0402_6.3V6K
B B
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
P27 L1002
FBVDDQ_34
DIS@ C1051
DIS@ C1052
DIS@ C1053
R27 1 1 1 BLM18PG121SN1D_0603
FBVDDQ_35
T27 FBVDDQ_36 120mA GL@N13P
T30 J8 +VDD33 0_0603_5% 0_0603_5%
T33
FBVDDQ_37 VDD33_0
K8
Reference Sch = 300R@100MHz GM@ GS@
FBVDDQ_38 VDD33_1 2 2 2 Design Guide page69 沒定義
V27 FBVDDQ_39 VDD33_2 L8 Design guide no define SD013000080 SD013000080
W27 FBVDDQ_40 VDD33_3 M8
W30 FBVDDQ_41
W33 FBVDDQ_42
Y27 FBVDDQ_43
AH8 +IFPAB_PLLVDD R1130 1 DIS@ 2 10K_0402_5%
IFPAB_PLLVDD R1069 1 @
IFPAB_RSET AJ8 2 1K_0402_5%
+1.5VSDGPU AG8 +IFPAB_IOVDD R1131 1 DIS@ 2 10K_0402_5%

IFPA_IOVDD +3VSDGPU
IFPB_IOVDD AG9
2 1 FB_VDDQ_SENSE F1 Under GPU (one per pin)
R1070 DIS@ 10_0402_5% FB_VDDQ_SENSE
2 DIS@ 1
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
AF7 +IFPC_PLLVDD R1071 1 DIS@ 2 10K_0402_5%
IFPC_PLLVDD R1068
DIS@ C1054
DIS@ C1055
DIS@ C1056
DIS@ C1057
DIS@ C1058
DIS@ C1059
DIS@ C1060
2 1 FB_GND_SENSE F2 AF8 R1073 1 @ 2 1K_0402_5% 1 1 1 1 1 1 1
+1.5VSDGPU R1072 DIS@ 10_0402_5% FB_GND_SENSE IFPC_RSET 0_0603_5%
AF6 +IFPC_IOVDD R1074 1 DIS@ 2 10K_0402_5%
DIS@ 1 FB_CAL_PD_VDDQ J27 IFPC_IOVDD
2 FB_CAL_PD_VDDQ
R1075 40.2_0402_1% 2 2 2 2 2 2 2
AG7 +IFPD_PLLVDD R1076 1 DIS@ 2 10K_0402_5%
IFPD_PLLVDD
2 DIS@ 1 FB_CAL_PU_GND H27
FB_CAL_PU_GND IFPD_RSET AN2 R1078 1 @ 2 1K_0402_5%
R1077 42.2_0402_1%
AG6 +IFPD_IOVDD R1079 1 DIS@ 2 10K_0402_5%
IFPD_IOVDD
2 DIS@ 1 FB_CAL_TERM_GND H25
FB_CAL_TERM_GND
R1080 51.1_0402_1%
AB8 +IFPEF_PLLVDD R1081 1 DIS@ 2 10K_0402_5%
IFPEF_PLVDD R1082 1 @ 2 1K_0402_5%
IFPEF_RSET AD6
A +IFPEF_IOVDD R1083 1 DIS@ A
IFPE_IOVDD AC7 2 10K_0402_5%
IFPF_IOVDD AC8
N13P-PES-A1_FCBGA908
GF108@ Security Classification Compal Secret Data Compal Electronics, Inc.
SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1
U1001F
Part 6 of 7
A2 GND_0 GND_100 D2
D D
AA17 GND_1 GND_101 D31
AA18 GND_2 GND_102 D33
AA20 GND_3 GND_103 E10
AA22 GND_4 GND_104 E22
AB12 E25 +VGA_CORE U1001G +VGA_CORE
GND_5 GND_105
AB14 GND_6 GND_106 E5
AB16 GND_7 GND_107 E7
AB19 F28 50A Part 7 of 7 V17
GND_8 GND_108 VDD_56
AB2 GND_9 GND_109 F7 AA12 VDD_0 VDD_57 V18
AB21 GND_10 GND_110 G10 AA14 VDD_1 VDD_58 V20
A33 GND_11 GND_111 G13 AA16 VDD_2 VDD_59 V22
AB23 GND_12 GND_112 G16 AA19 VDD_3 VDD_60 W12
AB32 GND_15 GND_115 G22 AB13 VDD_6 VDD_63 W19
AC13 GND_18 GND_118 G3 AB18 VDD_9 VDD_66 Y13
AC18 GND_21 GND_121 G33 AC12 VDD_12 VDD_69 Y18
AA13 GND_22 GND_122 G5 AC14 VDD_13 VDD_70 Y20
AC20 GND_23 GND_123 G7 AC16 VDD_14 VDD_71 Y22
AC22 GND_24 GND_124 K2 AC19 VDD_15
AE2 GND_25 GND_125 K28 AC21 VDD_16
AE28 GND_26 GND_126 K30 AC23 VDD_17 XVDD_1 U1
AE30 GND_27 GND_127 K32 M12 VDD_18 XVDD_2 U2
POWER
AE7 GND_31 GND_131 M13 M21 VDD_22 XVDD_6 U6
AH10 GND_32 GND_132 M15 M23 VDD_23 XVDD_7 U7
C C
AA15 GND_33 GND_133 M17 N13 VDD_24 XVDD_8 U8
AH13 GND_34 GND_134 M18 N15 VDD_25
AH16 GND_35 GND_135 M20 N17 VDD_26
AH19 GND_36 GND_136 M22 N18 VDD_27 XVDD_9 V1
AH2 GND_37 GND_137 N12 N20 VDD_28 XVDD_10 V2
AH22 GND_38 GND_138 N14 N22 VDD_29 XVDD_11 V3
AH24 GND_39 GND_139 N16 P12 VDD_30 XVDD_12 V4
AH30 GND_42 GND GND_142 N21 P19 VDD_33 XVDD_15 V7
AH33 GND_44 GND_144 N28 P23 VDD_35
AH5 GND_45 GND_145 N30 R13 VDD_36
AH7 GND_46 GND_146 N32 R15 VDD_37 XVDD_17 W2
AJ7 GND_47 GND_147 N33 R17 VDD_38 XVDD_18 W3
AK10 GND_48 GND_148 N5 R18 VDD_39 XVDD_19 W4
AK7 GND_49 GND_149 N7 R20 VDD_40 XVDD_20 W5
AL12 GND_50 GND_150 P13 R22 VDD_41 XVDD_21 W7
AL14 GND_51 GND_151 P15 T12 VDD_42 XVDD_22 W8
AL15 GND_52 GND_152 P17 T14 VDD_43
AL17 GND_53 GND_153 P18 T16 VDD_44
AL18 GND_54 GND_154 P20 T19 VDD_45 XVDD_23 Y1
AL2 GND_55 GND_155 P22 T21 VDD_46 XVDD_24 Y2
AL20 GND_56 GND_156 R12 T23 VDD_47 XVDD_25 Y3
AL21 GND_57 GND_157 R14 U13 VDD_48 XVDD_26 Y4
AL30 GND_62 GND_162 T13 U22 VDD_53
AL32 GND_63 GND_163 T15 V13 VDD_54
AL33 GND_64 GND_164 T17 V15 VDD_55 XVDD_31 AA1
B B
AL5 GND_65 GND_165 T18 XVDD_32 AA2
AM13 GND_66 GND_166 T2 XVDD_33 AA3
AM22 GND_69 GND_169 AG11 XVDD_36 AA6
AN1 GND_71 GND_171 T32 XVDD_38 AA8
AN10 GND_72 GND_172 T5
AN13 GND_73 GND_173 T7
AN16 GND_74 GND_174 U12
AN19 GND_75 GND_175 U14
AN22 U16 N13P-PES-A1_FCBGA908
GND_76 GND_176 GF108@
AN25 GND_77 GND_177 U19
AN30 GND_78 GND_178 U21
AN34 GND_79 GND_179 U23
AN4 GND_80 GND_180 V12
AN7 GND_81 GND_181 V14
AP2 GND_82 GND_182 V16
AP33 GND_83 GND_183 V19
B1 GND_84 GND_184 V21
B10 GND_85 GND_185 V23
B22 GND_86 GND_186 W13
B25 GND_87 GND_187 W15
B28 GND_88 GND_188 W17
B31 GND_89 GND_189 W18
B34 GND_90 GND_190 W20
B4 GND_91 GND_191 W22
B7 GND_92 GND_192 W28
C10 GND_93 GND_193 Y12
C13 GND_94 GND_194 Y14
C19 GND_95 GND_195 Y16
C22 GND_96 GND_196 Y19
A A
C25 GND_97 GND_197 Y21
C28 GND_98 GND_198 Y23
C7 GND_99 GND_199 AH11
GND_OPT C16
GND_OPT W32

N13P-PES-A1_FCBGA908 2011/06/02 2012/06/02 Title
GF108@
SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1
VRAM DDR3 chips (1GB) Mode D

Address 0..31 32..63
CMD0 CS0_L#
D 64Mx16 DDR3 *8==>1GB CMD1 D
128Mx16 DDR3 *8==>2GB CMD2 ODT_L

CMD3 CKE
R02 modify CMD4 A14 A14
DQSA[7..0] Swap MDA13 and MDA14 CMD5 RST RST
<23,28> DQSA[7..0]
U1002 X76@ U1003 X76@
<23,28> DQSA#[7..0]
DQSA#[7..0] CMD6 A9 A9
+MEM_VREF0 M8 E3 MDA12 +MEM_VREF1 M8 E3 MDA3
VREFCA DQL0 VREFCA DQL0
<23,28> DQMA[7..0]
DQMA[7..0] H1 VREFDQ DQL1 F7 MDA13 H1 VREFDQ DQL1 F7 MDA4 CMD7 A7 A7
F2 MDA8 F2 MDA2
DQL2 DQL2
<23,28> MDA[63..0]
MDA[63..0] CMDA9 N3 A0 DQL3 F8 MDA15 CMDA9 N3 A0 DQL3 F8 MDA7 CMD8 A2 A2
CMDA11 P7 H3 MDA9 Group1 CMDA11 P7 H3 MDA0 Group0
A1 DQL4 A1 DQL4
<23,28> CMDA[30..0]
CMDA[30..0] CMDA8 P3 A2 DQL5 H8 MDA11 CMDA8 P3 A2 DQL5 H8 MDA5 CMD9 A0 A0
CMDA25 N2 G2 MDA10 CMDA25 N2 G2 MDA1
A3 DQL6 A3 DQL6
CMDA10 P8 A4 DQL7 H7 MDA14 CMDA10 P8 A4 DQL7 H7 MDA6 CMD10 A4 A4
CMDA24 P2 CMDA24 P2
A5 A5
CMDA22 R8 A6
CMDA22 R8 A6 CMD11 A1 A1
+1.5VSDGPU CMDA7 R2 D7 MDA17 CMDA7 R2 D7 MDA27
A7 DQU0 A7 DQU0
CMDA21 T8 A8 DQU1 C3 MDA21 CMDA21 T8 A8 DQU1 C3 MDA29 CMD12 BA0 BA0
CMDA6 R3 C8 MDA18 CMDA6 R3 C8 MDA25
A9 DQU2 A9 DQU2
CMDA29 L7 A10/AP DQU3 C2 MDA23 CMDA29 L7 A10/AP DQU3 C2 MDA30 CMD13 WE* WE*
DIS@ CMDA23 R7 A7 MDA19 Group2 CMDA23 R7 A7 MDA24 Group3
A11 DQU4 A11 DQU4
R1084 CMDA28 N7 A12 DQU5 A2 MDA22 CMDA28 N7 A12 DQU5 A2 MDA28 CMD14 A15 A15
240_0402_1% CMDA20 T3 B8 MDA16 CMDA20 T3 B8 MDA26
A13 DQU6 A13 DQU6
CMDA4 T7 A14 DQU7 A3 MDA20 CMDA4 T7 A14 DQU7 A3 MDA31 CMD15 CAS* CAS*
CMDA14 M7 CMDA14 M7
A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU
+MEM_VREF0 CMD16 CS0_H#
CMD17
DIS@
C C
0.1U_0402_16V4Z
1 CMDA12 M2 B2 CMDA12 M2 B2
DIS@ CMDA27 BA0 VDD CMDA27 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
R1085 CMDA26 M3 BA2 VDD G7 CMDA26 M3 BA2 VDD G7 CMD18 ODT_H
240_0402_1% K2 K2
2 VDD VDD
CMD19 CKE_H
C1069
VDD K8 VDD K8
VDD N1 VDD N1
CLKA0 J7 CK VDD N9 CLKA0 J7 CK VDD N9 CMD20 A13 A13
CLKA0# K7 R1 CLKA0# K7 R1
CK VDD CK VDD
CMDA3 K9 CKE/CKE0 VDD R9
+1.5VSDGPU
+1.5VSDGPU
CMD21 A8 A8
CMD22 A6 A6
+1.5VSDGPU CMDA2 K1 A1 CMDA2 K1 A1
ODT/ODT0 VDDQ ODT/ODT0 VDDQ
CMDA0 L2 CS/CS0 VDDQ A8 CMDA0 L2 CS/CS0 VDDQ A8 CMD23 A11 A11
CMDA30 J3 C1 CMDA30 J3 C1
RAS VDDQ RAS VDDQ
CMDA15 K3 CAS VDDQ C9 CMDA15 K3 CAS VDDQ C9 CMD24 A5 A5
DIS@ CMDA13 L3 D2 CMDA13 L3 D2
WE VDDQ WE VDDQ
R1086 310mAVDDQ E9 VDDQ E9 CMD25 A3 A3
240_0402_1% F1 310mAVDDQ F1
VDDQ
DQSA1 F3 DQSL VDDQ H2 DQSA0 F3 DQSL VDDQ H2 CMD26 BA2 BA2
DQSA2 C7 H9 DQSA3 C7 H9
DQSU VDDQ DQSU VDDQ
+MEM_VREF1 CMD27 BA1 BA1
CMD28 A12 A12
DIS@
0.1U_0402_16V4Z
1 DQMA1 E7 A9 DQMA0 E7 A9
DIS@ DQMA2 DML VSS DQMA3 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3
R1087
VSS E1 VSS E1 CMD29 A10 A10
240_0402_1% G8 G8
2 VSS VSS
CMD30 RAS* RAS*
C1070
DQSA#1 G3 J2 DQSA#0 G3 J2
DQSA#2 DQSL VSS DQSA#3 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 Not Available
VSS M9 VSS M9
CMDA5 VSS P1
CMDA5 VSS P1 LOW HIGH
T2 RESET VSS P9 T2 RESET VSS P9
B B
VSS T1 VSS T1
ZQ0 L8 T9 ZQ1 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
CLKA0 1 2
<23> CLKA0
R1088 DIS@ J1 B1 DIS@ J1 B1 CMDA2 R1091 1 DIS@ 2 10K_0402_5% Command Bit Default Pull-down
NC/ODT1 VSSQ NC/ODT1 VSSQ
1
@ R1089 L1 B9 R1090 L1 B9 CMDA3 R1093 1 DIS@ 2 10K_0402_5%

DIS@ 80.6_0402_1% 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ CMDA5 R1094 1 DIS@ 10K_0402_5%
J9 D1 J9 D1 2 ODTx 10k
R1092 NC/CE1 VSSQ NC/CE1 VSSQ CMDA18 R1095 1 DIS@ 10K_0402_5%
L9 D8 L9 D8 2
2
2
160_0402_1% NCZQ1 VSSQ NCZQ1 VSSQ CMDA19 R1096 1 DIS@ 10K_0402_5% DDR3 CKEx 10k
VSSQ E2 VSSQ E2 2
E8 E8 RST 10k
2
CLKA0# 1 VSSQ VSSQ

<23> CLKA0# 2 F9 F9
R1097 VSSQ VSSQ CS* No Termination
VSSQ G1 VSSQ G1
@ 1 G9 G9
80.6_0402_1% @ VSSQ VSSQ
C1071 96-BALL 96-BALL
0.01U_0402_16V7K SDRAM DDR3 SDRAM DDR3
2 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
NV recommand 0720
+1.5VSDGPU +1.5VSDGPU
Hynix : SA00003YO20 (S IC D3 128M16 H5TQ2G63BFR-11C FBGA)
+1.5VSDGPU
Hynix : SA000041S40 (S IC D3 64MX16 H5TQ1G63DFR-11C FBGA )
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DIS@ C1076
DIS@ C1077
DIS@ C1078
DIS@ C1079
DIS@ C1080
DIS@ C1081
DIS@ C1086
DIS@ C1087
DIS@ C1088
DIS@ C1089
DIS@ C1090
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DIS@ C1072
DIS@ C1073
DIS@ C1074
DIS@ C1075
DIS@ C1082
DIS@ C1083
DIS@ C1084
DIS@ C1085
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
C2086
C2087
C2088
C2089
DIS@ DIS@ DIS@ DIS@

A 2 2 2 2 A
R04 modify for EMI

SCHEMATIC,MB A7912
Custom C
5 4 3 2 1
5 4 3 2 1
VRAM DDR3 chips (1GB) Mode D

Address 0..31 32..63
64Mx16 DDR3 *8==>1GB CMD0 CS0_L#
CMD1
128Mx16 DDR3 *8==>2GB
D
CMD2 ODT_L D
U1004 X76@ U1005 X76@
CMD3 CKE
+MEM_VREF2 M8 E3 MDA39 +MEM_VREF3 M8 E3 MDA45
VREFCA DQL0 VREFCA DQL0
H1 VREFDQ DQL1 F7 MDA35 H1 VREFDQ DQL1 F7 MDA40 CMD4 A14 A14
DQMA[7..0] F2 MDA37 F2 MDA46
<23,27> DQMA[7..0] DQL2 DQL2
CMDA9 N3 A0 DQL3 F8 MDA33 CMDA9 N3 A0 DQL3 F8 MDA41 CMD5 RST RST
CMDA[30..0] CMDA11 P7 H3 MDA38 Group4 CMDA11 P7 H3 MDA47 Group5
<23,27> CMDA[30..0] A1 DQL4 A1 DQL4
DQSA#[7..0] CMDA25 N2 G2 MDA36 CMDA25 N2 G2 MDA44
<23,27> DQSA#[7..0] A3 DQL6 A3 DQL6
DQSA[7..0] CMDA24 P2 CMDA24 P2
<23,27> DQSA[7..0] A5 A5
CMDA22 R8 A6
CMDA22 R8 A6 CMD8 A2 A2
MDA[63..0] CMDA7 R2 D7 MDA61 CMDA7 R2 D7 MDA53
<23,27> MDA[63..0] A7 DQU0 A7 DQU0
CMDA21 T8 A8 DQU1 C3 MDA59 CMDA21 T8 A8 DQU1 C3 MDA49 CMD9 A0 A0
CMDA6 R3 C8 MDA60 CMDA6 R3 C8 MDA55
A9 DQU2 A9 DQU2
CMDA29 L7 A10/AP DQU3 C2 MDA57 CMDA29 L7 A10/AP DQU3 C2 MDA50 CMD10 A4 A4
CMDA23 R7 A7 MDA63 Group7 CMDA23 R7 A7 MDA52 Group6
A11 DQU4 A11 DQU4
CMDA28 N7 A12 DQU5 A2 MDA56 CMDA28 N7 A12 DQU5 A2 MDA48 CMD11 A1 A1
+1.5VSDGPU CMDA20 T3 B8 MDA62 CMDA20 T3 B8 MDA54
A13 DQU6 A13 DQU6
CMDA4 T7 A14 DQU7 A3 MDA58 CMDA4 T7 A14 DQU7 A3 MDA51 CMD12 BA0 BA0
CMDA14 M7 CMDA14 M7
DIS@ CMD13 WE* WE*
R1098
240_0402_1% CMDA12 M2 BA0 VDD B2 CMDA12 M2 BA0 VDD B2 CMD14 A15 A15
CMDA27 N8 D9 CMDA27 N8 D9
BA1 VDD BA1 VDD
CMDA26 M3 BA2 VDD G7 CMDA26 M3 BA2 VDD G7 CMD15 CAS* CAS*
VDD K2 VDD K2
+MEM_VREF2
VDD K8 VDD K8 CMD16 CS0_H#
VDD N1 VDD N1
CMD17
DIS@
0.1U_0402_16V4Z
DIS@ 1 CLKA1 J7 N9 CLKA1 J7 N9

R1099 CLKA1# CK VDD CLKA1# CK VDD
K7 CK VDD R1 K7 CK VDD R1
C 240_0402_1% CMDA19 K9 CKE/CKE0 VDD R9
+1.5VSDGPU
+1.5VSDGPU
CMD18 ODT_H C
2
CMD19 CKE_H
C1091
CMDA18 K1 A1 CMDA18 K1 A1
CMDA16 L2 CS/CS0 VDDQ A8 CMDA16 L2 CS/CS0 VDDQ A8 CMD20 A13 A13
CMDA30 J3 C1 CMDA30 J3 C1
RAS VDDQ RAS VDDQ
CMDA15 K3 CAS VDDQ C9 CMDA15 K3 CAS VDDQ C9 CMD21 A8 A8
CMDA13 L3 D2 CMDA13 L3 D2
WE VDDQ WE VDDQ
310mAVDDQ E9 310mAVDDQ E9 CMD22 A6 A6
+1.5VSDGPU F1 F1
VDDQ VDDQ
DQSA4 F3 DQSL VDDQ H2 DQSA5 F3 DQSL VDDQ H2 CMD23 A11 A11
DQSA7 C7 H9 DQSA6 C7 H9
DQSU VDDQ DQSU VDDQ
DIS@ CMD24 A5 A5
R1100
240_0402_1% DQMA4 E7 DML VSS A9 DQMA5 E7 DML VSS A9 CMD25 A3 A3
DQMA7 D3 B3 DQMA6 D3 B3
DMU VSS DMU VSS
VSS E1 VSS E1 CMD26 BA2 BA2
VSS G8 VSS G8
+MEM_VREF3 DQSA#4 G3 DQSL VSS J2 DQSA#5 G3 DQSL VSS J2 CMD27 BA1 BA1
DQSA#7 B7 J8 DQSA#6 B7 J8
DQSU VSS DQSU VSS
CMD28 A12 A12
DIS@
0.1U_0402_16V4Z
DIS@ 1 M1 M1
R1101 VSS VSS
VSS M9 VSS M9
240_0402_1%
VSS P1 VSS P1 CMD29 A10 A10
CMDA5 T2 P9 CMDA5 T2 P9
2 RESET VSS RESET VSS
CMD30 RAS* RAS*
C1092
VSS T1 VSS T1
ZQ2 L8 T9 ZQ3 L8 T9
Not Available
1
1
DIS@
DIS@ J1 B1 R1103 J1 B1 LOW HIGH
R1102 NC/ODT1 VSSQ 243_0402_1% NC/ODT1 VSSQ
L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9
243_0402_1% J9 D1 J9 D1
CLKA1 1 NC/CE1 VSSQ NC/CE1 VSSQ
<23> CLKA1 2 L9 D8 L9 D8
2
2
B R1104 NCZQ1 VSSQ NCZQ1 VSSQ B
VSSQ E2 VSSQ E2
1
@ E8 E8
DIS@ 80.6_0402_1% VSSQ VSSQ
VSSQ F9 VSSQ F9
R1105 G1 G1
160_0402_1% VSSQ VSSQ
VSSQ G9 VSSQ G9
2
CLKA1# 1 2 96-BALL 96-BALL

<23> CLKA1#
R1106 SDRAM DDR3 SDRAM DDR3
@ 1 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
80.6_0402_1% @
C1093
0.01U_0402_16V7K
2
NV recommand 0720
+1.5VSDGPU +1.5VSDGPU
0.1U_0402_16V4Z
C1098
C1099
C1100
C1101
C1102
C1103
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DIS@ C1108
DIS@ C1109
DIS@ C1110
DIS@ C1111
DIS@ C1112
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2
DIS@ C1094
DIS@ C1095
DIS@ C1096
DIS@ C1097
DIS@ C1104
DIS@ C1105
DIS@ C1106
DIS@ C1107
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1
A A

SCHEMATIC,MB A7912
Custom C
5 4 3 2 1
5 4 3 2 1
Mode D
Address 0..31 32..63
VRAM DDR3 chips (1GB) CMD0 CS0_L#
CMD1
64Mx16 DDR3 *8==>1GB CMD2 ODT_L
D
CMD3 CKE D
128Mx16 DDR3 *8==>2GB
CMD4 A14 A14
CMD5 RST RST
DQSC[7..0]
<23,30> DQSC[7..0]
CMD6 A9 A9
DQSC#[7..0] U1006 X76@ U1007 X76@
<23,30> DQSC#[7..0]
CMD7 A7 A7
DQMC[7..0] +MEM_VREF4 M8 E3 MDC8 +MEM_VREF5 M8 E3 MDC3
<23,30> DQMC[7..0] VREFCA DQL0 VREFCA DQL0
H1 VREFDQ DQL1 F7 MDC12 H1 VREFDQ DQL1 F7 MDC7 CMD8 A2 A2
MDC[63..0] F2 MDC11 F2 MDC1
<23,30> MDC[63..0] DQL2 DQL2
CMDC9 N3 A0 DQL3 F8 MDC13 CMDC9 N3 A0 DQL3 F8 MDC4 CMD9 A0 A0
CMDC[30..0] CMDC11 P7 H3 MDC9 Group1 CMDC11 P7 H3 MDC2 Group0
<23,30> CMDC[30..0] A1 DQL4 A1 DQL4
CMDC8 P3 A2 DQL5 H8 MDC14 CMDC8 P3 A2 DQL5 H8 MDC6 CMD10 A4 A4
CMDC25 N2 G2 MDC10 CMDC25 N2 G2 MDC0
A3 DQL6 A3 DQL6
CMDC24 P2 CMDC24 P2
A5 A5
CMDC22 R8 A6
CMDC22 R8 A6 CMD12 BA0 BA0
+1.5VSDGPU CMDC7 R2 D7 MDC18 CMDC7 R2 D7 MDC26
A7 DQU0 A7 DQU0
CMDC21 T8 A8 DQU1 C3 MDC20 CMDC21 T8 A8 DQU1 C3 MDC31 CMD13 WE* WE*
CMDC6 R3 C8 MDC17 CMDC6 R3 C8 MDC25
A9 DQU2 A9 DQU2
CMDC29 L7 A10/AP DQU3 C2 MDC22 CMDC29 L7 A10/AP DQU3 C2 MDC30 CMD14 A15 A15
GSGL@ CMDC23 R7 A7 MDC16 Group2 CMDC23 R7 A7 MDC27 Group3
A11 DQU4 A11 DQU4
R1107 CMDC28 N7 A12 DQU5 A2 MDC23 CMDC28 N7 A12 DQU5 A2 MDC28 CMD15 CAS* CAS*
240_0402_1% CMDC20 T3 B8 MDC19 CMDC20 T3 B8 MDC24
A13 DQU6 A13 DQU6
CMDC4 T7 A14 DQU7 A3 MDC21 CMDC4 T7 A14 DQU7 A3 MDC29 CMD16 CS0_H#
CMDC14 M7 CMDC14 M7
+MEM_VREF4 CMD17
CMD18 ODT_H
C1113 GSGL@
0.1U_0402_16V4Z
1 CMDC12 M2 B2 CMDC12 M2 B2
GSGL@ CMDC27 BA0 VDD CMDC27 BA0 VDD
C R1108 CMDC26 M3 BA2 VDD G7 CMDC26 M3 BA2 VDD G7 CMD19 CKE_H C
240_0402_1% K2 K2
2 VDD VDD
VDD K8 VDD K8 CMD20 A13 A13
VDD N1 VDD N1
CLKC0 J7 CK VDD N9 CLKC0 J7 CK VDD N9 CMD21 A8 A8
CLKC0# K7 R1 CLKC0# K7 R1
CK VDD CK VDD
CMDC3 K9 CKE/CKE0 VDD R9
+1.5VSDGPU
+1.5VSDGPU
CMD22 A6 A6
CMD23 A11 A11
CMDC2 K1 A1 CMDC2 K1 A1
CMDC0 L2 CS/CS0 VDDQ A8 CMDC0 L2 CS/CS0 VDDQ A8 CMD24 A5 A5
CMDC30 J3 C1 CMDC30 J3 C1
RAS VDDQ RAS VDDQ
CMDC15 K3 CAS VDDQ C9 CMDC15 K3 CAS VDDQ C9 CMD25 A3 A3
+1.5VSDGPU CMDC13 L3 D2 CMDC13 L3 D2
WE VDDQ WE VDDQ
310mAVDDQ E9 VDDQ E9 CMD26 BA2 BA2
VDDQ F1 310mAVDDQ F1
DQSC1 F3 DQSL VDDQ H2 DQSC0 F3 DQSL VDDQ H2 CMD27 BA1 BA1
GSGL@ DQSC2 C7 H9 DQSC3 C7 H9
DQSU VDDQ DQSU VDDQ
R1109 CMD28 A12 A12
240_0402_1%
DQMC1 E7 DML VSS A9 DQMC0 E7 DML VSS A9 CMD29 A10 A10
DQMC2 D3 B3 DQMC3 D3 B3
DMU VSS DMU VSS
+MEM_VREF5
VSS E1 VSS E1 CMD30 RAS* RAS*
VSS G8 VSS G8
C1114 GSGL@
0.1U_0402_16V4Z
1 DQSC#1 G3 J2 DQSC#0 G3 J2 Not Available

GSGL@ DQSC#2 DQSL VSS DQSC#3 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8
R1110 M1 M1 LOW HIGH
240_0402_1% VSS VSS
VSS M9 VSS M9
2
VSS P1 VSS P1
CMDC5 T2 P9 CMDC5 T2 P9
RESET VSS RESET VSS
VSS T1 VSS T1
ZQ4 L8 T9 ZQ5 L8 T9
B ZQ/ZQ0 VSS ZQ/ZQ0 VSS B
1
1
GSGL@ J1 B1 GSGL@ J1 B1 Command Bit Default Pull-down
R1111 NC/ODT1 VSSQ R1112 NC/ODT1 VSSQ CMDC2 R1113 1 GSGL@ 10K_0402_5%
L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9 2
243_0402_1% J9 D1 243_0402_1% J9 D1 CMDC3 R1114 1 GSGL@ 2 10K_0402_5% ODTx 10k
NC/CE1 VSSQ NC/CE1 VSSQ CMDC5 R1115 1 GSGL@ 10K_0402_5%
L9 D8 L9 D8 2
2
2
NCZQ1 VSSQ NCZQ1 VSSQ CMDC18 R1116 1 GSGL@ 10K_0402_5% DDR3 CKEx 10k
VSSQ E2 VSSQ E2 2
E8 E8 CMDC19 R1117 1 GSGL@ 2 10K_0402_5% RST 10k
VSSQ VSSQ
VSSQ F9 VSSQ F9
CS* No Termination
VSSQ G1 VSSQ G1
CLKC0 1 2 G9 G9
<23> CLKC0 VSSQ VSSQ
@R1118
@ R1118
1
80.6_0402_1% 96-BALL 96-BALL

GSGL@ SDRAM DDR3 SDRAM DDR3
R1119 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
160_0402_1%
2
CLKC0# 1 2
<23> CLKC0# +1.5VSDGPU
@R1120
@ R1120
80.6_0402_1% +1.5VSDGPU
1
@
C1115
0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
GSGL@ C1120
GSGL@ C1121
GSGL@ C1122
GSGL@ C1123
GSGL@ C1124
GSGL@ C1125
GSGL@ C1130
GSGL@ C1131
GSGL@ C1132
GSGL@ C1133
GSGL@ C1134
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1U_0402_6.3V6K 1 1 1 1 1
NV recommand 0720
GSGL@ C1116
GSGL@ C1117
GSGL@ C1118
GSGL@ C1119
GSGL@ C1126
GSGL@ C1127
GSGL@ C1128
GSGL@ C1129
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

SCHEMATIC,MB A7912
Custom C
5 4 3 2 1
5 4 3 2 1
VRAM DDR3 chips (1GB)

64Mx16 DDR3 *8==>1GB
D 128Mx16 DDR3 *8==>2GB D
DQMC[7..0]
R02 modify
<23,29> DQMC[7..0] Swap MDC37 and MDC38
<23,29> CMDC[30..0]
CMDC[30..0] Mode D
Address 0..31 32..63
DQSC#[7..0] U1008 X76@ U1009 X76@
<23,29> DQSC#[7..0]
CMD0 CS0_L#
DQSC[7..0] +MEM_VREF6 M8 E3 MDC39 +MEM_VREF7 M8 E3 MDC63
<23,29> DQSC[7..0] VREFCA DQL0 VREFCA DQL0
H1 VREFDQ DQL1 F7 MDC33 H1 VREFDQ DQL1 F7 MDC58 CMD1
MDC[63..0] F2 MDC37 F2 MDC62
<23,29> MDC[63..0] DQL2 DQL2
CMDC9 N3 A0 DQL3 F8 MDC32 CMDC9 N3 A0 DQL3 F8 MDC59 CMD2 ODT_L
CMDC11 P7 H3 MDC36 Group4 CMDC11 P7 H3 MDC60 Group7
A1 DQL4 A1 DQL4
CMDC8 P3 A2 DQL5 H8 MDC34 CMDC8 P3 A2 DQL5 H8 MDC61 CMD3 CKE
CMDC25 N2 G2 MDC38 CMDC25 N2 G2 MDC57
A3 DQL6 A3 DQL6
CMDC24 P2 CMDC24 P2
A5 A5
CMDC22 R8 A6
CMDC22 R8 A6 CMD5 RST RST
+1.5VSDGPU CMDC7 R2 D7 MDC44 CMDC7 R2 D7 MDC54
A7 DQU0 A7 DQU0
CMDC21 T8 A8 DQU1 C3 MDC43 CMDC21 T8 A8 DQU1 C3 MDC48 CMD6 A9 A9
CMDC6 R3 C8 MDC47 CMDC6 R3 C8 MDC52
A9 DQU2 A9 DQU2
GSGL@ CMDC29 L7 A10/AP DQU3 C2 MDC40 CMDC29 L7 A10/AP DQU3 C2 MDC50 CMD7 A7 A7
R1121 CMDC23 R7 A7 MDC45 Group5 CMDC23 R7 A7 MDC53 Group6
A11 DQU4 A11 DQU4
240_0402_1% CMDC28 N7 A12 DQU5 A2 MDC42 CMDC28 N7 A12 DQU5 A2 MDC51 CMD8 A2 A2
CMDC20 T3 B8 MDC46 CMDC20 T3 B8 MDC55
A13 DQU6 A13 DQU6
CMDC4 T7 A14 DQU7 A3 MDC41 CMDC4 T7 A14 DQU7 A3 MDC49 CMD9 A0 A0
CMDC14 M7 CMDC14 M7
+MEM_VREF6 CMD10 A4 A4
CMD11 A1 A1
C1135 GSGL@
0.1U_0402_16V4Z
GSGL@ 1 CMDC12 M2 B2 CMDC12 M2 B2

R1122 CMDC27 BA0 VDD CMDC27 BA0 VDD
C 240_0402_1% CMDC26 M3 BA2 VDD G7 CMDC26 M3 BA2 VDD G7 CMD12 BA0 BA0 C
VDD K2 VDD K2
2
VDD K8 VDD K8 CMD13 WE* WE*
VDD N1 VDD N1
CLKC1 J7 CK VDD N9 CLKC1 J7 CK VDD N9 CMD14 A15 A15
CLKC1# K7 R1 CLKC1# K7 R1
CK VDD CK VDD
+1.5VSDGPU
+1.5VSDGPU
CMD15 CAS* CAS*
CMD16 CS0_H#
CMDC18 K1 A1 CMDC18 K1 A1
+1.5VSDGPU CMDC16 L2 CS/CS0 VDDQ A8 CMDC16 L2 CS/CS0 VDDQ A8 CMD17
CMDC30 J3 C1 CMDC30 J3 C1
RAS VDDQ RAS VDDQ
CMDC15 K3 CAS VDDQ C9 CMDC15 K3 CAS VDDQ C9 CMD18 ODT_H
GSGL@ CMDC13 L3 D2 CMDC13 L3 D2
WE VDDQ WE VDDQ
R1123 310mAVDDQ E9 310mAVDDQ E9 CMD19 CKE_H
240_0402_1% F1 F1
VDDQ VDDQ
DQSC4 F3 DQSL VDDQ H2 DQSC7 F3 DQSL VDDQ H2 CMD20 A13 A13
DQSC5 C7 H9 DQSC6 C7 H9
DQSU VDDQ DQSU VDDQ
CMD21 A8 A8
+MEM_VREF7
DQMC4 E7 DML VSS A9 DQMC7 E7 DML VSS A9 CMD22 A6 A6
C1136 GSGL@
0.1U_0402_16V4Z
GSGL@ 1 DQMC5 D3 B3 DQMC6 D3 B3

DMU VSS DMU VSS
R1124
VSS E1 VSS E1 CMD23 A11 A11
240_0402_1% G8 G8
VSS VSS
2
DQSC#4 G3 DQSL VSS J2 DQSC#7 G3 DQSL VSS J2 CMD24 A5 A5
DQSC#5 B7 J8 DQSC#6 B7 J8
DQSU VSS DQSU VSS
VSS M1 VSS M1 CMD25 A3 A3
VSS M9 VSS M9
VSS P1 VSS P1 CMD26 BA2 BA2
CMDC5 T2 P9 CMDC5 T2 P9
RESET VSS RESET VSS
VSS T1 VSS T1 CMD27 BA1 BA1
ZQ6 L8 T9 ZQ7 L8 T9
B
CMD28 A12 A12 B
1
1
J1 NC/ODT1 VSSQ B1 GSGL@ J1 NC/ODT1 VSSQ B1 CMD29 A10 A10

GSGL@ L1 B9 R1126 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ
R1125 J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 CMD30 RAS* RAS*
CLKC1 1 2 243_0402_1% L9 D8 L9 D8
<23> CLKC1
2
@ R1127 NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 Not Available
2
VSSQ VSSQ
1
80.6_0402_1% E8 E8
GSGL@ VSSQ VSSQ
R1128 VSSQ F9 VSSQ F9 LOW HIGH
VSSQ G1 VSSQ G1
160_0402_1% G9 G9
VSSQ VSSQ
2
CLKC1# 1 2 96-BALL 96-BALL

<23> CLKC1#
@R1129
@ R1129 SDRAM DDR3 SDRAM DDR3
80.6_0402_1% 1 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
@
C1137
0.01U_0402_16V7K +1.5VSDGPU
NV recommand 0720 2 +1.5VSDGPU
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
GSGL@ C1142
GSGL@ C1143
GSGL@ C1144
GSGL@ C1145
GSGL@ C1146
GSGL@ C1147
GSGL@ C1152
GSGL@ C1153
GSGL@ C1154
GSGL@ C1155
GSGL@ C1156
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
GSGL@ C1138
GSGL@ C1139
GSGL@ C1140
GSGL@ C1141
GSGL@ C1148
GSGL@ C1149
GSGL@ C1150
GSGL@ C1151
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A

SCHEMATIC,MB A7912
Custom C
5 4 3 2 1
5 4 3 2 1
D D
+LCDVDD
LCD POWER CIRCUIT
R02 Modify +3VALW +3VS
W=60mils
R5 1 R6 1 Place closed to JLVDS1 B+ L2 +INVPWR_B+
2
200_0603_1% 10K_0402_5% C479 +LCDVDD FBMA-L11-201209-221LMA30T_0805
4.7U_0603_6.3V6K +3VS 1 2
2
L1 W=60mils
2 FBMA-L11-201209-221LMA30T_0805
R2 1 1 1 1 1 2
D
1
1
3
10K_0402_5% C484 C485 C11 @
Q2 2 2 1 2 AP2301GN-HF_SOT23-3 C2040 1 1
SSM3K7002F_SC59-3 G 0.1U_0402_16V4Z 10U_0603_6.3V6M 0.1U_0402_16V4Z 47P_0402_50V8J SM010014520 3000ma C6 C9
S Q28 2 2 2 2 68P_0402_50V8J 680P_0402_50V7K
1 220ohm@100mhz
3
C2 +LCDVDD
1U_0402_6.3V6K DCR 0.04 2 2
D W=60mils
1
1
LCDVDD_ON Q1 2 RF request
<16> PCH_ENVDD 2
G SSM3K7002F_SC59-3 1 1
S C562 C10
3
4.7U_0603_6.3V6K 0.1U_0402_16V4Z
LCD/LED PANEL Conn.
1
2 2
R4
C 100K_0402_5% C
R2130 @
2
1 2
W=60mils 0_0402_5%
+INVPWR_B+ JLVDS1
1
2
1
41
add on 7912_0.3
2 G1
3 3 G2 42
4 4 G3 43
+LCDVDD 5 5 G4 44
U13 +3VS W=60mils 6 6 G5 45

+3VS 7 7 G6 46
1 R783 2 1 INVTPWM 8
100K_0402_5% OE# BKOFF# 8
VCC 5 9 9
@ PCH_LCD_CLK 10
<16> PCH_LCD_CLK 10
2 INVTPWM 220P_0402_50V7K 1 2 C5 PCH_LCD_DATA 11
<16> DPST_PWM IN <16> PCH_LCD_DATA 11
12 12
4 INVTPWM BKOFF# 220P_0402_50V7K 1 2 C8 PCH_TXOUT0- 13
OUT <40> BKOFF# <16> PCH_TXOUT0- 13
3 PCH_TXOUT0+ 14
GND <16> PCH_TXOUT0+ 14
15 15
74AHC1G125GW_SOT353-5 R18 1 2 10K_0402_5% PCH_TXOUT1- 16
<16> PCH_TXOUT1- 16
@ PCH_TXOUT1+ 17
<16> PCH_TXOUT1+ 17
18 18
PCH_TXOUT2- 19
<16> PCH_TXOUT2- 19
1 2 PCH_TXOUT2+ 20
<16> PCH_TXOUT2+ 20
R85 0_0402_5% 21 21
1
PCH_TXCLK- 22
<16> PCH_TXCLK- 22
R86 PCH_TXCLK+ 23
<16> PCH_TXCLK+ 23
10K_0402_5% 24 24
TZOUT0- 25
TZOUT0+ 25
26
2
B 26 B
27 27
TZOUT1- 28
TZOUT1+ 28
29 29
30 30
TZCLK- 31
TZCLK+ 31
32 32
33 33
EDP_HPD 34 34
35 35
+3VS 36
+3VS eDP For Camera
<17> USB20_N10
USB20_N10
37
38
36
37
USB20_P10 38
<17> USB20_P10 39 39
40 40
1
<4> EDP_HPD# 1 1
R550 I-PEX_20143-040E-20F
10K_0402_5% C480 C481
22P_0402_50V8J 22P_0402_50V8J
PCH_GPIO71 .1U_0402_16V7K 1 TZOUT0+ 2 2 @
PCH_GPIO71 <18> D <4> EDP_TXP0 2EDP@ C910 @
2
.1U_0402_16V7K 1 2EDP@ C911 TZOUT0-

<4> EDP_TXN0
Q22 2 EDP_HPD
D
1
SSM3K7002F_SC59-3 G .1U_0402_16V7K 1 2EDP@ C912 TZOUT1+

<4> EDP_TXP1
1
EDP_HPD 2 Q29 EDP@ S .1U_0402_16V7K 1 2EDP@ C913 TZOUT1-

<4> EDP_TXN1
3
G SSM3K7002F_SC59-3 EDP@
S EDP@ R02 modify R480 .1U_0402_16V7K 1 2EDP@ C914 TZCLK+
<4> EDP_AUXP
3
100K_0402_5% <4> EDP_AUXN .1U_0402_16V7K 1 2EDP@ C915 TZCLK- D15 @

1 4 USB20_N10
2
I/O1 I/O3
2 GND VDD 5 +3VS

A A
GPIO71 USB20_P10 3 I/O2 I/O4 6
PCH_GPIO71 AZC099-04S.R7G_SOT23-6 Modify R02

eDP 0
LVDS 1
SCHEMATIC,MB A7912
Custom C
4019ID
5 4 3 2 1
A B C D E
1 1
W=40mils
+5VS
2
R04 modify +R_CRT_VCC +CRT_VCC
F1
D5 1.1A_6V_SMD1812P110TFW=40mils
2 1 1 2
@ @
D17 D18 CH491DPT_SOT23-3 1
L30ESDL5V0C3-2 L30ESDL5V0C3-2 C215
0.1U_0402_16V4Z
CRB1.0 use 47ohm@100Mhz Bead
1
2
CRT Connector
L32 L33
BLM18BA470SN1D_2P BLM18BA470SN1D_2P
PCH_CRT_R 1 2 CRT_R_1 1 2 CRT_R_2 JCRT1
<16> PCH_CRT_R
L29 L30 6
BLM18BA470SN1D_2P BLM18BA470SN1D_2P PAD JCRT1.11 11
PCH_CRT_G 1 2 CRT_G_1 1 2 CRT_G_2 @ T71 1
<16> PCH_CRT_G
L27 L28 7
BLM18BA470SN1D_2P BLM18BA470SN1D_2P 12
PCH_CRT_B 1 2 CRT_B_1 1 2 CRT_B_2 2
<16> PCH_CRT_B
8
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
13
1
1
1 1 1 1 1 1 1 1 1 3
R524 R520 R510 9
C636
C613
C596
C621
C601
C588
C637
C614
C597
150_0402_1% 150_0402_1% 150_0402_1% 14 G 16
4 G 17
2 2 2 2 2 2 2 2 2
10
2
2 2
15
1 JCRT1.5 5
C589 @ T72
PAD C-H_13-12201513CP
100P_0402_50V8J CONN@
2
SM010012010 300ma 120ohm@100mhz DCR 0.4
1 2 CRT_HSYNC_2
+CRT_VCC L13 MBC1608121YZF_0603 DSUB_12
C243 1 2 0.1U_0402_16V4Z R147 2 1 10K_0402_5% 1 2 CRT_VSYNC_2 1

L10 MBC1608121YZF_0603 1 1
5
R428 U10 C230 C220 DSUB_15

0_0402_5% 10P_0402_50V8J 10P_0402_50V8J C623 2
P
OE#
PCH_CRT_HSYNC CRT_HSYNC CRT_HSYNC_1 2 2 68P_0402_50V8J 1

<16> PCH_CRT_HSYNC 1 2 2 A Y 4
G
C586
74AHCT1G125GW_SOT353-5 68P_0402_50V8J
3
2
+CRT_VCC
C228 1 2 0.1U_0402_16V4Z
5
1
R426 U9
0_0402_5%
P
OE#
PCH_CRT_VSYNC 1 2 CRT_VSYNC 2 4 CRT_VSYNC_1

<16> PCH_CRT_VSYNC A Y
G
74AHCT1G125GW_SOT353-5
3
+CRT_VCC
3 3
+3VS
1
R146 R142
4.7K_0402_5% 4.7K_0402_5%
2
2
PCH_CRT_DATA 1 6 DSUB_12
<16> PCH_CRT_DATA
Q11A
5
<16> PCH_CRT_CLK PCH_CRT_CLK 4 3 DSUB_15
Q11B
4 4

SCHEMATIC,MB A7912
Custom C
4019ID
A B C D E
5 4 3 2 1
SM070001310 400ma 90ohm@100mhz DCR 0.3
HDMI_CLK- R574 1 2 0_0402_5% HDMI_R_CK-
1 1 2 2
L38
WCM-2012-900T_0805
@ 4 3
4 3
D HDMI_CLK+ R579 1 0_0402_5% HDMI_R_CK+ D
2
HDMI_TX0- R565 1 2 0_0402_5% HDMI_R_D0-

@ R242
0_0603_5% 1 2
L36 1 2
1 2 W=40mils WCM-2012-900T_0805
+HDMI_5V_OUT @ 4 3
D10 F2 4 3
+5VS 2 1 +HDMI_5V 1 2 HDMI_TX0+ R569 1 2 0_0402_5% HDMI_R_D0+
1
CH491DPT_SOT23-3 1.1A_6V_SMD1812P110TF
C345 HDMI_TX1- R584 1 2 0_0402_5% HDMI_R_D1-
0.1U_0402_16V4Z
2
1 1 2 2
L39
WCM-2012-900T_0805
@ 4 3
4 3
+3VS HDMI_TX1+ R586 1 2 0_0402_5% HDMI_R_D1+
HDMI_TX2- R591 1 2 0_0402_5% HDMI_R_D2-
1
1 1 2 2
R198 L40
1M_0402_5% WCM-2012-900T_0805
<16> PCH_DPB_N0 C280 2 1 .1U_0402_16V7K HDMI_TX2- @ 4 3
4 3
2
C281 1 .1U_0402_16V7K HDMI_TX2+
G
<16> PCH_DPB_P0 2
2
HDMI_TX2+ R593 1 2 0_0402_5% HDMI_R_D2+
C C283 HDMI_TX1- HDMI_HPD C
<16> PCH_DPB_N1 2 1 .1U_0402_16V7K 1 3 PCH_DPB_HPD <16>
C282 2 1 .1U_0402_16V7K HDMI_TX1+ Q14
S
<16> PCH_DPB_P1
220P_0402_50V7K
C324
1 SSM3K7002F_SC59-3
1
<16> PCH_DPB_N2 C287 2 1 .1U_0402_16V7K HDMI_TX0-
<16> PCH_DPB_P2 C286 2 1 .1U_0402_16V7K HDMI_TX0+ R219
100K_0402_5% HDMI_TX2- R589 1 2 680_0402_5% HDMI_GND
C285 2
<16> PCH_DPB_N3 2 1 .1U_0402_16V7K HDMI_CLK- HDMI_TX2+ R594 1 2 680_0402_5%
<16> PCH_DPB_P3 C284 2 1 .1U_0402_16V7K HDMI_CLK+
2
HDMI_TX1- R583 1 2 680_0402_5%
HDMI_TX1+ R587 1 2 680_0402_5%
HDMI_TX0- R564 1 2 680_0402_5%

HDMI_TX0+ R570 1 2 680_0402_5%
HDMI_CLK- R573 1 2 680_0402_5%

HDMI_CLK+ R580 1 2 680_0402_5%
1
+3VS 2 Q37
+3VS G
SSM3K7002F_SC59-3 S
3
R250 1 2 2.2K_0402_5% SDVO_SCLK +HDMI_5V_OUT
R253 1 2 2.2K_0402_5% SDVO_SDATA

+3VS
2
B B
HDMI connector
2
D12 D11
RB751V40_SC76-2 RB751V40_SC76-2
R785 JHDMI1
0_0402_5% HDMI_HPD 19
2 1
2 1
HP_DET
+HDMI_5V_OUT 18
1
+5V
2.2K_0402_5%
2.2K_0402_5%
17 DDC/CEC_GND
HDMI_SDATA 16 SDA
R256
R255
HDMI_SCLK 15 SCL
14 Reserved
2
G
13
1
CEC
RF request HDMI_R_CK- 12 CK- GND 20
SDVO_SCLK 3 1 HDMI_SCLK 11 21
<16> SDVO_SCLK CK_shield GND
HDMI_R_CK+
S
1 10 CK+ GND 22
2
G
HDMI_R_D0- 9 23
Q16 SSM3K7002F_SC59-3 C357 D0- GND
8 D0_shield
SDVO_SDATA 3 1 HDMI_SDATA 47P_0402_50V8J HDMI_R_D0+ 7
<16> SDVO_SDATA 2 D0+
@ HDMI_R_D1-
S
1 6 D1-
5 D1_shield
Q17 SSM3K7002F_SC59-3 C358 HDMI_R_D1+ 4
47P_0402_50V8J HDMI_R_D2- D1+
Place closed to JHDMI1 2 @
3 D2-
2 D2_shield
HDMI_R_D2+ 1 D2+
ACON_HMR2E-AK120D
CONN@
A A

SCHEMATIC,MB A7912
Custom C
4019ID
5 4 3 2 1
5 4 3 2 1
D D
SATA HDD1 Conn.

CL 4.0 mm
JHDD1
1 GND
<13> SATA_PTX_DRX_P0 SATA_PTX_DRX_P0 C708 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2
SATA_PTX_DRX_N0 C711 1 RX+
<13> SATA_PTX_DRX_N0 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3 RX-
4 GND
SATA_PRX_DTX_N0 C712 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 5
<13> SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C713 1 SATA_PRX_C_DTX_P0 TX-
<13> SATA_PRX_DTX_P0 2 0.01U_0402_16V7K 6 TX+
7 GND +3VS
+3VS 8 3.3V 1
9 C453
3.3V
10 3.3V
11 0.1U_0402_16V4Z
+5VS GND 2
12 GND
R2051 13
+5VS_HDD1 GND
10_0805_5%2 14 5V
15 5V
16 5V
17 +5VS_HDD1
GND
18 Rsv
C C
19 GND 100mils
20 12V
21 12V
10U_0603_6.3V6M
C744
1U_0402_6.3V6K
C740
0.1U_0402_16V4Z
C743
1000P_0402_50V7K
C742
22 12V 1 1 1 1
23 GND
24 GND
OCTEK_SAT-22DD1G 2 2 2 2
CONN@
R02 Modify
SATA ODD Conn.

JODD1
1 GND
<13> SATA_PTX_DRX_P2 SATA_PTX_DRX_P2 C643 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P2 2
SATA_PTX_DRX_N2 C639 1 SATA_PTX_C_DRX_N2 A+
<13> SATA_PTX_DRX_N2 2 0.01U_0402_16V7K 3 A-
4 GND
SATA_PRX_DTX_N2 C628 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N2 5
<13> SATA_PRX_DTX_N2 B-
SATA_PRX_DTX_P2 C624 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P2 6
<13> SATA_PRX_DTX_P2 B+ +5VS_ODD
7 GND
+5VS 80mils
R2052 8 DP
10U_0603_6.3V6M
C199
1U_0402_6.3V6K
C201
0.1U_0402_16V4Z
C200
1000P_0402_50V7K
C192
10_0805_5%2 +5VS_ODD 9 +5V 1 1 1 1
B B
10 +5V GND 17
PAD T79 @ 11 16
MD GND
12 GND GND 15
2 2 2 2
13 GND GND 14
OCTEK_SLS-13SB1G_RV
CONN@
R02 Modify
A A

SCHEMATIC,MB A7912
Custom C
4019ID
5 4 3 2 1
5 4 3 2 1
+1.2V_LAN
R03 modify
+VDDO_CR U32
+3VALW +3V_LAN
4.7U_0603_6.3V6K
37 +LAN_BIASVDDH
BIASVDDH +3V_LAN
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1 1 1 +VDDO_CR 20 @ R2097
VDDO_CR
C678
C302
C674
C301
C671
C298
C668
10_0805_5%2 60mil
+1.2V_LAN
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 35 17 +LAN_XTALVDDH 1 1 1 1
VDDC XTALVDDH
C2077
C683
C690
C680
C667
61 VDDC
2 2 2 2 2 2 2
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
48 +LAN_AVDDH 3 1 1 1
D
2 AVDDH 2 2 2 2
C666
AVDDH 42
+3V_LAN
C662
G
7 Q2007
LAN_PWR_EN#2
VDDO AO3413L_SOT23-3 2 2
56 VDDO
D D
62 VDDO
49 LAN_MIDI3-
R02 Modify TRD3_N LAN_MIDI3- <36>
50 LAN_MIDI3+
TRD3_P LAN_MIDI3+ <36>
47 LAN_MIDI2- R2131 @
TRD2_N LAN_MIDI2- <36>
46 LAN_MIDI2+ 2 1
TRD2_P LAN_MIDI2+ <36> <40> LAN_PWR_EN# PCH_PWR_EN# <20,44>
+LAN_AVDDL 39 43 LAN_MIDI1- 0_0402_5% 20mil
AVDDL TRD1_N LAN_MIDI1- <36>
45 44 LAN_MIDI1+ L20
AVDDL TRD1_P LAN_MIDI1+ <36>
51 +LAN_XTALVDDH 1 1 2 +3V_LAN
AVDDL LAN_MIDI0- C323 BLM18AG601SN1D_2P
TRD0_N 41 LAN_MIDI0- <36>
+LAN_GPHYPLLVDDL 36 40 LAN_MIDI0+ 0.1U_0402_16V4Z
GPHY_PLLVDDL TRD0_P LAN_MIDI0+ <36>
R02 modify for ESD +LAN_PCIEPLLVDD
20mil 2 L34
32 PCIE_PLLVDDL +LAN_BIASVDDH 1 1 2
29 C657 BLM18AG601SN1D_2P
C2069 1 PCIE_PLLVDDL
2 0.1U_0402_16V4Z PLT_RST_BUF# SO_LINKLED# 65 LAN_LINK# <36>
0.1U_0402_16V4Z
2
SCLK_SPD1000LED# 66 20mil L15
R02 Modify 2 +LAN_AVDDH 1 2
SPD100LED#_SERIALDO BLM18AG601SN1D_2P
1 1
C299 C294
<14> PCIE_PRX_DTX_P1 .1U_0402_16V7K 1 2 C670 PCIE_PRX_C_DTX_P1 28 67 R200 2 1 0_0402_5%
.1U_0402_16V7K 1 PCIE_TXD_P TRAFFICLED#_SERIALDI LAN_ACTIVITY# <36>
<14> PCIE_PRX_DTX_N1 2 C673 PCIE_PRX_C_DTX_N1 27
PCIE_TXD_N
0.1U_0402_16V4Z 0.1U_0402_16V4Z
+VDDO_CR 2 2
<14> PCIE_PTX_C_DRX_P1 33 PCIE_RXD_P
34 8 +VDDO_CR_R R214 1 2 0_0603_5% +VDDO_CR
<14> PCIE_PTX_C_DRX_N1 PCIE_RXD_N GPIO1_LR_OUT
5 CR_5IN1_LED#_R R229 2 1 0_0402_5% CR_5IN1_LED#
R201 1 GPIO_0 CR_5IN1_LED# <41>
<37,40> EC_PME# 2 0_0402_5%
+3V_LAN R209 1 @ 2 4.7K_0402_5% 64 SPROM_DOUT

C SI_EEDATA SPROM_CLK C
CS#_EECLK 63
R213 1 @ 2 0_0402_5% LAN_PME# 3
<15,37> PCH_PCIE_WAKE# WAKE#
R225 1 2 0_0402_5% 11
<17,37,40> PLT_RST_BUF# PREST#
<14> CLK_PCIE_LAN 31 PCIE_REFCLK_P
<14> CLK_PCIE_LAN# 30 PCIE_REFCLK_N
1 CR_XD_WE#_SD_DETECT_R R576 2 1 0_0402_5% CR_XD_WE#_SD_DETECT
SD_DETECT/XD_WE# CR_XD_WE#_SD_DETECT <36>
68 CR_XD_DETECT#_R R572 2 1 0_0402_5% CR_XD_DETECT#
CR_DATA0 R199 33_0402_5% CR_DATA0_R SR_DISABLE/XD_DETECT# CR_XD_DETECT# <36>
1 2 25 CR_DATA0
<36> CR_DATA0 CR_DATA1 R207 1 2 33_0402_5% CR_DATA1_R 24 59 CR_XD_CE#_MS_INS#_R R192 1 2 33_0402_5% CR_XD_CE#_MS_INS#
<36> CR_DATA1 CR_DATA2 R211 33_0402_5% CR_DATA2_R CR_DATA1 MS_INS#/XD_CE# CR_XD_CE#_MS_INS# <36>
1 2 23 CR_DATA2
<36> CR_DATA2 CR_DATA3 R215 1 2 33_0402_5% CR_DATA3_R 22 9 CR_XD_RE#_R R227 2 1 0_0402_5% CR_XD_RE#
<36> CR_DATA3 CR_DATA4 R168 33_0402_5% CR_DATA4_R CR_DATA3 GPIO2_MEDIA_SENSE/XD_RE# CR_XD_RE# <36>
1 2 52 CR_DATA4
<36> CR_DATA4 CR_DATA5 R171 1 2 33_0402_5% CR_DATA5_R 53 57 CR_WP#_XD_WP#_R R185 2 1 0_0402_5% CR_WP#_XD_WP#
<36> CR_DATA5 CR_DATA6 R179 33_0402_5% CR_DATA6_R CR_DATA5 CR_WP#/XD_WP# CR_WP#_XD_WP# <36>
1 2 54 CR_DATA6
<36> CR_DATA6 CR_DATA7 R182 1 2 33_0402_5% CR_DATA7_R 55 60 CR_PWR_EN_R R196 2 1 0_0402_5% CR_PWR_EN For EMI request
<36> CR_DATA7 CR_DATA7 CR_LED_CR_BUS_PWR/XD_ALE CR_PWR_EN <36>
21 CR_CLK_XD_RY_BY#_R R216 1 2 0_0402_5% CR_CLK_XD_RY_BY#
CR_CLK/XD_RY_BY# CR_CLK_XD_RY_BY# <36>
+3VS 26 CR_CMD_XD_CLE_R R195 1 2 22_0402_5% CR_CMD_XD_CLE
CR_CMD_XD_CLE CR_CMD_XD_CLE <36> 1
R190 1 2 1K_0402_5% 58 VMAIN_PRSNT C329
+3V_LAN 0.01U_0402_16V7K
2
R824 (CP_PWR_XD_ALE) R228 1 2 4.7K_0402_5% 6 TEST1 @
for B0 version 1 2 10 40mil L37 40mil
R226 4.7K_0402_5% TEST2 +1.2V_LAN_OUT 1
SR_LX 16 2 +1.2V_LAN
4.7UH_PG031B-4R7MS_1.1A_20%
CR_PWR_XD_ALE R208 2 1 0_0402_5% 4 13 1 1
<36> CR_PWR_XD_ALE LOW_PWR SR_VFB
EMI Request...2010/07/27
C689 C691
B LAN_XTALI LAN_XTALO_R 0.1U_0402_16V4Z 10U_0603_6.3V6M B
19 XTALO
LAN_XTALO_R LAN_XTALI 2 2
18 XTALI SM010005500 500ma 600ohm@100mhz DCR 0.38
1
R02 Modify
R562
20mil L18
40mil +LAN_PCIEPLLVDD
GND PLANE
200_0402_1% SR_VDDP 15 +3V_LAN 1 2 +1.2V_LAN

25MHZ 10PF 7V25000014 15mil 14 BLM18AG601SN1D_2P
Y4 SR_VDD
1 2 LAN_RDAC 38 1 0.1U_0402_16V4Z 1 4.7U_0603_6.3V6K 1 1
2
R541 1.24K_0402_1% RDAC C684 C692 C306 C303

1 1 3 3LAN_XTALO <14> LAN_CLKREQ# 12 CLK_REQ# 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
GND GND BCM57785XA0KMLG_QFN68_8X8 2 2 2 2
1 1
69
+3V_LAN 2 R2120 1
C681 2 4 C679 10K_0402_5% PLACE NEXT P14
15P_0402_50V8J 15P_0402_50V8J 20mil
2 2 L35
+LAN_GPHYPLLVDDL 1 2 +1.2V_LAN
BLM18AG601SN1D_2P
1 1
C658 C659
R02 modify
0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2 2
+3V_LAN
SPROM_CLK SPROM_DOUT
(EECLK) (EEDATA) C634 1 2 0.1U_0402_16V4Z 20mil L17
2
On chip 1 0
1K_0402_5%
1K_0402_5%
+LAN_AVDDL 1 2 +1.2V_LAN
2
BLM18AG601SN1D_2P
R537
R536
1 1
AT24C02 1 1 @ C656 C297
U31 @
1
8 1 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
1
A VCC A0 2 2 A
7 WP A1 2
SPROM_CLK 6 3
SPROM_DOUT SCL A2
5 SDA GND 4
2
1K_0402_5%
1K_0402_5%
AT24C04BN-SH-T_SO8
2
R538
R525
SA00004QG00
@ Security Classification Compal Secret Data Compal Electronics, Inc.

1

1
SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1
D D
LAN Connector
C474,C475 and D14
T28 ME interefer,do not pop!!
+3V_LAN 2 1
220P_0402_50V7K
1 24 R384 1K_0402_5% 1
LAN_MIDI3+ TCT1 MCT1 RJ45_MIDI3+
<35> LAN_MIDI3+ 2 TD1+ MX1+ 23
C473
<35> LAN_MIDI3- LAN_MIDI3- 3 22 RJ45_MIDI3-
TD1- MX1-
2 C474 68P_0402_50V8J
4 TCT2 MCT2 21 JRJ45
<35> LAN_MIDI2- LAN_MIDI2- 5 20 RJ45_MIDI2- @
LAN_MIDI2+ TD2+ MX2+ RJ45_MIDI2+
<35> LAN_MIDI2+ 6 TD2- MX2- 19 2 1 9 Green LED+
7 18 LAN_LINK# 10
LAN_MIDI1+ TCT3 MCT3 RJ45_MIDI1+ <35> LAN_LINK# Green LED-
<35> LAN_MIDI1+ 8 TD3+ MX3+ 17
<35> LAN_MIDI1- LAN_MIDI1- 9 16 RJ45_MIDI1- RJ45_MIDI0+ 1 14
TD3- MX3- PR1+ SHLD1
SHLD2 13
10 15 RJ45_MIDI0- 2
LAN_MIDI0- TCT4 MCT4 RJ45_MIDI0- PR1-
<35> LAN_MIDI0- 11 TD4+ MX4+ 14
<35> LAN_MIDI0+ LAN_MIDI0+ 12 13 RJ45_MIDI0+ RJ45_MIDI1+ 3
TD4- MX4- PR2+
RJ45_MIDI2+ 4 PR3+
1
75_0603_1%
75_0603_1%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z IH-160 RJ45_MIDI2- 5

SP050006F00 PR3-
R493
R492
1 1 1 1 RJ45_MIDI1- 6 PR2-
C617
C618
C619
C620
RJ45_MIDI3+ 7
2
PR4+
1
75_0603_1%
75_0603_1%
2 2 2 2 RJ45_MIDI3- 8 PR4-
R491
R490
C C
+3V_LAN 2 1 11 Yellow LED+

R385 1K_0402_5%1
2
LAN_ACTIVITY# 12
<35> LAN_ACTIVITY# Yellow LED-
220P_0402_50V7K
RJ45_GND LAN_ACTIVITY#
68P_0402_50V8J
C476
Place close to TCT pin LAN_LINK#
2 SANTA_130451-K
2 1
@ CONN@
C475
BOTHHAND: S X'FORM_ GST5009-D LF LAN, SP050006B00
3
TIMAG:S X'FORM_ IH-160 LAN , SP050006F00 D14
L30ESDL5V0C3-2 @ JP1 40mil
@ B88069X9231T203_4P5X3P2-2 EMI Request
2 1
R04 modify for EMI
RJ45_GND C478 1 2 10P_0402_50V8J LANGND
B88069X9231T203_4P5X3P2-2
100UH_SSC0301101MCF_0.18A_20%
1
100P_0402_50V8J
1
JP3
RJ45_GND
Card Reader Connector
@ C832
J10 C2097 1 2 120P_1206_2KV8J
3
@
40mil JUMP_43X118
2 R03 Modify
L53
L30ESDL5V0C3-2
@ @
2
JREAD1
2
2
1
+XDPWR_SDPWR_MSPWR 11 31 CR_DATA0
SD_VCC XD_D0 CR_DATA0 <35>
D36
18 32 CR_DATA1 2 1
MS_VCC XD_D1 CR_DATA2 CR_DATA1 <35>
39 XD_VCC XD_D2 33
34 CR_DATA3 CR_DATA2 <35> B88069X9231T203_4P5X3P2-2
XD_D3 CR_DATA4 CR_DATA3 <35> JP2
35
1
CR_CLK_XD_RY_BY# XD_D4 CR_DATA5 CR_DATA4 <35> @
8 SD_CLK XD_D5 36
B <35> CR_CLK_XD_RY_BY# CR_CMD_XD_CLE 16 37 CR_DATA6 CR_DATA5 <35> R04 modify B
CR_XD_WE#_SD_DETECT SD_CMD XD_D6 CR_DATA7 CR_DATA6 <35>
1 SD_CD XD_D7 38
CR_WP#_XD_WP# 2 CR_DATA7 <35>
CR_DATA0 SD_WP CR_XD_DETECT#
4 SD/MMC_DAT0 XD_CD 22
CR_DATA1 3 23 CR_CLK_XD_RY_BY#_23 CR_XD_DETECT# <35> +VDDO_CR
CR_DATA2 SD/MMC_DAT1 XD_R/B CR_XD_RE#
21 SD/MMC_DAT2 XD_RE 24
CR_DATA3 19 25 CR_XD_RE# <35>
SD/MMC_DAT3 XD_CE CR_XD_CE#_MS_INS# <35>
XD_CLE 26
27 CR_PWR_XD_ALE CR_CMD_XD_CLE <35> +3VALW 1 @ 2
XD_ALE CR_PWR_XD_ALE <35> R303
XD_WE 28
29 CR_XD_WE#_SD_DETECT <35> 0_0805_5% +XDPWR_SDPWR_MSPWR
XD_WP-IN CR_WP#_XD_WP# <35>
1
CR_DATA0 SD_GND 6
U16
40mil
10 MS_DATA0 SD_GND 13
CR_DATA1 9 5 R304 1 8
CR_DATA2 MS_DATA1 MS_GND 300_0603_5% GND VOUT
12 MS_DATA2 MS_GND 20 2 VIN VOUT 7
R04 modify
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CR_DATA3 15 30 3 6 1 1 1
2
MS_DATA3 XD_GND VIN VOUT
C421
C433
C434
EPAD
CR_CLK_XD_RY_BY#_17 17 40 4 5
CR_XD_CE#_MS_INS# MS_SCLK XD_GND EN FLG
14 MS_INS GND 41 D
1
+3VS +3VALW CR_CMD_XD_CLE 7 42
MS_BS GND 1 2 2 2
1 1 2 AP2301MPG-13_MSOP8
9
<35> CR_PWR_EN
C381
G
0.1U_0402_16V4Z
TAITW_R013-P17-HM_NR
C2091
C2092
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CONN@ Q31 S
3
SSM3K7002F_SC59-3 2
2 2
A
R02 modify for SD3.0 issue A
CR_CLK_XD_RY_BY# 1 2 CR_CLK_XD_RY_BY#_17 R2102 1 2 0_0402_5% 2 CR_CLK_XD_RY_BY#_23

R2088 10_0402_5%
C2096
C2094
R2101
1 2 1 2
1
6P_0402_50V8D
@
22_0402_5%
6.8P_0402_50V8C
SCHEMATIC,MB A7912
Custom C
4019ID
5 4 3 2 1
A B C D E
For Wireless LAN or MSATA

+3VS_FULL +1.5VS_FULL +3VS_FULL
60mil
+3VS 2 1 +3VS_FULL 1 1 1 1 1
R352 0_0805_5% C455 C467 1 C442 C441 C466
NOAC@ 4.7U_0603_6.3V6K 0.1U_0402_16V4Z C443 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
4.7U_0603_6.3V6K
2 2 2 2 2
60mil 2
+1.5VS 2 1 +1.5VS_FULL
R2040 0_0805_5% R02 Modify R02 Modify
1 AC@ R2108 1
0_0402_5%
<40> WLAN_PME# 1 2PCH_PCIE_WAKE#_R
<14> PCIE_PRX_DTX_N2 R2044 1 PCIE@ 2 0_0402_5% WWAN_PRX_C_DTX_P1
<14> PCIE_PRX_DTX_P2 R2045 1 PCIE@ 2 0_0402_5% WWAN_PRX_C_DTX_N1 @R2109
@ R2109
0_0402_5%
R2046 1 PCIE@ 2 0_0402_5% WWAN_PTX_C_DRX_N1 1 2
<14> PCIE_PTX_C_DRX_N2 <35,40> EC_PME# +1.5VS_FULL +3VS_FULL
R2047 1 PCIE@ 2 0_0402_5% WWAN_PTX_C_DRX_P1
<14> PCIE_PTX_C_DRX_P2
@ R702
SATA_PRX_DTX_P1 mSATA@ 2 1 WWAN_PRX_C_DTX_P1 0_0402_5% JMINI1
<13> SATA_PRX_DTX_P1
C2045 0.01U_0402_16V7K 1 2 1 2
<15,35> PCH_PCIE_WAKE# 1 2
SATA_PRX_DTX_N1 mSATA@ 2 1 WWAN_PRX_C_DTX_N1 3 4
<13> SATA_PRX_DTX_N1 3 4
C2046 0.01U_0402_16V7K 5 6
SATA_PTX_DRX_N1 mSATA@ 2 5 6
<13> SATA_PTX_DRX_N1 1 WWAN_PTX_C_DRX_N1 <14> MINI1_CLKREQ# R2060 1 PCIE@ 2 0_0402_5% MINI1_CLKREQ#_R 7 7 8 8
C2047 0.01U_0402_16V7K 9 10
SATA_PTX_DRX_P1 mSATA@ 2 9 10
<13> SATA_PTX_DRX_P1 1 WWAN_PTX_C_DRX_P1 <14> CLK_PCIE_MINI1#
R2061 1 PCIE@ 2 0_0402_5% CLK_PCIE_MINI1#_R 11 11 12 12
C2048 0.01U_0402_16V7K R2062 1 PCIE@ 2 0_0402_5% CLK_PCIE_MINI1_R 13 14
<14> CLK_PCIE_MINI1 13 14
15 15 16 16
17 17 18 18
MSATA_DET# 2 mSATA@1 E51RXD_P80CLK_R 19 20 WL_OFF#
<18> MSATA_DET# 19 20 WL_OFF# <18,40>
R2058 0_0402_5% 21 22 PLT_RST_BUF#
21 22 PLT_RST_BUF# <17,35,40>
WWAN_PRX_C_DTX_P1 23 24
WWAN_PRX_C_DTX_N1 23 24
25 25 26 26
27 27 28 28
29 30 MINI1_SMBCLK R337 1 @ 2 0_0402_5% PCH_SMBCLK <14>
WWAN_PTX_C_DRX_N1 29 30 MINI1_SMBDATA R335 1 @
31 31 32 32 2 0_0402_5% PCH_SMBDATA <14>
WWAN_PTX_C_DRX_P1 33 34
33 34
35 35 36 36 USB20_N8 <17>
37 37 38 38 USB20_P8 <17>
39 39 40 40
+3VS_FULL 41 42 MINI1_LED#
D32 41 42
2
WLAN&BT Combo module circuits 43 43 44 44 MINI1_LED# <40> 2
<40,44,47,49,50> SUSP# SUSP# 1 2 BT_CTRL 45 46 R2134 1 AC@ 2BT_LED# BT_LED# <40>
45 46
BT BT 47 47 48 48 0_0402_5%
(9~16mA)
1
on module on module CH751H-40PT_SOD323-2 R299 1 2 0_0402_5% E51TXD_P80DATA_R 49 50 1 @ 2 +3VS_FULL
<40> E51TXD_P80DATA 49 50
@ R287 1 2 0_0402_5% E51RXD_P80CLK_R 51 52 R2135 4.7K_0402_5% R305
D <40> E51RXD_P80CLK 51 52
1
Enable Disable 100K_0402_5%
2 Q57 BT_CTRL 2 1 53 54
<18,39,40> BT_ON# GNDGND
1
G R288 1K_0402_5%
2
BT_CTRL H L SSM3K7002F_SC59-3 S ACES_51711-0520W-001
3
R300
BT_ON# 100K_0402_5%
CONN@
+3VS_FULL
L H
2
+3VALW +3VS_FULL
@
2 1
R2111 0_0805_5% 1
C2098 AC@
Q2009 AC@
AO3419L_SOT23-3 4.7U_0603_6.3V6K
2
3 1
S
3
40mil(1A) 3
G
2
+3VALW AC@1 23VSWLAN_GATE_R AC@1 2 3VSWLAN_GATE AC@ R2114

R2112 100K_0402_5% R2113 1K_0402_5% 470_0603_5%
1
1
C2099 AC@
3
0.1U_0402_16V7K 3VSWLAN_R
AC@ R2115
AC@R2115
2
1K_0402_5%
<40> WLAN_ON 1 2 5
1
AC@ C2100 Q2010B AC@

4
0.1U_0402_16V7K DMN66D0LDW-7_SOT363-6
2
2 3VSWLAN_GATE
Q2010A AC@
1
4 4

SCHEMATIC,MB A7912
Custom C
4019ID
A B C D E
5 4 3 2 1
D D
C C
B B
A A

SCHEMATIC,MB A7912
5 4 3 2 1
A B C D E
Deafult use PCH side USB3.0 signal For USB2.0 ESD request
1 Deafult use PCH side USB3.0 signal 1

+5VALW +USB3_VCCA
R9 1 @ 2 0_0402_5%
C432 U17 W=60mils
PUSB3@ L3PUSB3@ .1U_0402_16V7K 1 8
GND VOUT
<17> PCH_USB3_TX1_N 2 1PCH_USB3_TX1_N_C 2 2 1 1 U3TXDN1 1 2 2 VIN VOUT 7
CI18 0.1U_0402_16V4Z 3 6 PUSB@
VIN VOUT
EPAD
PUSB3@ 4 5 1 R314 2
<44> SYSON# EN FLG USB_OC0# <17>
<17> PCH_USB3_TX1_P 2 1PCH_USB3_TX1_P_C 3 3 4 4 U3TXDP1 0_0402_5%
CI19 0.1U_0402_16V4Z R05 modify
OCE2012120YZF_0805 AP2301MPG-13_MSOP8
9
R10 1 @ 2 0_0402_5%
1
R11 1 @ 2 0_0402_5% C417
0.1U_0402_16V4Z
L4PUSB3@ 2 +USB3_VCCA
<17> PCH_USB3_RX1_N
PCH_USB3_RX1_N 2 2 1 1 U3RXDN1 W=60mils
R02 modify for ESD 1 2
470P_0402_50V7K
C391
PCH_USB3_RX1_P 3 4
<17> PCH_USB3_RX1_P 3 4 +
220U_6.3V_M
C390
U3RXDP1
OCE2012120YZF_0805
1
For ESD request
R12 1 @ 2 0_0402_5%
2
USB3.0 Conn.
D35 @
U3TXDP1 1 10 U3TXDP1 JUSB1
U3TXDP1 U3TXDP1 9
U3TXDN1 U3TXDN1 SSTX+
2 9 1 VBUS
2 U3TXDN1 2
U3TXDN1 8 SSTX-
U3RXDP1 4 7 U3RXDP1 U2DP0 3
U2DP0 D+
7 GND
1 PUSB@ 2 U2DP0 U3RXDN1 5 6 U3RXDN1 U2DN0 2 10
<17> USB20_P0 U2DN0 D- GND
R687 0_0402_5% U3RXDP1 U3RXDP1 6 11
L52 @ SSRX+ GND
3 4 GND GND 12
2 2 1 1 For USB2.0 ESD request 8
U3RXDN1 U3RXDN1 5 SSRX- GND 13
ACON_TARA4-9K1311
3 4 L05ESDL5V0NA-4 CONN@
3 4 D24 DC233007O00
WCM-2012-900T_0805 6 3 U2DN0
I/O4 I/O2
<17> USB20_N0 1 PUSB@ 2 U2DN0
R686 0_0402_5%
+USB3_VCCA 5 VDD GND 2

R03 modify
U2DP0 4 1
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
R04 modify
3 3
USB/B Conn. BT Conn. +3VS

R02 modify for ESD
+5VALW W=100mils
JUSB2 1
+5VALW +BT_VCC C731
(Port 0,2)
3
BT@
1
2
1 (Port 13) JBT1 BT_ON# 1 BT@ 2 2 Q41 1U_0603_10V6K
2 <18,37,40> BT_ON# 2
2 3 10 8 R710 BT@
C2070 3 GND 8 10K_0402_5%
4 4 7 7
0.1U_0402_16V4Z SYSON# 5 6 2
5 6 USB20_P11 <17>
6 5 C738 AP2301GN-HF_SOT23-3
USB20_N11 <17>
1
1 USB20_N2 6 5 (WLAN_BT_DATA) BT@
<17> USB20_N2 7 7 4 4
USB20_P2 8 3 (WLAN_BT_CLK) 0.1U_0402_16V4Z W=40mils
<17> USB20_P2 8 3 1
9 9 2 2 WL_EN# <18> +BT_VCC
USB20_N1 10 9 1
<17> USB20_N1 10 GND 1
1
USB20_P1 11 13 1
<17> USB20_P1 11 GND
12 14 ACES_87213-0800G C730 C729 R709
12 GND CONN@ BT@ BT@ 300_0603_5%
ACES_85201-1205N
BT Wire Cable Note: 4.7U_0603_6.3V6K
2
BT@
2
R05 modify CONN@ Pin 3, Pin 4 NC 0.1U_0402_16V4Z
1
2 Q42
G
4 SSM3K7002F_SC59-3 S 4
3
BT@

SCHEMATIC,MB A7912
Custom C
4019ID
A B C D E
A B C D E
+3VS
C714 R675 EC_MUTE# R317 2 @ 1 10K_0402_5%

22P_0402_50V8J 33_0402_5%
2 1 2 1 CLK_PCI_LPC
@
@
L21 +EC_VCC 1 930@ 2 +3VALW +5VS

+3VALW R2038
FBMA-L11-160808-800LMT_0603 R875 0_0402_5%
1 2 +3VALW_EC 1 2 +EC_VCCA 1 9012@ 2 +3VLP TP_CLK R363 1 2 4.7K_0402_5%
+3VALW R328 2 1 47K_0402_5% EC_RST# 1 1 1 1 2 2 1 R876 0_0402_5%
0.1U_0402_16V4Z
C418
0.1U_0402_16V4Z
C456
0.1U_0402_16V4Z
C728
0.1U_0402_16V4Z
C720
1000P_0402_50V7K
C400
1000P_0402_50V7K
C399
TP_DATA R364 1 2 4.7K_0402_5%
C431 2 0.1U_0402_16V4Z 0_0805_5% +EC_VCC C457
1
1 0.1U_0402_16V4Z +3VS 1
2 2 2 2 1 1 2
ECAGND
+3VALW BKOFF# R735 1 @ 2 10K_0402_5%
111
125
22
33
96
67
U20
9
R336 1 930@ 2 47K_0402_5% KSO1
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
EC_VDD0
R02 Modify
R339 1 930@ 2 47K_0402_5% KSO2 2 9012@ 1 +3VLP
R2085 200K_0402_5%
R682 1 2 1K_0402_5% EC_SMI# GATEA20 1 21 2 R2124 1 BT_ON# 2 930@ 1 +3VALW
<18> GATEA20 GATEA20/GPIO00 GPIO0F BT_ON# <18,37,39>
EC_KBRST# 2 23 BEEP# 0_0402_5% R676 200K_0402_5%
<18> EC_KBRST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# <42>
SERIRQ 3 26
<13> SERIRQ SERIRQ GPIO12 BT_LED# <37>
R359 1 2 2.2K_0402_5% EC_SMB_DA1 LPC_FRAME# 4 27 ACOFF 2 1 ACIN <15,44,47,48>
<13> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF <45>
LPC_AD3 5 D23 RB751V-40_SOD323-2
<13> LPC_AD3 LPC_AD3
LPC_AD2 7 PWM Output C452 2 1 100P_0402_50V8J ECAGND
<13> LPC_AD2 LPC_AD2
R358 1 2 2.2K_0402_5% EC_SMB_CK1 LPC_AD1 8 63 BATT_TEMP EC_ACIN C719 2 1 100P_0402_50V8J
<13> LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP <46>
LPC_AD0 10 LPC & MISC 64
<13> LPC_AD0 LPC_AD0 GPIO39
65 ADP_I
ADP_I/GPIO3A ADP_I <46,47>
R807 1 2 100K_0402_5% EC_PME# CLK_PCI_LPC 12 AD Input 66 AD_BID0
<17> CLK_PCI_LPC CLK_PCI_EC GPIO3B
PLT_RST_BUF# 13 75
<17,35,37> PLT_RST_BUF# PCIRST#/GPIO05 GPIO42
EC_RST# 37 76
R2110 1 AC@ EC_RST# IMON/GPIO43
2 4.7K_0402_5% WLAN_PME#
<18> EC_SCI#
EC_SCI# 20 EC_SCII#/GPIO0E
WLAN_ON 38 R367
<37> WLAN_ON GPIO1D
68 0_0402_5%
R2136 1 AC@ DAC_BRIG/GPIO3C
2 4.7K_0402_5% BT_LED#
EN_DFAN1/GPIO3D 70 EN_DFAN1
EN_DFAN1 <43> <52> VR_HOT#
VR_HOT# 2 1 H_PROCHOT# <5,46>
DA Output IREF/GPIO3E 71
KSI0 55 72
KSI0/GPIO30 CHGVADJ/GPIO3F D
1
KSI1 56
+3VS KSI2 KSI1/GPIO31 EC_MUTE# <42> H_PROCHOT#_EC Q26
57 KSI2/GPIO32 2
KSI3 58 83 EC_MUTE# G 2N7002H_SOT23-3
2 KSI3/GPIO33 EC_MUTE#/GPIO4A 2
R360 1 2 2.2K_0402_5% EC_SMB_CK2 KSI4 59 84 GPIO4B R2132 2 1 0_0402_5% LAN_PWR_EN# LAN_PWR_EN# <35> S
3
KSI5 KSI4/GPIO34 USB_EN#/GPIO4B WLAN_PME#
60 KSI5/GPIO35 CAP_INT#/GPIO4C 85 WLAN_PME# <37> R02 Modify
R361 1 2 2.2K_0402_5% EC_SMB_DA2 KSI6 61 PS2 Interface 86 EAPD
KSI6/GPIO36 EAPD/GPIO4D EAPD <42>
KSI7 62 87 TP_CLK Latest design guide suggest change to
KSI[0..7] KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <41>
KSO0 39 88 TP_DATA
<41> KSI[0..7] KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <41> 74LVC1G06.
R685 1 2 10K_0402_5% EC_SCI# KSO1 40 KSO1/GPIO21
KSO[0..17] KSO2 41
<41> KSO[0..17] KSO2/GPIO22 +3VALW
KSO3 42 97 VGATE
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 VGATE <15,52>
KSO4 43 98
KSO5 KSO4/GPIO24 WOL_EN/GPXIOA01 ME_EN
44 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 99 ME_EN <13> R02 Modify
R02 modify for ESD KSO6 45 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 109 2 @ 1 VCIN0_PH <46>
KSO7 46 SPI Device Interface R880 0_0402_5% LID_SW# R696 2 1 100K_0402_5%
KSO8 KSO7/GPIO27
47 KSO8/GPIO28 1 2 +3VLP
KSO9 48 119 R2063 10K_0402_5%
C2074 1 KSO9/GPIO29 SPIDI/GPIO5B R05 Modify
2 0.1U_0402_16V4Z PLT_RST_BUF# KSO10 49 KSO10/GPIO2A SPIDO/GPIO5C 120
KSO11 50 SPI Flash ROM 126
KSO12 KSO11/GPIO2B SPICLK/GPIO58
51 KSO12/GPIO2C SPICS#/GPIO5A 128
C2071 1 2 0.1U_0402_16V4Z PM_SLP_S3# KSO13 52 2 1
KSO14 KSO13/GPIO2D R691 100K_0402_5%
53 KSO14/GPIO2E
C2072 1 2 0.1U_0402_16V4Z PM_SLP_S4# KSO15 54 73 ENBKL
KSO16 KSO15/GPIO2F ENBKL/GPIO40 KB930_PECI ENBKL <16> R355 2 930@ 1 43_0402_1%
81 KSO16/GPIO48 PECI_KB930/GPIO41 74 H_PECI <5,18>
KSO17 82 89 FSTCHG
KSO17/GPIO49 FSTCHG/GPIO50 FSTCHG <47>
90 BATT_BLUE_LED#
BATT_CHG_LED#/GPIO52 BATT_BLUE_LED# <41>
91 GPU_OVERT R02 Modify
CAPS_LED#/GPIO53 GPU_OVERT <22>
EC_SMB_CK1 77 GPIO 92 PWR_LED
<46,47> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_LED <41>
X1 EC_SMB_DA1 78 93 BATT_AMB_LED#
<46,47> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_AMB_LED# <41>
32.768KHZ_12.5PF_CM31532768DZFT EC_SMB_CK2 79 SM Bus 95 SYSON
<14,22> EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <44,49>
EC_XCLK1 2 1EC_XCLK0 EC_SMB_DA2 80 121 VR_ON
<14,22> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON <52>
127 PM_SLP_S4#
@ PM_SLP_S4#/GPIO59 PM_SLP_S4# <15> R2059 1
1 1 2 10K_0402_5%
C723 C721
@ @ PM_SLP_S3# 6 100 PCH_RSMRST# Modify R05
3 <15> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 PCH_RSMRST# <15> 3
15P_0402_50V8J 15P_0402_50V8J PM_SLP_S5# 14 101 EC_LID_OUT# @ R891
2 2 <15> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <18>
EC_SMI# 15 102 2 0_0402_5%
1
R03 modify <18> EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 VCIN1_PROCHOT <46>
PCH_PWR_EN 16 103 H_PROCHOT#_EC
<44> PCH_PWR_EN GPIO0A H_PROCHOT#_EC/GPXIOA06
MINI1_LED# 17 104 GPXIOA07 R894 2 930@ 1 0_0402_5% PCH_PWROK
<37> MINI1_LED# GPIO0B VCOUT0_PH/GPXIOA07
GPU_HOT# 18 GPO 105 BKOFF#
<53> GPU_HOT# GPIO0C BKOFF#/GPXIOA08 BKOFF# <31>
<18,37> WL_OFF# WL_OFF#
2 1 19 GPIO 106 PBTN_OUT# R893 2 @ 1 0_0402_5% MAINPWON
GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# <15> MAINPWON <46,48>
R2125 0_0402_5% 25 107 GPU_ACIN
EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 GPU_ACIN <22> R02 Modify Modify R04
FAN_SPEED1 28 108 SA_PGOOD SA_PGOOD <51>
<43> FAN_SPEED1 EC_PME# FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
29
Board ID <35,37> EC_PME#
<37> E51TXD_P80DATA
E51TXD_P80DATA 30
EC_PME#/GPIO15
EC_TX/GPIO16
+3VALW E51RXD_P80CLK 31 110 EC_ACIN
<37> E51RXD_P80CLK EC_RX/GPIO17 AC_IN/GPXIOD01
Analog Board ID definition, R283 2 9012@ 10_0402_5% PCH_PWROK_901232 112 EC_ON
<15> PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <41,48>
PWR_SUSP_LED# 34 114 ON/OFF
<41> PWR_SUSP_LED# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFF <41>
2
Please see page 3. <41> WLAN_LED#

WLAN_LED# 36 GPI 115 LID_SW#
LID_SW# <41>
R354 NUM_LED#/GPIO1A LID_SW#/GPXIOD04 SUSP#
SUSP#/GPXIOD05 116 SUSP# <37,44,47,49,50>
Ra 100K_0402_5%
GPXIOD06 117 GPU_THERMAL_ALERT#
GPU_THERMAL_ALERT# <22>R02 Modify
PECI_KB9012/GPXIOD07 118
AGND/AGND
EC_XCLK1 122 KB9012_PECI R898 2 9012@ 1 43_0402_1% H_PECI

1
AD_BID0 EC_XCLK0 XCLKI/GPIO5D +V18R

GND/GND
GND/GND
GND/GND
GND/GND
<15> SUSCLK 1 2 123 XCLKO/GPIO5E V18R 124

R697 0_0402_5% 1
2
GND0
1 C398
R353 C454
Rb 100K_0402_5% 0.1U_0402_16V4Z
2
4.7U_0603_6.3V6K
R769 2 1 100K_0402_5% KB9012QF-A2_LQFP128_14X14
11
24
35
94
113
69
2 R03 Modify R04 Modify

20mil
1
L23 Co_lay NPCE885N Delete Co_lay NPCE885N

R04 modify 1 2 ECAGND 2 1 R02 Modify
FBMA-L11-160808-800LMT_0603
C834 20P_0402_50V8J
Follow KB930 checking List

+3VALW
4
R02 Modify 4
+3VALW
R2086 2 1 10K_0402_5% GPU_OVERT
1 2 GPIO4B R2087 2 1 10K_0402_5% GPU_THERMAL_ALERT#

R2133 10K_0402_5%
1 AC@ 2 WL_OFF#
R2126 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
1 @ 2 BT_ON# 2011/06/13 2012/06/13 Title
R2127 10K_0402_5%
SCHEMATIC,MB A7912
modify on LA7912 V0.3 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D E
1 2 3 4 5 6 7 8
ON/OFF BTN
+3VALW +3VLP
Test Only
2
Bottom Side
2
R144
100K_0402_5% R907
930@ 9012@
100K_0402_5%
1
@ SW1
SMT1-05-A_4P
+3VS 1 3 2
A ON/OFF <40> A
JKB1
2 4 ON/OFFBTN# 1
KSO0 1
KSO1 1 +3VS 51ON#
2 3 51ON# <45>
6
5
2
2
KSO2 3
KSO3 3 R496
4 4 D6
KSO4 5 10K_0402_5% CHN202UPT_SC70-3
KSO5 5 KSI[0..7]
6 6 KSI[0..7] <40> D
1
KSO6 7
1
7
5
KSO7 8 KSO[0..17] U8 EC_ON 2 Q7
8 KSO[0..17] <40> <40,48> EC_ON
KSO8 9 2 G SSM3K7002F_SC59-3
P
9 B CR_5IN1_LED# <35>
2
KSO9 10 MEDIA_LED# 4 S 930@
3
KSO10 10 Y R104
11 11 A 1 PCH_SATALED# <13>
G
KSO11 12 930@
KSO12 12 MC74VHC1G08DFT2G_SC70-5 10K_0402_5%
13
3
KSO13 13
14
1
14
KB Conn.
KSO14 15
KSO15 15
16 16
KSO16 17
KSO17 17
18 18
KSI0 19
KSI1 19
20 20
KSI2 21 LED3
21
PWR/B
KSI3 22
KSI4 22 @ MEDIA_LED#
23 23 +5VS 1 2 2 1
KSI5 24 24
R380 680_0402_5% A
KSI6 25 27
KSI7 25 G1 LTST-C191TBKT-CA_BLUE JPWR1
26 26 G2 28
1 1 +3VALW
LED7 2 LID_SW# LID_SW# <40>
ACES_85201-26051 2
3 3
CONN@ +3VS 1 2 2 1 4
B R2116 130_0402_5% A 4 B
5 5 +3VS
6 PWR_LED#
KSO16 C261 1 100P_0402_50V8J LTST-C191TBKT-CA_BLUE 6 ON/OFFBTN#
2 7 7
EMI request 8 8
KSO17 C262 1 2 100P_0402_50V8J 9
GND
+3VALW 1 2 GND 10
KSO15 C260 1 2 100P_0402_50V8J KSO7 C252 1 2 100P_0402_50V8J R2121 390_0402_5%
LED4 ACES_85201-0805N
KSO14 C259 1 2 100P_0402_50V8J KSO6 C251 1 2 100P_0402_50V8J CONN@
+3VS 1 @ 2 2 1 WLAN_LED#
WLAN_LED# <40>
KSO13 C258 1 2 100P_0402_50V8J KSO5 C250 1 2 100P_0402_50V8J R377 390_0402_5% A
KSO12 C257 1 2 100P_0402_50V8J KSO4 C249 1 2 100P_0402_50V8J LTST-C191KFKT-2CA_ORANGE
KSI0 C263 1 2 100P_0402_50V8J KSO3 C248 1 2 100P_0402_50V8J
KSO11
KSO10
C256 1
C255 1
2
2
100P_0402_50V8J
100P_0402_50V8J
KSI4
KSO2
C267 1
C247 1
2
2
100P_0402_50V8J
100P_0402_50V8J
LED6 R03 modify TP Conn.
+5VALW 1 @ 2 2 1 BATT_GRN_LED# BATT_BLUE_LED# <40> +5VS
KSI1 C264 1 2 100P_0402_50V8J KSO1 C246 1 2 100P_0402_50V8J R379 560_0402_5% A +3VS
JTP1 TP_VDD 0_0402_5% 2 1 R2099
1 2 LTST-C191TBKT-CA_BLUE 1 D_CK_SCLK TP_VDD 0_0402_5% 2 @ 1 R2100
1 D_CK_SCLK <11,12,14>
KSI2 C265 1 2 100P_0402_50V8J KSO0 C245 1 2 100P_0402_50V8J R2117 51_0402_5% 2 TP_VDD
LED2 2
3 3 TP_CLK <40>
KSO9 C254 1 2 100P_0402_50V8J KSI5 C268 1 2 100P_0402_50V8J 4
4 TP_DATA <40>
1 @ 2 2 1 BATT_AMB_LED# BATT_AMB_LED# <40> 5 LEFT_BTN#
KSI3 C266 1 100P_0402_50V8J KSI6 C269 1 100P_0402_50V8J R376 560_0402_5% A 5 RIGHT_BTN# GM@ GM@
2 2 6 6
7 C2102 C2103
KSO8 C253 1 100P_0402_50V8J KSI7 C270 1 100P_0402_50V8J LTST-C191KFKT-2CA_ORANGE 7 D_CK_SDATA 56P_0402_50V8K56P_0402_50V8K
2 2 +3VALW 1 2 8 8 D_CK_SDATA <11,12,14> 1 1
1
R2118 390_0402_5% 9
GND
1
C @ C
GND 10
C2101 GM@ C217 @
2
ACES_85201-0805N 56P_0402_50V8K 2 C2162
2
LED5 CONN@ 100P_0402_50V8J 100P_0402_50V8J
+5VALW 1 @ 2 2 1 PWR_LED#
R374 560_0402_5% A TP_CLK LEFT_BTN#
D_CK_SCLK
LTST-C191TBKT-CA_BLUE TP_DATA RIGHT_BTN# TP_VDD
+3VALW 1 2
3
R2119 51_0402_5% @ @ GM@ GM@
1
+5VS D4 D3 C2104 C2105
LED1 AZ5125-02S AZ5125-02S
1 56P_0402_50V8K56P_0402_50V8K
2
+3VALW 1 2 2 1 PWR_SUSP_LED# PWR_SUSP_LED# <40> C196
R378 390_0402_5% A 0.1U_0402_16V4Z
LTST-C191KFKT-2CA_ORANGE 2
LEFT_BTN#
1
R04 modify RIGHT_BTN#
GM@ GM@
1
PWR_LED# SW2 SW3 C2106 C2107
SMT1-05-A_4P SMT1-05-A_4P
LEFT_BTN# 3 1 RIGHT_BTN# 3 1 56P_0402_50V8K56P_0402_50V8K
2
D
1
4 2 4 2
<40> PWR_LED 2 Q32
G
5
6
5
6
2
S SSM3K7002F_SC59-3
3
R512
100K_0402_5%
D D
R04 modify
1
Delete SW5,SW6

SCHEMATIC,MB A7912
Custom C
4019ID
1 2 3 4 5 6 7 8
5 4 3 2 1
+VDDA
1 2
R711 0_0805_5%
+5VS
U40
60mil 1 IN
40mil
1
1 OUT 5 +VDDA
C737 2 R712
GND +3VS
4.75V 10K_0402_5%
0.1U_0402_16V4Z 3 4
1 2
2 SHDN BYP C741
2
G9191-475T1U_SOT23-5 0.01U_0402_16V7K 1 2
1
@ @ C739 1U_0402_6.3V6K
1
D30 R725
SM010014520 3000ma 220ohm@100mhz DCR 0.04 CH751H-40PT_SOD323-2 R728
D +PVDD_HDA (output = 300 mA) 10K_0402_5% 10K_0402_5% D
2
L46 2 1 0.1U_0402_16V4Z +PVDD_HDA C766
+VDDA
2
FBMA-L11-201209-221LMA30T_0805 MONO_IN
@ @
1
C748
1 20mil 1
1U_0402_6.3V6K
2
1
C745 C
10U_0603_6.3V6M C759 1 R723
<40> BEEP# 2 1 2 2 1 2
2
2 2 B Q44 R729
R02 Modify R713 1U_0402_6.3V6K 560_0402_5% E 2.4K_0402_1%
3
0_0603_5% 2SC2411K_SOT23-3
C771 1 R724
Place near Pin46 <13> PCH_SPKR 2 1 2
1
SM010014520 3000ma 220ohm@100mhz DCR 0.04 1U_0402_6.3V6K 560_0402_5%
D29
CH751H-40PT_SOD323-2
L50 2 1 0.1U_0402_16V4Z +PVDD1_HDA
+VDDA
FBMA-L11-201209-221LMA30T_0805 1 1 20mil HD Audio Codec
2
C749
C750
10U_0603_6.3V6M
2 2
R02 Modify
SM010030010 200ma 120ohm@100mhz DCR 0.2
Place near Pin39
SM010030010 200ma 120ohm@100mhz DCR 0.2
10mil +3VS_DVDD 10U_0603_6.3V6M L48 2 1
+AVDD_HDA +3VS
BLM18AG121SN1D_0603
L51 2 1 0.1U_0402_16V4Z 10mil 1

C754
1
C761
1
C753
Int. Speaker Conn.
+VDDA
BLM18AG121SN1D_0603 1 1 1
0.1U_0402_16V4Z 20mil
C756 C772 C752 2 2 2 JSPK1
C 10U_0603_6.3V6M 0.1U_0402_16V4Z SPKR+ L2003 1 SPK_R+ C
2 FBMA-L11-160808-800LMT_0603 1 1
2 2 2 SPKR- L2004 1
Place near Pin1, 9 2 FBMA-L11-160808-800LMT_0603 SPK_R- 2 2
R02 Modify 0.1U_0402_16V4Z
3
25
38
39
46
9
Place near Pin25, 38 U41 D2 3
AZ5125-02S G1
Internal MIC 4
DVDD
AVDD1
AVDD2
PVDD1
PVDD2
DVDD_IO
INT_MIC_R INT_MIC C770 1 LINE2_C_L G2
<43> INT_MIC_R 2 1 2 14 LINE2_L
R726 1K_0402_5% 4.7U_0603_6.3V6K ACES_88266-02001
C769 1 LINE2_C_R CONN@
1
C2054
2
1000P_0402_50V7K
2
4.7U_0603_6.3V6K
15 LINE2_R 35mA SPKL+
Combo MIC C765 1 2 MIC2_C_L 16
68mA 600mA SPK_OUT_L+ 40
COM_MIC MIC2_L
<43> COM_MIC 2 1 COM_MIC_R 4.7U_0603_6.3V6K
1
R719 1K_0402_5% C764 1 2 MIC2_C_R 17 41 SPKL-
4.7U_0603_6.3V6K MIC2_R SPK_OUT_L-
23 45 SPKR+ 20mil
LINE1_L SPK_OUT_R+
JSPK2
24 SPKL+ L2006 1 2 FBMA-L11-160808-800LMT_0603 SPK_L+ 1
LINE1_R SPKR- SPKL- L2005 1 1
SPK_OUT_R- 44 2 FBMA-L11-160808-800LMT_0603 SPK_L- 2 2
<43> MIC1_L MIC1_L C763 1 2 MIC1_C_L 21
4.7U_0603_6.3V6K MIC1_L HP_LEFT
External MIC HPOUT_L 32 HP_LEFT <43>
3
<43> MIC1_R MIC1_R C762 1 2 MIC1_C_R 22 3
4.7U_0603_6.3V6K MIC1_R HP_RIGHT D1 G1
HPOUT_R 33 HP_RIGHT <43> 4 G2
1 35 AZ5125-02S
CBN HDA_SDIN0_AUDIO 1 R721 ACES_88266-02001
SDATA_IN 8 2 HDA_SDIN0 <13>
C755 33_0402_5% CONN@
2.2U_0402_6.3V6M 36 5 HDA_SDOUT_AUDIO <13>
2 CBP SDATA_OUT
Combo MIC +MIC2_VREFO 29 MIC2_VREFO SYNC 10 HDA_SYNC_AUDIO <13>
10mil
1
RESET# 11 HDA_RST_AUDIO# <13>
Internal MIC 30 MIC1_VREFO_R
B
10mil BCLK 6 HDA_BITCLK_AUDIO <13> B
External MIC +MIC1_VREFO 31 MIC1_VREFO_L
10mil @
+INTMIC_VREFO 1 @ 2 1 2 C757
R717 0_0402_5% 22P_0402_50V8J
1 2 28 LDD_CAP
C760 10U_0603_6.3V6M 2 For EMI
GPIO0/DMIC_DATA
R02 Modify 3
GPIO1/DMIC_CLK
2 1 19 JDREF
R730 20K_0402_1% 4
PD# EC_MUTE# <40>
C758
HP_PLUG# 2 1 1 2 2.2U_0402_6.3V6M 34 12 MONO_IN
<43> HP_PLUG# R731 39.2K_0402_1% CPVEE PCBEEP
MIC_PLUG#
10mil
SENSE_A
<43> MIC_PLUG# 2 1 13 SENSE A MONO_OUT 20
R727 20K_0402_1% MIC2JD R718 1 271X@ 2 20K_0402_1% SENSE_B 18 37
SENSE B AVSS2
<40> EAPD
R715 1 271X@ 2 0_0402_5% EAPD_R 47 EAPD R02 modify for ESD
27 CODEC_VREF C767 1 2 0.1U_0402_16V4Z
VREF C768 1
48 SPDIFO 10mil 2 10U_0603_6.3V6M
@ C2073 1 2 0.1U_0402_16V4Z
2
7 DVSS AVSS1 26 Place next pin27

R2057
PVSS2 43 R03 modify
0_0402_5% 49 42 PJ21 PJ22
GND PVSS1 @ JUMP_43X39 @ JUMP_43X39
@
1 1 2 2 1 1 2 2
1
+MIC2_VREFO ALC271X-VB6-CG_QFN48_6X6
EAPD_R R2056 1 281X@ 2 0_0402_5%
DGND AGND PJ23 PJ24
@ JUMP_43X39 @ JUMP_43X39
1
1 1 2 2 1 1 2 2
MIC2JD R722
2.2K_0402_5% PJ25 PJ26
A @ JUMP_43X39 @ JUMP_43X39 A
D
1
1 1 2 2 1 1 2 2
2
271X@ Q43 2 1 2 COM_MIC

BSS138_NL_SOT23-3 G R720
S 1 22K_0402_5% GND GNDA GND GNDA
3
C746 R791
10U_0603_6.3V6M
2
22K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
1
R02 Modify
SCHEMATIC,MB A7912
Custom C
4019ID
5 4 3 2 1
Singatron 2SJ2326
C751
2 2
C747 Headphone
JHP1
Out DC021007151
R02 Modify 330P_0402_50V7K 330P_0402_50V7K <42> COM_MIC COM_MIC 3
FBMA-L11-160808-800LMT_0603 1 1
6
L49
HP_LEFT R716 1 2 47_0603_1% HPOUT_L_1 1 2 HPOUT_L_2 1 +INTMIC_VREFO
<42> HP_LEFT
L47
HP_RIGHT R714 1 2 47_0603_1% HPOUT_R_1 1 2 HPOUT_R_2 2 SM010004010 300ma 70ohm@100mhz DCR 0.3
<42> HP_RIGHT
1
FBMA-L11-160808-800LMT_0603 4
R394 For EMI
<42> HP_PLUG#
HP_PLUG# 5 10K_0402_5%
15mil 15mil
Int. MIC
L24 JMIC2
2
<42> INT_MIC_R INT_MIC_R 1 2 INT_MIC_L 1
SINGA_2SJ2326-001111 1
MIC_PLUG# FBMA-L11-160808-800LMT_0603 2
CONN@ 2
1
HP_PLUG# C500
3 G1
3
2
COM_MIC 220P_0402_50V7K 4
D28 +MIC1_VREFO 2 G2
AZ5125-02S ACES_88266-02001
3
CONN@
2
D26 D27 D1001
CH751H-40PT_SOD323-2 CH751H-40PT_SOD323-2 AZ5125-02S
1
1
INT_MIC_L
1
MIC JACK
3
R705 R708
4.7K_0402_5% 4.7K_0402_5% D16
FBMA-L11-160808-800LMT_0603 JMIC1 AZ5125-02S
2
L45 1 @
<42> MIC1_L MIC1_L 1 2 MIC1_L_1 1 2 MIC1_L_R 2
R707 1K_0603_5% L44
MIC1_R 1 2 MIC1_R_1 1 2 MIC1_R_R 3
<42> MIC1_R
R706 1K_0603_5% FBMA-L11-160808-800LMT_0603
3
4
1
1 1 MIC_PLUG# 5
<42> MIC_PLUG#
C732 C733
220P_0402_50V7K 220P_0402_50V7K
2 2 D25 6
AZ5125-02S
SINGA_2SJ-A960-C01
1
CONN@
FAN Stand-Off JUSB3 Stand-Off

H1 H2 H3 H7
H_3P4 H_3P4 H_3P4 H_3P4
@ @ @ @
1
FAN1 Conn H8
H_3P0
H9
H_3P0
H10
H_3P0
H11
H_3P0
H12
H_3P0
H13
H_3P0
H14
H_3P0
H15
H_3P0
H16
H_3P0
H17
H_3P5
H18
H_3P0
+5VS R02 Modify

C580 10U_0603_6.3V6M @ @ @ @ @ @ @ @ @ @ @
1
1 2
U30
1 EN GND 8
2 7 H19 H20
+VCC_FAN1 VIN GND H_4P0 H_4P0
3 VOUT GND 6
<40> EN_DFAN1 2 1 4 VSET GND 5
R509 300_0402_5% R02 Modify
1 APL5607KI-TRG_SO8 @ @
1
C598 C585
0.1U_0402_16V4Z 10U_0603_6.3V6M
2
1 2
+3VS C587
1000P_0402_50V7K H21 H22 H23 H24 R03 modify
1 2 H_4P2 H_4P2 H_4P2 H_4P2
1
H25 H26 H27 H28

R489 H_7P0N H_3P0N H_3P5X3P0N H_3P5N
10K_0402_5% @ @ @ @
1
1
40mil JFAN1 @ @ @ @
2
1
+VCC_FAN1
1
<40> FAN_SPEED1 2
3
1
C579 ACES_85205-03001 FD1 FD3 FD2 FD4
1000P_0402_50V7K CONN@
2 @ @ @ @
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

SCHEMATIC,MB A7912
Custom C
4019ID
A B C D E
+5VALW
+5VALW TO +5VS +1.5VSDGPUH to +1.5VSDGPU for GPU
2
+5VALW +1.5VSDGPUH +1.5VSDGPU R246
U22 +5VS U2 100K_0402_5%
DMN3030LSS-13_SOP8L-8 R02 Modify AO4430L_SO8
8 1 8 1
1
7 2 7 2 SUSP
<49> SUSP
2
4.7U_0603_6.3V6K
C468
6 3 2 1 6 3 1
2
4.7U_0603_6.3V6K
C465
4.7U_0603_6.3V6K
C464
2 2 5 R382 1 1 2 @ 2 @ 2 @ 5 2 @ 1 @ @ @
6
+ +
1U_0402_6.3V6K
C469
4.7U_0603_6.3V6K
C818
4.7U_0603_6.3V6K
C819
4.7U_0603_6.3V6K
C7
4.7U_0603_6.3V6K
C156
1U_0402_6.3V6K
C157
330U_2.5V_M_R15
C514
330U_B2_2.5VM_R15M
C826
470_0603_5% @ @ R26
1U_0402_6.3V6K
C824
.1U_0402_16V7K
C823
D
47_0603_5% 2 G Q27B
<37,40,47,49,50> SUSP#
4
1 2 @ @ S DMN66D0LDW-7_SOT363-6
1
1 1 2 2 1 1 1 1 2 2 R04 modify
1
1 R251 1
6
R2106 @ 10K_0402_5%
6
D
G
2 SUSP 10_0402_5%2 VGA_PWROK#
20mil 10mil S
10mil
2
2 1 5VS_GATE Q19B
+VSB
1
R372 DMN66D0LDW-7_SOT363-6 20mil +VSB 2 @ 1 1.5VSDGPU_GATE 2 1@ R2107 2 VGA_ON#
20K_0402_1% 1 R27 Q3A 0_0402_5%
3
C470 R04 modify R2104 @ 510K_0402_5% @ +5VALW

1
1
3
1
510K_0402_5%
D
SUSP 5 G 0.1U_0603_25V7K VGA_PWROK# 10_0402_5%2 C29 DMN66D0LDW-7_SOT363-6
R02 Modify
R28
S @
2
2 @R2105
@ R2105 @ 0.1U_0603_25V7K
4
Q19A VGA_ON# 2 R383

1 2 5
DMN66D0LDW-7_SOT363-6 0_0402_5% 100K_0402_5%
2
@ Q3B
4
D
1
1
<15,40,47,48> ACIN <39> SYSON#
ACIN 2 Q4
G SSM3K7002F_SC59-3
3
S @
3
D
SYSON 5 G Q27A
<40,49> SYSON S DMN66D0LDW-7_SOT363-6
1
R04 modify
+3VALW TO +3VS
4
@ PJ28 R373
2 1 100K_0402_5%
+3VALW 2 1
+3VS R02 modify for EMI
U21 JUMP_43X118
2
DMN3030LSS-13_SOP8L-8
8 1 @ PJ27 +5VALW +5VS +3VALW
7 2 +1.5V 2 1 +1.5VSDGPUH +5VALW
2 1
2
4.7U_0603_6.3V6K
C460
4.7U_0603_6.3V6K
C459
4.7U_0603_6.3V6K
C461
2 2 6 3 2 1
5 R369 JUMP_43X118 1 1
2
1U_0402_6.3V6K
C458
150_0603_5% C821 C822 1 1 1 1 1 1 DIS@

2 1U_0402_6.3V6K .1U_0402_16V7K R134 2
4
1 1 1 2
.1U_0402_16V7K
C2080
.1U_0402_16V7K
C2081
.1U_0402_16V7K
C2082
.1U_0402_16V7K
C2083
.1U_0402_16V7K
C2084
.1U_0402_16V7K
C2079
100K_0402_5%
1
2 2 R02 Modify
2 2 2 2 2 2
1
R368 10mil VGA_ON#
<51> VGA_ON#
6
20mil 47K_0402_5% D
+VSB 2 1 3VS_GATE G
2 SUSP
S
D
1
Q25B
1
1
3
C463 DMN66D0LDW-7_SOT363-6 2 Q8
D <14,17,25,51,53> VGA_ON
SUSP 5 G 0.1U_0603_25V7K G SSM3K7002F_SC59-3
2
S S DIS@
3
2 DIS@
4
Q25A R04 modify Use 100k to make sure the R135

DMN66D0LDW-7_SOT363-6 100K_0402_5%
+3VALW TO +3VALW(PCH AUX Power) divided voltage is enough!!
1
+3VALW J11 @
1 2 +3VALW_PCH
1 2
JUMP_43X79 +3VALW
U2006 40mil
+1.5V to +1.5VS SI4178DY-T1-GE3_SO8
2
+1.5V +1.5VS 8 1 R2103
U12 7 2 100K_0402_5%
2
AO4430L_SO8 6 3
1
10U_0805_10V4Z
C2057
1U_0603_10V6K
C2058
8 1 5
1
1
4.7U_0603_6.3V6K
C339
7 2 2 1 C2056 R2073
2
0.1U_0402_16V4Z
C377
0.1U_0402_16V4Z
C376
6 3 470_0603_5% VGA_PWROK#
<51> VGA_PWROK#
2
4.7U_0603_6.3V6K
C375
4.7U_0603_6.3V6K
C374
1U_0402_6.3V6K
C338
2 2 1 1 5 R245 10U_0805_10V4Z
3 1
3 470_0603_5% 3
D
1
1 2 Q2008
4
<51,53> VGA_PWROK 2 2N7002E_SOT23-3

1
1 1 2 2 G
20mil 10mil PCH_PWR_EN#
5 S
3
6
D +VSB R2074 2 1 200K_0402_5% 3V_GATE

G
2 SUSP Q2003B
4
6
20mil 10mil S DMN66D0LDW-7_SOT363-6
1
2 1 1.5VS_GATE Q15B Modify R05
+VSB
1
R269 DMN66D0LDW-7_SOT363-6 C2059

200K_0402_5% 1 PCH_PWR_EN# 2 0.1U_0603_25V7K
2
1
@ C380 R04 modify

3
510K_0402_5%
R268
D
0.1U_0603_25V7K Q2003A 1
SUSP 5 G DMN66D0LDW-7_SOT363-6
S 2 Modify R03 +5VALW
4
Q15A
2
U46 R2075
+3VALW 1 14 +3VS 100K_0402_5%
D VIN1 VOUT1
1
2 VIN1 VOUT1 13
<15,40,47,48> ACIN ACIN 2 Q21 47K_0402_5% C953
1
G @ SUSP# 2 R927 1 3VS_ON 3 12 2 @1 330P_0402_50V7K
SSM3K7002F_SC59-3 @ C951 ON1 CT1 PCH_PWR_EN#
S <20,35> PCH_PWR_EN#
3
1@ 2 +5VALW 4 VBIAS GND 11

0.1U_0402_16V4Z
D
1
2 R926 1 5VS_ON 5 10 2 1 Q2004
@ 20K_0402_1% ON2 CT2 @ 330P_0402_50V7K 2N7002E_SOT23-3
<40> PCH_PWR_EN 2
C952 +5VALW 6 9 C954 G
VIN2 VOUT2
1
1@ 2 7 8 +5VS S
3
+0.75VS +1.05VS_VTT +1.8VS +1.5V 0.1U_0402_16V4Z VIN2 VOUT2
15 R2076
4 GPAD 100K_0402_5% 4
1
@ TPS22966DPUR_SON14_2X3~D
2
R366 R29 R508 @ R365
22_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
Modify R02
Reserved
1 2
1 1
1 1
1 1
Q24
D Q23 D Q5 D Q34 D @
2 SUSP 2 SUSP 2 SUSP 2 SYSON# Security Classification Compal Secret Data Compal Electronics, Inc.
G G G G 2011/06/02 2012/06/02 Title
SSM3K7002F_SC59-3 SSM3K7002F_SC59-3 SSM3K7002F_SC59-3 SSM3K7002F_SC59-3
S S S S
SCHEMATIC,MB A7912
3
Custom C
4019ID
A B C D E
A B C D
VIN
1
PL1 Pre_CHG 1
PJP1 SMB3025500YA_2P
DC_IN_S1 1 2 DC_IN_S2 PR1
1 1K_1206_5%
2
3 1 2
PQ1
4 PR2 PD1 TP0610K-T1-E3_SOT23-3
GND
1
VIN 1K_1206_5% LL4148_LL34-2
GND PC1 PC2 PC3 PC4 1 2 2 1 3 1
B+
ACES_50305-00441-001 1000P_0402_50V7K 100P_0402_50V8J 100P_0402_50V8J 1000P_0402_50V7K
2
PR3
1K_1206_5%
1 2
100K_0402_5%
100K_0402_5%
1
1
PR4
PR5
PR6
1K_1206_5%
2
1 2
1
PR7
1
100K_0402_5%
PD2 PQ2
BAS40CW_SOT323-3 PDTC115EU_SOT323
1 2
<40> ACOFF 2
1 2
2
+5VALWP 3 PQ3 2
PDTC115EU_SOT323
3
PJ1 PJ2
+3VALWP 1 1 2 2 +3VALW +5VALWP 1 1 2 2 +5VALW
VIN JUMP_43X118 JUMP_43X118
2
@ PD3
LL4148_LL34-2 @ PJ3 PJ4
+VSBP 1 1 2 2 +VSB +1.5VP 1 1 2 2 +1.5V
930@ PD4
1
3
LL4148_LL34-2 @ PJ10 JUMP_43X39 JUMP_43X118 3
2 1 1 2 PJ5
1 2
1
BATT+ JUMP_43X39 @ PR8

@PR8 @ PR9
@PR9
1 1 2 2
68_1206_5% 68_1206_5% JUMP_43X118
930@ PQ4
TP0610K-T1-E3_SOT23-3
2
N1 3 1
VS @ PJ6 PJ7
+1.8VSP 1 1 2 2 +1.8VS +1.05VS_VCCPP 1 1 2 2 +1.05VS_VTT
1
930@ PR10 @ PC6

@PC6 JUMP_43X79 JUMP_43X118
100K_0402_1% 930@ PC5 0.1U_0603_25V7K PJ8
0.22U_0603_25V7K 1 1 2 2
2
930@ PR11
2
22K_0402_1% JUMP_43X118
1 2 @ PJ9
<41> 51ON# 1 2
+0.75VSP 1 2 +0.75VS
JUMP_43X79
PJ11 PJ19
+VCCSAP 1 1 2 2 +VCCSA +1.05VS_DGPUP 1 1 2 2 +1.05VSDGPU
+3VLP
JUMP_43X118 JUMP_43X118
PR12
4
0_0402_5% 4
1 2 PJ18
+CHGRTC +1.5VSDGPUP 1 1 2 2 +1.5VSDGPU
JUMP_43X118

SCHEMATIC,MB A7912
Size Document Number
Rev
A B C D
A B C D
+3VLP
VMB
CONN@ PJP2 PL2
SUYIN_200275GR008G13GZR
BATT+ <45,47>
SMB3025500YA_2P
BATT_S1
1 1 1 2
1
2 2 PI @ PC7
3 3
1
TH PR20 0.1U_0603_25V7K
4 4
2
1
EC_SMCA 6.49K_0402_1% PC8 PC9
5 5 EC_SMDA 1000P_0402_50V7K 0.01U_0402_25V7K @ PR13 @ PR14
6 2 1 +3VALWP
2
6
1
PR19 10K_0402_1% 10K_0402_1%
7 7
1
PR17 1K_0402_5%
8 8
2
1 1
100_0402_1% PR21
GND 9
1
PR15 1K_0402_1% @PU1
@ PU1
GND 10 100_0402_1% @ PR16
1 2 BATT_TEMP <40> 1 8
2
2
100K_0402_1% VCC TMSNS1
1 2 EC_SMB_CK1 <40,47> 2 GND RHYST1 7 2 1
PR102
1
0_0402_5% MAINPWON 3 6 @ PR18
EC_SMB_DA1 <40,47> OT1 TMSNS2
<40,48> MAINPWON 47K_0402_1%
4 5 @PH2
@ PH2
OT2 RHYST2 100K_0402_1%_NCP15WF104F03RC
G718TM1U_SOT23-8
2
VL VS +3VALWP
VS
1
2
H_PROCHOT# @ PR22 @ PR23 2
47K_0402_1% 10K_0402_1%
2
8
@ PC10
D
8
0.022U_0402_16V7K 3 TH @ PU2B
P
PQ5A + LM393DR_SO8
2 2 1 1 5
P
DMN66D0LDW-7_SOT363-6 G O +
- 2 7 O
G
@ PU2A 6
-
G
S LM393DR_SO8
4
@ PD5
4
1
LL4148_LL34-2 @ PR24
1
1.5M_0402_5%
@ PC11 @ PR25
2
100P_0402_50V8J 100K_0402_1%
2
PQ6
TP0610K-T1-E3_SOT23-3
PH1 under CPU botten side :

B+ 3 1 +VSBP
CPU thermal protection at 92 degree C
0.22U_0603_25V7K
0.1U_0603_25V7K
1
Recovery at 56 degree C
1
1
PC12
PC13
PR26 +3VLP
100K_0402_1%
2
3 3
PR27 @
2
VL 22K_0402_1% ADP_I <40,47>

2 1
65W@ PR33
1
3.92K_0402_1%
1
PC14 PR29
PR28 0.1U_0603_25V7K 21K_0402_1%
2
1
1
100K_0402_1%
2
PR34 PR31 PU3
D
2
1K_0402_5% PQ7 100K_0402_1% @ PR32 1 8 90W@ PR33

100K_0402_1% VCC TMSNS1 8.87K_0402_1%
1 2 2
2
<48> SPOK G <5,40> H_PROCHOT# 2 7 2 1 1 2 VCIN0_PH <40>
2
GND RHYST1 PR35 @ PR37
2N7002KW_SOT323-3
1
S MAINPWON 3 6 9.53K_0402_1% 0_0402_5%

D
3
~OT1 TMSNS2
3
PC15
1U_0402_6.3V6K PQ5B 5 4 5 1 2 1 2
2
DMN66D0LDW-7_SOT363-6 G ~OT2 RHYST2 @ PR57

G718TM1U_SOT23-8 90W@ PR36 <40>
0_0402_5% VCIN1_PROCHOT
S 16.2K_0402_1%
4
1
65W@ PR36
100K_0402_1%_NCP15WF104F03RC
1
1
10.5K_0402_1%
9012@ PC17 PR38
For 65W adapter==>action 70W , Recovery 54W 1000P_0402_50V7K 10K_0402_1%
PH1
2
2
For 90W adapter==>action 97W , Recovery 75W
4 4

SCHEMATIC,MB A7912
Rev
A B C D
A B C D
for reverse input protection

D
1
2 PQ8
G SI1304BDL-T1-E3_SC70-3
S
3
1 2 1 2
1 PR39 PR40 1
1M_0402_5% 3M_0402_5%
VIN P1 P2 PR41 B+ CHG_B+

PQ9 PQ10 0.02_2512_1% PL3 PQ11
AO4466L_SO8 AO4466L_SO8 1.2UH_PNS40201R2YAF_3A_30% AO4466L_SO8
8 1 1 8 1 4 1 2 8 1
2200P_0402_50V7K
7 2 2 7 7 2
0.1U_0402_25V6
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
6 3 3 6 2 3 6 3
0.1U_0402_25V6
5 5 5
0.01U_0402_50V7K
1
1
0_0402_5%
PC21
PC22
PC23
PC24
PR42
1
VIN
0_0402_5%
PC16
PR43
4
4
1
PC25
PC26 PC87 PC86
PC27
2
1
@ 2 0.1U_0402_25V6 @ 0.1U_0402_25V6 0.1U_0402_25V6
2
1 2 @
2
2
0.1U_0402_25V6
PD6
BAS40CW_SOT323-3
1
BQ24725_BATDRV 1 2
PC28
PR44
1
4.12K_0603_1%
4.12K_0603_1%
PC29 4.12K_0603_1%
0.047U_0402_25V7K
1
1 2
PR45
PR46
5
10_1206_1%
2.2_0603_5%
1
VIN
PR48
PR47
0.1U_0603_25V7K
2
2
1
2 PR50 PQ12 2
1
@ PR49 2.2_0402_5% SIS412DN-T1-GE3_POWERPAK8-5
BQ24725_ACN
PC30
BQ24725_ACP
BQ24725_BST 2
1
3.3_1210_5% DH_CHG 1 2DH_CHG-1 4
2
PC31 PD7
BQ24725_LX
2
1 2 RB751V-40_SOD323-2 BATT+
1 2
DH_CHG
1U_0603_25V6K PC33 PL4 PR52
3
2
1
1 2 10UH_FDVE1040-H-100M=P3_6.5A_20% 0.01_1206_1%
@ PR51 BQ24725_LX 1 2 CHG 1 4
3.3_1210_5% 1U_0603_25V6K
5
20
19
18
17
16
SIS412DN-T1-GE3_POWERPAK8-5
2 3
2
CSOP1
4.7_1206_5%
PU4
2200P_0402_50V7K
0.01U_0402_50V7K
CSON1
1
PHASE
HIDRV
BTST
VCC
REGN
PR53
10U_0805_25V6K
10U_0805_25V6K
1
21
0.1U_0402_25V6
0.1U_0402_25V6
@ PC32 PAD
PC39
PC36
PC34
PC35
1
1
PQ13
2.2U_0805_25V6K 1 15 DL_CHG 4
2
ACN LODRV
PC37
PC38
2
2
2 14
680P_0402_50V7K
ACP GND PR54
3
2
1
2
1
BQ24725ARGRR_VQFN20_3P5X3P5 10_0603_5%
PC40
BQ24725_CMSRC 3 13 SRP 1 2 CSOP1
CMSRC SRP
2
0.1U_0603_25V7K
BQ24725_ACDRV 4 12 SRN 1 2 CSON1
2
ACDRV SRN
PC41
PR55
6.8_0603_5%
+3VLP 1 2 5 11 BQ24725_BATDRV
PR56 ACOK ACDET BATDRV
100K_0402_1%
IOUT
3 3
SDA
SCL
ILIM
<15,40,44,48> ACIN
Pre_CHG +3VALW
6
10
ACDET
1
1 2
0.01U_0402_25V7K
PD9 PR58
1
100K_0402_1%
RB751V-40_SOD323-2 316K_0402_1%
1
PR59 VIN PR60
PC42
PR61
1
2M_0402_1% 280K_0603_0.1%
2
1 2
Vin Dectector
2
2
2
1
1
PR62
PR63
154K_0603_0.1%
Min. Typ Max.
2M_0402_1% L-->H 17.852V 18.063V 18.275V
H-->L 17.476V 17.687V 17.898V
2
1 2
ACDET
ILIM and external DPM

0.1U_0402_16V7K
EC_SMB_CK1 <40,46>
1
PR64
PC43
100K_0402_1% PR65
<40> FSTCHG 1 2 2 PQ14 66.5K_0603_0.1%
Min. Typ Max.
2
PDTC115EUA_SC70-3
EC_SMB_DA1 <40,46>
PR66 3.906A 4.006A 4.108A
2
PQ15 0_0402_5%
D
1
4 2N7002KW_SOT323-3 2 1 1 2 4
ADP_I <40,46>
3
7,40,44,49,50> SUSP# 2
1
G PC44 @ PC45
100P_0402_50V8J 0.1U_0402_16V7K
S Close EC
3

SCHEMATIC,MB A7912
Custom C
4019ID
A B C D
5 4 3 2 1
Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
2VREF_8205
1U_0603_10V6K
D D
1
PC46
2
PR67 PR68
13.7K_0402_1% 30K_0402_1%
1 2 2 1
PR69 PR70
RT8205_B+ 20K_0402_1% 20K_0402_1% RT8205_B+
2 1 1 2
B+
PL5 Typ: 175mA
SUPPRE_ FBMA-L11-453215-800LMA90T_1812
1 2 +3VLP
ENTRIP2
ENTRIP1
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0603_25V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.1U_0603_25V7K
PR71 PR72
560P_0402_50V7K
560P_0402_50V7K
SIS412DN-T1-GE3_POWERPAK8-5
174K_0402_1% 174K_0402_1%
PC49
PC57
4.7U_0805_10V6K
2 1 1 2
1
1
PC47
PC48
PC50
PC51
PC52
PC55
PC56
PC53
5
5
PU5
2
2
PQ16
PC54
ENTRIP2
FB2
TONSEL
REF
FB1
ENTRIP1
1
25 P PAD PQ17
2
C SIS412DN-T1-GE3_POWERPAK8-5 C
4 4
7 VO2 VO1 24
SPOK <46>
8 23 PR74 PC59
PR73 VREG3 PGOOD 2.2_0603_5% 0.1U_0603_25V7K
1
2
3
3
2
1
2 1 2 1 BST_3V 9 BOOT2 BOOT1 22 BST_5V 1 2 1 2
PL6 PC58
2.2_0603_5%
UG_3V 10
VFB=2.0V 21 UG_5V PL7
4.7UH_FDSD0630-H-4R7M-P3_5.5A_20% 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1
1
4.7_1206_5%
4.7_1206_5%
LG_3V 12 19 LG_5V
LGATE2 LGATE1
5
PR75
PR76
SKIPSEL
PQ18
VREG5
SI7716ADN-T1-GE3_POWERPAK8-5
GND
VIN
@ RT8205LZQW(2) WQFN 24P PWM @
NC
EN
1 1
2
2
4
PC60 + 4 PC62 +
13
14
15
16
17
18
1
1
680P_0402_50V7K
680P_0402_50V7K
PC61
220U_6.3V_M PR77 PQ19 330U_6.3V_M
PC63
PD10 499K_0402_1% SI7716ADN-T1-GE3_POWERPAK8-5
2 2
B+ 1 2 1 2
2
1
2
3
2
@
3
2
1
GLZ5.1B_LL34-2 @
1
150K_0402_1%
1U_0603_10V6K
VL
1
PC64
1
Typ: 175mA
PR78
PC65
4.7U_0805_10V6K
2
ENTRIP1 ENTRIP2
2
2
RT8205_B+
1
B RT8205 B
0.1U_0603_25V7K
D D 2VREF_8205 TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
6
2
(2)SMPS2=375KHZ(+3VALWP)
PC66
PQ20A 2 5 PQ20B
DMN66D0LDW-7_SOT363-6 G G DMN66D0LDW-7_SOT363-6
TPS51125A
S S TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP)
1
(2)SMPS2=305KHZ(+3VALWP)
3.3VALWP Delta I = 1.5836A (Freq=305KHz)
PR79 Iocp = 7.4965A ~ 10.349A
100K_0402_1% 5VALWP Delta I = 2.6342A (Freq=245KHz)
VL 2 1 Iocp = 7.4965A ~ 10.349A
9012@ PR100
9012@PR100
2.2K_0402_5%
1 2
<40,41> EC_ON
PR80
0_0402_5% +3.3VALWP Ipeak=7A ; Imax=4.9A +5VALWP Ipeak=7A ; Imax=4.9A
1
1 2
<40,46> MAINPWON Delta I=1.5836A=>1/2Delta I=0.7918A (F=375K Hz) Delta I=2.6342A=>1/2Delta I=1.3171A (F=300K Hz)
930@ PD11 930@ PR81 Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
LL4148_LL34-2 1M_0402_1%
2 1 1 2 2 PQ21 Ilimit_min=(174K*10uA)/(10*18m*1.2)=7.4965A Ilimit_min=(174K*10uA)/(10*18m*1.2)=7.4965A
VIN Ilimit_max=(174K*10uA)/(10*15m*1.2)=10.349A Ilimit_max=(174K*10uA)/(10*15m*1.2)=10.349A
ACIN
PDTC115EUA_SC70-3
402K_0402_1%
1U_0603_10V6K
Iocp=Ilimit+1/2Delta I=7.4965A~10.349A Iocp=Ilimit+1/2Delta I=7.4965A ~ 10.349A

1
930@ PR82
PC67
930@ PR83
3
316K_0402_1%
1 2
VS
2
930@ PR84
2
1
10K_0402_1%
930@ PR85
A 1M_0402_1% A
VL 1 2
D
1
3 2
2
VS G D
5 930@ PQ23B
2 930@ PQ22 S 930@ PQ23A G DMN66D0LDW-7_SOT363-6 Security Classification Compal Secret Data Compal Electronics, Inc.
1
PDTC115EUA_SC70-3DMN66D0LDW-7_SOT363-6 2011/06/02 2012/06/02 Title

S
SCHEMATIC,MB A7912
4
3
5 4 3 2 1
A B C D
PL8
1.5V_B+ 2 1 B+
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
1
PC68
PC69
PC70
MDU1516URH_POWERDFN56-8-5
560P_0402_50V7K
2
1
+1.5VP 1
PQ24
4
1 1
PJ13
3
2
1
JUMP_43X79
2
PR86 PC71 PL9
BST_1.5V
2
UG_1.5V
2.2_0603_5% 0.1U_0603_25V7K 0.36UH_PDME104T-R36MS0R825_37A_20%
LX_1.5V
1 2 BST_1.5V-1 1 2 1 4
+0.75VSP +1.5VP
MDU1511RH_POWERDFN56-8-5
靠近Output Cap PAD
10U_0805_25V6K
10U_0805_25V6K
2 3
1
5
DCR: 0.82mΩ±5%
20
19
18
17
16
1
1
PC72
PC73
PU6 @ PR87
@PR87
4.7_1206_5% 1
VTT
VLDOIN
BOOT
UGATE
PHASE
PQ25
21
2
2
PAD + PC74
1 15 LG_1.5V 4 330U_6.3V_M
VTTGND LGATE
1
@ PC75
@PC75 2
2 14 Rds=2.7mΩ(Typ) 680P_0402_50V7K
2
VTTSNS PGND PR88
3.3mΩ(Max)
3
2
1
9.1K_0402_1%
3 GND CS 13 2 1
RT8207MZQW_WQFN20_3X3
4 12
2
+VTT_REFP VTTREF VDDP
2
5 11 2 1
+1.5VP VDDQ VDD
+5VALW
PGOOD
PR89
+3VALW
1
1U_0603_10V6K
5.1_0603_5%
TON
PC76
FB
S3
S5
0.033U_0402_16V7K
2
1
10K_0402_5%
PC77
6
10
PR90
PC78
1U_0603_10V6K
S3_1.5V
S5_1.5V
2
PR91
267K_0402_1% @
2
<37,40,44,47,50> SUSP# 1 2 PGOOD_1.5V
PR92 PR93
0_0402_5% 887K_0402_1%
<40,44> SYSON 1 2 2 1 1.5V_B+
D
1
@ PR94
1
<44> SUSP 2
G
PC325
0.1U_0402_16V7K
@ PC79
0.1U_0402_16V7K
5.9K_0402_1%
2 1
2
PQ27 S FB=0.75V
3
2N7002KW_SOT323-3
To GND = 1.5V
PR95 To VDD = 1.8V
5.76K_0402_1%
2
FB=0.6V
3
STATE S3 S5 1.5VP VTT_REFP 0.75VSP Note:Iload(max)=3.5A
3
@ PJ14
@PJ14 PU7 PL10
4
S0 Hi Hi On On On +3VALW
JUMP_43X79
1 1
SY8033BDBC_DFN10_3X3
LX_1.8V
1UH_NRS4018T1R0NDGJ_3.2A_30%
2 2 10 PVIN 2 1 2
PG
LX +1.8VSP
Off
S3 Lo Hi On On
68P_0402_50V8J
9 3
(Hi-Z) PVIN LX
1
4.7_1206_5%
22U_0805_6.3VAM
22U_0805_6.3VAM
PC81
PC80 8 SVIN
1
PR96
22U_0805_6.3VAM PR97
2
S4/S5 Lo Lo Off Off Off
PC82
PC83
6 20K_0402_1%
2
FB
5
(Discharge) (Discharge) (Discharge)
2
PR257 EN
NC
NC
TP
100K_0402_1% FB_1.8V
SUSP# 1 2 +1.8VSP_ON
11
1
Note: S3 - sleep ; S5 - power off
0.1U_0402_16V7K
1
680P_0402_50V7K
PC84
1
PC85
47P_0402_50V8J
PR98 PR99
PC90
1M_0402_5% 10K_0402_1%
2
2
2
2 @
Notice: Internal resistance about 500K on 2nd EN pin
4 4

SCHEMATIC,MB A7912
Rev
A B C D
5 4 3 2 1
+3VS VFB= 0.704V

Vo=VFB*(1+PR116/PR119)= 1.05V
Freq= 266~314KHz , 290KHz(typ)
1
PR261 PL13
10K_0402_1% Cesr= 15m ohm FBMA-L11-322513-151LMA50T_1210
Ipeak= 15.37A Imax= 10.759A +1.05VS_VTTP_B+ 2 1
Delta I= 3.4368A ==>1/2 Delta I= 1.7184A B+
2
PR101
0_0402_5% Vtrip=Rtrip*10uA= 0.255V
5
2 1 Iocp= 19.108A~29.416A
MDV1525URH_PDFN33-8-5
<51> VCCPPWRGOOD
2200P_0402_50V7K
0.1U_0402_25V6
4.7U_0805_25V6-K
4.7U_0805_25V6-K
D D
1
PQ29
PC95
PC96
PC97
PC98
@ PR274
0_0402_5% 4
2
2
PR111 PC99
3
2
1
PU9 2.2_0603_5% 0.1U_0603_25V7K
PR112 1 10 BST_+1.05VS_VTTP 1 2 1 2
38.3K_0402_1% PGOOD VBST
PR113 2 1 TRIP_+1.05VS_VTTP2 9 UG_+1.05VS_VTTP PL14
330K_0402_1% TRIP DRVH 1UH_MMD-10DZ-1R0M-X1A_18A_20%
<37,40,44,47,49> SUSP# 1 2 EN_+1.05VS_VTTP 3
EN SW 8 SW_+1.05VS_VTTP 1 2 +1.05VS_VCCPP
5
FB_+1.05VS_VTTP 4 7 +1.05VS_VTTP_5V
PC100 VFB V5IN
+5VALW PQ30
1
0.1U_0402_16V7K RF_+1.05VS_VTTP 5 6 LG_+1.05VS_VTTP MDU1511RH_POWERDFN56-8-5 1
2
TST DRVL
1
11 @ PR115 + PC102
TP PC101 4.7_1206_5% 330U_6.3V_M
4
PR114 TPS51212DSCR_SON10_3X3 1U_0603_10V6K PR276
1
470K_0402_1% 2 0_0402_5%
PC103 1 2 VSSIO_SENSE <8>
1
Rds=2.7mΩ(Typ) @ PC104 0.1U_0402_16V7K
3
2
1
2
680P_0402_50V7K
3.3mΩ(Max)
2
C C
PR116
VFB=0.7V 4.99K_0402_1%
2 1
PC105 PR117 PR118

1000P_0402_50V7K 1.2K_0402_1% 100_0402_1%
1
2 1 2 1 1 2 VCCIO_SENSE <8>
PR119
10K_0402_1%
2
B B
A A

SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1
+3VALW
VID [0] VID[1] VCCSA Vout
1
GPU@ PC328
1U_0402_6.3V6K The 1k PD on the VCCSA VIDs are empty.
0 0 0.9V
0 1 0.8V
2
+1.5VSDGPU These should be stuffed to ensure that
GPU@ PU16
+3VS VCCSA VID is 00 prior to VCCIO stability.
1 0 0.725V
APL5930KAI-TRG_SO8
6
5
VCNTL
3 PR121
1 1 0.675V
VIN VOUT +1.05VS_DGPUP
100K_0402_5%
9 4 1K_0402_5%
VIN VOUT
1
2 1 output voltage adjustable network
1
D D
GPU@ PC329 8 GPU@ PR259
EN
PR120
4.7U_0603_6.3V6K 7 2 1.91K_0402_1% GPU@ PC326
GND
POK FB 0.022U_0402_25V7K GPU@ PC330
1
FB=0.8V 22U_0805_6.3V6M
H_VCCSA_VID1 <9>
2
1
2
GPU@ PR263 GPU@ PR277
+VCCSA_PWRGD
1
18K_0402_1% 47_0603_5%
1 2
2
<44,53> VGA_PWROK GPU@ PR260
+VCC_SAP
@ PR258 6.04K_0402_1%
H_VCCSA_VID0 <9>
18K_0402_1% TDC 4.2A
2
1 2
<14,17,25,44,53> VGA_ON PR122 Peak Current 6A
1
GPU@ PR264 1K_0402_5%
GPU@ PC327
1
@ PR270 0_0402_5%
<40> SA_PGOOD
2 1 OCP current 7.2A
1U_0402_6.3V6K 22K_0402_5% 1 2
<44> VGA_PWROK# @ PR266
D
2
1
0_0402_5%
+VCCSA_VID1
+VCCSA_VID0
1U_0603_10V6K
<44> VGA_ON#
1 2 2
G +5VALW
+VCCSA_PWRGD
2
GPU@ PQ50 S
PC106
3
2N7002KW_SOT323-3 PR123 PR124
10_0402_1% 0_0402_5%
1
2 1 +VCCSA_EN 1 2 VCCPPWRGOOD <50>
PC107
Ien=10uA, Vth=0.3V, notice 2.2U_0603_10V7K
1 2
the res. and pull high
voltage from HW
18
17
16
15
14
13
PU10
PR125 PC108
V5DRV
V5FILT
PGOOD
VID1
VID0
EN
0_0603_5% 0.22U_0603_16V7K
BST 12 1 2+VCCSA_BT_1 1 2
19 PL15
PGND 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
C
SW 11 +VCCSA_PHASE 1 2 +VCCSAP C
20 PGND
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2200P_0402_50V7K
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
.1U_0402_16V7K
SW 10
2200P_0402_50V7K
@PR126
@PR126
0.1U_0603_25V7K
21 PGND
2
PC110
PC111
PC112
PC113
PC114
PC115
PC116
PC117
10U_0805_25V6K
10U_0805_25V6K
4.7_1206_5%
TPS51461RGER_QFN24_4X4 9
SW
1 22
1
VIN
2
PC118
PC119
PC120
PC121
8 @ @ @ @
SW
1
23 @ PC109
1
2 VIN 680P_0402_50V7K
PJ15 7
2
+3VALW 1 2 +VCCSA_PWR_SRC +VCCSA_PWR_SRC 24 VIN
SW
PAD-OPEN 43X118 25
COMP
MODE
TP
SLEW
VOUT
VREF
1GND
6
2 1
@ PR127
33K_0402_5% PR128
100_0402_5%
PC122 2 1
2 1
GNDA_VCCSA
0.22U_0402_10V6K
PR130
2 1 2 1 PJ16 0_0402_5%
0.01U_0402_25V7K
2 1 2 1 +VCCSA_SENSE <9>
PC123 PR129
2
3300P_0402_50V7K 10K_0402_5% PAD-OPEN1x1m
PC124
1
B B
GNDA_VCCSA
GPU@ PL26
1 2 1.5VSDGPU_B+
B+
560P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
GPU@ PC321
GPU@ PC318
GPU@ PC316
560P_0402_50V7K
1
1
5
GPU@ PC322
2
2
GPU@ PQ46
4 SIS412DN-T1-GE3_POWERPAK8-5
GPU@ PR265
47K_0402_1%
1 2 GPU@ PR251 GPU@ PC317
<44,53> VGA_PWROK GPU@ PU15 2.2_0603_5% 0.1U_0603_25V7K
3
2
1
GPU@ PR253 1 10 BST_1.5VSDGPU 1 2 1 2

137K_0402_1% PGOOD VBST
@ PR246 2 1 2 9 DH_1.5VSDGPU GPU@ PL27
47K_0402_1% TRIP DRVH 1.2UH_1164AY-1R2N=P3_9.8A_30%
1 2 1.5VSDGPU_EN 3 8 LX_1.5VSDGPU 1 2
<14,17,25,44,53> VGA_ON EN SW +5VALW +1.5VSDGPUP
1
4 VFB V5IN 7
1
GPU@ PC324
@ PR256 0.1U_0402_16V7K 5 6 DL_1.5VSDGPU @ PR247
TST DRVL
5
10K_0402_5% 4.7_1206_5% 1
2
11
2
1 2
TP
1
+ GPU@ PC320 VFB= 0.704V

TPS51212DSCR_SON10_3X3 GPU@ PQ45 330U_6.3V_M
Vo=VFB*(1+PR248/PR255)= 1.5V
1
GPU@ PR250 GPU@ PC323 SI7716ADN-T1-GE3_POWERPAK8-5 @ PC319

470K_0402_1% 4.7U_0805_10V6K 4 680P_0402_50V7K 2 Freq= 266~314KHz , 290KHz(typ)
2
2
A
Cesr= 15m ohm A
Ipeak= 10.40A Imax= 7.28A
3
2
1
Rds=13.5mΩ(Typ) Delta I= 4.002A ==>1/2 Delta I= 2.001A

GPU@ PR248 16.5mΩ(Max) Vtrip=Rtrip*10uA= 1.13V
VFB=0.7V 2K_0402_1% Iocp= 12.464A~14.167A
2 1
1
GPU@ PR255
1.74K_0402_1%
Title
Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2012/06/02
SCHEMATIC,MB A7912
2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 4019ID C
5 4 3 2 1
5 4 3 2 1
2 1
1
+VGFX_CORE +5VS
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
@ PC125 CPU_B+
5
@ PR131 10_0402_1% 1000P_0402_50V7K
QC@ PC128
QC@ PC130
<9> VCC_AXG_SENSE
2 2
PC129
PC131
<9> VSS_AXG_SENSE
1
1U_0603_10V6K
QC@ PC132
DC@ PC133 PC127
1
0_0603_5%
QC@ PR133
33P_0402_50V8J 2 1 0.01UF_0402_25V7K UGATE2G 4 QC@ PQ31 @ @
2
@ PR132 QC@ PC133 PC134
2
10_0402_1% 47P_0402_50V8J 470P_0402_50V7K
2 1 2 1 2 1
3
2
1
PR134
DC@ PR135 PC135 499_0402_1% QC@ PL17
357_0402_1% 150P_0402_50V8J QC@ PU11 0.36UH_PDME104T-R36MS0R825_37A_20%
VSUMG- 2 1 2 1 2 1 2 1 6 VCC UGATE 1 PHASE2G 1 4 +VGFX_CORE
2
QC@ PR135 PR136 QC@ PR137
5
DCR: 0.82mΩ±5%
680P_0402_50V7K 4.7_1206_5%
D PH3 316_0402_1% 267K_0402_1% 3.65K_0402_1% 7 2 BOOT2G
2 1 2 2 3 D
MDV1525URH_PDFN33-8-5 MDU1511RH_POWERDFN56-8-5
FCCM BOOT
1
10KB_0402_5%_ERTJ0ER103J
PR140
PR139 QC@ PR138
169K_0402_1%
3.65K_0603_1%
.1U_0402_16V7K
0.1U_0603_25V7K
2K_0402_1% PWMG2 2.2_0603_5%
0.022U_0402_16V7K
0.22U_0603_16V7K
3 PWM PHASE 8
1
PC137
QC@ PR143
PR144
10K_0603_1%
QC@ PR145
QC@ PC136
2 1
QC@ PQ32
+5VS
11K_0402_1%
4 5 0.22U_0603_16V7K @ QC@ PR146
2.61K_0402_1%
1 2
GND LGATE
2
PR142
QC@ PC139
QC@ PC140
PC141
9 LGATE2G 4 1_0402_5%
+3VS
1 2
TP
QC@
PR141
2 1 VSUMG-
PC142
PC138 DC@ PR137 ISL6208BCRZ-T_QFN8_2X2
@
1.91K_0402_1%
330P_0402_50V7K 2.55K_0402_1% PR148
2
1
DC@ PR143 VSUMG+ 10K_0402_1%
3
2
1
2
1
0_0603_5%
QC@ PR149
154K_0402_1% 1 2 ISEN1G
1U_0603_10V6K
VSUMG+ @ ISEN2G PL18
QC@ PC143
LGATE1G QC@ PR151 SUPPRE_ FBMA-L11-453215-800LMA90T_1812
0_0402_5% CPU_B+ 2 1 B+
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PHASE1G UGATE31 2UGATE3-1
1
PWMG2 PR147
PC145
QC@ PC146
QC@ PC147
PC148
680P_0402_50V7K
680P_0402_50V7K
UGATE1G QC@ PR150
PC149
PC150
QC@ PU12 2.2_0603_5%
DC@ PC140 BOOT1G
0.22U_0603_16V7K
6 1 2 1
2
VCC UGATE
QC@ PQ33
0.1U_0603_25V7K
2
2
QC@ PC144
7 2 BOOT3 4 @ @
FCCM BOOT @ @
3 8 PHASE3
1
PWM PHASE
0.22U_0603_10V7K
0.22U_0603_10V7K
4 5 LGATE3
3
2
1
GND LGATE
QC@ PC151
QC@ PC152
40
39
38
37
36
35
34
33
32
31
9 TP
QC@ PR153
PU13 QC@ PL19
0_0603_5%
1
2
ISL6208BCRZ-T_QFN8_2X2 0.36UH_PDME104T-R36MS0R825_37A_20%
ISUMNG
RTNG
FBG
COMPG
PGOODG
PWM2G
LGATE1G
PHASE1G
UGATE1G
BOOT1G
BOOT2 1 4 +CPU_CORE
PR152
2
PR156
4.7_1206_5%
27.4K_0402_1% UGATE2 QC@ PR157 2 3 2 1ISEN1
1
2 1 DC@ PR155 1 30 10K_0603_1% @PR154
@ PR154
1
ISUMPG BOOT2
PR158 0_0402_5% ISEN1G 2 29 PHASE2 DC@ PR159 ISEN3 1 2 DCR: 0.82mΩ±5% 10K_0402_1%
3.83K_0402_1% PH4 +5VS 1 2 ISEN2G 3
ISEN1G
ISEN2G
UGATE2
PHASE2 28 0_0603_5% @
QC@ PQ34
1 2 2 1 NTCG 4 27 LGATE2 2 1
C NTCG LGATE2 +5VS C
680P_0402_50V7K
470K_0402_5%_
1 TSM0B474J4702RE
2 SCLK 5 26 4 QC@ PR166
<8> VR_SVID_CLK
1 2
SCLK VCCP
PC153
<8> VR_SVID_ALRT# 1 2 PR160 0_0402_5% ALERT# 6 ALERT# VDD 25 2 1 3.65K_0603_1% 2 1ISEN2
1U_0603_10V6K
PR161 0_0402_5%
1 2 SDA 7 24 PR162 VSUM+ 1 2 @PR163
@ PR163
<8> VR_SVID_DAT SDA PWM3
PC154
PC155
1U_0603_10V6K
PR164 0_0402_5% 8 23 LGATE1 1_0603_5% 10K_0402_1%
<40> VR_HOT# VR_HOT# LGATE1
1
1 2 9 22 QC@ PR167
<40> VR_ON
3
2
1
2
VR_ON PHASE1
1
54.9_0402_1%
PR165 0_0402_5% 10 21 PHASE1 @ 1_0402_5%

NTC UGATE1
2
ISEN3/FB2
0_0402_5%
130_0402_1%
75_0402_5%
PR168
PR169
PR170
PR171
VSUM- 2 1
2
1
27.4K_0402_1%
@ PC156 UGATE1
PGOOD
470K_0402_5%_ TSM0B474J4702RE
BOOT1
ISUMN
ISUMP
2
COMP
ISEN2
ISEN1
47P_0402_50V8J 41
RTN
TP
1
@ @ BOOT1
FB
2
PR172
1
PH5
ISL95836HRTZ-T_TQFN40_5X5~D CPU_B+
11
12
13
14
15
16
17
18
19
20
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
1
220U_25V_M
2
+1.05VS_VTT +
PC157
2
1
PC158
PC159
PC160
PC161
VGATE <15,40>
1
3.83K_0402_1%
PR175
1
@ PC126 PR174 1.91K_0402_1% 0_0402_5% 2
2
+3VS
PR173
0.1U_0402_16V7K 2 1 UGATE2 1 2 UGATE2-1 4 PQ35 @ @

2
2
PL20
3
2
1
0.36UH_PDME104T-R36MS0R825_37A_20%
PHASE2 1 4
+CPU_CORE
4.7_1206_5%
VSUM+ PR178 2 3
1
PR179
PC162 PR176 QC@ PR177 DC@ PC163 2.2_0603_5%
10KB_0402_5%_ERTJ0ER103J
DCR: 0.82mΩ±5%
11K_0402_1%
2.61K_0402_1%
560P_0402_50V7K 2K_0402_1% 5.76K_0402_1% 10P_0402_50V8J BOOT2 2 1 1 2
1
0.22U_0603_16V7K
0.22U_0603_16V7K
2 1 2 1 2 1 2 1 0.068U_0402_16V7K
PR180
680P_0402_50V7K
PC164 @
ISEN3
ISEN2
ISEN1
QC@ PC169
QC@ PC168
PC166
0.22U_0603_16V7K
1 2
1
PQ36
QC@ PR187
475_0402_1%
LGATE2 4 ISEN21 2 2 1ISEN1

2
PC172
PC167 QC@ PC170 1 2 PR181 @PR182
@ PR182
12
B 470P_0402_50V7K 47P_0402_50V8J PC165 10K_0603_1% 10K_0402_1% B
2
PR184
2 1 2 1 2 1 DC@ PR177 0.22U_0402_6.3V6K
2
PH6
PR183 20.5K_0402_1% 1 2 @
3
2
1
499_0402_1% PC171 VSUM+
1 2 2 1 ISEN3
1
0.22U_0402_6.3V6K PR185 @PR254

@ PR254
2
1 2 VSUM- 3.65K_0603_1% 10K_0402_1%
QC@ PR189
3.65K_0402_1%
PC174
150P_0402_50V8J
QC@ PC173
0.22U_0402_6.3V6K
Close Phase 1 choke VSUM- 2
PR188
1
1
DC@ PR189
.1U_0402_16V7K
2 1 2 1 2 1 PC175 1_0402_5%
2.15K_0402_1% PR190 DC@ PC170 CPU_B+
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
267K_0402_1% 33P_0402_50V8J
2
1
PC176
PC177
PC178
PC179
DC@ PR187 DC@ PC168
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
390_0402_1% 0.1U_0603_25V7K PR192

0_0402_5%
2
+CPU_CORE 2 1 UGATE1 1 2 UGATE1-1 4
1
PQ37
PC181
PC182
PC183
PC184
@ PR191 @ PC180
330P_0402_50V7K
10_0402_1% 330P_0402_50V7K
PC185
2 1
2
CPU_B+ PL21
<8> VCCSENSE
3
2
1
For 45W 3+2 0.36UH_PDME104T-R36MS0R825_37A_20%
PHASE1
<8> VSSSENSE CPU_CORE LL= -1.9mΩ, OCP ~116A 1 4
2
+CPU_CORE
5
2 1 @
GFX_CORE LL= -3.9mΩ, OCP ~55A
4.7_1206_5%
PR194 2 3
5
1
PC186 2.2_0603_5%
For DC 35W 2+1 DCR: 0.82mΩ±5%
PR195
2 1 0.01UF_0402_25V7K BOOT1 2 1 1 2
@ PR193
CPU_CORE LL= -1.9mΩ, OCP ~70A
680P_0402_50V7K
UGATE1G 4 10_0402_1% PC187
PQ38 GFX_CORE LL= -3.9mΩ, OCP ~40A 0.22U_0603_16V7K @
1 2
PC188
MDV1525URH_PDFN33-8-5 LGATE1 4 ISEN11 2 2 1 ISEN2
PQ39
PR196 @ PR197
PL22 10K_0603_1% 10K_0402_1%
3
2
1
0.36UH_PDME104T-R36MS0R825_37A_20%
2
PHASE1G 1 4 @
3
2
1
A
+VGFX_CORE VSUM+
1 2 2 1 ISEN3 A
5
4.7_1206_5%
2 3 PR198 @ PR262
1
@ PR200
3.65K_0603_1% 10K_0402_1%
2
DCR: 0.82mΩ±5% VSUM- 2 1

10K_0603_1%
3.65K_0603_1%
PC189
10K_0402_1%
PR201
2
1
QC@ PR202
0.22U_0603_16V7K 1_0402_5%
1 1
1_0402_5%
PR203
PR204
680P_0402_50V7K
@PR205
PR205
4
1 2
PQ40
PC190
PR206
LGATE1G
2.2_0603_5%
1
VSUMG+ 1
ISEN2G 2

3
2
1
@
VSUMG-
SCHEMATIC,MB A7912
ISEN1G
2
BOOT1G
Custom 4019ID C
5 4 3 2 1
8 7 6 5 4 3 2 1
VGA Chipset Default VID6 VID5 VID4 VID3 VID2 VID1 VID0 +VGA_B+ GPU@ PL23
Voltage FBMA-L11-322513-151LMA50T_1210
2 1 B+
N12P GS4 0.975V 0 1 0 1 0 1 0
2200P_0402_50V7K
0.1U_0603_25V7K
10U_0805_25V6K
10U_0805_25V6K
H H
N12P GV4 0.9V 0 1 1 0 0 0 0
PC191
2S@ PC192
2S@ PC193
2S@ PC194
1
1
2
2
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
<22>
<22>
<22>
<22>
<22>
<22>
N13P GL 0.9V 0 1 1 0 0 0 0
@ PR278 @
5
0_0402_5%
+3VSDGPU 1 2
2
N13P GV 0.9V 0 1 1 0 0 0 0
2S@ PQ41
GPU@ PR207
0_0402_5%
GPU@ PR209 4
68K_0402_1%
1
<14,17,25,44,51> VGA_ON 1 2
2S@ PR208 2S@ PC195
1
GPU@ PC331 2.2_0603_5% 0.22U_0603_10V7K
3
2
1
0.1U_0402_16V7K BOOT2_VGA 2 1 BOOT2_2_VGA 1 2
2
GPU@ PR210 UGATE2_VGA 2S@ PL24
G 10K_0402_1% 0.36UH_PDME104T-R36MS0R825_37A_20% G
1 2 PHASE2_VGA 1 4 +VGA_CORE
2 3 V2N_VGA
5
10K_0402_5%
2S@ PR214
2S@ PR211
3.65K_0402_1%
1
1
DCR: 0.82mΩ±5%
+3VS @ PR212 2S@ PR215
2S@ PQ42
1.91K_0402_1% 1_0402_5%
1 2 CLK_ENABLE#_VGA 2S@ PR217
LGATE2_VGA 4 @ PR213 10K_0402_5%
2
1
2.2_1206_5% 1 2V1N_VGA
GPU@ PR216
1.91K_0402_1%
GPU@ PR218 @ PD12 VSUM+_VGA VSUM-_VGA
3
2
1
1
0_0402_5% RB751V-40TE17_SOD323-2
2
1 2 2 1 @ PC198 ISEN2_VGA
51> VGA_PWROK
680P_0402_50V7K
GPU_VID6
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
2
2S@ PR219
100K_0402_5%
F F
+3VS 1 2
GPU@ PR220
47K_0402_1%
2 1
+3VS
2S@ PC199
1U_0603_10V6K
40
39
38
37
36
35
34
33
32
31
GPU@ PU14 1 2
1
CLK_EN#
DPRSLPVR
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VR_ON
<40> GPU_HOT# @ PR275

10K_0402_5% BOOT2 30
UGATE2 29
@ PH8 1 28
2
470K_0402_5%_ TSM0B474J4702RE PGOOD PHASE2

2 PSI# VSSP2 27
2 1 3 RBIAS LGATE2 26
4 25 GPU@ PR222 0_0402_5% 1 2 +5VS
VR_TT# VCCP
E 2 1 2 1 5 NTC PWM3 24 1 2 E
6 23 GPU@ PR221
@ PR186 @ PR199 VW LGATE1 0_0402_5%
7 COMP VSSP1 22
27.4K_0402_1% 3.83K_0402_1% 8 21
FB PHASE1
1 2 9 ISEN3
UGATE1
10
BOOT1
ISUM+
ISEN2
1
ISEN1
ISUM-
VSEN
1000P_0402_50V7K
IMON
8.06K_0402_1%
@ PC200 GPU@ PC201

VDD
RTN
VIN
120K_0402_1%
GPU@ PR224
GPU@ PC202
33P_0402_50V8J 41 1U_0603_10V6K
AGND
2
1
1S@ PR223
ISL62883CHRTZ-T_TQFN40_5X5
11
12
13
14
15
16
17
18
19
20
GPU@ PR225 1S@ PR252

2
499_0402_1% 0_0402_5%
1 2 1 2 2 1
1
GPU@ PC203
GPU@ PC204 470P_0402_50V7K 1 2 +5VS
47P_0402_50V8J GPU@ PR226
1 2 1 2 GPU@ PR228 0_0402_5%
GPU@ PR227 0_0402_5%
D 3.57K_0402_1% 1 2 +VGA_B+ D
ISEN2_VGA 1S@ PR249
1 2 1 2 0_0402_5% GPU@ PR230
ISEN1_VGA 1 2 1_0402_5%
GPU@ PC205 GPU@ PR229 1 2 +VGA_B+
+5VS
1
150P_0402_50V8J 324K_0402_1%
0.22U_0402_10V4Z
0.22U_0402_10V4Z
1
1
2S@ PC206
2S@ PC207
GPU@ PC208
GPU@ PC209
1U_0603_10V6K
0.22U_0603_25V7K
GPU@ PR231
255K_0402_1% +5VS
2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
BOOT1_VGA
0.1U_0603_25V7K
2
GPU@ PC211
GPU@ PC212
GPU@ PC213
1
1
PC210
LL Disable
GPU@ PQ43
2
UGATE1_VGA 4 @
1
VSUM-_VGA
2
1 phase OCP ~33A
+VGA_CORE VSUM+_VGA
C GPU@ PR232
GPU@ PR235
2.2_0603_5%
GPU@ PC214
0.22U_0603_10V7K 2 phase OCP ~57A C
3
2
1
10_0402_5% 2 1 BOOT1_1_VGA 1 2
1
82.5_0402_5%
2.61K_0402_1%
GPU@ PL25
GPU@ PR234
<24> VCCSENSE_VGA 1 2 0.36UH_PDME104T-R36MS0R825_37A_20%

1
PR233
PHASE1_VGA 1 4 +VGA_CORE
GPU@ PR236
0.1U_0603_25V7K
0.22U_0603_16V7K
1
2S@ PC217
GPU@ PC218
0_0402_5% 2 3 V1N_VGA
2
1
5
11K_0402_1%
GPU@ PR241
GPU@ PR238
GPU@ PC215 @
1
1
DCR: 0.82mΩ±5%
10K_0402_5%
2S@ PR239
56P_0402_50V8
56P_0402_50V8
56P_0402_50V8
3.65K_0402_1%
330P_0402_50V7K
2
GPU@ PC88
GPU@ PC89
GPU@ PC91
GPU@ PR240
1
GPU@ PQ44
1_0402_5%
0.01U_0402_25V7K
2
PC216
330P_0402_50V7K
LGATE1_VGA 4 @ PR237
2
1
1
PC222
2.2_1206_5% 2S@ PR242
2
1
GPU@ PC221 GPU@ PH7 10K_0402_5%

GPU@ PR243 1000P_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ 1 2V2N_VGA
2
0_0402_5% @
2
3
2
1
1 2 @ VSUM+_VGA VSUM-_VGA
<24> VSSSENSE_VGA
2
1
B
Layout Note: B
@ PC223
GPU@ PR244 2S@ PR245 Place near Phase1 Choke 680P_0402_50V7K ISEN1_VGA
2
10_0402_5% 953_0402_1%
1 2 1 2 VSUM-_VGA
1
GPU@ PC224
0.1U_0402_16V7K
2
1S@ PR245 1S@ PC217

590_0402_1% 0.1U_0603_25V7K
A A
SCHEMATIC,MB A7912
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 4019ID C
8 7 6 5 4 3 2 1
5 4 3 2 1
PWR Rule +CPU_CORE

CPU 330uF/9m *5,22uF *16,10uF*10
+VGFX_CORE
GFX 470uF/4.5m*1,330uF/9m*1,22uF*12
1
10U_0805_25V6K
PC225
10U_0805_25V6K
PC226
10U_0805_25V6K
PC227
10U_0805_25V6K
PC228
10U_0805_25V6K
PC229
PC230
PC231
PC232
PC233
PC234
PC235
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1
2
D D
2 2 2 2 2 2
1
10U_0805_25V6K
PC236
10U_0805_25V6K
PC237
10U_0805_25V6K
PC238
10U_0805_25V6K
PC239
10U_0805_25V6K
PC240
2
2
PC241
PC242
PC243
PC244
PC245
PC246
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1
2 2 2 2 2 2
+CPU_CORE
1 1 1 1 1 1 1 1
22U_0805_6.3V6M
PC247
22U_0805_6.3V6M
PC248
22U_0805_6.3V6M
PC249
22U_0805_6.3V6M
PC250
22U_0805_6.3V6M
PC251
22U_0805_6.3V6M
PC252
22U_0805_6.3V6M
PC253
22U_0805_6.3V6M
PC254
470U_D2_2VM_R4.5M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
330U_D2_2V_Y
2 2 2 2 2 2 2 2
330U_D2_2V_Y
330U_D2_2V_Y
1 1 1 1 1 1 1 1
PC257
PC258
PC259
PC260
PC261
PC262
+ + + +
PC255
PC256
2 2 2 2
C 2 2 2 @ 2 @ @ @ @ @ C
1 1 1 1 1 1 1 1
22U_0805_6.3V6M
PC263
22U_0805_6.3V6M
PC264
22U_0805_6.3V6M
PC265
22U_0805_6.3V6M
PC266
22U_0805_6.3V6M
PC267
22U_0805_6.3V6M
PC268
22U_0805_6.3V6M
PC269
22U_0805_6.3V6M
PC270
2 2 2 2 2 2 2 2
Vaxg
‧ Can connect to GND if motherboard only
supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
‧ VAXG can be left floating in a common
motherboard design (Gfx VR keeps VAXG from +CPU_CORE
floating) if the VR is stuffed
1 1 1 1 1
+ QC@ PC271 + PC272 + PC273 + PC274 + PC275
470U_D2_2VM_R4.5M 330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y
2 2 2 2 2
B B
+1.05VS_VTT
DC@ PC271
+1.05VS_VTT 330U_D2_2V_Y
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1
PC276
PC277
PC278
PC279
PC280
PC281
PC282
PC283
PC284
PC285
2 2 2 2 2 2 2 2 2 2
330U_D2_2.5VY_R15M
330U_D2_2.5VY_R15M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1
PC286
PC287
PC288
PC289
PC290
PC291
+ +
2 2 2 2
@ @ 2 @ 2
A A
INTEL Recommend
3*330uF(1 in other page),12*22uF, 5 no stuff Security Classification Compal Secret Data Compal Electronics, Inc.
from PDDG 1.0 Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title
SCHEMATIC,MB A7912
5 4 3 2 1
A
B
C
D
5
5
2
1
GPU@ PC308
+VGA_CORE
4.7U_0603_6.3V6K 2 1
2
1
+VGA_CORE
2 1
2
1
2
1
+
GPU@ PC300 GPU@ PC292
GPU@ PC335 GPU@ PC196 GPU@ PC309 4.7U_0603_6.3V6K 0.1U_0402_16V7K
4.7U_0603_6.3V6K 390U_2.5V_M 4.7U_0603_6.3V6K 2 1
2
1
2 1
2
1
+
GPU@ PC336 @ PC197 4.7U_0603_6.3V6K 0.1U_0402_16V7K
4.7U_0603_6.3V6K 330U_D2_2V_Y 2 1
2
1
2 1
2
1
+
GPU@ PC337 GPU@ PC219 4.7U_0603_6.3V6K 0.1U_0402_16V7K
4.7U_0603_6.3V6K 390U_2.5V_M 2 1
2
1
2 1
2
1
+
Near GPU
4.7U_0603_6.3V6K 470U_V_2.5VM 2 1
2
1
2 1
2
1
+
4.7U_0603_6.3V6K 470U_V_2.5VM 2 1
2
1
2 1
Under GPU

GPU@ PC311 4.7U_0603_6.3V6K 0.1U_0402_16V7K
47U_0805_4V6 2 1
4
4
2
1
2
1
GPU@ PC312 4.7U_0603_6.3V6K 0.1U_0402_16V7K
22U_0805_6.3V6M 2 1
2
1
2
1
GPU@ PC313 4.7U_0603_6.3V6K 0.1U_0402_16V7K
22U_0805_6.3V6M
2
1
GPU@ PC314
22U_0805_6.3V6M
2
1
GPU@ PC315
22U_0805_6.3V6M
Issued Date
Security Classification
3
3
2011/06/02
Compal Secret Data
Deciphered Date
2012/06/02
2
2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
Size
Title
Date:
Document Number
Friday, February 10, 2012

4019ID
1
1
Sheet
55
SCHEMATIC,MB A7912
of
63
Rev
C
A
B
C
D
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
S3 sequence @ DC Meet Intel sequence SPEC Change RP91 to 267K
1 49 2011 DVT
D 1208 D
1.5VSDGPU lose Improve FB pin anit-noise Change RP248 to 2K, PR255 to 1.74K, PR253 to 137K
2 51 2011 DVT
1208
Cut-in SMT memo Add PC182, PC184
3 52 2011 DVT
1208
Standard design Change PR138, PR150, PR178, PR194, RP205 , PR235 to 2.2
2011 DVT
4 1208
Vth has risk Change PU16 from G971 to APL5930
5 51 2011 DVT
1212
Enable select Add PR266
6 51 2011 PVT
1217
Cut-in EMI solution Add PC88, PC89, PC91
7 53 2011 PVT
1221
Consider part rating Change PR277 from 0402 to 0603
8 51 2011 PVT
1222
Tune transient character Add PC139, PC169
9 52 Swap PC271 & PC275
2011 PVT
C
1222 C
PH1 OTP and ADP_I throttling by H/W control Delete PR37, PR57
10 46 2011 PVT
1222
Follow Power design Add PC313, PC314, PC315
11 55 2011 PVT
1222
VGA sequence meet nVidia SPEC Swap PR258 & PR263, PR266 & PR264, PR246 & PR265
12 51 2011 PVT
1223
Cut-in EMI solution Add PR53, PC40
13 47 2012 PVT2
0104
10
11
B B
12
13
14
15
16
17
18
A A
19

SCHEMATIC,MB A7912
Rev
Custom C
4019ID
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 2 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
D
1 D
6
C C
10
11
B B
12
13
14
15
16
A A
17

SCHEMATIC,MB A7912
Rev
Custom C
4019ID
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 P.40.13 9/7 EC Change th HDA_SDO to ME_EN
D 0.2 D
2 P.40 9/7 HW Add R2085 ,change the EC_ACIN pull high to +3VLP 0.2
3 P.37 9/7 HW Add fl1009 USB3.0 TX coupling capacitor (c2060,c2061) 0.2
4 P.38.39.40 9/7 HW Add USB chargaer schematic(C2060.C2061.R2077~R2084,R2065~R2072) 0.2
5 P.22.40 9/7 HW Follow ABO request,add ADPS function(Q2005),R2086.R2087) 0.2
6 P.20 9/7 HW Add +5VALW TO +5VALW_PCH schematic(Q2006.C2062.R2088) 0.2
7 P.44 9/7 HW Add +3VALW TO +3VALW_PCH schematic(U2006,R2073~R2076,C2056~C2059,Q2003,Q2004) 0.2
8 P.43 9/7 HW For FSOV spec,Chang R714,R716 from 75ohm to 47ohm. 0.2
9 P.13 9/7 HW For WIN8,Change R681.R651.R684.R652 to 33ohm 0.2

C C
10 P.44 9/7 HW Delete C817,Change C826 from D2 size to B2 size 0.2
11 P.17.37 9/7 HW Follow chief river common design, please chang Mini-Card 2(port 11) to port 9 0.2
12 P.38 9/7 HW Delete +1.5V to +1.05V_V128 Transfer(U2002.R2002.R2003.R2005.C2002.C2003.C2005.R2008)

0.2
13 P.38 9/7 HW Delete USB3.0 EEPROM(U2004.R2035.R2034.C2039) 0.2
14 P.37 9/7 HW Reserve Mini-Card 2 0.2

F2 flick issue on projector P5202 D-sub
15 P.19 9/7 HW 0.2
Add C2063.C2064
Change VGA GPIO12 of dGPU connection to EC controlled for the power limited usage
16 P.22.40 9/8 HW 0.2
Add EC pin 107-->GPU_ACIN
17 P41 9/14 HW Add SW5.SW6 for EG project. 0.2
B B
Swap MDC37 and MDC38

18 P27.30 9/14 HW 0.2
Swap MDA13 and MDA14
P06.11.17.35. For ESD request
19 9/14 HW 0.2
P39.40.42 Add C2065~C2075
P16 HW For HDMI PCH_DPB_HPD noise
20 9/16 0.2
Add C2076
For LVDS power sequence
21 P31 9/16 HW Change R5 from 300 to 200 ohm 0.2
Change R2 from 1k to 10k ohm
change C2 from 0.047uF to 1uF
22 P18 9/16 HW Delete PCH test ponit(T31~T46,T49~T61,T63~T65) 0.2
23 P21,40 9/19 HW Change Q22,Q26 from SB000008J10 to SB000009080 0.2
24 P14,22,35,38 9/19 HW For Crystal
A
Change Y2 ,Y4 from SJ10000DJ00 to SJ10000E800 0.2
A
Change Y1000 from SJ10000DK00 to SJ100009700

Change C630,C631,C2019,C2028,C1008,C1009 to 10pF
Change C681,C679 to 15pF
SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1

Request
25 P.44 9/20 EMI For EMI request (Add C2079~C2084)
D 0.2 D
26 P.36 9/20 HW For SD3.0 issue (Add R2088.R2089) 0.2
27 P.20 10/17 HW Add +5VALW TO +5VALW_PCH schematic(Q2006.C2062.R2090) 0.3
28 P.44 10/17 HW Add +3VALW TO +3VALW_PCH schematic(U2006,R2073~R2076,C2056~C2059,Q2003,Q2004) 0.3

Board ID error.
29 P.40 10/17 HW 0.3
Add R353.
Board ID 0.3.
30 P.40 10/17 HW 0.3
Change R353 to 18K
Follow Intel’s suggestion;
31 P.17,39 10/17 HW 0.3
Change USB3.0 from port 2 to port 1
Change USB2.0 from port 0,1 to port 2,9
Support eDP
32 P.18 10/18 HW 0.3
C
GPIO71-->0 (eDP) C
GPIO71-->1 (LVDS)
33 P.13.40 10/25 HW Co_lay NPCE885N
0.3
Delete U38,C722,R690,R695,C727
Add C2085,R2091~R2096
B B
A A

SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1

Request
Delete SW5,SW6,
43 P.41 11/16 ME
D Pop SW2,SW3 0.4 D
44 P.05 11/16 HW BUF_CPU_RST# noise Add C2090

0.4
De-pop U31,R537
45 P.35 11/17 HW LAN SPROM on Chip
Pop R538 0.4
46 P.36 11/17 EMI Change C478 to 10P_50V

0.4
47 P.13 11/17 HW Change C682,C686 to 15P

RTC issue 0.4
48 P.31,32,41 11/17 ESD De-pop D3,D4,D17,D18,D15

0.4
Pop D24,D36
49 P.40 11/17 HW De-pop R891,R893 0.4

C C
50 P.24 11/21 HW N13P_GS 0.4

Change strap2 to PD 15k
Change strap4 to PD 10k
51 P.13 11/21 HW Chip Select 0.4
Change R651,R2049 to 0ohm
52 P.13,40 11/21 HW Delete NPCE885N 0.4

(R2091.R2092.R2094.R2095.R2096,R698,
R699,R692,C2085)
53 P.45 11/22 HW Change +1.05VSDGPU JUMP size 0.4
PJ19 change to 43x118
B 55 P.35,36 11/23 HW Card Reader 0.4 B
Change R216 to 22 ohm

Change R2088 to 47ohm
Change R2089 to 22 ohm
Add C2091~C2093
Change R525,R536,R537,R538 to 1k
56 P.13 11/23 HW Delete R2093,R2049,R651(0ohm) 0.4
57 P.13 11/23 HW Change N13P-GS to SA000051880 0.4

Change U33 to SA00005AG00
58 P.35, P36 11/23 HW Del C2093, R222, R2089, 0.4

net(CR_CLK_XD_RY_BY#_23)
Add R2101, C2094
A 59 P.36 11/24 HW ADD R2102, C2096 for EMI ISSUE 0.4 A

SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1

Request
Change R1057 from 35kohm to 45kohm
58 P.24.25 12/02
D Change R1077 from 40.2ohm to 42.2ohm 0.4 D
Change R1080 from 60.4ohm to 51.1ohm

for N13P_GS, the boot voltage is 0.9V
59 P.22 12/02
pop R1022,R1021,R1036,R1035,R1034,R1033 0.4
for N13P_GL, the boot voltage is 0.95V
pop R1022,R1037,R1020,R1019,R1034,R1033
for N13M_GS, the boot voltage is 0.925V
pop R1022,R1037,R1020,R1019,R1018,R1033
Change R369 from 470ohm to 150ohm

60 P.44 12/02
Change R26 from 470ohm to 47ohm 0.4
Pop Q3
BIOS ROM(4M)
61 P.13 12/02 Change U36 to SA00003K800 0.4
C C
EMI suggestion for Card Reader

62 P.35 12/06
Change R195 from 33ohm to 22ohm 0.4
Change C2094 from 6pF to 6.8pF
De-pop C2096
EMI request for 家電下鄉

63 P.36 12/07 0.5
Add C2097
For PCH HM70

64 P.39 12/07
Change USB port0 to co-lay USB3.0 0.5
B
Change USB port2 to USB2.0 B
Change USB port 11 to BT

Change 1.5VSDGPU EN from VGA_ON# to VGA_PWROK#
65 P.44 12/07 0.5
Add R2103,Q2008
66 P.18 12/09 For eDP 0.5

Change Q2007 from SB501380020 to SB501110010
A A

SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1

Request
D 67 P.31 12/16 EE change Q2007 to 2N7002 for eDP_HPD circuit LA-7912 D
0.2
add WLAN_PME# on pin85.

LA-7912
68 P.40 12/16 EE add wlan_on signal on EC pin38
0.2
add AC circuit
LA-7912
69 P.35 12/16 EE reserve Q2007 for open +3V_LAN by
0.2
PCH_PWREN#
add R2063 for pull high VCIN0_PH to +3VL 10k LA-7912

70 P.40 12/16 EE
add R2059 for pull low VCIN1 10k 0.2
resever R2116 ~ R2119 for change LED power to 3VLA-7912

71 P.41 12/20 EE
resever C2101~C2107 56pF on T/P for EMI 0.2
change R384 & R385 power to +3V_LAN LA-7912

C C
72 P.36, 14 12/22 EE
unpop R630 & reserve R2120 to pull high +3V_LAN 0.2
change Q43 from 2n7002 to BSS138 LA-7912

73 P.42, 35 12/22 EE
unpop R209 0.2
change R353 to 56k for board ID 0.2

LA-7912
74 P.40 12/23 PWR power request pop R2063, R2059
0.2
un-pop R880, R891, R893
LA-7912
75 P.39 12/23 EMI change USB3 signal pass by chock (SM070001600)
0.2
Change LED(Blue) SC591NB5A30 to SC591TBKA10
Change LED(AMBEL) SC500007700 to SC500005930 LA-7912
76 P.41 12/23 ME change (R2116=130ohm),(R377,2118,378=390ohm) 0.2
B
(R2117,2119 = 51 ohm) B
78 P.36 12/23 EMI R2088 change to 10ohm LA-7912

0.2
L1002 use SM010028800 (for N13P_GL) LA-7912
79 P.25 12/23 EMI
use 0ohm on N13P_GS,N13M_GS 0.2
POP R2104, R2106 unpop R2105, R2107 LA-7912

80 P.44 12/24 EE
for VGA sequence 0.2
De-pop C217,C216 EMI request. LA-7912
81 P.41,24 12/24 EMI,EE
add R1019, R1020, R1037 for GM@ (VGA_CORE) 0.2
change R2059&R2063 to 10k ohm for EC request LA-7912

82 P.40,27 12/27 EE
C2086~C2089 change bom sturte to DIS@ 0.2
add R2125, R2123 for option WL_OFF# to EC or PCH
83 P.40 12/27 EE
for option BT_ON# to EC or PCH LA-7912
A A
add R2122, R2124
reserve R2126 to pull high 3VALW 0.3
reserve R2127 to pull high 3VALW
SCHEMATIC,MB A7912
5 4 3 2 1
5 4 3 2 1

Request
reserve R2121 for WLAN_LED connect +3VALW LA-7912
D 83 P.41 01/02 EE D
change C2101~2107 bomstucture to GM@ 0.3
add GPIO23 for define USB config. LA-7912

84 P.13 01/09 EE
(R2128 & R2092) 0.3
update power circuit LA-7912

85 P.45~56 01/09 PWR
0.3
change R2110 to pull high +3VS_FULL LA-7912

86 P.37 01/09 EE
0.3
LA-7912
87 P.31 01/10 EE add R2130 reserve for lvds short issue
0.3
LA-7912
88 P.40 01/10 EE change board ID to 0.3 (R353 100k)
0.3
LA-7912
C C
89 P.37 01/11 EE change R2110 to pull high +3VALW

0.3
LA-7912
90 P.37 01/11 EE pop +3VS_FULL 開電線路
0.3
add new bom structer usb2@ for usb flag LA-7912
91 P.13 01/11 EE
0.3
UNPOP +1.5VSDGPUH to +1.5VSDGPU circuit LA-7912
92 P.44 01/11 EE
0.3
add R2131,R2132 for option turn off 3VLAN power
93 P.35, 40 01/12 EE LA-7912
by PCH_PWR_EN# or LAN_PWR_EN# (from EC)
0.3
add R2134~R2136 reserve for AOIC LA-7912
94 P.37, 40 01/18 EE
for ACER request 0.3
reserve R2137 pull low USB_P8 for PCH leakage LA-7912

95 P.17 01/18 EE
B B
0.3
LA-7912
96 P.32 02/02 EE change R428 & R426 to 0 ohm for CRT issue
0.3
A A

SCHEMATIC,MB A7912
5 4 3 2 1
www.s-manuals.com

Compal Confidential: Q5WV1 M/B Schematics Document

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A B C D E

File Name : LA-7912P

Q5WV1 M/B Schematics Document

ZZZ2 1G@ ZZZ3 2G@

Security Classification Compal Secret Data Compal Electronics, Inc.

x16 Gen3(N13P-GS) Intel Memory BUS(DDRIII)

FDI x8 DMI x4 USB 2.0 conn x2 Bluetooth CMOS Camera

TMDS(UMA/OPTIMUS) Panther Point-M

Conn. page 35,36 page 36

Power On/Off CKT. Sub-board

+5VS +5VALW to +5VS switched power rail ON OFF OFF

USB Port Table N13P-GL GL@

4319IDBOL11SMT MB A7912 Q5WV1 HM77 DC 13PGL2G 3 UHCI6

4319IDBOL13SMT MB A7912 Q5WV1 HM77 DC 13MGS1G 3

PCI EXPRESS* - GRAPHICS

<15> FDI_LSYNC0 J19 G27 PEG_HTX_GRX_N5 C550 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N5

PEG_TX#[14] PEG_HTX_GRX_N0 C560 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_N0

PEG_TX[6] PEG_HTX_GRX_P8 C545 GSGL@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P8

D16 D25 PEG_HTX_GRX_P0 C561 1 2 DIS@ 0.22U_0402_10V6K PEG_HTX_C_GRX_P0

Security Classification Compal Secret Data Compal Electronics, Inc.

SNB_IVB# had changed the name to JCPU1B

AN34 SKTOCC# For LVDS

AR26 TCK @ +3VS

JTAG & BPM

Buffered reset to CPU

U7 R87 4 PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_R

43_0402_1% O R204 130_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY A

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

Follow CRB1.0 +1.5V

<5> SM_DRAMRST# SM_DRAMRST# 3 1 DIMM_DRAMRST#_R 1 2 DIMM_DRAMRST# <11,12>

R02 modify for ESD S TR SSM3K7002F 1N SC59-3

0.1U_0402_16V4Z 4.99K_0402_1% RST_GATE hgih ,MOS ON

CFG Straps for Processor

1: Normal Operation; Lane # definition matches

AJ26 RSVD5 RSVD_NCTF1 AR35

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

0: PEG Wait for BIOS for training

Security Classification Compal Secret Data

SV type CPU JCPU1F POWER

PEG AND DDR

VCC62 VIDALERT# VR_SVID_ALRT# <52>

TYCO_2013620-2_IVY BRIDGE CONN@

DDR3 -1.5V RAILS

+1.8VS from CR PDDG 0.8 1.2A VCCSA_SENSE H23 +VCCSA_SENSE <51>

1 VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <51>

1/NC : (Default) +1.05VS_VTT

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

Security Classification Compal Secret Data Compal Electronics, Inc.

DIMM_1 Reserve H:8mm 2 2 Security Classification Compal Secret Data

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

189 190 DDR_B0_DM5

DDR_B_D58 191 192 DDR_B_D62 DDR_B0_DM6

VDDSPD SDA D_CK_SCLK

Security Classification Compal Secret Data

+RTCVCC PCH_RTCX1 +RTCBATT +3VS

HDA_SDO as Capella ME override (GPIO33) +3VS R654 1

2 @ INTVRMEN SERIRQ MX25L1606EM2I-12G_SO8

AB13 SATA3_COMP1 2 R258

USB2.0 0 2011/06/02 2012/06/02 Title