Beruflich Dokumente
Kultur Dokumente
Operating Manual
Ver.1.1
TDM Pulse Code Modulation Transmitter and Receiver Trainer ST2153 and
ST2154
Table of Contents
1. TDM PCM ST2153’s Features 4
2. TDM PCM ST2153’s Technical Specifications 4
3. ST2154’s Features 5
4. ST2154’s Technical Specifications 5
5. Pulse Modulation Techniques 6
6. Pulse Code Modulation 9
7. Digital Communication System 12
• Experiment 1 16
Study of Error Check Codes
8. A/D Conversion 19
• Experiment 2 21
Study of Analog to Digital Conversion
9. Digital Transmission 23
• Experiment 3 26
Study of Control Signals and their Timings
10. Time Division Multiplexing 29
• Experiment 4 32
Study of Time Division Multiplexing
• Experiment 5 33
Study of Pseudo Random Sync Code Generator
• Experiment 6 35
Study of Three Modes of Transmission
• Experiment 7 44
Computer Communication using RS232 interface via ST2153 &
ST2154
• Experiment 8 46
Multi point to multipoint communication using RS232 interface
via ST2153 & ST2154
• Experiment 9 48
Point to multipoint communication using RS232 interface via
ST2153 & ST2154
11. Switched Faults 50
12. Setting up the Receiver’s clock regeneration circuit 52
13. Warranty 53
14. List of Accessories 53
ST2153 :
Features
• Crystal Controlled Clock.
• On-board Sine wave generator (Synchronized).
• 2 TDM Analog Channels.
• PCM Transmitter.
• Fast & Slow modes for real time operation and data flow examination.
• Error check code options (odd-even parity, Hamming Code).
• 4 Switched faults allow different Error Check Options.
• PC-PC Communication via RS232 interface.
Technical Specifications
ST2154 :
Features
Technical Specifications
Figure 2
b) Hamming Coding :
Hamming coding, decode each word at the transmitter into a new code by stuffing the
word with extra redundant bits. As the name suggests, the redundant bits do not
convey information but also provides a method of allowing the receiver to decide
when an error has occurred & which bit is in error since the system is binary, the bit
in error is easily corrected.
Three bit hamming code provides single bit error detection and correction.
The ST2153 & ST2154 involves the use of 7 bit word. Therefore only four bits are
used for transmitting data if hamming code is selected. The format becomes.
D6 D5 D4 D3 C2 C1 C0
Where C2, C1 & C0 are Hamming Code Bits
The Hamming code was invented by R.W. Hamming. It uses three redundant bits, as
opposed to the single redundant bit needed by simple parity checking. But it provides
a facility of single bit error detection & correction.
Code Generation on Trainer
The code on this trainer is generated by addicting parity check bit to each group as
shown below :
Group 1 D6, D5, D4 Parity Bit - C2
Group 2 D6, D5, D3 Parity Bit - C1
Group 3 D6, D4, D3 Parity Bit – C0
The Groups & Parity bit forms an even parity check group. If an error occurs in any of
the digits, the parity is lost & can be detected at receiver e.g. Let us encode binary
value D6, D5, D4, D3 of '1101'
Group 1 D6 D5 D4 C2
1 1 0 0
Group 2 D6 D5 D3 C1
1 1 1 1
Group 3 D6 D4 D3 C0
1 0 1 0
So, the data word after coding will be
D6 D5 D4 D3 C2 C1 C0
1 1 0 1 0 1 0
At the receiver, the four digits representing a particular quantized value are taken in as
three groups. The Error Detection/ Correction Logic carries out even parity checks on
the three groups.
Group 1 D6 D5 D4 C2
Group 2 D6 D5 D3 C1
Group 3 D6 D4 D3 C0
If none of them fails, then no error has occurred in transmission & all bit values are
valid. Suppose, a case, where the following parity check was carried out & the listed
groups failed.
Group 1 D6 D5 D4 C2
0 1 0 0 Failed
Group 2 D6 D5 D3 C1
0 1 1 1 Failed
Group 3 D6 D4 D3 C0
0 0 1 1 Passed
If we suppose only a signal bit corruption, the passing of Group 3 means that all D6,
D4, D3 & C0 are valid.
In the above two groups the only common element except D6, is D5. As D6 is
received correctly clear from Group 3 the only bit which can be in error is Bit 5 i.e.
D5. Since the corrupted bit has been detected, the receiver can now make changes in
D5 to convert it to other possible value i.e. '0'. Thus the data word is corrected to
0001010. The receiver now discards the redundant check bits (C2, C1 & C0) and
passes the valid data (0001) to the input of D/a converter table given below gives the
location of possible single bit errors.
Parity Check Results on ST2154
Group-l Group-2 Group-3 Location of
D6 D5 D4 C2 D6 D5 D3 C1 D6 D3 C0 Error
PASS PASS PASS No Error
PASS PASS FAIL C0
PASS PASS PASS C1
PASS PASS FAIL D3
PASS PASS PASS C2
PASS PASS FAIL D4
PASS PASS PASS D5
PASS PASS FAIL D6
Recommended testing instruments needed for experiments in this work book
1. Oscilloscope 20 MHz, Dual Trace, ALT Trigger with bandwidth
2. Oscilloscope Probes X1 – X10 etc.
Experiment 1
Objective :
Study of Error Check Codes
Procedure :
1. Set Up the following initial conditions on ST2153 :
a) Mode Switch in FAST Position.
b) DC l & DC 2 amplitude controls in function generator block in fully
clockwise position.
c) Set ~1 KHz & 2 KHz signal levels in function generator block to 10Vpp.
d) Pseudo random sync code generator switched ‘On’.
e) Error check code selector switches A & B in A = 0 & B =0 Position ('Off'
Mode).
f) All switched faults 'Off'.
2. Set Up the following initial conditions on ST2154 :
a) Mode Switch in FAST Position.
b) Pseudo random sync code generator switched ‘On’.
c) Error check code selector switches A & B in A = 0 & B =0 positions ('Off'
Mode).
d) All switched faults 'Off'.
e) Pulse generator delay adjusts control in fully clockwise position.
3. Make the following connections on ST2153 (See Figure 4) :
a) DC l Output to CH 0 input (TP 10).
b) CH 0 Input (TP10) to CH 1 input (TP12).
This ensures that the two channels contain the same information.
4. Make the following connections on ST2154 (See figure 4) :
a) PCM data input (TP1) to clock regeneration circuit input (TP3).
b) Output of clock regeneration circuit (TP8) to RX clock input (TP46).
5. Make the following connections between ST2153 & ST2154 see Figure.4.
a) PCM output (TP44) of ST2153 to PCM data input (TP1) of ST2154.
b) Connect the grounds of both the trainers.
6. Turn ‘On’ the power. Ensure that the frequency of the VCO in the receiver
clock regeneration circuit has been correctly adjusted
7. Connect
a) Channel 1 of oscilloscope to (TP10) on ST2153.
Figure 4
A/D Conversion
The PCM Transmitter samples the analog input, time division multiplex and many
such channels, quantizes it & code it by analog to digital conversion. As it is known,
the binary number system consists of binary digits '0' and '1'. The group of n bits is
called as word and is used to distinguish one code from the other. The range of
decimal numbers represented by such n bits code is equal to 2n (including 0) e.g. If we
take an 8 bit word, the number or different codes possible is equal to 28 = 256 i.e. we
have 0 to 255 code levels available.
This range can be used to indicate any range of voltage. The process of allocating the
binary values to each sample taken in PAM system is known as quantization. Every
binary number indicates one level. Since binary value changes in discrete steps & is
not continuous like analog waveform, some distortion creeps in at the time of value
assignment; this is discussed in forth coming parts. The range of binary values used is
the design feature of the system & depends upon the amplitude range of the signal and
the accuracy of the conversion to be achieved.
Most systems use an 8 bit word length which is practically found most suitable to
cover the sufficient range & provide the accuracy needed for speech signals. As with
all engineering processes, quantization produces its own problems & an engineering
compromise is then called for. The two major problems associated with quantization
are :
1) One major problem associated with quantization is due to the discrete nature of
binary numbers which are used to represent continuously variable analog
waveform, It is not possible to represent all the analog values (which are infinite
in number) by limited binary words e.g. if in the figure 5, the analog value lies
in between the two voltages represented by 0011 & 0100 binary words, what
will happen?
Figure 5
In such cases the system allocate a binary number closest to the sample value. This
leads to distortion of the information signal & the approximation is random for
different voltage levels. Hence it is known as quantization noise. Quantization noise
can be reduced by increasing the number of bits used to represent a sample. But it can
never be eliminated. Increasing the number of bits in a word has an effect of
increasing the number of quantization levels.
2) The second problem is associated with the finite time taken by the A/D
Converter to complete the translation from analog to binary code. An A/D
Converter requires that the sample value should remain unchanged till the
conversion is complete, but usually the duration of the sample pulse is much
smaller than the conversion time. This problem can be overcome by using a
sample and hold circuit prior to A/D input. The sample and hold circuit holds
the sample value for the A/D Conversion time. The quantization & Coding
process is carried by the A/D Converter. On ST2153 the A/D converter used is
AD670. It is an 8 bit A/D converter. The A/D conversions are controlled by
R/W, CS, & CE pins. The R/W pin directs the converter to read or start a
conversion. The CE & CS pins are tied to logic 0. The Status pin goes High
indicating that a conversion is in process. At the end of the conversion the Status
pin goes Low. On ST2153 the R/W pin is named as SC (TP7) and pin after
inversion is named as EC (TP8). This EC is used to latch the valid data into D-
type Flip-Flops (see circuit description in operating manual). Only 7 most
significant bits out of 8 data outputs are used on ST2153. The LSB (D0) is
ignored.
Experiment 2
Objective :
Study of Analog to Digital Conversion
Procedure :
1. Ensure the following initial conditions on the ST2153.
a. Mode switch in fast position.
b. DC l & DC 2 Controls in function generator block, fully clockwise.
c. ~ 1 KHz & ~2 KHz signal controls set to 10Vpp.
d. Pseudo - random sync code generator switched 'Off'.
e. Error check code selector switches A & B in A = 0 & B= 0 position ('Off'
Mode).
f. All switched faults 'Off'.
2. Connect on ST2153 :
a. DC l output to CH 0 input
b. DC 2 output to CH 1 input
3. Turn ‘On’ the power. With the help of digital voltmeter / oscilloscope, adjust
the DC l amplitude control until the DC 1 output measures 0V: The accuracy
should be within +/-20mV. Turn the DC 2 amplitude control, fully counter
clockwise.
4. Observe the output on the A/D converter block LEDs (D0 to D6). The LEDs
represent the state of the binary PCM word allocated to the PAM sample being
processed.
An illuminated LED represent a '1' state, while non illuminated LED indicates a
'0' state. D6 is the MSB & D0 is the LSB. The LED output looks as follows.
D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0
This output is the digital representation of 0V input to CH 0
5. Adjust the DC1 amplitude control clockwise to increase the amplitude &
anticlockwise to decrease it. Try varying the DC input from + 5V to - 5V in
steps of 1V. Take care that the input value is within the specified range of +/-
20mV. Observe that the output for +5V is as follows :
D6 D5 D4 D3 D2 D1 D0
1 1 1 1 1 1 1
Where for the negative values it is less than 1000000 for -5V the output is as
follows
D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0
This is obtained at the approximately full anti-clockwise position of the DC
Control.
6. Turn the DC 1 control fully anti-clockwise and repeat the above procedure by
varying DC 2 control. Check that the digital code for the set voltage value is
identical to that of the DC 1 setting.
Once again take the precaution of maintaining the set input within +/- 20mV
range of the specified voltage.
7. Switch 'Off' the trainer. Disconnect the DC 1 & DC 2 supply from CH 0 & CH
1. Connect ~1 KHz signal to CH 0 & 2 KHz signal to CH 1 input.
8. Trigger the dual trace oscilloscope externally by the CH 1 signal available at
TP12. Observe the signal at CH 0 & CH 1 sample output (TP5) with reference
to the SC Signal (TP7) on the second trace. Give a special attention to the phase
relation between the two signals.
9. Now connect the oscilloscope channel 1 to CH 1 sample (TP6) sketch the three
waveforms with utmost importance to the relationship between the three
waveforms.
10. Connect oscilloscope channel 1 input to SC test points (TP7) & oscilloscope
channel 2 input to EC test point (TP8).
Observe the phase relation between the two SC & EC test point. Notice that EC
goes high at the end of conversion & remains latched until next SC Pulse.
Digital Transmission
There are two methods for sending digital data over a distance, namely
a. Parallel transmission
b. Serial transmission
In short distance communication like inside terminal equipment or two computer
terminals located near each other, the signals are passed in parallel, format over
parallel wires. Thus the signal in the form of a word is passed. This mode is faster.
For long distances, even more than few feet’s, this is uneconomical & inefficient way
of transmission. It is a wasteful of transmission media as each bit requires a separate
link. Therefore the digital signals are transmitted serially over a single link.
The two important parameters in serial signaling are
1. The modulation rate or the signaling rate (in Bauds) &
2. data transmission rate or bit rate (in Bits per second)
The signaling rate or modulation rate is defined as the maximum rate at which the
signal is switched between signaling rate (or number of symbols transmitted per
second).
The other way of defining modulation rate is that it is the reciprocal of the shortest
time for which the signal remains in any state. The modulation rate is measured in
Baud which is equal to one unit signal element per second. See figure 6.
Figure 6
The ST2153's A/D Converter outputs data in parallel format which is change into
serial format by the shift register. This is known as parallel to serial conversion.
Figure 8
Experiment 3
Objective :
Study of Control Signals and their Timings
Procedure :
1. Set up the following initial conditions on ST2153 :
a. Mode switch in fast position
b. DC 1 & DC 2 Controls in function generator block fully clock wise
c. ~1 KHz & -2 KHz control levels set to give 10Vpp.
d. Pseudo random sync code generator on / 'Off' switch in 'Off' Position.
e. Error check code generator switches A & B m A= 0 & B = 0 Position
('Off' Mode).
f. All switched faults 'Off'.
2. Make the following connections as shown in figure 9:
I. DC 1 TO CH 0
II. DC 2 TO CH 1
3. Turn ‘On’ the power.
Adjust the DC1 amplitude control such that the voltage measured at TP10 (CH
0) with the help of DMM / oscilloscope is + 3 Volts.
Adjust the DC 2 amplitude control so that the voltage at TP12 (CH 1) is 2 V.
4. The LED outputs of A/D Converter & shift register are a combination of the
two input voltages. Also since the trainer is working in fast mode, it is
impossible to detect the code.
5. As stated earlier, the two channels are sampled at different time.
Approximately, after 10 seconds, when the system has settled down to slow
mode, observe the LEDs of A/D converter Block.
Notice that a particular combination of LEDs is lit in the A/D converter Block
for approximately 7 seconds.
These LEDs represent the latched output from the A/D Converter for every
sample of CH 0 & CH 1 Channels. Note the output of the A/D Converter,
Note : You may find the A/D Converter's output may not be identical every time you
switch the circuit from fast to slow mode for the same DC Control setting. This is due
to the slight change in voltage at Sample / Hold circuit at the time of switching.
However the change in code will only be 1 Bit.
Figure 9
6. The parallel data from the A/D Converter is then loaded in the shift register
which converts in serial output. Connect the oscilloscope at following points :
a) Oscilloscope channel 1 to TX. clock output (TP3)
b) Oscilloscope channel 2 to S/L test point (TP9)
c) External trigger to TX. to output (TP4)
You may have to adjust the oscilloscope trigger levels to obtain a stable display.
7. Observe the interdependence of S/L, TX clock output and the shift register
outputs as shown by their respective LEDs. Record the waveforms. The timing
diagram for the process is shown in figure 10.
Pulse Amplitude Modulated wave with large time Intervals between samples
Figure 11
On ST2153, the sequence of operation is synchronized to the transmitter clock TX.
Clock (TP3). The time occupied by each clock pulse is called a Bit. The sequence of
operation is repeated after every 15 bits. The complete cycle of 15 bits is called timing
frame. The start of the timing frame is denoted by the TX.TO signal (TP4) which goes
high during the bit time 0. The various bits reserved for the data appearing in the
middle of each transmitter clock cycle is shown in figure the figure 12 shows the
complete timing frame
The ST2153 provides these two signals at TX. Clock output (TP3) & TX.TO output
(TP4). In this mode the Pseudo random sync code generator & detector (on ST2154)
are switched 'Off'.
The second technique is to transmit the synchronization code along with transmitted
data to be sufficiently different from the information samples.
The ST2153 involves the use of a pseudo-random sync code generator. These codes
are bit streams of '0's & '1's whose occurrence is detected by some rules. The Pseudo -
Random Sync Code gets its name from the fact that the occurrence of '0's & '1 's in the
stream is random for a portion of sequence i.e. there is equal probability of occurrence
of '0' and '1 '. This portion of sequence is 15 bit long on ST2153.
On the receiver the pseudo-random sync code detector recognizes the Pseudo random
code & use it to identify, which incoming data bit is associated with which transmitter
timeslot The advantage of this technique is that if the synchronization is temporarily
lost, due to noise corruption, it can be re-established as the signal clears. Hence there
is minimal loss of transmitted information. Also this technique also reduces the
separate link required for the synchronization signal of transmission.
Mode 1 : Mode 1 is TDM system of three transmission links between transmitter &
receiver. They are information, TX clock & TX.TO (synchronization) signal links.
The Pseudo random sync code generator & Detector are switched 'Off' in this case.
Mode 2 : Mode 2 is TDM system of two transmission links between transmitter &
receiver. These are information & TX clock signal links. The synchronization is
established by sync codes transmitted along with the data stream. No need to say that
the pseudo random sync generator & detector are switched ‘On’.
Mode 3 : Mode 3 is TDM system of one link between transmitter & receiver, namely
the link carrying information. Synchronization is again established by the sync codes.
The clock signal is regenerated by the phase locked loop (PLL) circuit at the receiver
from the transition of the information data bits.
Experiment 4
Objective :
Study of Time Division Multiplexing
Procedure :
1. Set up the following initial conditions on ST2153:
a) Mode Switch in fast position
b) DC 1 & DC2 Controls in function generator block fully clockwise.
c) ~ 1 KHz and ~2 KHz control levels set to give 10Vpp.
d) Pseudo - random sync code generator on/'Off' switch in 'Off' Position.
e) Error check code generator switch A & B in A=0 & B=0 position ('Off'
Mode)
f) All switched faults 'Off'.
2. First, connect only the 1 KHz output to CH 0
3. Turn ON the power. Check that the PAM output of 1 KHz sine wave is
available at TP15 of the ST2153.
4. Connect channel 1 of the oscilloscope to TP10 & channel 2 of the oscilloscope
to TP15. Observe the timing & phase relation between the sampling signal
TP10 & the sampled waveform at TP15.
5. Turn 'Off' the power supply. Now connect also the 2 KHz supply to CH 1.
6. Connect channel 1 of the oscilloscope to TP12 & channel 2 of the oscilloscope
to TP15.
7. Observe & explain the timing relation between the signals at TP10, 5, 6, 12&15.
Experiment 5
Objective :
Study of Pseudo Random Sync Code Generator
Procedure :
1. Ensure the following initial conditions on ST2153 :
a) Mode Switch in fast position.
b) DC l & DC 2 Controls in function generator block, fully clockwise.
c) ~ 1 KHz & ~2 KHz signal control set at 10Vpp.
d) Pseudo random sync code generator switched 'Off'.
e) All switched faults 'Off'.
f) Error check code selector switches, A & B in A=0 & B=0 position (‘Off’
Mode).
2. Ensure the following initial conditions on ST2154
3. Mode switch in fast position.
a) Pseudo random sync code detector switched ‘Off’.
b) Error check code selector Switches A=0 & B=0 Position. (‘Off’ Mode)
c) All four switched faults 'Off'.
d) Pulse generator delay adjust control fully clockwise.
4. Make following connection on board of ST2153 :
1 KHz To CH 0 Input
2 KHz To CH 1 Input
5. Make the following connections between ST2153 & ST2154.
ST2153 ST2154
TX. Clock output TP3 RX clock input TP46
TX. To output TP4 RX sync input TP47
PCM output TP44 PCM input TP1
6. Display channel CH 0 Input (TP10) on oscilloscope channel 1 & use it to trigger
the oscilloscope. Display the ST2153 PCM output (TP44) on channel 2 of the
oscilloscope.
7. Vary the amplitude of the 1 KHz & 2 KHz sine wave signal & note that the
transmitted data changes.
8. Also observe the two input signals TP10 & TP12 of ST2153 with the received
sine wave samples TP32 & 35 of ST2154 and at the respective low pass filter
outputs CH 0 & CH 1 (TP33 & 36) of ST2154.
9. Vary the amplitude of ~1 KHz & ~2 KHz signals at the ST2153. Observe how
the output at receiver changes. Set a value of 4Vpp for channel 0. Note what is
the output voltage of the received signal.
10. Turn ‘Off’ the power. Rearrange the connections between ST2153 & ST2154 as
follows.
ST2153 ST2154
TX. clock output RX clock input
PCM output PCM input
11. Connect
Channel 1 of the oscilloscope to TP12 on ST2153.
Channel 2 of the oscilloscope to TP36 on ST2154.
12. Turn ‘On’ the power. Notice the waveforms & confirm that they are different.
13. Vary the setting of ~2 KHz signal & observe the waveform at TP36. Explain
the reason behind the mismatch.
14. Turn 'Off' the power. Connect TX.TO output from ST2153 to RX sync input on
ST2154.
15. Turn ‘On’ the power. Now notice the two waveforms again. Do you notice any
change? Why it has happened?
16. Now you must have observed the importance of synchronization. But now the
synchronization has been established because of the separate link between
ST2153 & ST2154.
17. Turn 'Off' the power Remove the link between RX.SYNC & TX.TO. Turn ‘On’
the trainer. Observe the two mismatched waveforms. Now turn ‘On’ the pseudo
random sync code generator on ST2153. Do you notice any change in the
observed waveform at TP36 on ST2154.
18. Turn the pseudo random sync code detector on ST2154 ON. Notice the changes
observed waveform at TP36 of ST2154.
19. To be able to perceive the pattern of the sync code generated, connect the
oscilloscope probes to TP4 (TX.TO output & TP42) (Pseudo random sync code
generator output).
Notice the sync coded output for a high level occurrence at the TX to output. If
necessary switch the two trainers to slow mode.
20. Notice the sync Bit counter LED, in pseudo random sync code detector Block of
ST2154 is ‘On’ in FAST Mode. This is an indication that the receiver has
identified the transmitted bit time 0 & is using it for all its timing operations.
This also confirms that the two are in 'Frame Synchronization'.
Observe the TX.TO (TP4) output signal on ST2153 & RX.TO (TP48) output
signal on ST2154. They should be identical when frame synchronization has
been achieved.
21. Switch 'Off' the pseudo random sync code generator. Notice that the sync bit
counter LED goes 'Off' indicating that the synchronization has been lost. Notice
at the same time that the sync error counter led goes ‘On’. Note the LED
indication may be faint. There fore observe carefully. This goes to show that
synchronization has been lost.
Experiment 6
Objective :
Study of Three Modes of Transmission
Procedure :
1. Set up following initial conditions on the ST2153:
a) Mode Switch in fast Position.
b) DC l & DC 2 Controls in function generator block fully clockwise.
c) Pseudo random sync code generator switched 'Off'.
d) Error check code selector switches A & B in A=0 & B=0 Position.
e) All switched faults 'Off'.
2. Set up following initial conditions on ST2154 :
a) Mode Switch in fast Position.
b) Pseudo random sync code detector switched 'Off'.
c) Error check code selector switches A & B in A=0 & B=0 position.
d) All switched faults 'Off'.
e) Pulse generator delay adjusts control in fully clockwise position.
3. Make connections as shown in figure 13.
a. ‘On’ ST2153 :
I. ~ KHz Signal to CH 0 Input.
II. ~2 KHz Signal to CH 1 Input.
b. Between ST2153 & Receiver trainer
ST2153 ST2154
TX. Clock output RX. Clock input
TX.TO output RX sync input
PCM output PCM data input
4. Turn ‘On’ the power. Observe that the 1 KHz sine wave input appears at TP10
(CH 0 Input) & 2 KHz sine wave input appears at TP12 (CH 1 Input).
5. Connect
Channel 1 of oscilloscope to CH 0 Input (TP10)
Channel 2 of oscilloscope to PCM output (TP44)
Trigger the oscilloscope with CH 0 input. Observe the two waveforms. Vary the
ST2153's ~1 KHZ and ~2 KHz controls (which vary the amplitude of the two
sine waves) and note how the transmitter data changes.
Figure 13
10. As it has been discussed earlier, for correct operation the receiver needs to be
clocked" at the same rate as the transmitter & it should be able to decide which
timeslot is for which information transmit TX clock & TX.TO signals on
separate links. TX clock signals clocks the receiver at the same rate where as
the TX. TO signal helps the receiver to identify the timeslot 0.
11. The three wire connections can be reduced to two wires by developing the
ST2153's ability to transmit the synchronization information along the data.
Similarly, the receiver must be able to detect & distinguish these sync bits from
the normal information bits.
This ability is imparted by the Pseudo random sync code generator & detector
present on ST2153 & receiver trainer respectively. The pseudo random sync
code is a sequence of 15 bits generated by the pseudo random sync code
generator.
0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 .............................................................. Repeating.
One bit of this sequence is transmitted in every frame at timeslot 0. The receiver
detects it & uses it to decide which timeslot is for which frame.
12. The above mode is termed as 'connecting Mode 2'. The ST2153 / Receiver can
be configured in this mode as shown in figure 14.
a. Switch the boards to FAST mode.
b. Remove the link connecting TX.TO (TP 4) & RX sync (TP 47).
c. Switch ‘On’ the pseudo random sync code generator on ST2153.
d. Switch ‘On’ the pseudo random sync code detector on ST2154.
e. Connect DC 1 to CH 0 & CH 0 to CH 1
13. Vary DC 1 and note that the LEDs on the A/D converter block on ST2153 &
D.A. converter of ST2154 always carries the same code.
Also observe that the sync bit counter led in the pseudo random sync code
detector block is ‘On’. This signifies that the receiver knows the transmitted
timeslot & can identify them. We say that the receiver is 'Frame Synchronized'
to the transmitter. Once the transmitter & receiver is frame synchronized, the
TX.TO & RX.TO signals are identical. You can observe the two waveform at
TP4 of ST2153 & at TP48 of ST2154 respectively.
14. Switch 'Off' the pseudo random sync code generator. Notice that the A/D
converter block output observed on LEDs is not similar to the D/ A Converter
Block input. We say that the receiver has lost the frame synchronization. The
Receiver indicates this by turning 'Off' the sync bit counter led in pseudo
random sync code detector block.
Figure 14
15. If you desire to examine the timing of data flow & control signal in detail,
switch the ST2153 & receiver into slow mode.
16. The number of connecting links can be reduced further to one by configuring
the ST2153 & receiver in connecting Mode 3. The only connecting link
between transmitter & receiver is the data/information link. The receiver
establishes the synchronization from pseudo random sync code transmitted
along with the P.C.M. data. In this case it has to regenerate the clock signal as
well. The receiver does this by on board phase locked loop circuit which
regenerates the clock from the transitions of the data bit whose timing with
respect to the clock signal is fixed.
17. Configure the ST2153 & receiver as shown in figure 15 and ensure the
following statements :
a. Both trainers are switched in FAST Mode.
b. Link between TX clock (TP3) & RX clock (TP46) has been removed.
c. PCM data input (TP1) on ST2154 is connected to the input (TP3) of phase
locked loop circuit on the same trainer.
d. The phase locked loop output (TP8) is connected to the RX clock input
(TP46) on the ST2154.
18. Before operating in connecting Mode 3 it may be necessary to trim the voltage
controlled oscillator (VCO) frequency, so that the regenerated clock remains in
synchronization with the incoming data even when few transitions occur. (This
happens when there is a long stream of '0's to '1's in the. NRZ (L) waveform).
Follow the procedures given below to trim the VCO frequency :
a. Turn the DC1 control in the function generator block on ST2153 fully
clockwise.
b. Slowly, turn the VCO frequency adjust control on ST2154 until the sync bit
counter led in the pseudo random sync code detector Block turns ‘On’.
c. Repeat the above steps till position of the control is found such that the sync
bit counter led remains ‘On’ for both fully clock wise & anticlockwise
positions of the DC1 Control.
19. At the ST2153, remove the CH 0 & CH 1 inputs & connect.
a. ~ 1 KHz Signal to CH 0 input.
b. ~ 2 KHz Signal to CH 1 input.
Note : Turn 'Off' the power when new connections are made or disconnected.
Adjust the outputs of the two generators to 8Vpp by the amplitude controls
provided in the Function generator block. You can observe the two signals at
TP10 & 12).
20. Observe the ST2154 analog outputs (TP33 & 36). Verify that the two outputs
are identical to that applied at the transmitter's inputs.
21. The trainers have on board error check generator & detector (on ST2153 &
ST2154 respectively). This provides an opportunity to detect & if possible to
correct the erroneous trainer data. The Error check code generator replaces
some least significant bits of the 7 Bit word with some error check bits. The
following error check options are available on board :
a. 'Off' : The error check generator is 'Off' when this mode is selected by
switching the A & B switches in the error check code generator block in
ST2153 in A = 0 & B = 0 position.
No error check code is inserted in the 7 Bit word. The word format is
D6 D5 D3 D2 D1 D0
Where D6-D0 are the A/D Converters latched outputs.
b. Even Parity : This option is selected by placing A & B switches in the error
check code generator block in ST2153. In A = 0 & B=1 position. The least
significant bit of the 7 bit word is replaced by a single parity bit.
The word format is :
D6 D5 D4 D3 D2 D1 C0
Where C0 is the parity check bit which is chosen such that the total no of '1's
in the 7 bit word are even. If the error check code detector in ST2154 is also
configured in this mode, it can detect the error in the transmitted data, but it
cannot tell which bit is in error. It indicates 'the error by switching ‘On’ of
the Parity Error LED.
c. Odd Parity : This option is selected by placing the A & B switches in the
error check generator block in A = l & B = 0 position. The least significant
bit of the 7 - Bit word is replaced by a single parity bit.
The word format is.
D6 D5 D4 D3 D2 D1 C0
Where C0 is the parity check bit such that the total no of '1's in the 7 bit word
are odd.
If the error check code detector in ST2154 is also included in this mode, it
can detect the error in the transmitted data, but cannot tell which bit is in
error. It indicates the error by switching ‘On’ of the parity error LED.
d. Hamming Code : This option is selected when the A & B switches in the
Error check code generator on ST2153 are placed in A=1 & B=1 position.
In this case the three check bits replace the three least significant bits of the
7 bit word. The word format is :
D6 D5 D4 D3 C2 C1 C0
Where C2, C1 & C0 are the Hamming check bits. If the Error Check Code
Detector in ST2154 is switched into same .mode, it can detect the error &
even connect the erroneous transmitted data bit (only single). It indicates the
erroneous bit by lighting the corresponding LED in hamming code error
block. Illustration of various check codes are given in steps 22nd to 29th :
22. Connect the ST2154's CH 0 (TP33) & CH 1 output (TP36) to the two channels
of the oscilloscope. Now introduce the switched fault '2' in the trainer system by
switching ‘On’ the pole 2 of switched faults Block. This fault forces the D6 bit
(MSB) of the transmitted 7 bit word to be always '1' even when there must have
been a '0'. Notice the distortion in the output in the output sine waves at the
ST2154's CH 0 (TP33) & CH 1 (TP36) outputs.
23. Switch 'Off' the fault. Introduce even parity error check code option on both the
trainers by switching the A & B switches in the corresponding block to A=0 &
B=1 position.
24. Observe the two output waveforms at ST2154's CH 0 (TP33) & CH 1 (TP36)
outputs are distortion less & also observe the LEDs in the error check code
detector block are 'Off'.
25. Switch ‘On’ fault '2' again.
Observe that the parity error indicator LED in error check code detector glows
i.e. the receiver has detected the error in transmitted data but is not in a position
to locate which bit is in error. Therefore the output at CH 0 & CH 1 on ST2154
still remains distorted.
26. You can carry on the same experiment by selecting the odd parity option. You
will get the same result as the earlier ones. Note switch 'Off' the fault prior to
selecting the Error check code option.
27. Switch ''Off'' the fault. Select the hamming code option by placing the A & B
switches in the corresponding block to A = 1 & B = 1 position.
28. Switch ‘On’ fault '2'
Observe that the D6 LED marked in error check code detector's hamming code
error bit glows. Since its 3 bit hamming code, it can detect as well as correct one
bit error in a sample. It reveals the erroneous bit in the data format by lighting
the corresponding LED (D6 in the present case). Notice, now that the outputs at
CH 0 & CH 1 on ST2154 are now distortion less. This is because the erroneous
bit has even been corrected by the receiver.
29. You can induce any switched fault /faults in the ST2153 & ST2154 trainer to
investigate the effect of particular faults on the whole system. This also allows
you the opportunity to practice & test your skills in fault detection trouble -
shooting. The list of various faults that can be induced in the system is given in
this manual.
Figure 15
Experiment 7
Objective :
Computer Communication using RS232 interface via ST2153 & ST2154
There are two channels provided on ST2153 & ST2154. It utilizes these two channels
to communicate between two computers, thus forming a full duplex link. It will need
the following :
System :
Microsoft Windows 95, 98, or above
Software :
Supplied with the trainer in CD
Procedure :
1. Keep PCs on either side of the ST2153 & ST2154.
2. Connect the RS232 cable to the serial port of the computer and the other end to
ST2153 & ST2154 as shown in figure 16.
3. Make the interconnections between ST2153 & ST2154 as shown in the figure
16. (Before connecting perform the experiment no.6 in mode 3).
4. Install the Software on both the PCs.
5. After establishing a connection, select the com port in the "COM Port" window,
and select Baud rate (same on both PC’s).
6. Follow this procedure for both the computers.
7. Switch ‘On’ the trainers.
8. Now type a message in the message window of PC1 and click send, you will see
the message in receiver window of PC2 and in transmit window of PC1.
9. If you send a message from PC2 you will receive the message in the receiver
window of PC1 and in transmitter window of PC2.
10. If you disconnect any of the transmitting or receiving wire, you will see that the
data transmission has failed.
11. You can reduce the baud rate of both PCs and you will observe that the transmit
rate is lower.
Figure 16
Experiment 8
Objective :
Multi point to multipoint communication using RS232 interface via ST2153 &
ST2154
There are two channels provided on ST2153 & ST2154. It utilizes these two links to
communicate from two PCs on one end to two PCs on other end. The two PCs
connected to ST2153 will act as transmitter, and those connected to ST2154 will act
as receiver. This will be a one way communication. It will need the following:
System :
Microsoft Windows 95, 98, or above
Software :
Supplied with the trainer in CD.
Procedure :
1. Keep the PCs on either sides of the ST2153 & ST2154.
2. Connect the RS232 cable to the serial port of the computer and the other end to
ST2153 & ST2154 as shown in figure 17.
3. Make the interconnections between ST2153 & ST2154 as shown in the figure
17 (Before connecting perform the experiment no.6 in mode 3).
4. Install the software provided with the trainer in all the four PCs.
5. Run the software in all the PCs and select the respective COM ports and the
same baud rate in all the PCs.
6. Switch ‘On’ the trainers.
7. Now the data transmitted by PC1 and PC2 will be multiplexed, Pulse code
modulated and transmitted via single wire and then, demodulated–de-
multiplexed and received by PC 3 and PC4 respectively.
Figure 17
Experiment 9
Objective :
Point to multipoint communication using RS232 interface via ST2153 & ST2154
There are two channels provided on ST2153 & ST2154. It utilizes these two links to
communicate from one PC to the two other PC's on the other end. The PC on the
transmitter side will act as master and the PCs on receiver side will act as slaves. This
will also be a one way communication.
System :
Microsoft Windows 95, 98, or above
Software :
Supplied with the trainer in CD
Procedure :
1. Keep one PC to the left of ST2153 (master) & two PCs to ST2154 (slaves) as
shown in figure 18.
2. Connect the RS232 cable to the serial port of the computer and the other end to
ST2153 & ST2154 as shown in the figure 18.
3. Make the interconnections between ST2153 & ST2154 as shown.
4. Install the software provided with the trainer in all the three PCs. Run the
software and select the respective COM ports and same BAUD rate in all the
PCs.
5. Switch ‘On’ the trainers.
6. Now the data or instructions transmitted by the master will be received by the
two slaves.
Figure 18
Switched Faults
1. Transmitter Switched Faults :
Following faults can be induced in the ST2153 to study their effects on the system &
to practice fault-diagnosis techniques.
Switched Fault 1 :
Switching ON of this fault causes the A/D Converter's D6 Output to be always '0',
irrespective of the applied analog input. The fault occurs before error check code
generator & hence cannot be detected by the receiver’s error detection correction
logic. Hence the output of the receiver is not always a true representation of the
applied analog input at the transmitter.
Switched Fault 2 :
The switching ‘On’ of this fault cause D6 bit of the P.C.M. output of the transmitter to
be always '1' irrespective of the connect D6 bit level. This fault is induced after the
error check code generator block & hence can be detected & in case of hamming code
selected, can be corrected also if the same mode is selected on error detection &
correction logic on receiver trainer also. This fault can be used to study the utility of
the error check codes in case of bit corruption in the P.C.M. data along the
transmission path.
Switched Fault 3 :
This fault causes the error check code generator to treat the A/D converter's D5 output
to be always high irrespective of the actual D5 bit in P.C.M. data transmitted. This
fault has no effect when none of the error check code option is selected the receiver
may wrongly decide that the P.C.M. data has a fault.
In case of hamming code, the receiver may try to correct the wrongly diagnosed 'error'
thus distorting the output in this process.
Switched Fault 4 :
This fault affects the pseudo random sync code generator. It causes the generator to
generator a sequence which is not Pseudo Random in Nature. Hence if the receiver is
relying on pseudo random sync code for synchronization as in connecting Modes 2 &
3, the receiver loses frame synchronization. This distorts the receiver's output.
2. Receiver Switched Faults
The Following faults can be induced in the ST2154 receiver trainer to study their
effects on the system & to practice fault diagnosis techniques
Switched Fault 1 :
This fault breaks the loop between phase locked loop output & loop filter's input on
ST2154 receiver trainer. Thus induction of this fault cause the malfunctioning of
phase locked loop circuit. Hence the receiver doesn't clock into synchronization in
connecting Mode 3. Remember PLL circuit is used to extract clock information in
connecting Mode 3.
Switched Fault 2 :
This fault affects the functioning of ST2154's pseudo random sync code detector.
When this fault is induced, the receiver cannot detect the transmitted pseudo random
sync code. Hence in connecting Mode 2 & 3 in which the ST2154 depends on sync
code detection for frame synchronization this fault cause the receiver to continuously
try to resynchronize but to do so every time.
Switched Fault 3 :
This fault affects the ST2154's error detection/correction logic when the hamming
option is selected. It causes an error in C1 to be indicated when the received data and
check bits are correct. If the received data actually contains an incorrect bit, the
receiver may decide that the wrong bit is in error, and if that bit is a data bit, try to
correct it. The effect of this fault is detailed in the table below.
Warranty
1. We guarantee the product against all manufacturing defects for 24 months from
the date of sale by us or through our dealers. Consumables like dry cell etc. are
not covered under warranty.
2. The guarantee will become void, if
a) The product is not operated as per the instruction given in the operating
manual.
b) The agreed payment terms and other conditions of sale are not followed.
c) The customer resells the instrument to another party.
d) Any attempt is made to service and modify the instrument.
3. The non-working of the product is to be communicated to us immediately giving
full details of the complaints and defects noticed specifically mentioning the
type, serial number of the product and date of purchase etc.
4. The repair work will be carried out, provided the product is dispatched securely
packed and insured. The transportation charges shall be borne by the customer.
List of Accessories
1. Patch Cord 16" ...........................................................................................4 Nos
2. Patch Cord 20" ...........................................................................................1 No.
3. Mains Cord.................................................................................................1 No.
4. RS232 Cable .............................................................................................2 Nos
5. e- Manual ..................................................................................................1 No.
Updated 05-08-2008